View ADE7753_973861.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Single-Phase Multifunction Metering IC with di/dt Sensor Interface ADE7753
FEATURES
High accuracy; supports IEC 61036/61827 and IEC61268 On-chip digital integrator enables direct interface to current sensors with di/dt output Active, reactive, and apparent energy; sampled waveform; current and voltage RMS Less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25C Positive-only energy accumulation mode available On-chip user programmable threshold for line voltage surge and SAG and PSU supervisory Digital calibration for power, phase, and input offset On-chip temperature sensor (3C typical) SPI(R) compatible serial interface Pulse output with programmable frequency Interrupt request pin (IRQ) and status register Reference 2.4 V with external overdrive capability Single 5 V supply, low power (25 mW typical)
voltage and current. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog integrator and resulting in excellent long-term stability and precise phase matching between the current and voltage channels. The ADE7753 provides a serial interface to read data, and a pulse output frequency (CF), which is proportional to the active power. Various system calibration features, i.e., channel offset correction, phase calibration, and power calibration, ensure high accuracy. The part also detects short duration low or high voltage variations. The positive-only accumulation mode gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit any creep when there is no load. The zero-crossing output (ZX) produces a pulse that is synchronized to the zero-crossing point of the line voltage. This signal is used internally in the line cycle active and apparent energy accumulation modes, which enables faster calibration. The interrupt status register indicates the nature of the interrupt, and the interrupt enable register controls which event produces an output on the IRQ pin, an open-drain, active low logic output. The ADE7753 is available in a 20-lead SSOP package.
GENERAL DESCRIPTION
The ADE7753 features proprietary ADCs and DSP for high accuracy over large variations in environmental conditions and time. The ADE7753 incorporates two second order 16-bit - ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurements, line-voltage period measurement, and RMS calculation on the
AVDD
FUNCTIONAL BLOCK DIAGRAM
RESET DVDD DGND
PGA V1P
ADC
WGAIN[11:0]
INTEGRATOR MULTIPLIER LPF2
ADE7753
dt
HPF1 PHCAL[5:0]
2
V1N
TEMP SENSOR
APOS[15:0]
DFC
CFNUM[11:0]
IRMSOS[11:0]
x2
CF
CFDEN[11:0]
VAGAIN[11:0]
PGA V2P
V2N
ADC
x2
VRMSOS[11:0]
LPF1 4k
VADIV[7:0]
%
%
WDIV[7:0]
ZX
2.4V REFERENCE
REGISTERS AND SERIAL INTERFACE
SAG
AGND
REFIN/OUT
CLKIN CLKOUT
DIN DOUT SCLK
CS
IRQ
02875-0-001
Figure 1. ADE7753 Functional Block Diagram
*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; Others Pending
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADE7753 TABLE OF CONTENTS
ADE7753-Specifications ................................................................. 3 ADE7753-Timing Characteristics ................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Terminology ...................................................................................... 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 15 Analog Inputs.............................................................................. 15 di/dt Current Sensor and Digital Integrator ........................... 16 Zero-Crossing Detection........................................................... 17 Period Measurement .................................................................. 18 Power Supply Monitor ............................................................... 18 Line Voltage Sag Detection........................................................ 19 Peak Detection ............................................................................ 19 ADE7753 Interrupts................................................................... 20 Temperature Measurement ....................................................... 21 ADE7753 Analog-to-Digital Conversion................................ 21 Channel 1 ADC........................................................................... 22 Channel 2 ADC........................................................................... 24 Phase Compensation.................................................................. 26 Active Power Calculation .......................................................... 27 Energy Calculation..................................................................... 28 Power Offset Calibration........................................................... 30 Energy-to-Frequency Conversion............................................ 30 Line Cycle Energy Accumulation Mode ................................. 32 Positive-Only Accumulation Mode ......................................... 32 No Load Threshold .................................................................... 32 Reactive Power Calculation ...................................................... 33 Sign of Reactive Power Calculation ......................................... 34 Apparent Power Calculation..................................................... 34 Apparent Energy Calculation ................................................... 35 Line Apparent Energy Accumulation ...................................... 36 Energies Scaling.......................................................................... 37 Calibrating the Energy Meter ................................................... 37 CLKIN Frequency ...................................................................... 38 Suspending ADE7753 Functionality........................................ 38 Checksum Register..................................................................... 38 ADE7753 Serial Interface.......................................................... 39 ADE7753 Registers......................................................................... 42 ADE7753 Register Descriptions................................................... 44 Communications Register......................................................... 44 Mode Register (09h) .................................................................. 44 Interrupt Status Register (0Bh), Reset Interrupt Status Register (0Ch), Interrupt Enable Register (0Ah) .................. 45 CH1OS Register (08h)............................................................... 46 Outline Dimensions ....................................................................... 47 Ordering Guide............................................................................... 47
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 48
ADE7753 ADE7753-SPECIFICATIONS1, 2
Table 1. (AVDD = DVDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = -40C to +85C)
Parameter ENERGY MEASUREMENT ACCURACY Active Power Measurement Error Channel 1 Range = 0.5 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.25 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.125 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Active Power Measurement Bandwidth Phase Error 1 between Channels AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF) Irms Measurement Error Irms Measurement Bandwidth Vrms Measurement Error Vrms Measurement Bandwidth ANALOG INPUTS3 Maximum Signal Levels Input Impedance (dc) Bandwidth Gain Error1,3 Channel 1 Range = 0.5 V Full Scale Range = 0.25 V Full Scale Range = 0.125 V Full Scale Channel 2 Offset Error 1 Channel 1 Channel 2 WAVEFORM SAMPLING Channel 1 Signal-to-Noise Plus Distortion Bandwidth(-3 dB) Spec Unit Test Conditions/Comments CLKIN = 3.579545 MHz Channel 2 = 300 mV rms/60 Hz, Gain = 2 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Line Frequency = 45 Hz to 65 Hz, HPF on AVDD = DVDD = 5 V + 175 mV rms/120 Hz Channel 1 = 20 mV rms, Gain = 16, Range = 0.5 V Channel 2 = 300 mV rms/60 Hz, Gain = 1 AVDD = DVDD = 5 V 250 mV dc Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V Channel 2 = 300 mV rms/60 Hz, Gain = 1 Over a dynamic range 100 to 1 Over a dynamic range 20 to 1 See Analog Inputs section V1P, V1N, V2N, and V2P to AGND CLKIN/256, CLKIN = 3.579545 MHz External 2.5 V reference, Gain = 1 on Channels 1 and 2 V1 = 0.5 V dc V1 = 0.25 V dc V1 = 0.125 V dc V2 = 0.5 V dc Gain 1 Gain 16 Gain 1 Gain 16 Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS See Channel 1 Sampling section 150 mV rms/60 Hz, Range = 0.5 V, Gain = 2 CLKIN = 3.579545 MHz
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.1 0.1 0.2 0.2 14 0.05 0.2
% typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ kHz max % typ
0.3 0.5 14 0.5 140 0.5 390 14
% typ % typ kHz % typ Hz V max k min kHz
4 4 4 4 32 13 32 13
% typ % typ % typ % typ mV max mV max mV max mV max
62 14
dB typ kHz
Rev. 0 | Page 3 of 48
ADE7753
Parameter Channel 2 Signal-to-Noise Plus Distortion Bandwidth (-3 dB) REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS SAG and IRQ Output High Voltage, VOH Output Low Voltage, VOL ZX and DOUT Output High Voltage, VOH Output Low Voltage, VOL CF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD
1 2
Spec 60 140 2.6 2.2 10
Unit dB typ Hz V max V min pF max
Test Conditions/Comments See Channel 2 Sampling 150 mV rms/60 Hz, Gain = 2 CLKIN = 3.579545 MHz 2.4 V + 8% 2.4 V - 8%
Nominal 2.4 V at REFIN/OUT pin 200 10 3.4 30 4 1 mV max A max k min ppm/C typ All specifications CLKIN of 3.579545 MHz MHz max MHz min
2.4 0.8 3 10
V min V max A max pF max
DVDD = 5 V 10% DVDD = 5 V 10% Typically 10nA, VIN = 0 V to DVDD
4 0.4 4 0.4 4 1 4.75 5.25 4.75 5.25 3 4
V min V max V min V max V min V max V min V max V min V max mA max mA max
Open-drain outputs, 10 k pull-up resistor ISOURCE = 5 mA ISINK = 0.8 mA ISOURCE = 5 mA ISINK = 0.8 mA ISOURCE = 5 mA ISINK = 7 mA For specified performance 5 V - 5% 5 V + 5% 5 V - 5% 5 V + 5% Typically 2.0 mA Typically 3.0 mA
See Terminology section for explanation of specifications. See plots in Typical Performance Characteristics. 3 See Analog Inputs section.
200 A
IOl
TO OUTPUT PIN
CL 50pF 1.6mA IOH
+2.1V
02875-0-002
Figure 2. Load Circuit for Timing Specifications
Rev. 0 | Page 4 of 48
ADE7753 ADE7753-TIMING CHARACTERISTICS1, 2
Table 2. (AVDD = DVDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = -40C to +85C)
Parameter Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Read Timing t93 t10 t11 t124 t135 Spec 50 50 50 10 5 400 50 100 4 50 30 100 10 100 10 Unit ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) s (min) ns (min) ns (min) ns (max) ns (min) ns (max) ns (min) Test Conditions/Comments CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width. Valid data setup time before falling edge of SCLK. Data hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS hold time after SCLK falling edge. Minimum time between read command (i.e., a write to communication reigster) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the communications register. Bus relinquish time after falling edge of SCLK. Bus relinquish time after rising edge of CS.
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See Figure 3, Figure 4, and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
t8
CS
t1
SCLK
t3 t2 t4
A4
t6 t7 t5
A2 A1 A0 DB7 DB0 DB7 DB0
t7
DIN
1
0
A5
A3
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 3. Serial Write Timing
CS
t1
SCLK
t13 t9 t10
DIN
0
0
A5
A4
A3
A2
A1
A0
t11
DOUT COMMAND BYTE DB7
t11
DB0 DB7
t12
DB0
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 4. Serial Read Timing
Rev. 0 | Page 5 of 48
ADE7753 ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25C, unless otherwise noted.
Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND V1P, V1N, V2P, and V2N Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 20-Lead SSOP, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -6 V to +6 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V -40C to +85C -65C to +150C 150C 450 mW 112C/W 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 48
ADE7753 TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE7753 is defined by the following formula:
Energy Register ADE 7753 - True Energy x 100% Percentage Error = True Energy
onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading--see Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied 5%. Any error introduced is again expressed as a percentage of reading. ADC Offset Error The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection--see the Typical Performance Characteristics. However, when HPF1 is switched on, the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets may be removed by performing an offset calibration-- see the Analog Inputs section. Gain Error The difference between the measured ADC output code (minus the offset) and the ideal output code--see the Channel 1 ADC and Channel 2 ADC sections. It is measured for each of the input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a percentage of the ideal code.
Phase Error between Channels The digital integrator and the HPF (high-pass filter) in Channel 1 have non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase-correction networks are placed in Channel 1: one for the digital integrator and the other for the HPF. Each phase correction network corrects the phase response of the corresponding component and ensures a phase match between Channel 1 (current) and Channel 2 (voltage) to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range 40 Hz to 1 kHz. Power Supply Rejection This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced
Rev. 0 | Page 7 of 48
ADE7753 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET 1
20
DIN
DVDD 2 AVDD 3 V1P 4 V1N 5
19 18
DOUT SCLK CS
CLKOUT TOP VIEW V2N 6 (Not to Scale) 15 CLKIN
16
ADE7753
17
V2P 7 AGND 8 REFIN/OUT 9 DGND 10
02875-0-005
14 13 12 11
IRQ SAG ZX CF
Figure 5. Pin Configuration (SSOP Package)
Table 4. Pin Function Descriptions
Pin No. 1 2 Mnemonic RESET DVDD Description Reset Pin for the ADE7753. A logic low on this pin will hold the ADCs and digital circuitry (including the serial interface) in a reset condition. Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The supply should be maintained at 5 V 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer such as Rogowski coil or another current sensor such as shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 V, 0.25 V, and 0.125 V, depending on the full-scale selection--see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is 0.5 V. Both inputs have internal ESD protection circuitry, and, in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of 0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is 0.5 V. Both inputs have internal ESD protection circuitry, and an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. Analog Ground Reference. This pin provides the ground reference for the analog circuitry in the ADE7753, i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. To keep ground noise around the ADE7753 to a minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane--see the Applications Information section. Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V 8% and a typical temperature coefficient of 30 ppm/C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor. Digital Ground Reference. This pin provides the ground reference for the digital circuitry in the ADE7753, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane of the system--see the Applications Information section. However, high bus capacitance on the DOUT pin may result in noisy digital current, which could affect performance. Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers--see the Energy-to-Frequency Conversion section.
Rev. 0 | Page 8 of 48
3
AVDD
4, 5
V1P, V1N
6, 7
V2N, V2P
8
AGND
9
REFIN/OUT
10
DGND
11
CF
ADE7753
Pin No. 12 13 14 Mnemonic ZX SAG IRQ Description Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2--see the Zero Crosssing Detection section. This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration--see the Line Voltage Sag Detection section. Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples--see the ADE7753 Interrupts section. Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer's data sheet for load capacitance requirements. A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share the serial bus with several other devices--see the ADE7753 Serial Interface section. Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock--see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, e.g., opto-isolator outputs. Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus--see the ADE7753 Serial Interface section. Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK--see the ADE7753 Serial Interface section.
15
CLKIN
16
CLKOUT
17 18
CS SCLK
19
DOUT
20
DIN
Rev. 0 | Page 9 of 48
ADE7753 TYPICAL PERFORMANCE CHARACTERISTICS
0.5 0.4 0.3 0.2
ERROR (%)
0.3 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 40C, PF = 0.5 0.1
ERROR (%)
0.2
GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 85C, PF = 1 25C, PF = 1
0.1 0 -0.1 -0.2 -0.3
25C, PF = 1
0
25C, PF = 0.5
-0.1 -40C, PF = 1
+85C, PF = 0.5 -0.4 -0.5 0.1 1 10 FULL-SCALE CURRENT (%) 100
02875-0-006
-0.2
-0.3 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-010
Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off
0.4 0.3 0.2 0.1
ERROR (%)
Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off
0.6 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE
25C, PF = 1
GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE -40C, PF = 1
0.4
0.2
ERROR (%)
85C, PF = 0.5 25C, PF = 1
0 -0.1 -0.2 -0.3 -0.4 0.1 85C, PF = 1
0
-0.2
-40C, PF = 0.5 25C, PF = 0.5
-0.4
1 10 FULL-SCALE CURRENT (%)
100
02875-0-008
-0.6 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-011
Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off
0.8 0.6 -40C, PF = 0.5 0.4
ERROR (%)
Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off
0.5 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 25C, PF = 0
GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE
0.4 0.3 0.2
25C, PF = 0
ERROR (%)
0.2 0 -0.2
0.1 0 40C, PF = 0.5 -0.1 -0.2 -0.3 -0.4 +85C, PF = 0.5 25C, PF = 0.5
25C, PF = 0.5 85C, PF = 0.5
-0.4 -0.6 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-009
-0.5 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-012
Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off
Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off
Rev. 0 | Page 10 of 48
ADE7753
0.5 0.4 0.3 0.2 25C, PF = 0
ERROR (%) ERROR (%)
0.35 GAIN = 1 INTEGRATOR OFF EXTERNAL REFERENCE 0.25 0.15 25C, PF = 0 0.05 -0.05 -0.15 -0.25 85C, PF = 0 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE
0.1 0 25C, PF = 0.5 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 FULL-SCALE CURRENT (%) 100
02875-0-013
+85C, PF = 0.5 40C, PF = 0.5
-40C, PF = 0
-0.35 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-016
Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Temperature with External Reference and Integrator Off
0.20 0.15 -40C, PF = 0 0.10 0.05
ERROR (%)
Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off
0.5 0.4 0.3 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE
25C, PF = 0
0 -0.05 -0.10 -0.15 -0.20 0.1 85C, PF = 0
ERROR (%)
GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -40C, PF = 0.5 85C, PF = 0.5 25C, PF = 0.5
25C, PF = 0
1 10 FULL-SCALE CURRENT (%)
100
02875-0-014
-0.5 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-017
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off
0.3 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE -40C, PF = 0.5 25C, PF = 0 0
Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off
0.3
0.2
0.2 5.25V 0.1
ERROR (%)
0.1
ERROR (%)
GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE
0 5.0V -0.1 4.75V
-0.1 85C, PF = 0.5 -0.2 25C, PF = 0.5
-0.2
-0.3 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-015
-0.3 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-018
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator Off
Rev. 0 | Page 11 of 48
ADE7753
0.1 0.8 0.6 0.4
ERROR (%)
1.0 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.8 0.6 0.4 25C, PF = 0.5
ERROR (%)
-40C, PF = 0.5
GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE
PF = 1
0.2 0 -0.2 -0.4 -0.6 -0.8 -0.1 45 50 55 LINE FREQUENCY (Hz) 60 100
02875-0-019
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 1 10 FULL-SCALE CURRENT (%) 100
02875-0-022
25C, PF = 1
PF = 0.5
85C, PF = 0.5
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with External Reference and Integrator Off
0.5 0.4 0.3 0.2
ERROR (%)
Figure 21. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On
1.0 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE -40C, PF = 1
GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE
0.8 0.6 0.4
ERROR (%)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 PF = 0.5
PF = 1
0.2 0 -0.2 -0.4 -0.6 -0.8 85C, PF = 1 25C, PF = 1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-020
-1.0 0.1
1 10 FULL-SCALE CURRENT (%)
100
02875-0-023
Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator Off
1.0 0.8 0.6 0.4
ERROR (%)
Figure 22. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator On
1.0 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE
GAIN = 1 EXTERNAL REFERENCE
0.8 0.6 0.4
ERROR (%)
-40C, PF = 0.5
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.01 0.1 FULL-SCALE VOLTAGE 1
02875-0-021
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 25C, PF = 0
85C, PF = 0.5
25C, PF = 0.5
1 10 FULL-SCALE CURRENT (%)
100
02875-0-024
Figure 20. VRMS Error as a Percentage of Reading (Gain = 1) with External Reference
Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On
Rev. 0 | Page 12 of 48
ADE7753
1.0 0.8 0.6 0.4
ERROR (%)
0.5 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE -40C, PF = 0 0.4 0.3 0.2
ERROR (%)
GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE PF = 1
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 1 10 FULL-SCALE CURRENT (%) 100
02875-0-025
0.1 0 -0.1 -0.2 PF = 0.5
25C, PF = 0
85C, PF = 0
-0.3 -0.4 -0.5 0.1 1 10 FULL-SCALE CURRENT (%) 100
02875-0-028
Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On
1.5 GAIN = 8 INTEGRATOR ON EXTERNAL REFERENCE
Figure 27. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator On
0.8 0.6 0.4 GAIN = 1 EXTERNAL REFERENCE
1.0
0.5
ERROR (%)
PF = 0.5
0.2
ERROR (%)
0 PF = 1
0 -0.2 -0.4
-0.5
-1.0
-0.6
-1.5 45
50
55 LINE FREQUENCY (Hz)
60
100
02875-0-026
-0.8
1
10 FULL-SCALE VOLTAGE
100
02875-0-029
Figure 25. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator On
0.3
Figure 28.VRMS Error as a Percentage of Reading (Gain = 1) with External Reference
0.2 5.25V 0.1
ERROR (%)
8
GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE
HITS
6
0 5.0V -0.1 4.75V -0.2
4
2
-0.3 0.1
0
1 10 FULL-SCALE CURRENT (%)
100
02875-0-027
-15
-12
0 -9 -6 -3 CH1 OFFSET (0p5V_1X) (mV)
3
6
02875-0-087
Figure 26. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator On
Figure 29. Channel 1 Offset (Gain = 1)
Rev. 0 | Page 13 of 48
ADE7753
VDD 10F di/dt CURRENT SENSOR 100 1k 33nF 100 33nF 33nF 1k 33nF 100nF AVDD V1P DVDD 100nF RESET DIN DOUT TO SPI BUS (USED ONLY FOR CALIBRATION) 10F
VDD 10F CURRENT TRANSFORMER 1k RB 33nF 1k 33nF
Y1 3.58MHz 22pF 22pF
I
I
100nF AVDD V1P DVDD
100nF RESET DIN DOUT
10F
V1N
ADE7753
V2N
U1
SCLK CS
V1N
CLKOUT 1k 600k 110V 1k 33nF 33nF V2P CLKIN IRQ SAG REFIN/OUT ZX CF
ADE7753
V2N
U1
SCLK CS
TO SPI BUS (USED ONLY FOR CALIBRATION)
CLKOUT 1k 600k 33nF V2P 33nF CLKIN IRQ SAG REFIN/OUT ZX CF
Y1 3.58MHz 22pF
22pF
NOT CONNECTED U3
110V
1k
NOT CONNECTED U3 TO FREQUENCY COUNTER PS2501-1
10F
100nF
AGND DGND CHANNEL 1 GAIN = 8 CHANNEL 2 GAIN = 1
10F
TO FREQUENCY COUNTER PS2501-1
100nF
AGND DGND CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 1 GAIN 1 (CH1) RB 10 1 1.21 8
02875-0-085
02875-0-030
Figure 30. Test Circuit for Performance Curves with Integrator On Figure 31. Test Circuit for Performance Curves with Integrator Off
Rev. 0 | Page 14 of 48
ADE7753 THEORY OF OPERATION
ANALOG INPUTS
The ADE7753 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are 0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/ V2N are 0.5 V with respect to AGND. Each analog input channel has a PGA (programmable gain amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the gain register--see Figure 33. Bits 0 to 2 select the gain for the PGA in Channel 1, and the gain selection for the PGA in Channel 2 is made via Bits 5 to 7. Figure 32 shows how a gain selection for Channel 1 is made using the gain register.
7 0 6 0 5 0 GAIN[7:0] 4 3 2 0 0 0 1 0 0 0
Table 5. Maximum Input Signal Levels for Channel 1
Max Signal Channel 1 0.5 V 0.25 V 0.125 V 0.0625 V 0.0313 V 0.0156 V 0.00781 V ADC Input Range Selection 0.5 V 0.25 V 0.125 V Gain = 1 - - Gain = 2 Gain = 1 - Gain = 4 Gain = 2 Gain = 1 Gain = 8 Gain = 4 Gain = 2 Gain = 16 Gain = 8 Gain = 4 - Gain = 16 Gain = 8 - - Gain = 16
GAIN REGISTER* CHANNEL 1 AND CHANNEL 2 PGA CONTROL 7 6 5 4 3 2 1 0 0 PGA 2 GAIN SELECT 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 * REGISTER CONTENTS SHOW POWER-ON DEFAULTS 0 0 0 0 0 0 0 ADDR: 0AH
GAIN (K) SELECTION V1P
VIN
K x VIN
PGA 1 GAIN SELECT 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 CHANNEL 1 FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V
02875-0-032
V1N
Figure 33. ADE7753 Analog Gain Register
+
4 0 3 0 2 0 1 0 0 0 OFFSET ADJUST (50mV)
7 0
6 0
5 0
CH1OS[7:0] BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6: NOT USED BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)
02875-0-031
Figure 32. PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register--see Figure 33. As mentioned previously, the maximum differential input voltage is 0.5 V. However, by using Bits 3 and 4 in the gain register, the maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference--see the ADE7753 Reference Circuit section. Table 5 summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections.
It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the offset correction registers (CH1OS and CH2OS, respectively). These registers allow channel offsets in the range 20 mV to 50 mV (depending on the gain setting) to be removed. Note that it is not necessary to perform an offset correction in an energy measurement application if HPF in Channel 1 is switched on. Figure 34 shows the effect of offsets on the real power calculation. As seen from Figure 34, an offset on Channel 1 and Channel 2 will contribute a dc component after multiplication. Since this dc component is extracted by LPF2 to generate the active (real) power information, the offsets will have contributed an error to the active power calculation. This problem is easily avoided by enabling HPF in Channel 1. By removing the offset from at least one channel, no error component is generated at dc by the multiplication. Error terms at cos(t) are removed by LPF2 and by integration of the active power signal in the active energy register (AENERGY[23:0])--see the Energy Calculation section.
Rev. 0 | Page 15 of 48
ADE7753
DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS x IOS Vx I 2
The current and voltage rms offsets can be adjusted with the IRMSOS and VRMSOS registers--see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
IOS x V VOS x I
A di/dt sensor detects changes in magnetic field caused by ac current. Figure 36 shows the principle of a di/dt current sensor.
2
02875-0-033
0
FREQUENCY (RAD/S)
Figure 34. Effect of Channel Offsets on the Real Power Calculation
MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)
The contents of the offset correction registers are 6-bit, sign and magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the offset correction registers. The maximum value that can be written to the offset correction registers is 31d--see Figure 35. Figure 35 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a gain setting of 1. In order to perform an offset adjustment, the analog inputs should be first connected to AGND, and there should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register will indicate the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1 offset register, or an equal value to the Channel 2 offset register. The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF. Table 6. Offset Correction Range--Channels 1 and 2
Gain 1 2 4 8 16 Correctable Span 50 mV 37 mV 30 mV 26 mV 24 mV
CH1OS[5:0] 1Fh
01,1111b
+ EMF (ELECTROMOTIVE FORCE) - INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt)
02875-0-035
Figure 36. Principle of a di/dt Current Sensor
LSB Size 1.61 mV/LSB 1.19 mV/LSB 0.97 mV/LSB 0.84 mV/LSB 0.77 mV/LSB
The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal, which is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up. Setting the MSB of CH1OS register will turn on the integrator. Figure 37 to Figure 40 show the magnitude and phase response of the digital integrator.
10
0
SIGN + 5 BITS
GAIN (dB)
-10
-20
00h -50mV 0mV +50mV OFFSET ADJUST
-30
-40
3Fh
11,1111b SIGN + 5 BITS
02875-0-034
-50
Figure 35. Channel 1 Offset Correction Range (Gain = 1)
102 FREQUENCY (Hz)
103
02875-0-036
Figure 37. Combined Gain Response of the Digital Integrator and Phase Compensator
Rev. 0 | Page 16 of 48
ADE7753
-88.0
-88.5
PHASE (Degrees)
-89.0
-89.5
Note that the integrator has a -20 dB/dec attenuation and approximately -90 phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates significant high frequency noise, therefore a more effective antialiasing filter is needed to avoid noise due to aliasing--see the Antialias Filter section. When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as current transformer (CT) or with a low resistance current shunt.
-90.0
-90.5 102 FREQ FREQUENCY (Hz) 103
02875-0-037
ZERO-CROSSING DETECTION
The ADE7753 has a zero-crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero-crossing signal (ZX), and it is also used in the calibration mode--see the Energy Calibration section. The zero-crossing signal is also used to initiate a temperature measurement on the ADE7753--see the Temperature Measurement section. Figure 41 shows how the zero-crossing signal is generated from the output of LPF1.
x1, x2, x1, x8, x16
V2P V2 V2N
ZERO CROSS
45 50 55 60 FREQUENCY (Hz) 65 70
02875-0-038
Figure 38. Combined Phase Response of the Digital Integrator and Phase Compensator
-1.0 -1.5 -2.0 -2.5
GAIN (dB)
-3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 40
REFERENCE
-63% TO +63% FS
{GAIN [7:5]}
PGA2
ADC 2
1
TO MULTIPLIER
ZX
f-3dB = 140Hz
1.0 0.93 2.32 @ 60Hz ZX
LPF1
Figure 39. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
-89.70 -89.75 -89.80
PHASE (Degrees)
V2
-89.85 -89.90 -89.95 -90.00 -90.05
LPF1
02875-0-040
Figure 41. Zero-Crossing Detection on Channel 2
40
45
50
55 60 FREQUENCY (Hz)
65
70
02875-0-039
Figure 40. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
The ZX signal will go logic high on a positive going zero crossing and logic low on a negative going zero crossing on Channel 2. The zero-crossing signal ZX is generated from the output of LPF1. LPF1 has a single pole at 140 Hz (at CLKIN = 3.579545 MHz). As a result, there will be a phase lag between the analog input signal V2 and the output of LPF1. The phase response of this filter is shown in the Channel 2 Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.14 ms (@ 60 Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX.
Rev. 0 | Page 17 of 48
ADE7753
The zero-crossing detection also drives the ZX flag in the interrupt status register. An active low in the IRQ output will also appear if the corresponding bit in the interrupt enable register is set to Logic 1. The flag in the interrupt status register as well as the IRQ output are reset to their default values when the interrupt status register with reset (RSTSTATUS) is read.
PERIOD MEASUREMENT
The ADE7753 also provides the period measurement of the line. The period register is an unsigned 15-bit register and is updated every period. The resolution of this register is 2.2 ms/LSB when CLKIN = 3.579545 MHz, which represents 0.013% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 7576d. The length of the register enables the measurement of line frequencies as low as 13.9 Hz. The period register is stable at 1 LSB when the line is established and the measurement does not change. A settling time of 1.8 seconds is associated with this filter before the measurement is stable.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full-scale value every time a zero crossing on Channel 2 is detected. The default power on value in this register is FFFh. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0, the SAG pin will go active low. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1. Irrespective of the enable bit setting, the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0--see the ADE7753 Interrupts section. The ZXOUT register can be written/read by the user and has an address of 1Dh--see the Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB. Thus the maximum delay for an interrupt is 0.15 second (128/CLKIN x 212). Figure 42 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/128 x ZXTOUT seconds.
12-BIT INTERNAL REGISTER VALUE ZXTOUT
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply monitor. The analog supply (AVDD) is continuously monitored by the ADE7753. If the supply is less than 4 V 5%, then the ADE7753 will go into an inactive state, i.e., no energy will be accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity to false triggering due to noisy supplies.
AVDD 5V 4V
0V
TIME
ADE7753 POWER-ON INACTIVE INACTIVE STATE
ACTIVE
INACTIVE
CHANNEL 2
SAG
02875-0-042
ZXTO DETECTION BIT
02875-0-041
Figure 43. On-Chip Power Supply Monitor
Figure 42. Zero-Crossing Timeout Detection
As seen from Figure 43, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about 5%. The SAG pin can also be used as a power supply monitor input to the MCU. The SAG pin will go logic low when the ADE7753 is in its inactive state. The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V 5%, as specified for normal operation.
Rev. 0 | Page 18 of 48
ADE7753
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 44.
CHANNEL 2
PEAK DETECTION
The ADE7753 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 45 illustrates the behavior of the peak detection for the voltage channel.
V2 VPKLVL[7:0]
FULL SCALE SAGLVL [7:0]
PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ
SAG RESET HIGH WHEN CHANNEL 2 EXCEEDS SAGLVL [7:0] SAGCYC [7:0] = 04H 3 LINE CYCLES
PKV INTERRUPT FLAG (BIT 8 OF STATUS REGISTER) READ RSTSTATUS REGISTER
02875-0-088
SAG
02875-0-043
Figure 45. ADE7753 Peak Level Detection
Figure 44. ADE7753 Sag Detection
Both Channel 1 and Channel 2 are monitored at the same time. Figure 45 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[7:0]). The voltage peak event is recorded by setting the PKV flag in the interrupt status register. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output will go active low. Similarly, the current peak event is recorded by setting the PKI flag in the interrupt status register--see the ADE7753 Interrupts section.
Figure 44 shows the line voltage falling below a threshold that is set in the sag level register (SAGLVL[7:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the sag cycle (SAGCYC[7:0]) contains 04h, the SAG pin will go active low at the end of the third line cycle for which the line voltage (Channel 2 signal) falls below the threshold, if the DISSAG bit in the mode register is Logic 0. As is the case when zero crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the interrupt status register. If the SAG enable bit is set to Logic 1, the IRQ logic output will go active low--see the ADE7753 Interrupts section. The SAG pin will go logic high again when the absolute value of the signal on Channel 2 exceeds the sag level set in the sag level register. This is shown in Figure 44 when the SAG pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of Channel 1 and Channel 2 after they are multiplied by 2.Thus, for example, the nominal maximum code from the Channel 1 ADC with a fullscale signal is 2851ECh--see the Channel 1 Sampling section. Multiplying by 2 will give 50A3D8h. Therefore, writing 50h to the IPKLVL register, for example, will put the Channel 1 peak detection level at full scale and set the current peak detection to its least sensitive value. Writing 00h will put the Channel 1 detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1 sample. The IRQ pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register (IRQEN[15:0]) at Address 0Ah.
Sag Level Set
The contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit, thus, for example, the nominal maximum code from LPF1 with a full-scale signal on Channel 2 is 2518h--see the Channel 2 Sampling section. Shifting one bit left will give 4A30h. Therefore writing 4Ah to the SAG level register will put the sag detection level at full scale. Writing 00h or 01h will put the sag detection level at 0. The SAG level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.
Peak Level Record
The ADE7753 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers--IPEAK and VPEAK, respectively. VPEAK and IPEAK are 24-bit unsigned registers. These registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register corresponds to 2 times the maximum absolute value observed on the Channel 2
Rev. 0 | Page 19 of 48
ADE7753
input. The contents of IPEAK represents the maximum absolute value observed on the Channel 1 input. Reading the RSTVPEAK and RSTIPEAK registers will clear their respective contents after the read operation. again to indicate the pending interrupt. See the next section for a more detailed description.
Using the ADE7753 Interrupts with an MCU
Figure 47 shows a timing diagram that shows a suggested implementation of ADE7753 interrupt management using an MCU. At time t1, the IRQ line will go active low indicating that one or more interrupt events have occurred in the ADE7753. The IRQ logic output should be tied to a negative edgetriggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled by using the global interrupt enable bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the status register with reset is carried out. This will cause the IRQ line to be reset logic high (t2)--see the Interrupt Timing section. The status register contents are used to determine the source of the interrupt(s) and therefore the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR, that event will be recorded by the MCU external interrupt flag being set again (t3). On returning from the ISR, the global interrupt mask will be cleared (same instruction cycle) and the external interrupt flag will cause the MCU to jump to its ISR once a gain. This will ensure that the MCU does not miss any external interrupts.
ADE7753 INTERRUPTS
ADE7753 interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs in the ADE7753, the corresponding flag in the status register is set to Logic 1-- see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, then the IRQ logic output goes active low. The flag bits in the status register are set irrespective of the state of the enable bits. To determine the source of the interrupt, the system master (MCU) should perform a read from the status register with reset (RSTSTATUS[15:0]). This is achieved by carrying out a read from Address 0Ch. The IRQ output will go logic high on completion of the interrupt status register read command--see the Interrupt Timing section. When carrying out a read with reset, the ADE7753 is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the status register is being read, the event will not be lost and the IRQ logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low
t1
IRQ
t2
t3
MCU INTERRUPT FLAG SET
MCU PROGRAM SEQUENCE
JUMP TO ISR
GLOBAL INTERRUPT MASK SET
CLEAR MCU INTERRUPT FLAG
READ STATUS WITH RESET (05h)
ISR ACTION (BASED ON STATUS CONTENTS)
ISR RETURN GLOBAL INTERRUPT MASK RESET
JUMP TO ISR
02875-0-044
Figure 46. ADE7753 Interrupt Management
CS
t1
SCLK
t9
DIN
0
0
0
0
0
1
0
1
t11
DOUT
t11
DB7 DB0 DB7 STATUS REGISTER CONTENTS DB0
READ STATUS REGISTER COMMAND
IRQ
02875-0-045
Figure 47. ADE7753 Interrupt Timing
Rev. 0 | Page 20 of 48
ADE7753
Interrupt Timing
The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)--see Figure 46. If an interrupt is pending at this time, the IRQ output will go low again. If no interrupt is pending, the IRQ output will stay high.
clock. In the ADE7753, the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and therefore the bit stream) will approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged will a meaningful result be obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the lowpass filter can produce 24-bit data-words that are proportional to the input signal level. The - converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7753 is CLKIN/4 (894 kHz) and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered--see Figure 49. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the - modulator, the noise is shaped by the integrator, which has a high-pass type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 49.
DIGITAL FILTER ANTILALIAS FILTER (RC) SHAPED NOISE SAMPLING FREQUENCY
TEMPERATURE MEASUREMENT
The ADE7753 also includes an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7753 will initiate a temperature measurement on the next zero crossing. When the zero crossing on Channel 2 is detected, the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. The resulting code is processed and placed in the temperature register (TEMP[7:0]) approximately 26 s later (24 CLKIN cycles). If enabled in the interrupt enable register (Bit 5), the IRQ output will go active low when the temperature conversion is finished. The contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 LSB/C. The temperature register will produce a code of 00h when the ambient temperature is approximately 70C. The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance that could be as high as 20C.
ADE7753 ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried out using two second order - ADCs. For simplicity, the block diagram in Figure 48 shows a first order - ADC. The converter is made up of two parts: the - modulator and the digital low-pass filter.
MCLK/4
SIGNAL
ANALOG LOW-PASS FILTER R C
+ -
NOISE
DIGITAL LOW-PASS FILTER 24
INTEGRATOR
+
LATCHED COMPARATOR
0
2
447 FREQUENCY (kHz)
894
VREF
-
SIGNAL
.....10100101.....
HIGH RESOLUTION OUTPUT FROM DIGITAL LPF
1-BIT DAC
02875-0-046
NOISE
Figure 48. First Order - ADC
0
2
447 FREQUENCY (kHz)
894
02875-0-047
A - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling
Rev. 0 | Page 21 of 48
Figure 49. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
ADE7753
Antialias Filter
Figure 48 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing. Aliasing is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC will appear in the sampled signal at a frequency below half the sampling rate. Figure 50 illustrates the effect. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency, i.e., 447 kHz) get imaged or folded back down below 447 kHz. This will happen with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 894 kHz, will move into the band of interest for metering, i.e., 40 Hz to 2 kHz. This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 900 kHz) noise, and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz will produce an attenuation of approximately 40 dB at 894 kHz--see Figure 50. The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This will neutralize the -20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the -40 dB per decade attenuation needed.
ALIASING EFFECTS
ADE7753 Reference Circuit
Figure 51 shows a simplified version of the reference output circuitry. The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7753. However, Channel 1 has three input range selections that are selected by dividing down the reference value used for the ADC in Channel 1. The reference value used for Channel 1 is divided down to 1/2 and 1/4 of the nominal value by using an internal resistor divider, as shown in Figure 51.
MAXIMUM LOAD = 10A OUTPUT IMPEDANCE 6k REFIN/OUT 2.42V
PTAT
60A
2.5V 1.7k
12.5k 12.5k 12.5k 12.5k
REFERENCE INPUT TO ADC CHANNEL 1 (RANGE SELECT) 2.42V, 1.21V, 0.6V
02875-0-049
Figure 51. ADE7753 Reference Circuit Output
The REFIN/OUT pin can be overdriven by an external source, e.g., an external 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V, not 2.42 V, which has the effect of increasing the nominal analog input signal range by 2.5/2.42 x 100% = 3% or from 0.5 V to 0.5165 V. The voltage of ADE7753 reference drifts slightly with temperature--see the ADE7753 Specifications for the temperature coefficient specification (in ppm/C). The value of the temperature drift varies from part to part. Since the reference is used for the ADCs in both Channels 1 and 2, any x% drift in the reference will result in 2x% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. However, if guaranteed temperature performance is needed, one needs to use an external voltage reference. Alternatively, the meter can be calibrated at multiple temperatures. Real-time compensation can be achieved easily by usingthe on-chip temperature sensor.
IMAGE FREQUENCIES
SAMPLING FREQUENCY
0
2
447 FREQUENCY (kHz)
894
02875-0-048
Figure 50. ADC and Signal Processing in Channel 1 Outline Dimensions
ADC Transfer Function
The following expression relates the output of the LPF in the - ADC to the analog input signal level. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level.
CHANNEL 1 ADC
(1)
Figure 52 shows the ADC and signal processing chain for Channel 1. In waveform sampling mode, the ADC outputs a signed twos complement 24-bit data-word at a maximum of 27.9 kSPS (CLKIN/128). With the specified full-scale analog input signal of 0.5 V (or 0.25 V or 0.125 V--see the Analog Inputs section) the ADC will produce an output code that is approximately between 2851ECh (+2,642,412d) and D7AE14h (-2,642,412d)--see Figure 52.
Code ( ADC ) = 3.0492 x
VIN x 262,144 VOUT
Therefore with a full-scale signal on the input of 0.5 V and an internal reference of 2.42 V, the ADC output code is nominally 165,151 or 2851Fh. The maximum code from the ADC is 262,144; this is equivalent to an input signal level of 0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.5 V not be exceeded.
Rev. 0 | Page 22 of 48
ADE7753
2.42V, 1.21V, 0.6V x1, x2, x4, REFERENCE x8, x16 {GAIN[2:0]}
PGA1 V1N 50Hz
1EF73Ch
{GAIN[4:3]}
CURRENT RMS (IRMS) CALCULATION
V1P V1
HPF
DIGITAL INTEGRATOR*
WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION
CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz)
ADC 1
V1 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV, 15.6mV,
0V
2851ECh 00000h D7AE4h
CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE
2851ECh
000000h EI08C4h
ANALOG INPUT RANGE
ADC OUTPUT WORD RANGE
000000h D7AE4h
60Hz
CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (60Hz)
19CE08h 000000h
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
E631F8h
02875-0-052
Figure 52. ADC and Signal Processing in Channel 1
Channel 1 Sampling
The waveform samples may also be routed to the waveform register (MODE[14:13] = 1,0) to be read by the system master (MCU). In waveform sampling mode, the WSMP bit (Bit 3) in the interrupt enable register must also be set to Logic 1. The active, apparent power, and energy calculation will remain uninterrupted during waveform sampling. When in waveform sample mode, one of four output sample rates may be chosen by using Bits 11 and 12 of the mode register (WAVSEL1,0). The output sample rate may be 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS--see the Mode Register section. The interrupt request output, IRQ, signals a new sample availability by going active low. The timing is shown in Figure 53. The 24-bit waveform samples are transferred from the ADE7753 one byte (eight bits) at a time, with the most significant byte shifted out first. The 24-bit data-word is right justified--see the ADE7753 Serial Interface section. The interrupt request output IRQ stays low until the interrupt routine reads the reset status register--see the ADE7753 Interrupt section.
IRQ SCLK DIN DOUT READ FROM WAVEFORM 0 0 0 01 HEX SIGN CHANNEL 1 DATA (24 BITS)
02875-0-050
Channel 1 RMS Calculation
Root mean square (RMS) value of a continuous signal V(t) is defined as
Vrms =
1 x V 2 (t ) dt T
T
0
(2)
For time sampling signals, RMS calculation involves squaring the signal, taking the average and obtaining the square root:
Vrms =
1 x N
V
i =1
N
2
(i )
(3)
ADE7753 calculates simultaneously the RMS values for Channel 1 and Channel 2 in different register. Figure 54 shows the detail of the signal processing chain for the RMS calculation on Channel 1. The Channel 1 RMS value is processed from the samples used in the Channel 1 waveform sampling mode. The Channel 1 RMS value is stored in an unsigned 24-bit register (IRMS). One LSB of the Channel 1 RMS register is equivalent to one LSB of a Channel 1 waveform sample. The update rate of the Channel 1 RMS measurement is CLKIN/4.
Figure 53. Waveform Sampling Channel 1
Rev. 0 | Page 23 of 48
ADE7753
CURRENT SIGNAL (i(t))
2851ECh 00h D7AE14h
IRMSOS[11:0] sgn 225 226 227
IRMS(t)
HPF1 CHANNEL 1
24
LPF3
217 216 215 1C82B3h 00h
24
+
IRMS
02875-0-0051
Figure 54. Channel 1 RMS Signal Processing
With the specified full-scale analog input signal of 0.5 V, the ADC will produce an output code that is approximately 2,642,412d--see the Channel 1 ADC section. The equivalent RMS values of a full-scale ac signal are 1,868,467d (1C82B3h). The current RMS measurement provided in the ADE7753 is accurate to within 1% for signal input between full scale and full scale/100. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant. To minimize noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings.
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] = 1,1 and WSMP = 1), the ADC output code scaling for Channel 2 is not the same as Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. For normal operation, the differential voltage signal between V2P and V2N should not exceed 0.5 V. With maximum voltage input (0.5 V at PGA gain of 1), the output from the ADC swings between 2852h and D7AEh (10,322d). However, before being passed to the waveform register, the ADC output is passed through a single-pole, low-pass filter with a cutoff frequency of 140 Hz. The plots in Figure 55 show the magnitude and phase response of this filter.
0 -10 -20
PHASE (Degrees)
Channel 1 RMS Offset Compensation
The ADE7753 incorporates a Channel 1 RMS offset compensation register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 1 RMS calculation. An offset may exist in the RMS calculation due to input noises that are integrated in the dc component of V2(t). The offset calibration will allow the content of the IRMS register to be maintained at 0 when no input is present on Channel 1. One LSB of the Channel 1 RMS offset is equivalent to 32,768 LSB of the square of the Channel 1 RMS register. Assuming that the maximum value from the Channel 1 RMS calculation is 1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1 RMS offset represents 0.46% of measurement error at -60 dB down of full scale.
60Hz, -0.73dB 50Hz, -0.52dB
0
-2 -4
-30 -40 -50 -60 -70 -80 -90 101
50Hz, -19.7
-6 -8 -10 -12 -14 -16
GAIN (dB)
60Hz, -23.2
I rms = I rms 0 2 + IRMSOS x 32768
(4)
102 FREUENCY (HzQ)
-18 103
02875-0-053
where IRMS0 is the RMS measurement without offset correction. To measure the offset of the RMS measurement, two data points are needed from non-zero input values, for example, the base current, Ib, and Imax/100. The offset can be calculated from these measurements.
Figure 55. Magnitude and Phase Response of LPF1
The LPF1 has the effect of attenuating the signal. For example, if the line frequency is 60 Hz, then the signal at the output of LPF1 will be attenuated by about 8%.
H( f ) =
1 60 Hz 1+ 140 Hz
2
= 0.919 = -0.73 dB
(5)
Note LPF1 does not affect the active power calculation. The signal processing chain in Channel 2 is illustrated in Figure 56.
Rev. 0 | Page 24 of 48
ADE7753
2.42V x1, x2, x4, REFERENCE x8, x16 {GAIN [7:5]}
PGA2
ADC 2
V2P V2 V2N
ANALOG V1 INPUT RANGE 0.5V, 0.25, 0.125, 62.5mV, 31.25mV 0V
LPF1
ACTIVE AND REACTIVE ENERGY CALCULATION VRMS CALCULATION AND WAVEFORM SAMPLING (PEAK/SAG/ZX)
2852h 2581h 0000h DAE8h D7AEh
LPF OUTPUT WORD RANGE
02875-0-054
Figure 56. ADC and Signal Processing in Channel 2
VOLTAGE SIGNAL (V(t))
2518h 0h DAE8h
VRMOS[11:0] sgn 29 28 22 21 20
VRMS[23:0]
00h
02875-0-0055
LPF1 CHANNEL 2
LPF3
+
+
17D338h
Figure 57. Channel 2 RMS Signal Processing
Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections of 1, 2, 4, 8, and 16. For energy measurement, the output of the ADC is passed directly to the multiplier and is not filtered. An HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. When in waveform sample mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register. The available output sample rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS--see the Mode Register section. The interrupt request output IRQ signals that a sample is available by going active low. The timing is the same as that for Channel 1, as shown in Figure 53.
(17D338h) in the VRMS register. The voltage RMS measurement provided in the ADE7753 is accurate to within 0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a volts/LSB constant. Since the low-pass filtering used for calculating the RMS value is imperfect, there is some ripple noise from 2 term present in the RMS measurement. To minimize the noise effect in the reading, synchronize the RMS reading with the zero crossings of the voltage input.
Channel 2 RMS Offset Compensation
The ADE7753 incorporates a Channel 2 RMS offset compensation register (VRMSOS). This is a 12-bit signed registers that can be used to remove offset in the Channel 2 RMS calculation. An offset may exist in the RMS calculation due to input noises and dc offset in the input samples. The offset calibration allows the contents of the VRMS register to be maintained at 0 when no voltage is applied. One LSB of the Channel 2 RMS offset is equivalent to one LSB of the RMS register. Assuming that the maximum value from the Channel 2 RMS calculation is 1,561,400d with full-scale ac inputs, then one LSB of the Channel 2 RMS offset represents 0.064% of measurement error at -60 dB down of full scale.
Channel 2 RMS Calculation
Figure 57 shows the details of the signal processing chain for the RMS calculation on Channel 2. The Channel 2 RMS value is processed from the samples used in the Channel 2 waveform sampling mode. The RMS value will be slightly attenuated because of LPF1. Channel 2 RMS value is stored in the unsigned 24-bit VRMS register. The update rate of the Channel 2 RMS measurement is CLKIN/4. With the specified full-scale ac analog input signal of 0.5 V, the output from the LPF1 swings between 2518h and DAE8h at 60 Hz--see the Channel 2 ADC section. The equivalent RMS value of this full-scale ac signal is approximately 1,561,400
Vrms = Vrmso + VRMSOS
(6)
Rev. 0 | Page 25 of 48
ADE7753
where Vrmso is the RMS measurement without offset correction. The voltage RMS offset compensation should be done by testing the RMS results at two non-zero input levels. One measurement can be done close to full scale and the other at approximately full scale/10. The voltage offset compensation can be derived from these measurements. If the voltage RMS offset register does not have enough range, the CH2OS register can also be used.
V1P V1 V1N
24
HPF
PGA1
ADC 1
24
LPF2
V2P V2 V2N
PGA2
ADC 2
1
DELAY BLOCK 4.48s/LSB
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1 and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled, Channel 1 has a phase response illustrated in Figure 59 and Figure 60. Also shown in Figure 61 is the magnitude response of the filter. As can be seen from the plots, the phase response is almost 0 from 45 Hz to 1 kHz. This is all that is required in typical energy measurement applications. However, despite being internally phase compensated, the ADE7753 must work with transducers, which may have inherent phase errors. For example, a phase error of 0.1 to 0.3 is not uncommon for a CT (current transformer). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7753 provides a means of digitally calibrating these small phase errors. The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1 to 0.5. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. The phase calibration register (PHCAL[5:0]) is a twos complement signed single-byte register that has values ranging from 21h (-31d) to 1Fh (31d). The register is centered at 0Dh, so that writing 0Dh to the register gives 0 delay. By changing the PHCAL register, the time delay in the Channel 2 signal path can change from -102.12 s to +39.96 s (CLKIN = 3.579545 MHz). One LSB is equivalent to 2.22 s (CLKIN/8) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.048 at the fundamental (i.e., 360 x 2.22 s x 60 Hz). Figure 58 illustrates how the phase compensation is used to remove a 0.1 phase lead in Channel 1 due to the external transducer. To cancel the lead (0.1) in Channel 1, a phase lead must also be introduced into Channel 2. The resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.048. The phase lead is achieved by introducing a time advance into Channel 2. A time advance of 4.48 s is made by writing -2 (0Bh) to the time delay block, thus reducing the amount of time delay by 4.48 s, or equivalently, a phase lead of approximately 0.1 at line frequency of 60 Hz. 0Bh represents -2 because the register is centered with 0 at 0Dh.
V2
5
0
001011
0.1
PHCAL [5:0] --100s TO +34s
CHANNEL 2 DELAY REDUCED BY 4.48s (0.1LEAD AT 60Hz) 0Bh IN PHCAL [5.0] V2 V1
V1
60Hz
60Hz
02875-0-056
Figure 58. Phase Calibration
0.9 0.8 0.7
PHASE (Degrees)
0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1
102 103 104
02875-0-057
FREQUENCY (Hz)
Figure 59. Combined Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz)
0.20 0.18 0.16 0.14
PHASE (Degrees)
0.12 0.10 0.08 0.06 0.04 0.02 0 40 45 50 55 60 FREQUENCY (Hz) 65 70
02875-0-058
Figure 60. Combined Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz)
Rev. 0 | Page 26 of 48
ADE7753
0.4 0.3 0.2 0.1 0.0
The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 62.
19999Ah INSTANTANEOUS POWER SIGNAL p(t) = vxi-vxixcos(2t) ACTIVE REAL POWER SIGNAL = v x i
ERROR (%)
-0.1 -0.2 -0.3 -0.4 54
VI CCCCDh
56 58 60 62 FREQUENCY (Hz) 64 66
02875-0-059
Figure 61. Combined Gain Response of the HPF and Phase Compensation
00000h CURRENT i(t) = 2xixsin(t)
VOLTAGE v(t) = 2xvxsin(t)
02875-0-060
ACTIVE POWER CALCULATION
Power is defined as the rate of energy flow from source to load. It is defined as the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 9 gives an expression for the instantaneous power signal in an ac system.
Figure 62. Active Power Calculation
v (t ) = 2 xV sin(t ) i (t ) = 2 xV sin(t )
where: V is the RMS voltage. I is the RMS current.
(7) (8)
Since LPF2 does not have an ideal "brick wall" frequency response--see Figure 63, the active power signal will have some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Since the ripple is sinusoidal in nature, it will be removed when the active power signal is integrated to calculate energy--see the Energy Calculation section.
0
-4
p (t ) = v ( t ) x i (t ) p (t ) = VI - VI cos(t )
The average power over an integral number of line cycles (n) is given by the expression in Equation 10. (9)
dB
-8
-12
-16
1 P= nT
where:
nT
0
p (t ) dt = VI
(10)
-20
-24
T is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 8, i.e., VI. This is the relationship used to calculate active power in the ADE7753.
1
3
10 FREQUENCY (Hz)
30
100
02875-0-061
Figure 63. Frequency Response of LPF2
Rev. 0 | Page 27 of 48
ADE7753
CURRENT CHANNEL
APOS[15:0]
LPF2
+ +
WDIV[7:0]
23
%
AENERGY [23:0]
0
UPPER 24 BITS ARE ACCESSIBLE THROUGH AENERGY[23:0] REGISTER
VOLTAGE CHANNEL
ACTIVE POWER SIGNAL = P*
WGAIN[11:0]
48
0
T
OUTPUT LPF2
4 CLKIN
WAVEFORM REGISTER VALUES
OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER
TIME (nT)
02875-0-063
Figure 64. ADE7753 Active Energy Calculation
Figure 64 shows the signal processing chain for the active power calculation in the ADE7753. As explained, the active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register:
ACTIVE POWER OUTPUT
13333h CCCDh 6666h 00000h F999Ah F3333h ECCCDh 000h 7FFh {WGAIN[11:0]} ACTIVE POWER CALIBRATION RANGE
02875-0-062
POSITIVE POWER
NEGATIVE POWER 800h
WGAIN Output WGAIN = Active Power x 1 + 212
(11)
For example, when 7FFh is written to the watt gain register, the power output is scaled up by 50%. 7FFh = 2047d, 2047/212 = 0.5. Similarly, 800h = -2048d (signed twos complement) and power output is scaled by -50%. Each LSB scales the power output by 0.0244%. Figure 65 shows the maximum code (in hex) output range for the active power signal (LPF2). Note that the output range changes depending on the contents of the watt gain register. The minimum output range is given when the watt gain register contents are equal to 800h, and the maximum range is given by writing 7FFh to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7753.
Figure 65. Active Power Calculation Output Range
Energy Calculation
As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 12.
P=
where:
dE dt
(12)
P is power. E is energy. Conversely, energy is given as the integral of power.
E = Pdt
(13)
Rev. 0 | Page 28 of 48
ADE7753
APOS [15:0] sgn 26 25 2-6 2-7 2-8
HPF
24
FOR WAVEF0RM SAMPLING
I
CURRENT SIGNAL - i(t)
MULTIPLIER
19999h
LPF2
24
+
+
32
FOR WAVEFORM ACCUMULATIOIN
CCCCDh
V
1
VOLTAGE SIGNAL- v(t)
INSTANTANEOUS POWER SIGNAL - p(t) 19999Ah
WGAIN[11:0]
000000h
02875-0-064
Figure 66. Active Power Signal Processing
The ADE7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal non-readable 49-bit energy register. The active energy register (AENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 14 expresses the relationship.
waveform register by setting MODE[14:13] = 0,0 and setting the WSMP bit (Bit 3) in the interrupt enable register to 1. Like the Channel 1 and Channel 2 waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS--see Figure 53. Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 7FFh, 000h, and 800h. The watt gain register is used to carry out power calibration in the ADE7753. As shown, the fastest integration time will occur when the watt gain register is set to maximum full scale, i.e., 7FFh.
AENERGY [23:0] 7F,FFFFh WGAIN = 7FFh WGAIN = 000h WGAIN = 800h
E = p (t )dt = Lim p (nT ) x T t 0 n =1
where: n is the discrete time sample number. T is the sample period.
(14)
The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1s (4/CLKIN). As well as calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 66 shows this discrete time integration or accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. This addition is a signed addition; therefore negative energy will be subtracted from the active energy contents. The exception to this is when POAM is selected in the MODE[15:0] register. In this case, only positive energy contributes to the active energy accumulation--see the Positive-Only Accumulation Mode section. The output of the multiplier is divided by WDIV. If the value in the WDIV register is equal to 0, then the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (AENERGY[23:0]). A read to the RAENERGY register will return the content of the AENERGY register and the upper 24 bits of the internal register are cleared. As shown in Figure 66, the active power signal is accumulated in an internal 49-bit signed register. The active power signal can be read from the
3F,FFFFh
00,0000h
4 6.2
8
12.5
TIME (minutes)
40,0000h
80,0000h
02875-0-065
Figure 67. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain)
Note that the energy register contents will roll over to full-scale negative (800000h) and continue increasing in value when the power or energy flow is positive--see Figure 67. Conversely, if the power is negative, the energy register would underflow to full-scale positive (7FFFFFh) and continue decreasing in value.
Rev. 0 | Page 29 of 48
ADE7753
By using the interrupt enable register, the ADE7753 can be configured to issue an interrupt (IRQ) when the active energy register is half-full (positive or negative) or when an overflow or underflow occurs.
provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 68 illustrates the energyto-frequency conversion in the ADE7753.
11 CFNUM[11:0] 0
Integration Time under Steady Load
As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 s (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the WGAIN register set to 000h, the average word value from each LPF2 is CCCCDh--see Figure 62. The maximum positive value that can be stored in the internal 49-bit register is 248 or FFFF,FFFF,FFFFh before it overflows. The integration time under these conditions with WDIV = 0 is calculated as follows:
Time = FFFF, FFFF, FFFFh x1.12s = 375.8s = 6.26min CCCCDh
DFC
48 AENERGY[48:0] 0
%
CF
11
CFDEN[11:0]
0
02875-0-066
Figure 68. ADE7753 Energy-to-Frequency Conversion
(15)
When WDIV is set to a value different from 0, the integration time varies, as shown on Equation 16.
A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power. The maximum output frequency, with ac input signals at full scale and CFNUM = 00h and CFDEN = 00h, is approximately 23 kHz. The ADE7753 incorporates two registers, CFNUM[11:0] and CFDEN[11:0], to set the CF frequency. These are unsigned 12-bit registers, which can be used to adjust the CF frequency to a wide range of values. These frequency-scaling registers are 12-bit registers, which can scale the output frequency by 1/212 to 1 with a step of 1/212. If the value 0 is written to any of these registers, the value 1 would be applied to the register. The ratio (CFNUM + 1)/ (CFDEN + 1) should be smaller than 1 to ensure proper operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the register values would be adjusted to a ratio (CFNUM + 1)/(CFDEN + 1) of 1. For example, if the output frequency is 1.562 kHz while the contents of CFDEN are 0 (000h), then the output frequency can be set to 6.1 Hz by writing FFh to the CFDEN register. The output frequency will have a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal--see the Active Power Calculation section. Equation 8 gives an expression for the instantaneous power signal. This is filtered by LPF2 which has a magnitude response given by Equation 17.
Time = TimeWDIV =0 x WDIV
(16)
Power Offset Calibration
The ADE7753 also incorporates an active power offset register (APOS[15:0]). This is a signed twos complement 16-bit register that can be used to remove offsets in the active power calculation--see Figure 66. An offset may exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration will allow the contents of the active power register to be maintained at 0 when no power is being consumed. The 256 LSBs (APOS = 0100h) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is CCCCDh (838,861d) when inputs on Channels 1 and 2 are both at full- cale. At -60 dB down on Channel 1 (1/1000 of the Channel 1 full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 x 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register, therefore the power offset correction resolution is 0.00047%/LSB (0.119%/256) at -60 dB.
ENERGY-TO-FREQUENCY CONVERSION
ADE7753 also provides energy-to-frequency conversion for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer will often verify the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the energy or active power under steady load conditions. This output frequency can
H( f ) =
1
(17)
f2 1+ 8.9 2
Rev. 0 | Page 30 of 48
ADE7753
The active power signal (output of LPF2 can be rewritten as
VI p (t ) = VI - x cos( 4 f L t ) 2 2 fL 1+ 8.9
where fL is the line frequency, for example, 60 Hz. From Equation 13,
(18)
VI E (t ) = VIt - x sin( 4 f L t ) 2 2 fL 4 f L 1 + 8.9
contribute to the energy calculation over time. However, the ripple can be observed in the frequency output, especially at higher output frequencies. The ripple will get larger as a percentage of the frequency at larger loads and higher output frequencies. The reason is simply that at higher output frequencies the integration or averaging time in the energy-tofrequency conversion process is shorter. As a consequence, some of the sinusoidal ripple is observable in the frequency output. Choosing a lower output frequency at CF for calibration can significantly reduce the ripple. Also, averaging the output frequency by using a longer gate time for the counter will achieve the same results.
E(t) Vlt
(19)
From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin(2t) component. This is shown graphically in Figure 69. The active energy calculation is shown by the dashed straight line and is equal to V x I x t. The sinusoidal ripple in the active energy calculation is also shown. Since the average value of a sinusoid is 0, this ripple will not
-
VI 4xxf1(1+2xf1/8.9Hz )
sin(4xxf1xt)
t
02875-0-067
Figure 69. Output Frequency Ripple
OUTPUT FROM LPF2
%
+
+
48
0
WDIV[7:0] ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LAENERGY REGISTER AT THE END OF LINECYC LINE CYCLES
LPF1 FROM CHANNEL 2 ADC
23
0
LAENERGY [23:0]
ZERO CROSS DETECTION
CALIBRATION CONTROL
LINECYC [15:0]
02875-0-068
Figure 70. Energy Calculation Line Cycle Energy Accumulation Mode
Rev. 0 | Page 31 of 48
ADE7753
LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumulation of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of half line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and in a shorter time because integration period can be shortened. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The ADE7753 is placed in line cycle energy accumulation mode by setting Bit 7 (CYCMODE) in the mode register. In line cycle energy accumulation mode, the ADE7753 accumulates the active power signal in the LAENERGY register (Address 04h) for an integral number of line cycles, as shown in Figure 70. The number of half line cycles is specified in the LINECYC register (Address 1Ch). The ADE7753 can accumulate active power for up to 65,535 half line cycles. Because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumulation cycle the CYCEND flag in the interrupt status register is set (Bit 2). If the CYCEND enable bit in the interrupt enable register is enabled, the IRQ output will also go active low. Thus the IRQ line can also be used to signal the completion of the line cycle energy accumulation. Another calibration cycle will start as long as the CYCMODE bit in the mode register is set. From Equations 13 and 18, Note that in this mode, the 16-bit LINECYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. At 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 seconds.
POSITIVE-ONLY ACCUMULATION MODE
In positive-only accumulation mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no load threshold, as shown in Figure 71. The CF pulse will also reflect this accumulation method when in this mode. The ADE7753 is placed in positiveonly accumulation mode by setting the MSB of the mode register (MODE[15]). The default setting for this mode is off. Transitions in the direction of power flow, going from negative to positive or positive to negative, set the IRQ pin to active low if the interrupt enable register is enabled. The interrupt status registers, PPOS and PNEG, show which transition has occurred--see the ADE7753 register descriptions in Table 10.
ACTIVE ENERGY
NO-LOAD THRESHOLD
VI E (t ) = VI dt - 2 f 0 1+ 8.9
nT
nT x cos( 2 f t ) dt 0
ACTIVE POWER
(20)
NO-LOAD THRESHOLD
IRQ
where: n is a integer. T is the line cycle period. Since the sinusoidal component is integrated over a integer number of line cycles, its value is always 0. Therefore,
PPOS
PNEG
PPOS PNEG PPOS PNEG
02875-0-069
INTERRUPT STATUS REGISTERS
Figure 71. Energy Accumulation in Positive-Only Accumulation Mode
NO LOAD THRESHOLD
The ADE7753 includes a no-load threshold feature on the active energy that will eliminate any creep effects in the meter. The ADE7753 accomplishes this by not accumulating energy if the multiplier output is below the no load threshold. This threshold is 0.001% of the full-scale output frequency of the multiplier. Compare this value to the IEC1036 specification, which states that the meter must start up with a load equal to or less than 0.4% Ib. This standard translates to .0167% of the full-scale output frequency of the multiplier.
E = VIdt + 0
0
nT
(21) (22)
E ( t ) = VInT
Rev. 0 | Page 32 of 48
ADE7753
REACTIVE POWER CALCULATION
Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90. The resulting waveform is called the instantaneous reactive power signal. Equation 25 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90.
v(t ) = 2 V sin( t + ) i (t ) 2 I sin( t )
The average power over an integral number of lines (n) is given in Equation 26.
1 RP = nT
where:
nT
Rp(t ) dt = VI sin( )
0
(26)
(23)
T is the line cycle period. RP is referred to as the reactive power. Note that the reactive power is equal to the dc component of the instantaneous reactive power signal Rp(t) in Equation 25. This is the relationship used to calculate reactive power in the ADE7753. The instantaneous reactive power signal Rp(t) is generated by multiplying Channel 1 and Channel 2. In this case, the phase of Channel 1 is shifted by +90. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter in order to obtain the reactive power information. Figure 72 shows the signal processing in the reactive power calculation in the ADE7753.
i '(t ) = 2 I sin(t + ) 2
where: is the phase difference between the voltage and current channel. V is the RMS voltage. I is the RMS current.
(24)
Rp (t ) = VI sin( ) + VI sin (2t + )
Rp (t ) = v (t ) x i ' (t )
(25)
90 DEGREE PHASE SHIFT
INSTANTANEOUS REACTIVE POWER SIGNAL (Rp(t))
I
2
MULTIPLIER
+
+
49
0
V
LPF1 FROM CHANNEL 2 ADC
23
ZERO CROSSING DETECTION
CALIBRATION CONTROL
0 LVARENERGY [23:0]
ACCUMULATE REACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LVARENERGY REGISTER AT THE END OF LINECYC HALF LINE CYCLES
LINECYC [15:0]
02875-0-070
Figure 72. Reactive Power Signal Processing
Rev. 0 | Page 33 of 48
ADE7753
The features of the line reactive energy accumulation are the same as the line active energy accumulation. The number of half line cycles is specified in the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7753 can accumulate reactive power for up to 65535 combined half cycles. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output will also go active low. Thus the IRQ line can also be used to signal the end of a calibration. The ADE7753 accumulates the reactive power signal in the LVARENERGY register for an integer number of half cycles, as shown in Figure 72.
v(t ) = 2 Vrms sin( t )
i (t ) = 2 I rms sin(t + ) p (t ) = v (t ) x i (t ) p (t ) = Vrms I rms cos( ) - Vrms I rms cos( 2t + )
(27)
(28)
The apparent power is defined as Vrms x Irms. This expression is independent from the phase angle between the current and the voltage. Figure 74 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7753.
IRMS
SIGN OF REACTIVE POWER CALCULATION
Note that the average reactive power is a signed calculation. The phase shift filter has -90 phase shift when the integrator is enabled, and +90 phase shift when the integrator is disabled. Table 7 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. Table 7. Sign of Reactive Power Calculation
Angle Between 0 to 90 Between -90 to 0 Between 0 to 90 Between -90 to 0 Integrator Off Off On On Sign Positive Negative Positive Negative
APPARENT POWER SIGNAL (P)
CURRENT RMS SIGNAL - i(t)
MULTIPLIER
AD055h
1C82B3h 00h
VRMS
VAGAIN
VOLTAGE RMS SIGNAL- v(t)
02875-0-072
17D338h 00h
Figure 74. Apparent Power Signal Processing
APPARENT POWER CALCULATION
The apparent power is defined as the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load; the apparent power (AP) is defined as Vrms x Irms. The angle between the active power and the apparent power generally represents the phase shift due to non-resistive loads. For single-phase applications, represents the angle between the voltage and the current signals--see Figure 73. Equation 28 gives an expression of the instantaneous power signal in an ac system with a phase shift.
APPARENT POWER
REACTIVE POWER
The gain of the apparent energy can be adjusted by using the multiplier and VA gain register (VAGAIN[11:0]). The gain is adjusted by writing a twos complement, 12-bit word to the VA gain register. Equation 29 shows how the gain adjustment is related to the contents of the VA gain register.
VAGAIN OutputVAGAIN = Apparent Power x 1 + (29) 212
For example, when 7FFh is written to the VA gain register, the power output is scaled up by 50%. 7FFh = 2047d, 2047/212 = 0.5. Similarly, 800h = -2047d (signed twos complement) and power output is scaled by -50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage RMS values obtained in the RMS blocks of the ADE7753. Figure 75 shows the maximum code (hexadecimal) output range of the apparent power signal. Note that the output range changes depending on the contents of the apparent power gain registers. The minimum output range is given when the apparent power gain register content is equal to 800h and the maximum range is given by writing 7FFh to the apparent power gain register. This can be used to calibrate the apparent power (or energy) calculation in the ADE7753.
ACTIVE POWER
02875-0-071
Figure 73. Power Triangle
Rev. 0 | Page 34 of 48
ADE7753
APPARENT POWER 100% FS APPARENT POWER 150% FS APPARENT POWER 50% FS 103880h AD055h 5682Bh 00000h 000h 7FFh 800h
Figure 76 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy remains theoretically always positive. The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, then the internal active energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAENERGY[23:0]). RVAENERGY register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation. Figure 77 shows this apparent energy accumulation for fullscale signals (sinusoidal) on the analog inputs. The three curves displayed illustrate the minimum time it takes the energy register to roll over when the VA gain registers content is equal to 7FFh, 000h, and 800h. The VA gain register is used to carry out an apparent power calibration in the ADE7753. As shown, the fastest integration time will occur when the VA gain register is set to maximum full scale, i.e., 7FFh.
23 VAENERGY [23:0] 0
{VAGAIN[11:0]}
APPARENT POWER CALIBRATION RANGE VOLTAGE AND CURRENT CHANNEL INPUTS: 0.5V/GAIN
02875-0-073
Figure 75. Apparent Power Calculation Output Range
Apparent Power Offset Calibration
Each RMS measurement includes an offset compensation register to calibrate and eliminate the dc component in the RMS value--see Channel 1 RMS calculation and Channel 2 RMS calculation sections. The Channel 1 and Channel 2 RMS values are then multiplied together in the apparent power signal processing. Since no additional offsets are created in the multiplication of the RMS values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual RMS measurement.
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
48
0
VADIV
%
Apparent Energy = Apparent Power (t ) dt
(30)
APPARENT POWER + +
48
0
The ADE7753 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 33 expresses the relationship
Apparent Energy = Lim Apparent Power ( nT ) x T T 0 n =0
ACTIVE POWER SIGNAL = P T
APPARENT POWER ARE ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER
TIME (nT)
(31)
Figure 76. ADE7753 Apparent Energy Calculation
02875-0-074
where: n is the discrete time sample number. T is the sample period. The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1 s (4/CLKIN).
Rev. 0 | Page 35 of 48
ADE7753
VAENERGY[23:0] FF,FFFFh VAGAIN = 7FFh VAGAIN = 000h VAGAIN = 800h 80,0000h
When VADIV is set to a value different from 0, the integration time varies, as shown on Equation 33.
Time = TimeWDIV =0 x VADIV
(33)
LINE APPARENT ENERGY ACCUMULATION
40,0000h
20,0000h
00,0000h
6.26
12.52
18.78
25.04
TIME (minutes)
02875-0-075
The ADE7753 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. By using the on-chip zero-crossing detection, the ADE7753 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 78. The line apparent energy accumulation mode is always active. The number of half line cycles is specified in the LINCYC register, which is an unsigned 16-bit register. The ADE7753 can accumulate apparent power for up to 65535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be compared easily. The active energy and the apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output will also go active low. Thus the IRQ line can also be used to signal the end of a calibration. The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent.
Figure 77. Energy Register Rollover Time for Full-Scale Power (Maximum and Minimum Power Gain)
Note that the apparent energy register contents roll over to fullscale negative (80,0000h) and continue increasing in value when the power or energy flow is positive--see Figure 77. By using the interrupt enable register, the ADE7753 can be configured to issue an interrupt (IRQ) when the apparent energy register is half full (positive or negative) or when an overflow/underflow occurs.
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 s (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 000h, the average word value from apparent power stage is AD055h--see the Apparent Power Output Range section. The maximum value that can be stored in the apparent energy register before it overflows is 224 or FF,FFFFh. The average word value is added to the internal register, which can store 248 or FFFF,FFFF,FFFFh before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows:
Time =
FFFFFFFFFFFF x 1.2 s = 888 s = 12.52 min AD 055h
(32)
APPARENT POWER
%
+
+
48
0
VADIV[7:0]
LVAENERGY REGISTER IS UPDATED EVERY LINECYC ZERO CROSSINGS WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION
23 0 LVAENERGY [23:0]
LPF1 FROM CHANNEL 2 ADC
ZERO CROSSING DETECTION
CALIBRATION CONTROL
LINECYC [15:0]
02875-0-076
Figure 78. ADE7753 Apparent Energy Calibration
Rev. 0 | Page 36 of 48
ADE7753
ENERGIES SCALING
The ADE7753 provides measurements of active, reactive, and apparent energies. These measurements do not have the same scaling and thus cannot be compared directly to each other. Table 8. Energies Scaling
PF = 1 Integrator On at 50 Hz Wh Active 0 Reactive Wh x 0.848 Apparent Integrator Off at 50 Hz Wh Active 0 Reactive Wh x 0.848 Apparent Integrator On at 60 Hz Wh Active 0 Reactive Wh x 0.827 Apparent Integrator Off at 60 Hz Wh Active 0 Reactive Wh x 0.827 Apparent PF = 0.707 Wh x 0.707 Wh x 0.983 Wh x 0.848 Wh x 0.707 Wh x 0.491 Wh x 0.848 Wh x 0.707 Wh x 0. Wh x 0.827 Wh x 0.707 Wh x 0.409 Wh x 0.827 PF = 0 0 Wh x 0.719 Wh x 0.848 0 Wh x 0.347 Wh x 0.848 0 Wh x 0.863 Wh x 0.827 0 Wh x 0.289 Wh x 0.827
For example, at 60 Hz line frequency, the elapsed time for 255 half cycles will be 2.125 seconds. Rewriting the above in terms of contents of various ADE7753 registers and line frequencies (fL):
CF Frequency =
LAENERGY [23 : 0] x 2 x f L LINCYC[15 : 0]
(36)
where fL is the line frequency. Alternatively, CF frequency can be calculated based on the average LPF2 output.
CF Frequency =
Average LPF 2 Output x CLKIN 2 27
Calibrating the Frequency at CF
When the frequency before frequency division is known, the pair of CF frequency divider registers (CFNUM and CFDEN) can be adjusted to produce the required frequency on CF. In this example, a meter constant of 3200 imp/kWh is chosen as an appropriate constant. This means that under a steady load of 1 kW, the output frequency on CF would be
Frequency (CF ) =
CALIBRATING THE ENERGY METER
When calibrating the ADE7753, the first step is to calibrate the frequency on CF to some required meter constant, e.g., 3200 imp/kWh. A convenient way to determine the output frequency on CF is to use the line cycle energy accumulation mode. As shown in Figure 68, the DFC generates a pulse each time a LSB in the LAENERGY register is accumulated. CF frequency (before the CF frequency divider) can be conveniently determined by the following expression:
3200 imp / kWh 3200 = = 0.8888 Hz (37) 60 minx 60 sec 3600
CF Frequency =
Content of LAENERGY [ 23 : 0] Register (34) Elapased Time
When the CYCMODE bit (Bit 7) in the mode register is set to Logic 1, energy is accumulated over an integer number of half line cycles. If the line frequency is fixed and the number of half cycles of integration is specified, the total elapsed time can be calculated by the following:
Assuming the meter is set up with a test current (basic current) of 20 A and a line voltage of 220 V for calibration, the load is calculated as 220 V x 20 A = 4.4 kW. Therefore the expected output frequency on CF under this steady load condition would be 4.4 x 0.8888 Hz = 3.9111 Hz. Under these load conditions, the transducers on Channel 1 and Channel 2 should be selected such that the signal on the voltage channel should see approximately half scale and the signal on the current channel about 1/8 of full scale (assuming a maximum current of 80 A). Assuming at line frequency of 60 Hz, energy is accumulated over FFh number of half line cycles; the resulting content of the LAENERGY register will be approximately 2971.4d). CF frequency is therefore calculated to be
Frequency (CF ) =
2971.4 x 2 x 60 = 1398.3 Hz 255
(38)
Elapsed Time =
1 x number of half cycles 2x fL
(35)
Alternatively, the average value from LPF2 under this condition is approximately 1/16 of the full-scale level. As described previously, the average LPF2 output at full-scale ac input is CCCCDh or 838,861d. At 1/16 of full scale, the LPF2 output is then 52,428.81. Then using digital-to-frequency conversion, the frequency under this load is calculated as
Frequency (CF ) = 52428.81 x 3.579545 MHz 2 27 = 1398.3 Hz
(39)
Rev. 0 | Page 37 of 48
ADE7753
This is the frequency with the contents of the CFNUM and CFDEN registers equal to 000h. The desired frequency out is 3.9111 Hz. Therefore, the CF frequency must be divided by 2797/3.9111 Hz or 357.5d. This is achieved by loading the pair of CF divider registers with the closest rational number. In this case, the closest rational number is found to be 1/358 (or 1h/166h). Therefore, 0h and 165h should be written to the CFNUM and CFDEN registers, respectively. Note that the CF frequency is multiplied by the contents of (CFNUM + 1)/(CFDEN + 1). With the CF divide registers contents equal to 1h/166h, the output frequency is given as 2797 Hz/358 = 3.905 Hz. This setting has an error of -0.1%. The critical part of this approach is that the exact line frequency needs to be known. If this is not possible, the frequency can be measured by using the period register of the ADE7753. Note that changing WGAIN[11:0] register will also affect the output frequency from CF. The WGAIN register has a gain adjustment of 0.0244%/LSB. The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). But one needs to observe the read/write timing of the serial data transfer--see the ADE7753 timing characteristics in Table 2. Table 9 lists various timing changes that are affected by CLKIN frequency. Table 9. Frequency Dependencies of the ADE7753 Parameters
Parameter Nyquist Frequency for CH 1 and CH 2 ADCs PHCAL Resolution (Seconds per LSB) Active Energy Register Update Rate (Hz) Waveform Sampling Rate (Number of Samples per Second) WAVSEL 1,0 = 00 01 10 11 Maximum ZXTOUT Period CLKIN Dependency CLKIN/8 4/CLKIN CLKIN/4
CLKIN/128 CLKIN/256 CLKIN/512 CLKIN/1024 524,288/CLKIN
Determine the kWHr/LSB Calibration Coefficient
The active energy register (AENERGY) can be used to calculate energy. A full description of this register can be found in the Energy Calculation section. The AENERGY register gives the user both sign and magnitude information regarding energy consumption. On completion of the CF frequency output calibration, i.e., after adjusting the CF frequency divider and the watt gain (WGAIN) register, the second stage of the calibration is to determine the kWh/LSB coefficient for the AENERGY register. Equation 40 shows how LAENERGY can be used to calculate the calibration coefficient.
kWHr / LSB =
SUSPENDING ADE7753 FUNCTIONALITY
The analog and the digital circuit can be suspended separately. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high--see the Mode Register section. In suspend mode, all waveform samples from the ADCs will be set to 0s. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on CLKIN pin. The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low.
CHECKSUM REGISTER
(40) The ADE7753 has a checksum register (CHECKSUM[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. The 6-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit will be added to the checksum register. In the end of the serial read operation, the content of the checksum register will equal to the sum of all ones in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register will also generate a checksum of the checksum register itself.
DOUT
CONTENT OF REGISTER (n-bytes)
Calibration Power (in kW ) LINECYC[15 : 0] x 3600 sec onds / Hr LAENERGY [ 23 : 0] x 2 x f L
CLKIN FREQUENCY
In this data sheet, the characteristics of the ADE7753 are shown with CLKIN frequency equals 3.579545 MHz. However, the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range. If the CLKIN frequency is not 3.579545 MHz, various timing and filter characteristics will need to be redefined with the new CLKIN frequency. For example, the cutoff frequencies of all digital filters such as LPF1, LPF2, or HPF1, will shift in proportion to the change in CLKIN frequency according to the following equation:
New Frequency = Original Frequency x CLKIN Frequency (41) 3.579545 MHz
+ +
CHECKSUM REGISTER ADDR: 3Eh
02875-0-077
Figure 79. Checksum Register for Serial Interface Read
Rev. 0 | Page 38 of 48
ADE7753
ADE7753 SERIAL INTERFACE
All ADE7753 functionality is accessible via several on-chip registers--see Figure 80. The contents of these registers can be updated or read using the on-chip serial interface. After poweron or toggling the RESET pin low or a falling edge on CS, the ADE7753 is placed in communications mode. In communications mode, the ADE7753 expects a write to its communications register. The data written to the communications register determines whether the next data transfer operation will be a read or a write and also which register is accessed. Therefore all data transfer operations with the ADE7753, whether a read or a write, must begin with a write to the communications register.
DIN
COMMUNICATIONS REGISTER REGISTER #1 IN OUT IN OUT IN OUT
CS SCLK COMMUNICATIONS REGISTER WRITE DIN DOUT 00 ADDRESS MULTIBYTE READ DATA
02875-0-079
Figure 81. Reading Data from the ADE7753 via the Serial Interface
CS SCLK COMMUNICATIONS REGISTER WRITE DIN 10 ADDRESS MULTIBYTE READ DATA
02875-0-080
Figure 82. Writing Data to the ADE7753 via the Serial Interface
DOUT
REGISTER #2
REGISTER #3
REGISTER ADDRESS DECODE
REGISTER #n-1
IN OUT IN OUT
02875-0-078
REGISTER #n
Figure 80. Addressing ADE7753 Registers via the Communications Register
The communications register is an 8-bit wide register. The MSB determines whether the next data transfer operation is a read or a write. The five LSBs contain the address of the register to be accessed--see the ADE7753 Communications Register section for a more detailed description. Figure 81 and Figure 82 show the data transfer sequences for a read and write operation, respectively. On completion of a data transfer (read or write), the ADE7753 once again enters communications mode. A data transfer is complete when the LSB of the ADE7753 register being addressed (for a write or a read) is transferred to or from the ADE7753.
The serial interface of the ADE7753 is made up of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt-trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7753 at the DIN logic input on the falling edge of SCLK. Data is shifted out of the ADE7753 at the DOUT logic output on a rising edge of SCLK. The CS logic input is the chip-select input. This input is used when multiple devices share the serial bus. A falling edge on CS also resets the serial interface and places the ADE7753 into communications mode. The CS input should be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. The CS logic input may be tied low if the ADE7753 is the only device on the serial bus. However, with CS tied low, all initiated data transfer operations must be fully completed, i.e., the LSB of each register must be transferred because there is no other way of bringing the ADE7753 back into communications mode without resetting the entire device, i.e., using RESET.
Rev. 0 | Page 39 of 48
ADE7753
ADE7753 Serial Write Operation
The serial write sequence takes place as follows. With the ADE7753 in communications mode (i.e., the CS input logic low), a write to the communications register first takes place. The MSB of this byte transfer is a 1, indicating that the data transfer operation is a write. The LSBs of this byte contain the address of the register to be written to. The ADE7753 starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses--see Figure 82. As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7753, data is transferred to all on-chip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ADE7753 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer should not finish until at least 4 s after the end of the previous byte transfer. This functionality is expressed in the timing specification t6--see Figure 82. If a write operation is aborted during a byte transfer (CS brought high), then that byte will not be written to the destination register. Destination registers may be up to 3 bytes wide--see the ADE7753 Register Description tables. Therefore the first byte shifted into the serial port at DIN is transferred to the MSB (most significant byte) of the destination register. If, for example, the addressed register is 12 bits wide, a 2-byte data transfer must take place. The data is always assumed to be right justified, therefore in this case, the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the ADE7753 would be the four MSBs of the 12-bit word. Figure 84 illustrates this example.
t8
CS
t1
SCLK
t3 t2 t4
A4
t6 t7 t5
A2 A1 A0 DB7 DB0 DB7 DB0
t7
DIN
1
0
A5
A3
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 83. Serial Interface Write Timing
SCLK
DIN
X
X
X
X
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-082
Figure 84. 12-Bit Serial Write Operation
Rev. 0 | Page 40 of 48
ADE7753
ADE7753 Serial Read Operation
During a data read operation from the ADE7753, data is shifted out at the DOUT logic output on the rising edge of SCLK. As is the case with the data write operation, a data read must be preceded with a write to the communications register. With the ADE7753 in communications mode (i.e., CS logic low), an 8-bit write to the communications register first takes place. The MSB of this byte transfer is a 0, indicating that the next data transfer operation is a read. The LSBs of this byte contain the address of the register that is to be read. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK--see Figure 85. At this point, the DOUT logic output leaves its high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface also enters communications mode again as soon as the read has been completed. At this point, the DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The read operation may be aborted by bringing the CS logic input high before the data transfer is complete. The DOUT output enters a high impedance state on the rising edge of CS. When an ADE7753 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. This allows the ADE7753 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. Note that when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 4 s after the end of the write operation. If the read command is sent within 4 s of the write operation, the last byte of the write operation may be lost. This timing constraint is given as timing specification t9.
CS
t1
SCLK
t13 t9 t10
DIN
0
0
A5
A4
A3
A2
A1
A0
t11
DOUT COMMAND BYTE DB7
t11
DB0 DB7
t12
DB0
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 85. Serial Interface Read Timing
Rev. 0 | Page 41 of 48
ADE7753 ADE7753 REGISTERS
Table 10. Summary of Registers by Address
Address 01h Name WAVEFORM R/W R No. Bits 24 Default 0h Description Waveform Register. This read-only register contains the sampled waveform data from either Channel 1, Channel 2, or the active power signal. The data source and the length of the waveform registers are selected by data Bits 14 and 13 in the mode register--see the Channel 1 and Channel 2 Sampling section. Active Energy Register. Active power is accumulated (integrated) over time in this 24-bit, read-only register--see the Energy Calculation section. Same as the active energy register except that the register is reset to 0 following a read operation. Line Accumulation Active Energy Register. The instantaneous active power is accumulated in this read-only register over the LINCYC number of half line cycles. Apparent Energy Register. Apparent power is accumulated over time in this read-only register. Same as the VAENERGY register except that the register is reset to 0 following a read operation. Line Accumulation Apparent Energy Register. The instantaneous real power is accumulated in this read-only register over the LINECYC number of half line cycles. Line Accumulation Reactive Energy Register. The instantaneous reactive power is accumulated in this read-only register over the LINECYC number of half line cycles. Mode Register. This is a 16-bit register through which most of the ADE7753 functionality is accessed. Signal sample rates, filter enabling, and calibration modes are selected by writing to this register. The contents may be read at any time--see the Mode Register section. Interrupt Enable Register. ADE7753 interrupts may be deactivated at any time by setting the corresponding bit in this 16- bit enable register to Logic 0. The status register will continue to register an interrupt event even if disabled. However, the IRQ output will not be activated--see the ADE7753 Interrupts section. Interrupt Status Register. This is an 16-bit read-only register. The status register contains information regarding the source of ADE7753 interrupts--the see ADE7753 Interrupts section. Same as the interrupt status register except that the register contents are reset to 0 (all flags cleared) after a read operation. Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on Channel 1 to be removed--see the Analog Inputs and CH1OS Register sections. Writing a Logic 1 to the MSB of this register enables the digital integrator on Channel 1, a 0 disables the integrator. The default value of this bit is 0. Channel 2 Offset Adjust. Bits 6 and 7 not used. Writing to Bits 0 to 5 of this register allows any offsets on Channel 2 to be removed--see the Analog Inputs section. PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for the PGA in Channels 1 and 2--see the Analog Inputs section. Phase Calibration Register. The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6-bit register. The valid content of this twos compliment register is between 1Dh to 21h. At line frequency of 60 Hz, this is a range from -2.06 to +0.7--see the Phase Compensation section. Active Power Offset Correction. This 16-bit register allows small offsets in the active power calculation to be removed--see the Active Power Calculation section. Power Gain Adjust. This is a 12-bit register. The active power calculation can be calibrated by writing to this register. The calibration range is 50% of the nominal full-scale active power. The resolution of the gain adjust is 0.0244%/LSB --see the Channel 1 ADC Gain Adjust section.
Rev. 0 | Page 42 of 48
02h 03h 04h
AENERGY RAENERGY LAENERGY
R R R
24 24 24
0h 0h 0h
05h 06h 07h
VAENERGY RVAENERGY LVAENERGY
R R R
24 24 24
0h 0h 0h
08h
LVARENERGY
R
24
0h
09h
MODE
R/W
16
000Ch
0Ah
IRQEN
R/W
16
40h
0Bh
STATUS
R
16
0h
0Ch 0Dh
RSTSTATUS CH1OS
R R/W
16 8
0h 00h
0Eh
CH2OS
R/W
8
0h
0Fh 10h
GAIN PHCAL
R/W R/W
8 6
0h 0Dh
11h
APOS
R/W
16
0h
12h
WGAIN
R/W
12
0h
ADE7753
Address 13h 14h Name WDIV CFNUM R/W R/W R/W No. Bits 8 12 Default 0h 3Fh Description Active Energy Divider Register. The internal active energy register is divided by the value of this register before being stored in the AENERGY register. CF Frequency Divider Numerator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register--see the Energy-toFrequency Conversion section. CF Frequency Divider Denominator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register--see the Energy-toFrequency Conversion section. Channel 1 RMS Value (Current Channel). Channel 2 RMS Value (Voltage Channel). Channel 1 RMS Offset Correction Register. Channel 2 RMS Offset Correction Register. Apparent Gain Register. Apparent power calculation can be calibrated by writing this register. The calibration range is 50% of the nominal full-scale real power. The resolution of the gain adjust is 0.02444%/LSB. Apparent Energy Divider Register. The internal apparent energy register is divided by the value of this register before being stored in the VAENERGY register. Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation--see the Line Cycle Energy Accumulation Mode section. Zero-Cross Timeout. If no zero crossings are detected on Channel 2 within a time period specified by this 12-bit register, the interrupt request line (IRQ) will be activated--see the Zero-Crossing Detection section. Sag Line Cycle Register. This 8-bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before the SAG output is activated--see the Voltage Sag Detection section. Sag Voltage Level. An 8-bit write to this register determines at what peak signal level on Channel 2 the SAG pin will become active. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated--see Line Voltage Sag Detection. Channel 1 Peak Level Threshold (Current Channel). This register sets the level of the current peak detection. If the Channel 1 input exceeds this level, the PKI flag in the status register is set. Channel 2 Peak Level Threshold (Voltage Channel). This register sets the level of the voltage peak detection. If the Channel 2 input exceeds this level, the PKV flag in the status register is set. Channel 1 Peak Register. The maximum input value of the current channel since the last read of the register is stored in this register. Same as Channel 1 Peak Register except that the register contents are reset to 0 after read. Channel 2 Peak Register. The maximum input value of the voltage channel since the last read of the register is stored in this register. Same as Channel 2 Peak Register except that the register contents are reset to 0 after a read. Temperature Register. This is an 8-bit register which contains the result of the latest temperature conversion--see the Temperature Measurement section. Period of the Channel 2 (Voltage Channel) Input Estimated by Zero-Crossing Processing. Reserved. Test Mode Register. Checksum Register. This 6-bit read-only register is equal to the sum of all the ones in the previous read--see the ADE7753 Serial Read Operation section. Die Revision Register. This 8-bit read-only register contains the revision number of the silicon.
15h
CFDEN
R/W
12
3Fh
16h 17h 18h 19h 1Ah
IRMS VRMS IRMSOS VRMSOS VAGAIN
R R R/W R/W R/W
24 24 12 12 12
0h 0h 0h 0h 0h
1Bh
VADIV
R/W
8
0h
1Ch
LINECYC
R/W
16
FFFFh
1Dh
ZXTOUT
R/W
12
FFFh
1Eh
SAGCYC
R/W
8
FFh
1Fh
SAGLVL
R/W
8
0h
20h
IPKLVL
R/W
8
FFh
21h
VPKLVL
R/W
8
FFh
22h 23h 24h 25h 26h 27h 28h-3Ch 3Dh 3Eh 3Fh
IPEAK RSTIPEAK VPEAK RSTVPEAK TEMP PERIOD
R R R R R R
24 24 24 24 8 15
0h 0h 0h 0h 0h 0h
TMODE CHKSUM DIEREV
R/W R R
8 6 8
- 0h -
Rev. 0 | Page 43 of 48
ADE7753 ADE7753 REGISTER DESCRIPTIONS
All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section.
COMMUNICATIONS REGISTER
The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 11 outlines the bit designations for the communications register.
DB7 W/R DB6 0 DB5 A5 DB4 A4 DB3 A3 DB2 A2 DB1 A1 DB0 A0
Table 11. Communications Register
Bit Location 0 to 5 6 7 Bit Mnemonic A0 to A5 RESERVED W/R Description The six LSBs of the communications register specify the register for the data transfer operation. Table 10 lists the address of each ADE7753 on-chip register. This bit is unused and should be set to 0. When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register will be interpreted as a write to the ADE7753. When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register will be interpreted as a read operation.
MODE REGISTER (09H)
The ADE7753 functionality is configured by writing to the mode register. Table 12 summarizes the functionality of each bit in the mode register. Table 12. Mode Register
Bit Location 0 1 2 3 4 Bit Mnemonic DISHPF DISLPF2 DISCF DISSAG ASUSPEND Default Value 0 0 1 1 0 Description HPF (high-pass filter) in Channel 1 is disabled when this bit is set. LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set. Frequency output CF is disabled when this bit is set. Line voltage sag detection is disabled when this bit is set. By setting this bit to Logic 1, both ADE7753's A/D converters can be turned off. In normal operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock signal at CLKIN pin. Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 when the temperature conversion is finished. Software Chip Reset. A data transfer should not take place to the ADE7753 for at least 18 s after a software reset. Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode. ADC 1 (Channel 1) inputs are internally shorted together. ADC 2 (Channel 2) inputs are internally shorted together. By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2. These bits are used to select the waveform register update rate. DTRT 1 DTRT0 Update Rate 0 0 27.9 kSPS (CLKIN/128) 0 1 14 kSPS (CLKIN/256) 1 0 7 kSPS (CLKIN/512) 1 1 3.5 kSPS (CLKIN/1024)
Rev. 0 | Page 44 of 48
5 6 7 8 9 10 12, 11
TEMPSEL SWRST CYCMODE DISCH1 DISCH2 SWAP DTRT1,0
0 0 0 0 0 0 00
ADE7753
Bit Location 14, 13 Bit Mnemonic WAVSEL1,0 Default Value 00 Description These bits are used to select the source of the sampled data for the waveform register. WAVSEL1,0 0 0 Length 0 1 Source 24 bits active power signal (output of LPF2) Reserved
15
POAM
0
1 0 24 bits Channel 1 1 1 24 bits Channel 2 Writing Logic 1 to this bit will allow only positive power to be accumulated in the ADE7753. The default value of this bit is 0.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
ADDR: 09H
DISHPF (DISABLE HPF1 IN CHANNEL 1) DISLPF2 (DISABLE LPF2 AFTER MULTIPLIER) DISCF (DISABLE FREQUENCY OUTPUT CF) DISSAG (DISABLE SAG OUTPUT) ASUSPEND (SUSPEND CH1 AND CH2 ADCs) TEMPSEL (START TEMPERATURE SENSING) SWRST (SOFTWARE CHIP RESET) CYCMODE (LINE CYCLE ENERGY ACCUMULATION MODE)
POAM (POSITIVE ONLY ACCUMULATION) WAVSEL (WAVEFORM SELECTION FOR SAMPLE MODE) 00 = LPF2 01 = RESERVED 10 = CH1 11 = CH2 DTRT (WAVEFORM SAMPLES OUTPUT DATA RATE) 00 = 27.9kSPS (CLKIN/128) 01 = 14.4kSPS (CLKIN/256) 10 = 7.2kSPS (CLKIN/512) 11 = 3.6kSPS (CLKIN/1024) SWAP (SWAP CH1 AND CH2 ADCs)
DISCH2 (SHORT THE ANALOG INPUTS ON CHANNEL 2)
DISCH1 (SHORT THE ANALOG INPUTS ON CHANNEL 1)
NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS
02875-0-084
Figure 86. Mode Register
INTERRUPT STATUS REGISTER (0Bh), RESET INTERRUPT STATUS REGISTER (0Ch), INTERRUPT ENABLE REGISTER (0Ah)
The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the ADE7753, the corresponding flag in the interrupt status register is set logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt. Table 13. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register
Bit Location 0h 1h 2h 3h 4h Interrupt Flag AEHF SAG CYCEND WSMP ZX Description Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the active energy register (i.e., the AENERGY register is half full). Indicates that an interrupt was caused by a SAG on the line voltage. Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the LINECYC register--see the Line Cycle Energy Accumulation Mode section. Indicates that new data is present in the waveform register. This status bit reflects the status of the ZX logic ouput--see the Zero-Crosssing Detection section.
Rev. 0 | Page 45 of 48
ADE7753
Bit Location 5h 6h Interrupt Flag TEMP RESET Description Indicates that a temperature conversion result is available in the temperature register. Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled to cause an interrupt. Indicates that the active energy register has overflowed. Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value. Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value. Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the apparent energy register, i.e., the VAENERGY register is half full. Indicates that the apparent enrgy register has overflowed. Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles--see the Zero-Crosssing Timeout section. Indicates that the power has gone from negative to positive. Indicates that the power has gone from positive to negative. Reserved.
7h 8h 9h Ah Bh Ch Dh Eh Fh
AEOF PKV PKI VAEHF VAEOF ZXTO PPOS PNEG RESERVED
CH1OS REGISTER (08h)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Channel 1, and Bits 0 to 5 indicates the amount of the offset correction in Channel 1. Table 14 summarizes the function of this register. Table 14. CH1OS Register
Bit Location 0 to 5 Bit Mnemonic OFFSET Description The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset correction is positive and a 1 indicates the offset correction is negative. This bit is unused. This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by setting this bit. This bit is set to be 0 on default.
6 7
Not Used INTEGRATOR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ADDR: 08H
SIGN AND MAGNITUDE CODED OFFSET CORRECTION BITS
02875-0-086
DIGITAL INTEGRATOR SELECTION 1 = ENABLE 0 = DISABLE NOT USED
Figure 87. Channel 1 Offset Register
Rev. 0 | Page 46 of 48
ADE7753 OUTLINE DIMENSIONS
7.50 7.20 6.90
20
11
1
10
5.60 5.30 5.00 8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65
0.25 0.09
8 4 0
0.05 MIN
0.65 BSC
COPLANARITY 0.10
0.38 0.22
SEATING PLANE
0.95 0.75 0.55
COMPLIANT TO JEDEC STANDARDS MO-150AE
Figure 88. 20-Lead Shrink Small Outline Package [SSOP]
ORDERING GUIDE
Table 15.
Model ADE7753ARS ADE7753ARSRL EVAL-ADE7753EB Package Description 20-Lead SSOP 20-Lead SSOP ADE7753 Evaluation Board Package Option* RS-20 RS-20 Temperature Range -40C to +85C -40C to +85C -40C to +85C
Rev. 0 | Page 47 of 48
ADE7753 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C02875-0-8/03(0)
Rev. 0 | Page 48 of 48

▲Up To Search▲

Price & Availability of ADE7753

	To Download ADE7753 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .