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| STS4NM20N N-CHANNEL 200V - 0.11 - 4A SO-8 ULTRA LOW GATE CHARGE MDmeshTM II MOSFET TARGET DATA TYPE STS4NM20N s s s s s s VDSS 200 V RDS(on) < 0.13 ID 4A WORLDWIDE LOWEST GATE CHARGE TYPICAL RDS(on) = 0.11 HIGH dv/dt and AVALANCHE CAPABILITIES LOW INPUT CAPACITANCE LOW GATE RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS SO-8 DESCRIPTION This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given on-resistance.Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications.Used in combination with secondary-side low-voltage STripFETTM products, it contributes to reducing losses and boosting efficiency INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmeshTM family is very suitable for increasing power density allowing system miniaturization and higher efficiencies ORDERING INFORMATION SALES TYPE STS4NM20N MARKING S4NM20N PACKAGE SO-8 PACKAGING TAPE & REEL March 2003 1/6 STS4NM20N ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID IDM (2) PTOT dv/dt (3) Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor (1) Peak Diode Recovery voltage slope Value 200 200 30 4 2.83 16 2.5 0.02 10 Unit V V V A A A W W/C V/ns THERMAL DATA Rthj-pcb Tj Tstg Thermal Resistance Junction-pcb Max (1) Max. Operating Junction Temperature Storage Temperature 50 150 -55 to 150 C/W C C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max Value TBD TBD Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 30 V VDS = VGS, ID = 250 A VGS = 10 V, ID = 2 A 3.5 4.2 0.11 Min. 200 1 10 100 5 0.13 Typ. Max. Unit V A A A V 2/6 STS4NM20N ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (4) Ciss Coss Crss Coss eq. (*) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Gate Input Resistance Test Conditions VDS = 15 V , ID = 2 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 1.4 670 180 12 TBD TBD Max. Unit S pF pF pF pF VGS = 0V, VDS = 0V to 400V f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain (*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 100 V, ID = 2 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 160 V, ID = 4 A, VGS = 10 V Min. Typ. TBD TBD 19 3.5 11 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol tr (Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-Over Time Test Conditions VDD = 100 V, ID = 2 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 3) Min. Typ. TBD TBD TBD Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (4) trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. 4 16 Unit A A V ns nC A ns nC A ISD = 2 A, VGS = 0 ISD = 2 A, di/dt = 100 A/s, VDD = 100 V, Tj = 25C (see test circuit, Figure 5) ISD = 2 A, di/dt = 100 A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 89 300 6.5 TBD TBD TBD 1.3 When mounted on 1 inch2 FR4 Board, 2oz of Cu, t 10 sec. Pulse width limited by safe operating area. ISD 4 A, di/dt 400 A/s, VDD V(BR)DSS, Tj TjMAX. Pulsed: Pulse duration = 400 s, duty cycle 1.5 %. 3/6 STS4NM20N Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STS4NM20N SO-8 MECHANICAL DATA DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 5/6 STS4NM20N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 6/6 |
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