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CY7C439
Bidirectional 2K x 9 FIFO
Features
* * * * * * * * * 2048 x 9 FIFO buffer memory Bidirectional operation High-speed 28.5-MHz asynchronous reads and writes Simple control interface Registered and transparent bypass modes Flags indicate Empty, Full, and Half Full conditions 5V 10% supply Available in 300-mil DIP, PLCC, LCC, and SOJ packages TTL compatible decoded to determine one of four states. Two 9-bit data ports are provided. The direction selected for the FIFO determines the input and output ports. The FIFO direction can be programmed by the user at any time through the use of the reset pin (MR) and the bypass/direction pin (BYPA). There are no control or status registers on the CY7C439, making the part simple to use while meeting the needs of the majority of bidirectional FIFO applications. FIFO read and write operations may occur simultaneously, and each can occur at up to 28.5 MHz. The port designated as the write port drives its strobe pin (STBX, X = A or B) LOW to initiate the write operation. The port designated as the read port drives its strobe pin LOW to initiate the read operation. Output port pins go to a high-impedance state when the associated strobe pin is HIGH. All normal FIFO operations require the bypass control pin (BYPX, X = A or B) to remain HIGH. In addition to the FIFO, two other data paths are provided; registered bypass and transparent bypass. Registered bypass can be considered as a single-word FIFO in the reverse direction to the main FIFO. The
Functional Description
The CY7C439 is a 2048 x 9 FIFO memory capable of bidirectional operation. As the term first-in first-out (FIFO) implies, data becomes available to the output port in the same order that it was presented to the input port. There are two pins that indicate the amount of data contained within the FIFO block--E/F (Empty/Full) and HF (Half Full). These pins can be
Logic Block Diagram
STBA BYPA STBB BYPB
Pin Configurations
PLCC/LCC Top View
PORT A CONTROL LOGIC
PORTB CONTROL LOGIC
A2 A3 A4 NCA 5 A6 A7 A1 A0 BYPA GND BYPB BDA B0 NC B1 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 A8 E/F NC STBA VCC MR STBB HF B8
PORT A A0 - A8
PORT B B0 - B8
TRANSPARENT BYPASS
5 6 7 8 7C439 9 10 11 12 13 14 15 16 17 1819
B2 B3 B4 NC B5 B6 B7
E/F
DIP Top View
A4 A3 A2 A1 A0 BYPA GND BYPB BDA B0 B1 B2 B3 B4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 7C439 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A5 A6 A7 A8 E/F STBA VCC MR STBB HF B8 B7 B6 B5
C439-2
BYPASS REGISTER RESET & DIRECTION LOGIC
FLAG CONTROL
HF BDA
MR
DIRECTION CONTROL
2048 x 9 FIFO
C439-1
C439-3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 1990 - Revised July 1994
CY7C439
Selection Guide
7C439-25 Frequency (MHz) Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military 28.5 25 147 7C439-30 25 30 140 170 7C439-40 20 40 130 160 7C439-65 12.5 65 115 145
Functional Description (continued)
bypass register provides a means of sending a 9-bit status or control word to the FIFO-write port. The bypass data available pin (BDA) indicates whether the bypass register is full or empty. The direction of the bypass register is always opposite to that of the main FIFO. The port designated to write to the bypass register drives its bypass control pin (BYPX) LOW. The other port detects the presence of data by monitoring BDA and reads the data by driving its bypass control pin (BYPX) LOW. Registered bypass operations require that the associated FIFO strobe pin (STBX) remains HIGH. Registered bypass operations do not affect data residing in the FIFO, or FIFO operations at the other port. Transparent bypass provides a means of transferring a single word (9 bits) of data immediately in either direction. This feature allows the device to act as a simple 9-bit bidirectional buffer. This is useful for allowing the controlling circuitry to access a dumb peripheral for control/programming information. For transparent bypass, the port wishing to send immediate data to the other side drives both its bypass and its strobe pins LOW simultaneously. This causes the buffered data to be driven out of the other port. On-chip circuitry detects conflicting use of the control pins and causes both data ports to enter a high-impedance state until the conflict is resolved. Additionally, a Test mode is offered on the CY7C439. This mode allows the user to load data into the FIFO and then read it back out of the same port. Built-In Self Test (BIST) and diagnostic functions can take advantage of these features. The CY7C439 is fabricated using an advanced 0.8 N-well CMOS technology. Input ESD protection is greater than 2000V
and latch-up is prevented by reliable layout techniques, guard rings, and a substrate bias generator.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................-65C to+150C Ambient Temperature with Power Applied...................................................-55C to+125C Supply Voltage to Ground Potential ..................-0.5V to+7.0V DC Voltage Applied to Outputs in High Z State......................................................-0.5V to+7.0V DC Input Voltage ................................................. -3.0V to +7.0V Power Dissipation .......................................................... 1.0W Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... > 200 mA
Operating Range
Range Commercial Military[1] Ambient Temperature 0C to +70C -55C to +125C VCC 5V 10% 5V 10%
Notes: 1. TA is the "instant on" case temperature.
Pin Definitions
Signal Name A(8-0) B(8-0) BYPA BYPB BDA STBA STBB E/F HF MR I/O I/O I/O I I O I I O O I Description Data Port Associated with BYPA and STBA Data Port Associated with BYPB and STBB Registered Bypass Mode Select for A Side Registered Bypass Mode Select for B Side Bypass Data Available Flag Data Strobe for A Side Data Strobe for B Side Encoded Empty/Full Flag Half Full Flag Master Reset
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CY7C439
Electrical Characteristics Over the Operating Range[2]
7C439-25 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 IOS Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VI < VCC STBX > VIH, GND < VO < VCC Com'l[3] Mil[4] Com'l Mil Com'l Mil -90 20 40 Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA Com'l Mil -3.0 -10 -10 0.8 +10 +10 147 2.2 Min. 2.4 0.4 VCC 2.2 2.2 -3.0 -10 -10 Max. 7C439-30 Min. 2.4 0.4 VCC VCC 0.8 +10 +10 140 170 40 45 20 25 -90 2.2 2.2 -3.0 -10 -10 Max. 7C439-40 Min. 2.4 0.4 VCC VCC 0.8 +10 +10 130 160 40 45 20 25 -90 2.2 2.2 -3.0 -10 -10 Max. 7C439-65 Min. 2.4 0.4 VCC VCC 0.8 +10 +10 115 145 40 45 20 25 -90 mA mA mA Max. Unit V V V V V A A mA
Operating Current VCC = Max., IOUT = 0 mA Standby Current Power-Down Current Output Short Circuit Current[5] All Inputs = VIH Min. All Inputs VCC - 0.2V
VCC = Max., VOUT = GND
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 4.5V Max. 8 10 Unit pF pF
Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. I CC (commercial) = 115 mA + [(f - 12.5) * 2 mA/MHz] for f > 12.5 MHz where f = the larger of the write or read operating frequency. 4. I CC (military) = 145 mA + [(f - 12.5) * 2 mA/MHz] for f > 12.5 MHz where f = the larger of the write or read operating frequency. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 6. Tested initially and after any design or process changes that may affect these parameters.
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CY7C439
AC Test Loads and Waveform
R1500 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 333 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 333 3.0V GND < 5 ns R1500
ALL INPUT PULSES
90% 10% 90% 10% < 5 ns
C439-5
C439-4
(a)
Equivalent to: THEVENIN EQUIVALENT 200 OUTPUT
(b)
2V
Switching Characteristics Over the Operating Range[2, 7]
7C439-25 Parameter tRC tA tRR tPR tLZR[8, 9] tDVR[8, 9] tHZR[8, 9] tWC tPW tHWZ[8, 9] tWR tSD tHD tMRSC tPMR tRMR tRPS tRPBS tRPBH tBDH tBSR tEFL tHFH tBRS tREF tRFF tWEF Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid from Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time STBX HIGH to MR HIGH BYPA to MR HIGH BYPA Hold after MR HIGH MR LOW to BDA HIGH STBX HIGH to BYPA LOW MR to E/F LOW MR to HF HIGH BYPX HIGH to STBX LOW STBX LOW to E/F LOW (Read) STBX HIGH to E/F HIGH (Read) STBX HIGH to E/F HIGH (Write) 10 25 25 25 10 35 35 10 30 30 30 35 25 10 10 15 0 35 25 10 25 10 0 35 10 40 40 10 35 35 35 10 25 3 3 18 40 30 10 10 18 0 40 30 10 30 10 0 40 10 50 50 15 60 60 60 Description Read Cycle Time Min. 35 25 10 30 3 3 20 50 40 10 10 20 0 50 40 10 40 15 0 50 15 80 80 Max. 7C439-30 Min. 40 30 10 40 3 3 25 80 65 10 15 30 10 80 65 15 65 20 0 80 Max. 7C439-40 Min. 50 40 15 65 3 3 30 Max. 7C439-65 Min. 80 65 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CY7C439
Switching Characteristics Over the Operating Range[2, 7] (Continued)
7C439-25 Parameter tWFF tBDA tBDB tBA tBHZ[8, 9] tTSB tTBS tTSN tTSD[8, 9] tTBN tTBD tTPD[8, 9] tDL tESD[ tEDS tEDB tBPW tTSP tBLZ[8, 9] tBDV tWHF tRHF tRAE tRPE tWAF tWPF tBSU tBHL
8, 9]
7C439-30 Min. Max. 30 30 30 30 20 10
7C439-40 Min. Max. 35 35 35 40 25 10
7C439-65 Min. Max. 60 60 60 60 30 15 0 15 10 30 15 30 55 30 30 30 30 30 65 55 10 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 80 80 60 65 60 65 30 10 ns ns ns ns ns ns ns ns
Description STBX LOW to E/F LOW (Write) BYPX HIGH to BDA LOW (Write) BYPX HIGH to BDA HIGH (Read) BYPX LOW to Data Valid (Read) BYPX HIGH to High Z (Read) STBX HIGH to BYPX LOW Set-Up STBX LOW after BYPX LOW STBX HIGH Recovery Time STBX HIGH to Data High Z BYPX HIGH Recovery Time BYPX HIGH to Data High Z STBX LOW to Data Valid Transparent Propagation Delay STBX LOW to High Z BYPX LOW to High Z STBX HIGH to Low Z BYPX HIGH to Low Z BYPX Pulse Width (Trans.) STBX Pulse Width (Trans.) BYPX LOW to Low Z (Read) BYPX HIGH to Data Invalid (Read) STBX LOW to HF LOW (Write) STBX HIGH to HF HIGH (Read) Effective Read from Write HIGH Effective Read Pulse Width after E/F HIGH Effective Write from Read HIGH Effective Write Pulse Width after E/F HIGH Bypass Data Set-Up Time Bypass Data Hold Time
Min.
Max. 25 25 25 30 18
10 0 10 18 10 18 20 20 18 18 18 18 25 20 10 3 35 35 25 25 25 25 15 0 10
0 10
10 20
0 10
10 25
10 20 20 20 20 20 20 20 30 20 10 3 40 40 30 30 30 30 18 0
10 25 30 25 25 25 25 25 40 30 10 3 50 50 35 40 35 40 20 0
tEBD[8, 9]
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, and output loading of the specified IOL/IOH and 30-pF load capacitance as in part (a) of AC Test Loads, unless otherwise specified. 8. t DVR, tBDV, tHZR, tTBD, tBHZ, tEBD, tESD, tTSD, tLZR, tHWZ, and tBLZ use capacitance loading as in part (b) of AC Test Loads. 9. t HZR, tTBD, tBHZ, tEBD, tESD, and tTSD transition is measured at +500 mV from VOL and - 500 mV from VOH. tDVR and tBDV transition is measured at the 1.5V level. tLZR, tHWZ, and tBLZ transition is measured at 100 mV from the steady state.
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CY7C439
Switching Waveforms
Asynchronous Read and Write Timing Diagram
tRC tA STBB [10] READ PORT B tPW STBB [10] WRITE PORTA tSD DATA VALID tHD DATA VALID
C439-6
tPR tRR tA
tLZR
tDVR DATA VALID tWC tWR DATA VALID
tHZR
Master Reset Timing Diagram
t MRSC MR t PMR t RMR STBA/STBB t RPS BYPA tRPBS BYPB t BDH BDA t EFL E/F tRPBH tRMR
HF tHFH
C439-7
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CY7C439
Switching Waveforms (Continued)
Half-F FlagTimingDiagram[11] ull
HALF FULL HALF FULL + 1 HALF FULL
STBA t RHF STBB HF
C439-8
tWHF
Last Write to First Read Empty/FullFlagTimingDiagram[11]
LAST WRITE FIRST READ ADDITIONAL READS FIRST WRITE
STBB
STBA tWFF E/F
C439-9
RFF
Last Read to First Write Empty/Full Flag Timing Diagram [11]
LAST READ STBA FIRST WRITE ADDITIONAL WRITES FIRST READ
STBB tREF E/F tA DATA OUT
VALID VALID
t WEF
C439-10
Notes: 10. Direction selected Port A to Port B. 11. Direction selected as A to B.
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CY7C439
Switching Waveforms (Continued)
Empty/Full Flag and Read Bubble-Through Mode Timing Diagram [11]
DATA IN (PORT A) tRAE STBA tWEF STBB t RPE
t REF E/F EMPTY tA t HWZ DATA OUT (PORT B) DATA VALID
C439-11
EMPTY
Empty/Full Flag and Write Bubble-Through Mode Timing Diagram [11]
STBB tWAF STBA tRFF E/F FULL tSD DATA IN (PORT A) tA DATA OUT (PORT B) DATA VALID
C439-12
tWPF
tWFF FULL tHD
DATA VALID
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CY7C439
Switching Waveforms (Continued)
Registered Bypass Read Timing Diagram [12]
tBPW STBB t BSR BYPB tHD PORT B t BDB t BLZ tBDV tBA tBRS
tBHZ
BDA
C439-13
Registered Bypass Write Timing Diagram [13]
STBA tBSR BYPA tHZR PORT A DATA OUT t BPW BDA DATA IN tBDA t BHL t BSU tBRS
C439-14
Transparent Bypass Read Timing Diagram [14]
t TSP STBA t TSB t TBS tBPW tTBN t TPD PORT A VALID INPUT 1 tDL PORT B VALID OUTPUT 1 VALID OUTPUT 2
C439-15
t BSR tTSN t BRS
BYPA
t TBD t TSD VALID INPUT 2
Notes: 12. Port B selected to read bypass register (FIFO direction Port B to Port A). 13. Port A selected to write bypass register (FIFO direction Port B to Port A. 14. Diagram shows transparent bypass initiated by Port A. Times are identical if initiated by Port B.
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CY7C439
Switching Waveforms (Continued)
Test Mode Timing Diagram
tMRSC MR tPMR t RMR STBA/STBB t RPS BYPA/BYPB tBDH tRPBS t RPBH tRMR
C439-16
ExceptionCondition Timing Diagram [14]
STBA
BYPA
STBB t ESD BYPB tEBD DATA B VALID OUTPUT HIGH Z t EDB VALID OUTPUT
C439-17
tEDS
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM array, a read pointer, a write pointer, data switching circuitry, buffers, a bypass register, control signals (STBA, STBB, BYPA, BYPB, MR), and flags (E/F, HF, BDA). Operation at Power-On Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. During an MR cycle, the user can initialize the device by choosing the direction of FIFO operation (see Table 1). There is a minimum LOW period for MR, but no maximum time. The state of BYPA is latched internally by the rising edge of MR and used to determine the direction of subsequent data operations. Resetting the FIFO During the reset condition (see Table 1), the FIFO three-states the data ports, sets BDA and HF HIGH, E/F LOW, and ignores the state of BYPA/B and STBA/B. The bypass registers are initialized to zero. During this time the user is expected to set the direction of the FIFO by driving BYPA HIGH or LOW, and BYPB, STBA, and STBB HIGH. If BYPA is LOW (selecting direction B>A), the FIFO will then
remain in a reset condition until the user terminates the reset operation by driving BYPA HIGH. If BYPA is HIGH (selecting direction A>B), the reset condition terminates after the rising edge of MR. The entire reset phase can be accomplished in one cycle time of tRC. FIFO Operation The operation of the FIFO requires only one control pin per port (STBX). The user determines the direction of the FIFO data flow by initiating an MR cycle (see Table 1), which clears the FIFO and bypass register and sets the data path and control signal multiplexers. The bypass register is configured in the opposite direction to the FIFO data flow. The FIFO direction can be reversed at any time by initiating another MR cycle. Data is written into the FIFO on the rising edge of the input, STBX, and read from the FIFO by a low level at the output, STBX. The two ports are asynchronous and independent. If the user attempts to read the FIFO when it is empty, no action takes place (the read pointer is not incremented) until the other port writes to the FIFO. Then a bubble-through read takes place, in which the read strobe is generated internally and the data becomes available at the read port shortly thereafter if the read strobe (STBX) is still LOW. Similarly, for an attempted write operation when the FIFO is full, no internal operation takes place until the other port performs a read operation, at
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CY7C439
which time the bubble-through write is performed if the write strobe (STBX) is still LOW. Registered Bypass Operation The registered bypass feature provides a means of transferring one 9-bit word of data in the opposite direction to normal data flow without affecting either the FIFO contents or the FIFO write operations at the other port. The bypass register is configured during reset to provide a data path in the opposite direction to that of the FIFO (see Table 1). For example, if port A is writing data to the FIFO (hence port B is reading data from the FIFO) then BYPB is used to write to the bypass register at port B, and BYPA is used to read a single word from the bypass register at port A. The bypass data available flag (BDA) is generated to notify port A that bypass data is available. BDA goes true on the trailing edge of the BYPX write operation and false upon the trailing edge of the BYPX read operation. Data is written on the rising edge of BYPX into the bypass register for later retrieval by the other port, regardless of the state of BDA. The bypass register is read by a low level at BYPX, regardless of the state of BDA. Transparent Bypass Operation The transparent bypass feature provides a means of sending immediate data "around" the FIFO in either direction. The FIFO contents are not affected by the use of transparent bypass, but the control signals for transparent bypass are shared with those of the normal FIFO operation. Hence there are limitations on the use of transparent bypass to ensure that data integrity and ease of use are preserved. The port wishing to send immediate data must ensure that the other port will not attempt a FIFO read or write during the transparent bypass cycle. If this is not possible, registered bypass or external circuitry should be used. Table 1. FIFO Direction Select Truth MR 1 BYPA X 1 0 0 X BYPB X 1 1 X STBA X 1 1 X STBB X 1 1 X Normal Operation FIFO Direction A to B, Registered Bypass Direction B to A FIFO Direction B to A, Registered Bypass Direction A to B Reset Condition Action Transparent bypass mode is initiated by bringing both BYPA and STBA LOW together. Care should be taken to observe the following constraints on the timing relationships. Since STBA is used for normal FIFO operations, it must follow BYPA falling edge by tTBS to prevent erroneous FIFO read or write operations. Since BYPA is used alone to initiate registered bypass read and write, it is internally delayed before initiating registered bypass. If STBA falls during this time, delay registered bypass is averted, and transparent bypass is initiated. Identical arguments apply to BYPB and STBB. If a transparent bypass sequence is successfully accomplished, data presented to the initiating port (port A in the above discussion) will be buffered to the other (port B) after tDL. Either port can initiate a transparent bypass operation at any time, but if the control signals (STBA/B, BYPA/B) are in conflict (exception condition), internal circuitry will switch both ports to high-impedance until the conflict is resolved. Test Mode Operation The Test mode feature provides a means of reading the FIFO contents from the same port that the data was written to the FIFO. This feature is useful for Built-In Self Test (BIST) and diagnostic functions. To utilize this capability, initialize FIFO direction A to B and load data into the FIFO using normal write timing. In order to read data back out of the same port (port A), initiate a MR cycle with both BYPA and BYPB LOW (see Test Mode Timing diagram). After completing the cycle, the data can be read out of port A in FIFO order. Data will be inverted when read out of the device. Also, flags are not valid when reading data. Flag Operation There are two flags, Empty/Full (E/F) and Half Full (HF), which are used to decode four FIFO states (see Table 4). The states are empty, 1-1024 locations full, 1025-2047 locations full, and full. Note that two conditions cause the E/F pin to go LOW, Empty and Full, hence both flag pins must be used to resolve the two conditions.
.
Table 2. Bypass Operation Truth Table Direction A AB A AB AAB 1 1 1 STBA BYPA 1 STBB BYPB 1 1 Action Normal FIFO Operations, Write at A, Read at B Normal FIFO Read at B, Bypass Register Read at A Normal FIFO Write at A, Bypass Register Write at B
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CY7C439
Table 2. Bypass Operation Truth Table BAA BAA BAA X X
.
1 1 1 0 1 0 1 1 1 0
1 1
Normal FIFO Operations, Write at B, Read at A Normal FIFO Write at B, Bypass Register Write at A Normal FIFO Read at A, Bypass Register Read at B
1 0
No FIFO Operations, Transparent Data A to B No FIFO Operations, Transparent Data B to A
Table 3. Exception Conditions: Operation Not Defined Direction X X X X X STBA 0 1 0 0 0 BYPA 1 0 0 0 0 STBB 0 0 0 1 0 BYBP 0 0 0 0 1 Data Buses High Impedance Data Buses High Impedance Data Buses High Impedance Data Buses High Impedance Data Buses High Impedance Action
Table 4. Flag Truth Table. E/F 0 1 1 0 HF 1 1 0 0 Empty 1-1024 Locations Full 1025-2047 Locations Full Full State
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CY7C439
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLYCURRENT vs. SUPPLY VOLTAGE 1.2 1.0 NORMALIZED I CC NORMALIZED I CC 1.4 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 60 50 40 30 20 10 0 0.0 VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
1.2
0.8
1.0 V CC =5.5V V IN =5.0V f=20MHz 25 125 AMBIENT TEMPERATURE(C)
0.6
VIN =5.0V TA =25C 4.5 5.0 5.5 6.0
0.8
0.4 4.0
0.0 -55
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.3 NORMALIZED t A 1.2 NORMALIZED tA 1.1 1.0 0.9 0.8 0.7 4.0 4.5 5.0
1.6 1.4 1.2 1.0 V CC =5.0V 0.8 TA =25C 5.5 6.0 0.6 -55 25 125
OUTPUT SINK CURRENT (mA)
NORMALIZED tA vs. SUPPLY VOLTAGE
NORMALIZED tA vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 V CC =5.0V TA =25C 3.0 4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE(C)
OUTPUT VOLTAGE (V)
NORMALIZED tA CHANGE vs. OUTPUT LOADING 1.6 NORMALIZED I CC 1.5 NORMALIZED t A 1.4 1.3 1.2 1.1 1.0 0 200 400 600 800 1000 VCC =5.0V TA =25C 1.3 1.1 0.9 0.7 0.5
NORMALIZED I CC vs. CYCLE FREQUENCY
0.0 10
VCC =5.0V TA =25C 20 30 40
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
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CY7C439
Ordering Information
Speed (ns) 25 30 Ordering Code CY7C439-25JC CY7C439-25PC CY7C439-30JC CY7C439-30PC CY7C439-30DMB CY7C439-30LMB 40 CY7C439-40JC CY7C439-40PC CY7C439-40DMB CY7C439-40LMB 6.5 CY7C439-65JC CY7C439-65PC CY7C439-65DMB CY7C439-65LMB Package Name J65 P21 J65 P21 D22 L55 J65 P21 D22 L55 J65 P21 D22 L55 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier Military Commercial Military Commercial Military Commercial Operating Range Commercial
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CY7C439
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters VOH VOL VIH VIL Max. IIX ICC ISB1 ISB2 IOS IOZ Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameters tEFL tHFH tBRS tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tBSU tBHL tBDA tBDB tBA tBHZ tTSB tTBS tTSN tTSD tTBN tTBD tTPD tDL tESD tEBD tEDS tEDB tBPW tTSP tBLZ tBDV Document #: 38-00126-D Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Switching Characteristics
Parameters tRC tA tRR tPR tLZR tDVR tHZR tWC tPW tHWZ tWR tSD tHD tMRSC tPMR tRMR tRPS tRPBS tRPBH tBDH tBSR Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
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CY7C439
Package Diagrams
28-Lead(300-Mil) CerDIP D22
MIL-STD-1835 D-15Config.A
32-Pin Rectangular Leadless ChipCarrier L55
MIL-STD-1835 C-12
32-Lead Plastic Leaded Chip Carrier J65
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CY7C439
Package Diagrams (Continued)
28-Lead (300-Mil) Molded DIP P21
(c) Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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