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INTEGRATED CIRCUITS
74F534 Octal D flip-flop, inverting (3-State)
Product specification Supersedes data of 1999 Jan 08 IC15 Data Handbook 2000 Aug 01
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
FEATURES
* 8-bit positive edge-triggered register * 3-State inverting output buffers * Common 3-State Output register * Independent register and 3-State buffer operation
DESCRIPTION
The 74F534 is an 8-bit edge-triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the Clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. TYPE 74F534 TYPICAL fMAX 165MHz TYPICAL SUPPLY CURRENT (TOTAL) 51mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F534N N74F534D PKG DWG #
20-Pin Plastic DIP 20-Pin Plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 OE CP Data inputs Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 3.0mA/24mA
Q0 - Q7 Data outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
OE 1 Q0 D0 D1 Q1 Q2 D2 D3 Q3 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
LOGIC SYMBOL
3
4
7
8
13
14
17
18
D0 11 CP
D1
D2
D3
D4
D5
D6
D7
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
GND 10
2 VCC=Pin 20 GND=Pin 10
5
6
9
12
15
16
19
SF00982
SF00984
2000 Aug 01
2
853-0374 24250
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
LOGIC SYMBOL (IEEE/IEC)
1 11 EN1 C1 2 5 6 9 12 15 16 19
3 4 7 8 13 14 17 18
2D
1
SF00986
LOGIC DIAGRAM
D0 3 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
11
OE
1 2 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF00988
FUNCTION TABLE
INPUTS OE L L L H H H= h= L= l= NC= X= Z= = = CP Dn l h X X Dn INTERNAL REGISTER L H NC NC Dn OUTPUTS Q0 - Q7 H L NC Z Z OPERATING MODES Load and read register Hold Disable outputs
High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
2000 Aug 01
3
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5.0 -0.5 to +VCC 48 0 to +70 -65 to +125 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -3 24 70 TYP 5.0 MAX 5.5 UNIT V V V mA mA mA C
2000 Aug 01
4
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX -60 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.4 2.7 3.3 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -150 TYP2 MAX UNIT V V V V V A A mA A A mA
VO OH
High-level High level output voltage
VO OL VIK II IIH IIL IOZH IOZL IOS
Low level output voltage Low-level Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Short-circuit output current3
ICC Supply current (total) VCC = MAX OE=4.5V, Dn=GND 51 86 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock frequency Propagation delay CP to Qn Output Enable time to High or Low level Output Disable time from High or Low level Waveform 1 Waveform 1 Waveform 3 Waveform 4 Waveform 3 Waveform 4 150 3.0 3.0 2.0 2.0 2.0 2.0 TYP 165 4.5 4.5 4.5 5.0 3.5 3.5 7.0 7.0 7.5 7.5 6.5 5.5 MAX Tamb = 0C to +70C VCC = +5V 10% CL = 50pF, RL = 500 MIN 135 2.5 2.5 2.0 2.0 2.0 2.0 7.5 7.5 8.5 8.5 7.5 6.5 MAX MHz ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, Dn to CP Hold time, Dn to CP CP pulse width, High or Low Waveform 2 Waveform 2 Waveform 1 2.0 2.0 0 0 3.0 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.5 2.5 0 0 3.5 4.0 MAX ns ns ns UNIT
2000 Aug 01
5
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX Dn CP VM tW(H) tPLH Qn VM VM tW(L) tPHL CP VM VM VM VM VM ts(H) VM th(H) VM ts(L) VM th(L)
SF00191 SF00989
Waveform 2. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency
OE OE VM tPZH Qn VM 0V VM tPHZ VOH -0.3V Qn
VM tPZL VM
VM tPLZ
VOL +0.3V
SF00994
SF00995
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
2000 Aug 01
6
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
2000 Aug 01
7
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
2000 Aug 01
8
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
NOTES
2000 Aug 01
9
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-00 Document order number: 9397-750-07377
Philips Semiconductors
2000 Aug 01 10

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