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INTEGRATED CIRCUITS
74ABT845 8-bit bus interface latch with set and reset (3-State)
Product data Supersedes data of 1995 Sep 06 2002 Dec 17
Philips Semiconductors
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
FEATURES
* High speed parallel latches * Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two additional OE pins, making a total of three Output Enable (OE0, OE1, OE2) pins. The multiple Output enables allow multiuser control of the interface, e.g., CS, DMA, and RD/WR.
* Broadside pinout * Output capability: +64 mA / -32 mA * Power-up 3-State * Power-up reset * Latch-up protection exceeds 500 mA per Jedec Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25 C; GND = 0 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC Outputs disabled; VO = 0 V or VCC Outputs disabled; VCC = 5.5 V TYPICAL 5.4 4 7 500 UNIT ns pF pF nA
ORDERING INFORMATION
PACKAGES 24-Pin Plastic DIP 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C PART NUMBER 74ABT845N 74ABT845DB 74ABT845PW DWG NUMBER SOT222-1 SOT340-1 SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER SYMBOL OE0 - OE2 D0 - D7 Q0 - Q7 MR LE PRE GND VCC FUNCTION Output enable inputs (active-LOW) Data inputs Data outputs Master reset input (active-LOW) Latch enable input (active-HIGH) Preset input (active-LOW) Ground (0 V) Positive supply voltage
OE0 OE1 D0 D1 D2 D3 D4 D5 D6
1 2 3 4 5 6 7 8 9 TOP VIEW
24 23 22 21 20 19 18 17 16 15 14 13
VCC OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PRE LE
1, 2, 23 3, 4, 5, 6, 7, 8, 9, 10 22, 21, 20, 19,18, 17, 16, 15 11 13 14 12 24
D7 10 MR 11 GND 12
SA00258
2002 Dec 17
2
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
LOGIC SYMBOL (IEEE/IEC)
1 2 23 14 11 13 S2 R C1 & EN
LOGIC SYMBOL
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7 13 14 LE PRE MR OE0 OE1 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
3 4 5 6 7 8 9 10
1D
2
22 21 20 19 18 17 16 15
11 1 2 23
22 21 20 19 18 17 16 15
SA00260
SA00259
FUNCTION TABLE
INPUTS OEn L L L L L L H L PRE L H H H H H X H MR X L H H H H X H LE X X H H X L Dn X X L H l h X X OUTPUTS Qn H L L H L H Z NC Preset Clear Transparent Latched High impedance Hold OPERATING MODE H = High voltage level h = High voltage level one set-up time prior to the HIGH-to-LOW LE transition L = Low voltage level l = Low voltage level one set-up time prior to the HIGH-to-LOW LE transition NC= No change X = Don't care Z = High impedance "off" state = HIGH-to-LOW transition
LOGIC DIAGRAM
D0 3 14 PRE D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10
P D D
P D
P D
P D
P D
P D
P D
P
L 11 MR
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
13 LE 1 OE0 2 OE1 OE2 23 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7
SA00261
2002 Dec 17
3
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
ABSOLUTE MAXIMUM RATINGS1,2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 V output in Off or HIGH state output in LOW state VI < 0 V CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current Input transition rise or fall rate Operating free-air temperature range 4.5 0 2.0 - - - 0 -40 LIMITS Max 5.5 VCC - 0.8 -32 64 5 +85 V V V V mA mA ns/V C UNIT
2002 Dec 17
4
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 C Min VIK Input clamp voltage VCC = 4.5 V; IIK = -18 mA VCC = 4.5 V; IOH = -3 mA; VI = VIL or VIH VOH HIGH-level output voltage VCC = 5.0 V; IOH = -3 mA; VI = VIL or VIH VCC = 4.5 V; IOH = -32 mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current LOW-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-state output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = GND or 5.5 V VCC = 0.0 V; VO or VI 4.5 V VCC = 2.1 V; VO = 0.5 V; V OE = VCC; VI = GND or VCC VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; Outputs HIGH, VI = GND or VCC VCC = 5.5 V; Outputs Low, VI = GND or VCC VCC = 5.5 V; Outputs 3-State; VI = GND or VCC VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND -50 2.5 3.0 2.0 Typ -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -80 0.5 24 0.5 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 30 250 1.5 -50 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40 C to +85 C Min Max -1.2 V V V V V V A A A A A A mA A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 msec. For VCC = 2.1 V to VCC = 5 V " 10%, a transition time of up to 100 sec is permitted.
2002 Dec 17
5
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
AC CHARACTERISTICS
GND = 0 V; tR = tF = 2.5 ns; CL = 50 pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay LE to Qn Propagation delay PRE to Qn Propagation delay MR to Qn Output enable time OEn to Qn Output disable time OEn to Qn 1 2 1 1 4 5 4 5 1.0 2.2 2.0 2.8 2.2 3.0 2.4 3.1 1.0 2.0 1.9 2.2 Tamb = +25 C VCC = +5.0 V Typ 3.9 5.4 5.1 6.4 4.9 5.3 4.9 5.9 3.8 4.7 4.6 4.7 Max 5.4 6.8 6.6 7.9 6.6 6.8 6.4 7.3 5.4 6.1 6.2 6.4 Tamb = -40 C to +85 C VCC = +5.0 V 0.5 V Min 1.0 2.2 2.0 2.8 2.2 3.0 2.4 3.1 1.0 2.0 1.9 2.2 Max 6.2 7.8 7.5 8.9 7.8 7.4 7.3 8.5 6.3 6.7 7.2 7.0 ns ns ns ns ns ns UNIT
AC SET-UP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec trec Set-up time, HIGH or LOW Dn to LE Hold time, HIGH or LOW Dn to LE LE pulse width, HIGH PRE pulse width, LOW MR pulse width, LOW PRE recovery time MR recovery time 3 3 3 6 6 6 6 2.8 3.5 1.0 1.0 3.0 3.5 2.8 3.0 3.4 Tamb = +25 C VCC = +5.0 V Typ 1.0 1.4 -1.2 -0.6 1.5 2.0 1.3 1.4 1.6 Tamb = -40 C to +85 C VCC = +5.0 V 0.5 V Min 2.8 3.5 1.0 1.0 3.0 3.5 2.8 3.0 3.4 ns ns ns ns ns ns ns UNIT
2002 Dec 17
6
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
Dn PRE VM MR, Dn LE tPLH Qn tPHL tPLH Qn tPHL VM VM VM
VM
VM
VM
VM
SA00254
SA00255
Waveform 1. Propagation Delay, Data to Output, Preset to Output, and Master Reset to Output
Waveform 2. Propagation Delay, Latch Enable to Output
Dn
Waveform 5. 3-State Output Enable Time to LOW Level and Output Disable Time from LOW Level
2002 Dec 17
EEEEEEEEEE EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) tw(H) LE VM VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
OE
VM tPZH
VM tPHZ VOH-0.3V 0V
Qn
VM
SA00256
SA00066
Waveform 3. Data Set-up and Hold Times and Latch Enable Pulse Width
Waveform 4. 3-State Output Enable Time to HIGH Level and Output Disable Time from HIGH Level
PRE, MR OE VM tPZL VM
VM tw(L)
VM tREC VM
tPLZ LE
Qn
VM
VOL +0.3V VOL Qn
SA00109
Qn
SA00257
Waveform 6. Master Reset and Preset Pulse Width and Master Reset and Preset to Latch Enable Recovery Time
7
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00012
2002 Dec 17
8
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
2002 Dec 17
9
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
2002 Dec 17
10
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
2002 Dec 17
11
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
REVISION HISTORY
Rev _2 Date 20021217 Description Product data (9397 750 10852); ECN 853-1703 29288 of 12 December 2002. Supersedes data of 06 September 1995. Modifications:
* Ordering information table: remove "North America" column; remove 74ABT845D package offering.
_1 19950906 Product specification. ECN 853-1703 15702 of 06 September 1995.
2002 Dec 17
12
Philips Semiconductors
Product data
8-bit bus interface latch with set and reset (3-State)
74ABT845
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 12-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10852
Philips Semiconductors
2002 Dec 17 13

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