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Si9168
New Product
Vishay Siliconix
Synchronous Buck or Boost Controller for 2-Cell Li+ Battery Operated Portable Communication Devices
FEATURES
D D D D Voltage Mode Control 5-V to 10-V Input Voltage Range for VDD 5-V to 12.6-V Input Voltage Range for VS - Boost Programmable PWM/PSM Control - Up to 2-MHz Switching Frequency in PWM - Synchronous Rectification in PWM - Less than 350-mA IDD in PSM Very High Efficiencies In Buck or Boost Modes Low Dropout Operation at 100% Duty Cycle In Buck Mode Integrated UVLO and POR Integrated Soft-Start Synchronization D Logic Controlled Micropower Shutdown Current <2 mA D Fast Line and Load Transient Response D Available in 16-Lead TSSOP Package
APPLICATIONS
D D D D D D Cellular Telephones Wireless Modems Portable Instruments Notebook and Palmtop Computers PDA's Battery Operated Devices
D D D D D
DESCRIPTION
The Si9168 is a synchronous buck or boost controller for 2-cell Li+ battery operated portable communication devices. Designed for use with external high-frequency MOSFETs, the Si9168 is ideal for providing power to various power amplifiers such as TDMA, CDMA, GSM, or PCS. For ultra-high efficiency, converters are designed to operate in synchronous rectified PWM mode under full load, while transforming into externally controlled pulse skipping mode (PSM) under light load conditions. All these features are provided by Si9168 without sacrificing system integration requirements of fitting these circuits into ever demanding smaller space. The Si9168 is capable of switching up to 2 MHz to minimize the size of the output inductor and capacitor, in order to decrease the overall converter footprint. The programmability to design a buck or boost converter with this IC makes it convenient to power either the high voltage (7.2-V) or low voltage (4-V) PAs. The Si9168 is available in TSSOP-16 pin package and specified to operate over the industrial temperature range of -25_C to 85_C.
FUNCTIONAL BLOCK DIAGRAM
VIN (5 - 10 V) VIN (5 - 10 V)
1.3 V X 10 V SMPS
VOUT (1.3 X 10 V)
VOUT (5 X 12.6 V)
5 V X 12.6 V SMPS
1.3 V Voltage Reference Shutdown Control
VREF (1.3 V)
1.3 V Voltage Reference Shutdown Control
VREF (1.3 V)
SD
SD
Buck Mode
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
Boost Mode
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Si9168
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to AGND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V VSS-VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V PWM/PSM, SYNC, SD, VREF, ROSC, COMP, FB, Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to VS + 0.3 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ."0.3V Voltages Referenced to PGND VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V DH, DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VS + 0.3 V Peak Output Current (DH, DL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (QJA) 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.4 mW/_C above 25_C.
New Product
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to AGND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 10 V FOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 kHz to 2 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 kW to 300 kW PWM/PSM, SYNC, SD, Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF Voltages Referenced to PGND VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V to 10 V (Buck) VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V to 12.6 V (Boost)
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage VREF Current Power Supply Rejection VREF IREF PSRR IREF = 0 A VDD = 7.2 V, 25_C 1.268 1.280 -500 60 1.3 1.3 1.332 1.320 V mA dB
Limits
-25_C to 85_C
Symbol
5 V v VDD, VS v 10 V
Mina
Typb
Maxa
Unit
UVLO
Under Voltage Lockout (Turn-On) Hysteresis VUVLO/LH VHYS 4.3 4.5 0.2 4.7 V
Soft-Start Time
SS Time tSS 3 ms
SD, SYNC, PWM/PSM
Logic High Logic Low Input Current VIH VIL IL -1.0 2.4 0.8 1.0 V mA
Mode
Logic High Logic Low Input Current VIH VIL IL -1.0 70% VDD 30% VDD 1.0 V mA
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Document Number: 70899 S-00022--Rev. A, 10-Jan--00
Si9168
New Product
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Oscillator
Maximum Frequency Accuracy Maximum Duty Cycle (Buck, Non LDO Mode) Maximum Duty Cycle (Boost) SYNC Range SYNC Low Pulse Width SYNC High Pulse Width SYNC tr, tf tr, tf FSYNC/FOSC DMAX FMAX 1% External Resistor FSW = 2 MHZ ROSC = 130 kW, VDD = 5 V, VS = 12.6 V 2 -20 75 65 1.2 50 50 50 ns 80 71 1.5 20 % MHz
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Limits
-25_C to 85_C
Symbol
5 V v VDD, VS v 10 V
Mina
Typb
Maxa
Unit
Error Amplifier
Input Bias Current Open Loop Voltage Gain Offset Voltage Unity Gain BW Output Current (Source) Output Current (Sink) Power Supply Rejection IBIAS AVOL VOS BW IEA PSRR VFB = 1.05 V VFB = 1.55 V 1 VFB = 1.4 V -1 50 -10 2 -2 3 60 -1 60 10 1 mA dB mV MHz mA dB
PSM Modulator
Switch On Time Switch Off Blanking Time tON tOFF VDD = 7.2 V, VOUT = 3.3 V, Buck Mode 180 330 ns
Output Drive (DH and DL)
Output High Voltage Output Low Voltage Peak Output Source Peak Output Sink Break-Before-Make VOH VOL ISOURCE ISINK tBBM VS = 7.2 V, IOUT = -20 mA VS = 7.2 V, IOUT = 20 mA VS = 7.2 V, DH = DL = VS/2 VS = VDD = 10 V 500 7.08 7.14 0.06 -1000 1000 40 0.12 -500 V
mA ns
Supply
Normal Mode PSM Mode Shutdown Mode IDD VDD = 7.2 V, fOSC = 2 MHz VDD = 7.2 V VDD = 7.2 V, SD = 0 V 1100 350 2.0 mA A
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. c. Guaranteed by design and characterization, not subject to production testing.
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
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Si9168
Vishay Siliconix
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
VREF vs. VDD
1.310 1.308 1.306 1.304 V REF (V) V REF (V) 1.302 1.300 1.298 1.296 1.294 1.292 1.29 4 6 8 10 12 14 1.320 1.316 1.312 1.308 1.304 1.300 1.296 1.292 1.288 1.284 1.28 -50 VDD = 7.2 V
VREF vs. Temperature
-25
0
25
50
75
100
VDD - (V)
Temperature (_C)
Frequency vs. Temperature
2.2 VDD = 7.2 V ROSC = 25 kW 10000
Frequency vs. ROSC
2.1 Frequency (MHz)
2.0
Frequency (kHz)
1000
1.9
1.8
1.7 -50
0
50 Temperature (_C)
100
100 10
100 ROSC (kW)
1000
Max Duty Cycle vs. Frequency (Buck Mode)
98 VIN = 7.2 V 94 90 86 82 78 74 70 400 74 70 66 % Max Duty Cycle 62 58 54 50 46
Max Duty Cycle vs. Frequency (Boost Mode)
VIN = 7.2 V
% Max Duty Cycle
600
800 1000 1200 1400 1600 1800 2000 2200 Frequency (kHz)
42 400
600
800 1000 1200 1400 1600 1800 2000 2200 Frequency (kHz)
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Document Number: 70899 S-00022--Rev. A, 10-Jan--00
Si9168
New Product
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
PWM Supply Current vs. VDD (Buck Mode)
1400 FOSC = 1.6 MHz 1200 1200 1400 FOSC = 1.6 MHz
Vishay Siliconix
PWM Supply Current vs. VDD (Boost Mode)
1000 I DD ( (m A) I DD ( (mA) 4 6 8 10 12 14
1000
800
800
600
600
400
400
200 VDD - (V)
200 4 6 8 10 VDD - (V) 12 14
PSM Supply Current vs. VDD (Buck Mode)
300 300
PSM Supply Current vs. VDD (Boost Mode)
250
250
I DD ( (mA)
150
I DD ( (mA) 4 6 8 10 12 14
200
200
150
100
100
50 VDD - (V)
50 4 6 8 10 VDD - (V) 12 14
100
Efficiency --Buck, VOUT = 3.6 V
PSM = 5 VIN
100
Efficiency --Boost, VOUT = 7.2 V
90 Efficiency (%) Efficiency (%) PWM = 5 VIN 80 PWM = 7.2 VIN PSM = 7.2 VIN 70 PSM = 8.4 VIN 60 PWM = 8.4 VIN
90 PSM: 5.4 VIN 80 PSM: 6.0 VIN PSM: 7.0 VIN 70
PWM: 5.4 VIN PWM: 6.0 VIN
PWM: 7.0 VIN
60
50 10
100
1000
10000
50 10
100
1000
10000
Load Current (mA)
Load Current (mA)
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
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Si9168
Vishay Siliconix
New Product
PIN CONFIGURATION
TSSOP-16
MODE DL PGND SD VO VDD ROSC COMP 1 2 3 4 5 6 7 8 Top View 16 15 14 VS N/C DH PWM/PSM SYNC GND VREF FB
ORDERING INFORMATION
Part Number
Si9168BQ-T1
Si9168BQ
13 12 11 10 9
Temperature Range
-25 to 85_C
Package
Tape and Reel
Eval Kit
Si9168DB
Temperature Range
-25 to 85_C
Board Type
Surface Mount
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
MODE DL PGND SD VO VDD ROSC COMP FB VREF GND SYNC PWM/PSM DH N/C VS
Function
Determines the converter topology. Connect to AGND for buck or VDD for boost. The gate drive output for the low-side n-channel MOSFET for buck and boost converter Power ground for output drive stage Logic low shuts down the IC completely and decreases the current consumption of IC to <2 mA. Direct output voltage sense Input supply voltage for the analog circuit. VDD voltage should be the ac filtered voltage of VSS. Input voltage range is 5 V to 10 V. External resistor to determine the switching frequency. Error amplifier output for external compensation network. Output voltage feedback connected to the inverting input of an error amplifier. 1.3-V reference voltage. Connected internally to non-inverting error amplifier input. Decouple with 0.1-mF ceramic capacitor. Low power controller ground Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD, or logic high. Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification drive is disabled. The gate drive output for the high-side p-channel MOSFET for buck and boost converter
Not used.
Supply voltage for the output driver section. Voltage range is 5 V to 10 V (Buck), 5 to 12.6 V (Boost).
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Document Number: 70899 S-00022--Rev. A, 10-Jan--00
Si9168
New Product
BLOCK DIAGRAM
VDD Positive Supply SD
Vishay Siliconix
Reference Threshold Generator VREF VO FB COMP
1.3 V
Soft-Start Timer
UVLO
POR System Monitor
Bias Generator
PWM Modulator 1.0 V Ramp Oscillator PWMIN 0.5 V PWMIN PWM/PFM Select PSMIN PSMIN PSM Modulator Drivers
VS
DH
SYNC ROSC COSC
DL
PGND
PWM/PSM MODE
Negative Return and Substrate GND
FIGURE 1.
DETAIL OPERATIONAL DESCRIPTION
Start-Up The UVLO circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on VDD pin is less than 4.5 V. With typical UVLO hysteresis of 0.2 V, the controller is continuously powered on until the VDD voltage drops below 4.3 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. After the POR time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging of the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. To prevent negative undershoot, the
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
synchronous switch is tri-stated until the duty cycle reaches about 10%. See start-up timing diagram. In tri-state, the high-side p-channel MOSFET is turned off by pulling up the gate voltage (DH) to VS potential. The low-side n-channel MOSFET is turned off by pulling down the gate voltage (DL) to PGND potential. Note that Si9168 will always soft starts in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown Si9168 is designed to conserve as much battery life as possible by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low level on the SD pin, current consumption of the Si9168 decreases to less than 2 mA by shutting off most of the circuits. The logic high enables the controller and starts up as described in "Start-Up" section above.
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Si9168
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DETAIL OPERATIONAL DESCRIPTION
PWM Mode With PWM/PSM mode pin in logic high condition, Si9168 operates in constant frequency (PWM) mode. As the load and input voltage vary, switching frequency remain constant. The switching frequency is programmed by the ROSC value as shown by the oscillator curve. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A. In continuous current mode, the transfer function of the converter remain constant providing fast transient response. If the converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be 10 times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltage regulation. Therefore, the PWM/PSM pin is available to dynamically program the controller. If the synchronous rectifier switch is not used, the converter may not operate in PWM mode if the load current is low enough to force the converter into pulse skipping mode. The maximum duty cycle of the Si9168 can reach 100% in buck mode. The duty cycle will continue to increase as the input voltage decreases until it reaches 100%. This allows the system designers to extract out the maximum stored energy from the battery. Once the controller delivers 100% duty cycle, the converter operates like a saturated linear regulator. At 100% duty cycle, synchronous rectification is completely turned off. At up to 80% duty cycle at 2-MHz switching frequency, the controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80% duty cycle, the controller will deliver 100% duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time and the internal propagation delays. In order to maintain regulation, the controller might fluctuate its duty cycle back and forth from 100% to something lower than 80% during this input voltage range. If the input voltage drops further, the controller will remain on for 100% duty cycle. If the input voltage increases to a point where it's requiring less than 80% duty cycle, synchronous rectification is once again activated. The maximum duty cycle under boost mode is internally limited to 75% to prevent inductor saturation. If the converter is turned on for 100% duty cycle, the inductor never gets a chance to discharge its energy and eventually saturate. In boost mode, the synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. The controller will deliver 0% duty cycle, if the input voltage is greater than the programmed output voltage. Because of fixed BBM time, the controller will not transition smoothly from minimum controllable duty cycle to 0% duty cycle. For example, controller may decrease its duty cycle from 5% to 0% abruptly, instead of the gradual decrease seen from 75% to 5%. Pulse Skipping Mode The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter
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during light load (i.e. < 200 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9168 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 350 mA, instead of 900 mA during the PWM mode. This is accomplished by turning off most of the internal control circuitry and utilizing a simple constant on-time control with the feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on the inductor used (2-mH typical) and the maximum load current. Therefore, with this control method, duty cycles ranging from 0 to 100% are possible depending on whether the boost or buck mode is chosen. Reference The reference voltage for the Si9168 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The REF pin requires a 0.1-mF decoupling capacitor. Error Amplifier The error amplifier gain-bandwidth product and slew rate are critical parameters which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, the error amplifier determines the converter response time. In order to minimize the response time, Si9168 is designed with a 2-MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and a 3.5-V/msec slew rate for ultra-fast large signal response. Oscillator The oscillator is designed to operate up to 2-MHz minimum. The 2-MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with a 2-MHz switching frequency, quiescent current is only 1100 mA (max) with the unique power saving circuit design. The switching frequency is easily programmed by attaching a resistor to the ROSC pin. See oscillator frequency versus Rosc curve to select the proper timing values for the desired operating frequency. The tolerance on the operating frequency is "20% with a 1% tolerance resistor.
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
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Si9168
New Product
DETAIL OPERATIONAL DESCRIPTION
Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. The logic high to low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. Break-Before-Make Timing A proper BBM time is essential in order to prevent shoot-through current and to maintain high efficiency. The break-before-make time is set internally at 20 to 60 ns @ VS = 7.2 V. The high- and low-side gate drive voltages are monitored and when the gate-to-source voltage reaches 3.5 V above or below the initial starting voltage, 20- to 60-ns BBM time is set before the other gate drive transitions to its proper state. The maximum and minimum duty cycle is limited by the BBM time. Since the BBM time is fixed, controllable maximum duty cycle will vary depending on the switching frequency. Output Driver Stage The DH pin is designed to drive the main switch MOSFET and DL pin is designed to drive the synchronous rectifier MOSFET. The driver stage is sized to sink and source peak currents up to 1000 mA with VS = 7.2 V. The ringing from the gate drive output trace inductance can produce negative voltage on the DH and DL respect to PGND. The gate drive circuit is capable of withstanding these negative voltages without any functional defects.
Vishay Siliconix
Document Number: 70899 S-00022--Rev. A, 10-Jan--00
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Si9168
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APPLICATIONS
VIN 5-10 V C1 22 mF 16 V COM U1 1 2 MODE DL VS NC DH 16 15 14 Q1A 13 12 11 10 9 C8 0.1 mF PWM/PSM to VIN for PWM mode; PWM/PSM to GND for PSM mode. SD to VIN for converter enable mode; SD to GND for shutdown mode. * = Optional C4 330 pF R2 200 W R3 22 kW C9 0.1 mF 4 R8* 5.6 W 8 1 5 R1* 51 W R9* 5.6 W 6, 7 Q1B
New Product
Si6803DQ
L1, 4.7 mH IHLP2525 VOUT 3.6 V 1.5 A
D1 MBR0520T1
C2 10 mF 10 V
C3 0.1 mF COM
3 PGND 4 5 6 SD VOUT VDD
2, 3
PWM/PSM SYNC GND VREF FB
Si6803DQ
7R OSC C5 0.1 mF R5 75 kW R6 8.2 kW C6 1 nF 8 COMP
Si9168BQ
C7 56 pF
R4 12.4 kW
FIGURE 2.
1.5-A Buck Regulator Using the Si9168BQ
VIN 5-7.2 V C1 10 mF 16 V R1* 51 W
L1, 4.7 mH IHLP2525
Q2
Si3442DV
3
1, 2, 5, 6
Q1
5, 6, 7, 8
SI9803DY
4 D1 B130LB 1, 2, 3
COM
U1 1 2 MODE DL VS NC DH 16 15 14 13 12 11 10 9
4
VOUT 7.2 V 2.5 A
3 PGND 4 5 6 SD VOUT VDD
PWM/PSM SYNC GND VREF FB
PWM/PSM to VIN for PWM mode; PWM/PSM to GND for PSM mode. SD to VIN for converter enable mode; SD to GND for shutdown mode. * = Optional
C2 47 mF 16 V
C3 0.1 mF COM
7R OSC C5 0.1 mF R5 75 kW R6 4.7 kW C6 5.6 nF C7 220 pF 8 COMP
C8 0.1 mF C4 560 pF
R2 1 kW
R3 56.2 kW
Si9168
R4 12.4 kW FIGURE 3. Si9168BQ Boost Regulator Application
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Document Number: 70899 S-00022--Rev. A, 10-Jan--00

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