 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 74VHCT74A DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR s s s s s s s s s HIGH SPEED: fMAX = 160 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 A (MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY SOP TSSOP ORDER CODES PACKAGE SOP TSSOP TUBE 74VHCT74AM T&R 74VHCT74AMTR 74VHCT74ATTR DESCRIPTION The 74VHCT74A is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS June 2001 1/11 74VHCT74A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asyncronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asyncronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC TRUTH TABLE INPUTS CLR L H L H H H X : Don't Care OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET PR H L L H H H LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 74VHCT74A ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) VCC = 0V 2) High or Low State RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V C ns/V 1) VCC = 0V 2) High or Low State 3) VIN from 0.8V to 2V 3/11 74VHCT74A DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 0 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 0.1 2 1.35 0.5 4.5 4.4 3.8 0.1 0.44 1.0 20 1.5 5.0 Typ. Max. Value -40 to 85C Min. 2 0.8 4.4 3.7 0.1 0.55 1.0 20 1.5 5.0 Max. -55 to 125C Min. 2 0.8 Max. V V V V A A mA A Unit VIH VIL VOH VOL II ICC High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current ICC IOPD AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0 (*) Value TA = 25C Min. Typ. 5.8 6.3 7.6 8.1 Max. 7.8 8.8 10.4 11.4 5.0 5.0 5.0 0.0 3.5 -40 to 85C Min. 1.0 1.0 1.0 1.0 Max. 9.0 10.0 12.0 13.0 5.0 5.0 5.0 0.0 3.5 80 65 80 65 -55 to 125C Min. 1.0 1.0 1.0 1.0 Max. 9.0 10.0 12.0 13.0 5.0 5.0 5.0 0.0 3.5 ns ns ns ns ns ns MHz ns Unit CL (pF) 15 50 15 50 tPLH tPHL tPLH tPHL tW tW ts th tREM fMAX Propagation Delay Time CK to Q or Q Propagation Delay Time PR or CLR to Q or Q CK Pulse Width HIGH or LOW PR or CLR Pulse Width LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Removal Time PR or CLR to CK Maximum Clock Frequency 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 15 50 100 80 160 140 (*) Voltage range is 5.0V 0.5V 4/11 74VHCT74A CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Min. CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) TA = 25C Typ. 6 21 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate) TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50) 5/11 74VHCT74A WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74VHCT74A WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: REMOVAL TIMES (f=1MHz; 50% duty cycle) 7/11 74VHCT74A WAVEFORM 4: PULSE WIDTH 8/11 74VHCT74A SO-14 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13G 9/11 74VHCT74A TSSOP14 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/11 74VHCT74A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 11/11 |
Price & Availability of 7074
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |