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HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
Features
x x
IDT7005S/L
x
x
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Military: 20/25/35/55/70ns (max.) Industrial: 35/55ns (max.) Commercial:15/17/20/25/35/55ns (max.) Low-power operation IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7005L Active: 700mW (typ.) Standby: 1mW (typ.) IDT7005 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than
x
x x x
x x
x x x
x
one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Devices are capable of withstanding greater than 2001V electrostatic discharge Battery backup operation2V data retention TTL-compatible, single 5V (10%) power supply Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin thin quad flatpack Industrial temperature range (-40C to +85C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL A12L A0L
(1,2)
I/O0R-I/O7R I/O Control BUSYR Address Decoder
13
(1,2)
MEMORY ARRAY
13
Address Decoder
A12R A0R
CEL OEL R/WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER OER R/WR
SEML (2) INTL
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.
M/S
SEMR INTR(2)
2738 drw 01
JUNE 1999
1
(c)1998 Integrated Device Technology, Inc. DSC 2738/11
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter
Description
a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500W from a 2V battery. The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military grade product is manufactured in compliance with the latest revision of MILPRF-38535 QML making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
INDEX I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
I/O1L I/O0L N/C OEL R/WL SEML CEL N/C N/C VCC A12L A11L A10L A9L A8L A7L A6L
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56
IDT7005J or F J68-1(4) F68-1(4) 68 Pin PLCC / FLATPACK Top View(5)
55 54 53 52 51 50 49 48 47 46 45
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
2738 drw 02
,
R/WL SEML
I/O1L I/O0L OEL
N/C VCC A12L A11L A10L 58 57 56 55 54
CEL
I/O7R N/C OER R/WR SEMR CER N/C N/C GND A12R A11R A10R A9R A8R A7R A6R A5R
INDEX
64 63 62
61 60
59
53 52
51 50 49
A9L A8L A7L A6L A5L
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J68-1 package body is approximately .95 in x .95 in x .12 in. F68-1 package body is approximately .97 in x .97 in x .08 in. PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking
17 18 19
20 21
23 24 25
26 27 28
29 30 31
22
16
32
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
A4L A3L A2L A1L A0L INTL BUSYL GND M/S . BUSYR INTR A0R A1R A2R A3R A4R
7005PF PN-64(4) 64-Pin TQFP Top View(5)
I/O6R
I/O7R OER
A12R A11R A10R
A9R A8R A7R A6R
R/WR SEMR
CER
GND
N/C
A5R
2738 drw 03
6.42 2
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations (1,2,3) (con't.)
51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L 50 A4L 49 A3L 48 A2L 47 A1L 46 44 42 A0L BUSYL M/S 40 38 INTR A1R 36 A3R 35 A4R 32 A7R 30 A9R 28 A11R 26 GND 24 N/C 34 A5R 33 A6R 31 A8R 29 A10R 27 A12R 25 N/C
10
45 43 41 39 37 INTL GND BUSYR A0R A2R
09
08
57 56 A11L A10L 59 58 VCC A12L 61 N/C 60 N/C
07
IDT7005G G68-1(4) 68-Pin PGA Top View(5)
06
63 62 05 SEML CEL 04 65 64 OEL R/WL 67 66 I/O0L N/C 1 3 68 I/O1L I/O2L I/O4L 2 01 A
INDEX
22 23 SEMR CER 20 OER 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 6 8 10 12 14 16 I/O6L VCC I/O0R I/O2R I/O3R I/O5R D E F G H J 21 R/WR
.
03
02
18 19 I/O7R N/C 17 I/O6R K L
2738 drw 04
4 I/O3L I/O5L B C
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.18in x 1.18in x .16in. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking
Pin Names
Left Port CEL R/WL OEL A0L - A12L I/O0L - I/O7L SEML INTL BUSYL CER R/WR OER A0R - A12R I/O0R - I/O7R SEMR INTR BUSYR M/S VCC GND Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground
2738 tbl 01
6.42 3
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1) Outputs
CE
H L L X
R/W X L H X
OE
X X L H
SEM
H H H X
I/O0-7 High-Z DATAIN DATAOUT High-Z Deselected: Power-Down Write to Memory Read Memory Outputs Disabled
Mode
NOTE: 1. A0L A12L is not equal to A0R A12R
2738 tbl 02
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1) Outputs
CE
H H L
R/W H X
OE
L X X
SEM
L L L
I/O0-7 DATAOUT DATAIN
____
Mode Read in Semaphore Flag Data Out Write I/Oo into Semaphore Flag Not Allowed
2738 tbl 03
NOTE: 1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
Absolute Maximum Ratings(1)
Symbol VTERM
(2)
Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current
Commercial & Industrial -0.5 to +7.0
Military -0.5 to +7.0
Unit V
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Military Ambient Temperature -55OC to+125OC 0 C to +70 C
O O
GND 0V 0V OV
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2738 tbl 05
TBIAS TSTG IOUT
-55 to +125 -55 to +125 50
-65 to +135 -65 to +150 50
o
C C
Commercial Industrial
o
-40 C to +85 C
O O
mA
2738 tbl 04
NOTES: 1. This is the parameter TA. 2 Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10% maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____ ____
Max. 5.5 0 6.0(2) 0.8
Unit V V V V
2738 tbl 06
Capacitance
Symbol CIN COUT
(1)
(TA = +25C, f = 1.0MHz)
Conditions
(2)
VIH VIL
Parameter Input Capacitance Output Capacitance
Max. 9 10
Unit pF pF
2738 tbl 07
VIN = 3dV VOUT = 3dV
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. These parameters are determined by device characterization but are not production tested (TQFP Package only). 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
6.42 4
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
7005S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___ ___ ___
7005L Max. 10 10 0.4
___
Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
2738 tbl 08
2.4
2.4
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
Data Retention Characteristics Over All Temperature RangeS (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2V CE > VHC VIN > VHC or < VLC tCDR tR
(3) (3)
Test Condition
Min. 2.0
Typ. (1)
___
Max.
___
Unit V A
Mil. & Ind. Com'l.
___ ___
100 100
___ ___
4000 1500
___ ___
Chip Deselect to Data Retention Time Operation Recovery Time
SEM > VHC
0 tRC
(2)
ns ns
2738 tbl 09
NOTES: 1. TA = +25C, VCC = 2V, and are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR VDR CE VIH VIH
2738 drw 05
VDR > 2V
4.5V tR
6.42 5
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6) (VCC = 5.0V 10%)
7005X15 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Open SEM = VIH f = fMAX (3) Version COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (2) 170 160
____ ____
7005X17 Com'l Only Typ. (2) 170 160
____ ____
7005X20 Com'l & Military Typ. (2) 160 150 160 150 20 10 20 10 95 85 95 85 1.0 0.2 1.0 0.2 90 80 90 80 Max. 290 240 370 320 60 50 90 70 180 150 240 210 15 5 30 10 155 130 225 200
7005X25 Com'l & Military Typ. (2) 155 145 155 145 16 10 16 10 90 80 90 80 1.0 0.2 1.0 0.2 85 75 85 75 Max. 265 220 340 280 60 50 80 65 170 140 215 180 15 5 30 10 145 120 200 170
2738 tbl 10
Max. 310 260
____ ____
Max. 310 260
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH SEMR = SEML = VIH f = fMAX (3)
20 10
____ ____
60 60
____ ____
20 10
____ ____
60 50
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Open, f=fMAX (3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open f = fMAX (3)
105 95
____ ____
190 160
____ ____
105 95
____ ____
190 160
____ ____
mA
ISB3
Full Standby Current (Both Ports - All CMOS Level Inputs)
1.0 0.2
____ ____
15 5
____ ____
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
100 90
____ ____
170 140
____ ____
100 90
____ ____
170 140
____ ____
mA
7005X35 Com'l, Ind & Military Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Open SEM = VIH f = fMAX (3) Version COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (2) 150 140 150 140 13 10 13 10 85 75 85 75 1.0 0.2 1.0 0.2 80 70 80 70 Max. 250 210 300 250 60 50 80 65 155 130 190 160 15 5 30 10 135 110 175 150
7005X55 Com'l, Ind & Military Typ. (2) 150 140 150 140 13 10 13 10 85 75 85 75 1.0 0.2 1.0 0.2 80 70 80 70 Max. 250 210 300 250 60 50 80 65 155 130 190 160 15 5 30 10 135 110 175 150
7005X70 Military Only Typ. (2)
____ ____
Max.
____ ____
Unit mA
140 130
____ ____
300 250
____ ____
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH SEMR = SEML = VIH f = fMAX (3)
mA
10 8
____ ____
80 65
____ ____
ISB2
Standby Current (One Port - TTL Level Inputs)
CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Open, f=fMAX (3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open f = fMAX (3)
mA
80 70
____ ____
190 160
____ ____
ISB3
Full Standby Current (Both Ports - All CMOS Level Inputs)
mA
1.0 0.2
____ ____
30 10
____ ____
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
mA
75 65
175 150
2738 tbl 11
NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VCC = 5V, TA = +25C and are not production tested. ICC DC = 120mA (typ) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the port opposite port "A". 6. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42 6
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
5V 5V 1250 DATAOUT BUSY INT DATAOUT 775 30pF 775 5pF* 1250
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1 and 2
2738 tbl 12
2738 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW) *Including scope and jig
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4,5)
7005X15 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time
(3)
7005X17 Com'l Only Min. Max.
7005X20 Com'l & Military Min. Max.
7005X25 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
15
____ ____ ____
____
17
____ ____ ____
____
20
____ ____ ____
____
25
____ ____ ____
____
ns ns ns ns ns ns ns ns ns ns ns
2738 tbl 13 a
15 15 10
____ ____
17 17 10
____ ____
20 20 12
____ ____
25 25 13
____ ____
Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2)
3 3
____
3 3
____
3 3
____
3 3
____
Output High-Z Time (1,2) Chip Enable to Power Up Time
(2,5) (2,5)
10
____
10
____
12
____
15
____
0
____
0
____
0
____
0
____
Chip Disable to Power Down Time
15
____
17
____
20
____
25
____
Semaphore Flag Update Pulse (OE or SEM) Semaphore Address Access Time
10
____
10
____
10
____
10
____
15
17
20
25
7005X35 Com'l, Ind & Military Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time
(3)
7005X55 Com'l, Ind & Military Min. Max.
IDT7005X70 Military Only Min. Max. Unit
Parameter
Min.
Max.
35
____ ____ ____
____
55
____ ____ ____
____
70
____ ____ ____
____
ns ns ns ns ns ns ns ns ns ns ns
2738 tbl 13b
35 35 20
____ ____
55 55 30
____ ____
70 70 35
____ ____
Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2)
3 3
____
3 3
____
3 3
____
Output High-Z Time (1,2) Chip Enab le to Power Up Time (2,5) Chip Disable to Power Down Time
(2,5)
15
____
25
____
30
____
0
____
0
____
0
____
35
____
50
____
50
____
Semaphore Flag Update Pulse (OE or SEM) Semaphore Address Access Time
15
____
15
____
15
____
35
55
70
NOTES: 1. Transition is measured 500mV from Low or High impedance voltage with load (Figures 1 and 2). 2. This parameter is guaranteed but not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42 7
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles
ADDR
(5)
tRC
CE
tAA(4) tACE(4) tAOE(4)
OE
R/W tLZ(1) DATAOUT VALID DATA
(4)
tOH
tHZ(2) BUSYOUT tBDD(3,4)
2738 drw 07
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH.
Timing of Power-Up Power-Down
CE ICC ISB
2738 drw 08
tPU
tPD
,
6.42 8
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5,6)
7005X15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time
(4) (1,2) (3)
7005X17 Com'l Only Min. Max.
7005X20 Com'l & Military Min. Max.
7005X25 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
15 12 12 0 12 0 10
____
____ ____ ____ ____ ____ ____ ____
17 12 12 0 12 0 10
____
____ ____ ____ ____ ____ ____ ____
20 15 15 0 15 0 15
____
____ ____ ____ ____ ____ ____ ____
25 20 20 0 20 0 15
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns ns ns
2738 tbl 14a
10
____
10
____
12
____
15
____
0
____
0
____
0
____
0
____
Write Enable to Output in High-Z(1,2) Output Active from End-of-Write (1,2,4) SEM Flag Write to Read Time SEM Flag Contention Window
10
____ ____ ____
10
____ ____ ____
12
____ ____ ____
15
____ ____ ____
0 5 5
0 5 5
0 5 5
0 5 5
7005X35 Com'l, Ind & Military Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time
(4) (1,2) (1,2) (3)
7005X55 Com'l, Ind & Military Min. Max.
7005X70 Military Only Min. Max. Unit
Parameter
Min.
Max.
35 30 30 0 25 0 15
____
____ ____ ____ ____ ____ ____ ____
55 45 45 0 40 0 30
____
____ ____ ____ ____ ____ ____ ____
70 50 50 0 50 0 40
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns ns ns
2738 tbl 14b
15
____
25
____
30
____
0
____
0
____
0
____
Write Enable to Output in High-Z
15
____ ____ ____
25
____ ____ ____
30
____ ____ ____
Output Active from End-of-Write (1,2,4) SEM Flag Write to Read Time SEM Flag Contention Window
0 5 5
0 5 5
0 5 5
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (S or L). 6. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42 9
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC ADDRESS tHZ(7) OE tAW CE or SEM
(9)
tAS(6) R/W tWZ(7) DATAOUT
(4)
tWP(2)
tWR(3)
tOW
(4)
tDW DATAIN
tDH
2738 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC ADDRESS tAW CE or SEM(9) tAS(6) R/W tDW DATAIN
2738 drw 10
tEW(2)
tWR(3)
tDH
NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIH and SEM = VIL. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42 10
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS tAW SEM tEW tDW DATA0 tAS R/W tSWRD OE
Write Cycle
tOH
VALID ADDRESS tWR tACE
tSOP DATA OUT VALID
DATAIN VALID tWP tDH
tAOE tSOP
Read Cycle
2738 drw 11
NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A" MATCH
SIDE
(2)
"A"
R/W"A"
SEM"A" tSPS A0"B"-A2"B" MATCH
SIDE
(2)
"B"
R/W"B"
SEM"B"
2738 drw 12
NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port A may be either left or right port. B is the opposite from port A. 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42 11
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7)
7005X15 Com'l Only Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Acce ss Time from Chip Enable Low BUSY Acce ss Time from Chip Enable High Arbitration Priority Set-up Time(2) BUSY Disable to Valid Data(3) Write Hold After BUSY
(5)
____ ____ ____ ____
7005X17 Com'l Only Min. Max.
7005X20 Com'l & Military Min. Max.
7005X25 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
15 15 15 15
____
____ ____ ____ ____
17 17 17 17
____
____ ____ ____ ____
20 20 20 17
____
____ ____ ____ ____
20 20 20 17
____
ns ns ns ns ns ns ns
5
____
5
____
5
____
5
____
18
____
18
____
30
____
30
____
12
13
15
17
BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY
(5)
0 12
____ ____
0 13
____ ____
0 15
____ ____
0 17
____ ____
ns ns
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay
(1)
____ ____
30 25
____ ____
30 25
____ ____
45 35
____ ____
50 35
ns ns
2738 tbl 15a
7005X35 Com'l, Ind & Military Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Acce ss Time from Chip Enable Low BUSY Acce ss Time from Chip Enable High Arbitration Priority Set-up Time(2) BUSY Disable to Valid Date(3) Write Hold After BUSY(5)
____ ____ ____ ____
7005X55 Com'l, Ind & Military Min. Max.
7005X70 Military Only Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20
____
____ ____ ____ ____
45 40 40 35
____
____ ____ ____ ____
45 40 40 35
____
ns ns ns ns ns ns ns
5
____
5
____
5
____
35
____
40
____
45
____
25
25
25
BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY
(5)
0 25
____ ____
0 25
____ ____
0 25
____ ____
ns ns
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay
(1)
____ ____
60 45
____ ____
80 65
____ ____
95 80
ns ns
2738 tbl 15b
NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD tWP (actual) or tDDD tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention with port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (S or L). 7. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42 12
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read with BUSY(2,5) (M/S = VIH)(4)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B"
(1)
tDH VALID
MATCH tBDA tBDD
BUSY"B" tWDD DATAOUT "B" tDDD
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
(3) 2738 drw 13
VALID
Timing Waveform of Write with BUSY
tWP R/W"A" tWB(3) BUSY"B" tWH
(1)
R/W"B"
NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH 3. tWB is only for the 'Slave' Version..
(2) 2738 drw 14
6.42 13
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A" and "B" ADDRESSES MATCH
CE"A" tAPS(2) CE"B" tBAC BUSY"B"
2738 drw 15
tBDC
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH)
ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
2738 drw 16 (2)
ADDRESS "N"
MATCHING ADDRESS "N" tBDA
NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2)
7005X15 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____ ____ ____
7005X17 Com'l Only Min. Max.
7005X20 Com'l & Military Min. Max.
7005X25 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
0 0
____ ____
____ ____
0 0
____ ____
____ ____
0 0
____ ____
____ ____
ns ns ns ns
2738 tb l 16a
15 15
15 15
20 20
20 20
7005X35 Com'l, Ind & Military Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____ ____ ____
7005X55 Com'l, Ind & Military Min. Max.
7005X70 Military Only Min. Max. Unit
Parameter
Min.
Max.
0 0
____ ____
____ ____
0 0
____ ____
____ ____
ns ns ns ns
2738 tb l 16b
25 25
40 40
50 50
NOTES: 1. 'X' in part number indicates power rating (S or L). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42 14
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC ADDR"A" tAS(3) CE"A" INTERRUPT SET ADDRESS(2) tWR(4)
R/W"A" tINS(3) INT"B"
2738 drw 17
tRC ADDR"B" tAS(3) CE"B" INTERRUPT CLEAR ADDRESS(2)
OE"B" tINR(3) INT"B"
2738 drw 18
NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III Interrupt Flag(1,4)
Left Port R/WL L X X X CEL L X X L OEL X X X L A12L-A0L 1FFF X X 1FFE INTL X X L
(3) (2)
Right Port R/WR X X L X CER X L L X OER X L X X A12R-A0R X 1FFF 1FFE X INTR L
(2) (3)
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
2738 tbl 17
H
X X
H
NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up.
6.42 15
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV Address BUSY Arbitration
Inputs CEL X H X L CER X X H L AOL-A12L AOR-A12R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
2738 tbl 18
NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions No Action Left Port Writes "0" to Semaphore Rig ht Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Rig ht Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Rig ht Port Writes "0" to Semaphore Rig ht Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D7 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free
2738 tbl 19
Status
NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2. 3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
The IDT7005 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7005 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted.
Functional Description
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE
Interrupts
(HEX), where a write is defined as CE = R/W= VIL per Truth Table III. The left port clears the interrupt through access of address location 1FFE when CE = OE = VIL. For this example, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (8 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation.
6.42 16
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
MASTER CE Dual Port RAM BUSY (L) BUSY (R)
SLAVE CE Dual Port RAM BUSY (L) BUSY (R)
BUSY (L)
MASTER CE Dual Port RAM BUSY (L) BUSY (R)
SLAVE CE Dual Port RAM BUSY (L) BUSY (R)
BUSY (R)
,
2738 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7005 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.
Busy Logic
address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
When expanding an IDT7005 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7005 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and
Width Expansion with Busy Logic Master/Slave Arrays
The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designers software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT7005 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7005's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying
Semaphores
6.42 17
DECODER
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
configurations. The IDT7005 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems.
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphores status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7005 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location,that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one sides output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must
How the Semaphore Flags Work
cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other sides semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first sides request latch. The second sides flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
Perhaps the simplest application of semaphores is their application as resource markers for the IDT7005s Dual-Port RAM. Say the 8K x 8 RAM was to be divided into two 4K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and
Using SemaphoresSome Examples
6.42 18
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was off-limits to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE
D Q
R PORT SEMAPHORE REQUEST FLIP FLOP
Q D
D0 WRITE
SEMAPHORE READ
Figure 4. IDT7005 Semaphore Logic
SEMAPHORE READ
2738 drw 20
,
6.42 19
IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0C to +70C) I(1) Industrial (-40C to +85C) B Military (-55C to +125C) Compliant to MIL-PRF-38538 QML PF G J F 15 17 20 25 35 55 70 S L 7005 64-pin TQFP (PN64-1) 68-pin PGA (G68-1) 68-pin PLCC (J68-1) 68-pin Flatpack (F64-1) Commercial Only Commercial Only Commercial & Military Commercial & Military Commercial, Industrial & Military Commercial, Industrial & Military Military Only Standard Power Low Power 64K (8K x 8) Dual-Port RAM
2738 drw 21
Speed in nanoseconds
NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For other speeds, packages and powers contact your sales office.
Datasheet Document History
12/21/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 & 3 Added additional notes to pin configurations Changed drawing format
6/3/99
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6.42 20
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