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6B273 8-BIT LATCHED DMOS POWER DRIVER
6B273
8-BIT LATCHED DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. The DMOS output inverts the DATA input. All of the output drivers are disabled (the DMOS sink drivers turned OFF) with the CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs are capable of sinking up to 500 mA. Similar devices with reduced rDS(on) will be available as the A6273. The A6B273KA is furnished in a 20-pin dual in-line plastic package. The A6B273KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85C.
Data Sheet 26180.122
PRODUCT PREVIEW
(Subject to change without notice) January 5, 1999
CLEAR IN 1 IN 2 OUT 1 OUT 2 OUT 3 OUT 4 IN 3 IN 4 GROUND
1 2 3 4
VDD
20 19 18 17
LOGIC SUPPLY IN 8 IN 7 OUT 8 OUT 7 OUT 6 OUT 5 IN 6 IN 5 STROBE
LATCHES
LATCHES
5 6 7 8 9 10
16 15 14 13 12 11
Dwg. PP-015-2
Note that the A6B273KA (DIP) and the A6B273KLW (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T A = 25C
Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 150 mA* Peak, IOM ................................... 500 mA Single-Pulse Avalanche Energy, EAS ................................................. 30 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40C to +125C Storage Temperature Range, TS ................................. -55C to +150C
* Each output, all outputs on. Pulse duration 100 s, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s 50 V Minimum Output Clamp Voltage s 150 mA Output Current (all outputs simultaneously) s 5 Typical rDS(on) s Low Power Consumption s Replacements for TPIC6B273N and TPIC6B273DW
This document contains information on a product under development. Allegro MicroSystems, Inc. reserves the right to change or discontinue this product without notice.
Always order by complete part number: Part Number Package A6B273KA 20-pin DIP A6B273KLW 20-lead SOIC
RJA 55C/W 70C/W
RJC 25C/W 17C/W
6B273 8-BIT LATCHED DMOS POWER DRIVER
LOGIC SYMBOL
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
1 11
SU FF IX
R C1 1D 1D 1D 1D 1D 1D 1D 1D 4 5 6 7 14 15 16 17
2.0
2
'A ', R
1.5
SU FF IX
J
3
A=
'LW ', R
55 C /W
8 9
1.0
J A=
70 C /W
12 13 18
0.5
0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150
19
Dwg. GS-004A
Dwg. FP-046-1
VDD IN
OUT
Dwg. EP-010-16
Dwg. EP-063
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
CLEAR
L H H H
Inputs STROBE
X
INX
X H L X
OUT X
H L H R
L
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
115 Northeast Cutoff, Box 15036 W Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1999, Allegro MicroSystems, Inc.
6B273 8-BIT LATCHED DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
IN 1 STROBE
D C1 CLR
OUT 1
IN2 LOGIC SUPPLY IN 3 V DD
D C1 CLR D C1 CLR
OUT 2
OUT 3
IN 4
D C1 CLR
OUT 4
IN5
D C1 CLR
OUT 5
IN6
D C1 CLR
OUT 6
IN 7
D C1 CLR
OUT 7
IN8
D C1
OUT 8 GROUND
CLEAR
(ACTIVE LOW)
CLR
Dwg. FP-016-2
6B273 8-BIT LATCHED DMOS POWER DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified).
Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol VDD V (BR)DSX IDSX Test Conditions Operating IO = 1 mA VO = 40 V, V DD = 5.5 V VO = 40 V, V DD = 5.5 V, TA = 125C Min. 4.5 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 5.0 -- 0.1 0.15 4.2 6.8 5.5 90 -- -- 150 90 200 200 20 150 Max. 5.5 -- 5.0 8.0 5.7 9.5 8.0 -- 1.0 -1.0 -- -- -- -- 100 300 Units V V A A mA A A ns ns ns ns A A
rDS(on)
IO = 100 mA, VDD = 4.5 V IO = 100 mA, VDD = 4.5 V, TA = 125C IO = 350 mA, VDD = 4.5 V (see note)
Nominal Output Current Logic Input Current
ION IIH IIL
VDS(on) = 0.5 V, TA = 85C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF VDD = 5.5 V, Outputs off VDD = 5.5 V, Outputs on
Prop. Delay Time
tPLH tPHL
Output Rise Time Output Fall Time Supply Current
tr tf IDD(OFF) IDD(ON)
Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 s, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273 8-BIT LATCHED DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
50%
50%
t su(D) STROBE
t h(D)
50%
t su(D)
t h(D)
t PLH OUTPUTx
10%
t PHL
90%
tr
tf
Dwg. WP-036-1
Input Active Time Before Strobe (Data Set-Up Time), tsu(D) .............................................. 20 ns Input Active Time After Strobe (Data Hold Time), th(D) ................................................... 20 ns Input Pulse Width, tw(D) ....................................................... 40 ns Input Logic High, VIH ................................................ 0.85VCC Input Logic Low, VIL ................................................. 0.15VCC
6B273 8-BIT LATCHED DMOS POWER DRIVER
TEST CIRCUITS
INPUT +15 V
tav IAS = 500 mA IO DUT
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066
E AS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit and Waveforms
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
200 mH
10.5
6B273 8-BIT LATCHED DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
Terminal No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name CLEAR Function When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF). CMOS data input to a latch. When strobed, the output then inverts the data input (IN1 = HIGH, OUT 1 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN2 = HIGH, OUT 2 = LOW). Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. CMOS data input to a latch. When strobed, the output then inverts the data input (IN3 = HIGH, OUT 3 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN4 = HIGH, OUT 4 = LOW). Reference terminal for all voltage measurements. A CMOS dynamic input to all latches. Data on each INx terminal is loaded into its associated latch on a low-to-high STROBE transition. CMOS data input to a latch. When strobed, the output then inverts the data input (IN5 = HIGH, OUT 5 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN6 = HIGH, OUT 6 = LOW). Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. CMOS data input to a latch. When strobed, the output then inverts the data input (IN7 = HIGH, OUT 7 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN8 = HIGH, OUT 8 = LOW). (VDD ) The logic supply voltage (typically 5 V).
IN1 IN2
OUT 1 OUT 2 OUT 3 OUT 4
IN3 IN4
GROUND STROBE
IN5 IN6
OUT5 OUT6 OUT7 OUT8
IN7 IN8
LOGIC SUPPLY
6B273 8-BIT LATCHED DMOS POWER DRIVER
A6B273KA
Dimensions in Inches (controlling dimensions)
20 11 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
0.100 1.060 0.980
BSC
10
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-20 in
Dimensions in Millimeters (for reference only)
20
11
0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
2.54 26.92 24.89
BSC
10
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-20 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273 8-BIT LATCHED DMOS POWER DRIVER
A6B273KLW
Dimensions in Inches (for reference only)
20 11 0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
1
2
3 0.5118 0.4961
0.050
BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-20 in
Dimensions in Millimeters (controlling dimensions)
20 11 0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
1
2
3 13.00 12.60
1.27
BSC
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-20 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
6B273 8-BIT LATCHED DMOS POWER DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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