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HM628128B Series
131,072-word x 8-bit High speed CMOS Static RAM
ADE-203-243B (Z) Rev. 2.0 Mar. 20, 1995 Description
The Hitachi HM628128B is a CMOS static RAM organized 131,072-word x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 m Hi-CMOS shrink process technology. It offers low power standby power dissipation, therefore, it is suitable for battery backup systems. The device, packaged in a 525 mil SOP or a 8 mm x 20 mm TSOP or a 600 mil plastic DIP is available.
Features
* High speed Fast access time: 70/85ns (max) * Low power Standby: 10 W (typ) (L/L-SL version) Operation: 50 mW/MHz (typ) * Single 5 V supply * Completely static memory No clock or timing strobe required * Equal access and cycle times * Common data input and output Three state output * Directly TTL compatible All inputs and outputs * Capability of battery backup operation (L/L-SL version) 2 chip selection for battery backup
HM628128B Series
Ordering Information
Type No. HM628128BLP-7 HM628128BLP-8 HM628128BLP-7SL HM628128BLP-8SL HM628128BLFP-7 HM628128BLFP-8 HM628128BLFP-7SL HM628128BLFP-8SL HM628128BLT-7 HM628128BLT-8 HM628128BLT-7SL HM628128BLT-8SL HM628128BLR-7 HM628128BLR-8 HM628128BLR-7SL HM628128BLR-8SL Access Time 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns Data Retention Current 50 A 50 A 15 A 15 A 50 A 50 A 15 A 15 A 50 A 50 A 15 A 15 A 50 A 50 A 15 A 15 A Reverse-bend type 32-pin plastic 8 mm x 20 mm TSOP (TFP-32DR) Normal-bend type 32-pin plastic 8 mm x 20 mm TSOP (TFP-32D) 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32)
2
HM628128B Series
Pin Arrangement
HM628128BT Series (Normal Type TSOP)
A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
HM628128BP/BFP Series NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
(Top View) HM628128BR Series (Reverse Type TSOP)
A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1 A10 OE
(Top View)
Pin Description
Pin Name A0 - A16 I/O0 - I/O7 CS1 CS2 WE OE NC VCC VSS Function Address Input/output Chip select 1 Chip select 2 Write enable Output enable No connection Power supply Ground
3
HM628128B Series
Block Diagram
LSB
A8 A13 A4 A5 A6 A7 A12 A14 A15
MSB
* * * * *
V CC V SS
Row Decoder
Memory Matrix 512 x 2,048
I/O0 Input Data Control I/O7
* *
Column I/O Column Decoder
* *
LSB MSB A0 A1 A2 A3 A10 A11A9 A16
* *
CS2 CS1 WE OE
Timing Pulse Generator Read/Write Control
4
HM628128B Series
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5 to V CC + 0.3 1.0 0 to +70 -55 to +125 -10 to +85
*1 *2
Unit V V W C C C
Notes: 1. -3.0 V for pulse half-width 30 ns 2. Maximum voltage is 7.0 V.
Function Table
WE X X H H L L Note: CS1 H X L L L L CS2 X L H H H H OE X X H L H L Mode Not selected Not selected Output disable Read Write Write VCC Current I SB , I SB1 I SB , I SB1 I CC I CC I CC I CC I/O Pin High-Z High-Z High-Z Dout Din Din Ref. Cycle -- -- -- Read cycle Write cycle (1) Write cycle (2)
1. X: H or L
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high voltage ( logic 1 ) Input low voltage ( logic 0 ) Note: VIH VIL Min 4.5 0 2.2 -0.3
*1
Typ 5.0 0 -- --
Max 5.5 0 VCC + 0.3 0.8
Unit V V V V
1. -3.0 V for pulse half-width 30ns
5
HM628128B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5V 10 %, VSS = 0 V)
Parameter Input leakage current Output leakage current Symbol |ILI| |ILO | Min -- -- Typ*1 -- -- Max 1 1 Unit A A Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/V IL, I I/O = 0mA Min.cycle, duty = 100 %, CS1 = VIL, CS2 = VIH, Others = VIH/V IL, I I/O = 0 mA Cycle time = 1 s, duty = 100 % I I/O = 0 mA, CS1 0.2 V CS2 V CC - 0.2 V, Others = VIH/V IL VIH V CC - 0.2 V, VIL 0.2 V CS2 = VIL or CS2 = VIH, CS1 =VIH 0V Vin V CC , (1) 0 V CS2 0.2V or (2) CS2 V CC - 0.2V , CS1 V CC - 0.2V
Operating power supply current : DC Operating power supply current
I CC I CC1
-- --
15 35
25 70
mA mA
I CC2
--
10
20
mA
Standby V CC current : DC Standby V CC current (1): DC
I SB I SB1
-- --
1 2
*2
2 100
*2
mA A
-- Output low voltage Output high voltage VOL VOH -- 2.4
2*3 -- --
50*3 0.4 --
A V V I OL = 2.1 mA I OH = -1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. For L-version 3. For L-SL version
Capacitance (Ta = 25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin C
*1
Min -- --
Typ -- --
Max 8 10
Unit pF pF
Test Conditions Vin = 0 V VI/O = 0 V
*1 I/O
1. This parameter is sampled and not 100 % tested.
6
HM628128B Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * Input pulse levels : 0.8 V to 2.4 V Input rise and fall time : 5 ns Input and output timing reference levels : 1.5 V Output load : 1 TTL Gate and C L ( 100 pF ) ( Including scope and jig )
Read Cycle
HM628128B -7 Parameter Read cycle time Address access time Chip selection to output valid Symbol t RC t AA t CO1 t CO2 Output enable to output valid Chip selection to output in low-Z t OE t LZ1 t LZ2 Output enable to output in low-Z Chip deselection to output in high-Z t OLZ t HZ1 t HZ2 Output disable to output in high-Z Output hold from address change t OHZ t OH Min 70 -- -- -- -- 10 10 5 0 0 0 10 Max -- 70 70 70 35 -- -- -- 25 25 25 -- -8 Min 85 -- -- -- -- 10 10 5 0 0 0 10 Max -- 85 85 85 45 -- -- -- 30 30 30 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
Notes: 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device to device. 3. This parameter is sampled and not 100% tested.
7
HM628128B Series
Read Cycle Timing (WE = VIH)
t RC
Address
Valid address t AA
CS1 t CO1 t LZ1 CS2 t CO2 t LZ2 t HZ2 t HZ1
OE t OE t OLZ Dout High Impedance t OHZ t OH Valid data
8
HM628128B Series
Write Cycle
HM628128B -7 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Write hold from write time Output active from end of write Output disable to output in High-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 70 60 0 60 50 0 0 30 0 5 0 Max -- -- -- -- -- -- 25 -- -- -- 25 -8 Min 85 75 0 75 55 0 0 35 0 5 0 Max -- -- -- -- -- -- 30 -- -- -- 25 Unit ns ns ns ns ns ns ns ns ns ns ns 6 5 1, 7 4 5, 6 2 3 Notes
Notes: 1. A write occures during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 6. This parameter is sampled and not 100% tested. 7. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of date bus contention, tWP tDW (min) + tWHZ (mix).
9
HM628128B Series
Write Cycle Timing (1) (OE Clock)
t WC Address Valid address t AW OE t CW
CS1
*1
t WR
CS2 t AS WE t OHZ High Impedance Dout t DW Din t DH t WP
Valid data Note: 1. If the CS1 goes low or CS2 goes high simultaneously with WE going low or after the WE going low, the outputs remain in a high impedance state.
10
HM628128B Series
Write Cycle Timing (2) (OE low fix)
t WC Address
Valid address t CW t WR
CS1
*1
CS2
t AW t WP WE t AS t WHZ t OW
*2 *3
t OH
Dout t DW Din High Impedance t DH
*4
Valid data
Notes: 1. If the CS1 goes low or CS2 goes high simultaneously with WE going low or after the WE going low, the outputs remain in a high impedance state. 2.Dout is the same phase of the latest written data in this write cycle. 3.Dout is the read date of next address. 4.If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of opposite phase to the outputs must not be applied to them.
11
HM628128B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ*3 -- Max -- Unit V Test conditions*4 0 V Vin V CC, (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V VCC = 3 V, 0 V Vin 3 V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V
Data retention current
I CCDR (L)
--
1
50*1
A
(L-SL) Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. t CDR tR
-- 0 5
1 -- --
15*2 -- --
A ns ms See retention waveform
This characteristics is guaranteed only for L-version, 20 A max at Ta = 0 to 40C. This characteristics is guaranteed only for L-SL version, 3 A max at Ta = 0 to 40C. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 VSS - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low V CC Data Retention Waveform (1) (CS1 Controlled)
t CDR V CC 4.5 V Data retention mode tR
2.2 V V DR1 CS1 0V CS1 > VCC - 0.2 V
12
HM628128B Series
Low V CC Data Retention Waveform (2) (CS2 Controlled)
t CDR V CC 4.5 V CS2 V DR2 0.4 V 0 V < CS2 < 0.2 V 0V Data retention mode tR
13
HM628128B Series
Package Dimensions
HM628128BLP Series (DP-32)
41.90 42.50 Max Unit: mm
32
17 13.40 13.70 Max
1 2.30 Max
5.08 Max
1.20
16 15.24
0.51 Min 2.54 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
HM628128BLFP Series (FP-32D)
20.45 20.95 Max 32 17
Unit: mm
1 1.00 Max
16 3.00 Max 14.14 0.30
+ 0.13 - 0.07
11.30
1.42
0.22
1.27
0.10 0.40 + 0.05 -
0.10 0.15 M
+ 0.12 - 0.10
0-8 0.80 0.20
14
0.15
HM628128B Series
HM628128BLT Series (TFP-32D)
8.00 8.20 Max 32 17
Unit: mm
1 0.20 0.10
16 0.50 0.08 M 0.45 Max 20.00 0.20 0 - 5 0.17 0.05 0.13 0.05 0.50 0.10 0.80
1.20 Max
0.10
18.40
15
HM628128B Series
HM628128BLR Series (TFP-32DR)
8.00 8.20 Max 17 32
Unit: mm
16 0.20 0.10
1 0.50 0.08 M 0.45 Max 20.00 0.20 0 - 5 0.17 0.05 0.13 0.05 0.50 0.10 0.80
1.20 Max
0.10
16
18.40

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