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| PRELIMINARY DATA ST10C167 16-bit MCU with 32KByte ROM s High performance CPU q q 16 32KByte ROM 32 CPU-Core 16 Internal RAM q q q q Port 4 Port 1 Port 0 GPT1 q 16-bit CPU with 4-stage pipeline. 80ns instruction cycle time at 25MHz CPU clock. 400ns 16 x 16-bit multiplication. 800ns 32 / 16-bit division. Enhanced boolean bit manip facilities. Additional instructions to support HLL and operating systems. Single-cycle context switching support. 16 16 16 PEC XRAM 16 Watchdog OSC. Interrupt Controller CAN 16 ASC usart CAPCOM2 10-Bit ADC PWM SSC GPT2 q q q q 32K Bytes on-chip ROM memory. Up to 16 MBytes linear address space for code and data (5 MByte with CAN). 2KByte on-chip internal RAM (IRAM). 2KByte on-chip extension RAM (XRAM). Programmable external bus characteristics for different address ranges. 8-Bit or 16-bit external data bus. Multiplexed or demultiplexed external address/data buses. Five programmable chip-select signals. Hold-acknowledge bus arbitration support. 8-channel peripheral event controller for single cycle, interrupt driven data transfer. 16-priority-level interrupt system with 56 sources, sample-rate down to 40 ns. Two multi-functional general purpose timer units with 5 timers. Two 16-channel capture/compare units. 16-channel 10-bit. 7.76 s con version time Programmable watchdog timer. Oscillator Watchdog. Port 2 s Memory organization External Bus Controller CAPCOM1 16 8 BRG Port 3 15 BRG Port 7 8 Port 8 8 Port 6 8 Port 5 16 s Fast and flexible bus q s s s On-chip CAN 2.0b interface On-chip bootstrap loader Clock generation q q q q On-chip PLL. Direct or prescaled clock input. Individually programmable as input, output or special function. s Up to 111 general purpose I/O lines q q q s Interrupt q s s s Programmable drive strength Programmable threshold (hysteresis) Idle and power down modes q q Idle Current <70mA. Power down supply current <100 A. q s s 4-Channel PWM Unit Serial channels q q s Timers q Synchronous/async serial channel High-speed synchronous channel. C-compilers, macro-assembler packages, emulators, evaluation boards, HLL-debuggers, simulators, logic analyzer disassemblers, programming boards. s Development support q q s A/D converter q q s Fail-safe protection q q s Package q 144-Pin PQFP Package. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 3/4/98 1 PRELIMINARY DATA 1 2 3 4 5 6 7 8 9 9.1 9.2 10 11 12 13 14 15 16 17 18 19 Introduction - - - - - - - - - - - - - - - - - - - - - - - - - -4 Pin Data - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5 Functional Description - - - - - - - - - - - - - - - - - - - - 14 Memory Organization - - - - - - - - - - - - - - - - - - - - 15 Central Processing Unit (CPU) - - - - - - - - - - - - - - - - 16 External Bus Controller - - - - - - - - - - - - - - - - - - - - 17 Interrupt System - - - - - - - - - - - - - - - - - - - - - - - 18 Capture/Compare (CAPCOM) Units - - - - - - - - - - - - - 23 General Purpose Timer Unit - - - - - - - - - - - - - - - - - 25 GPT1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25 GPT2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 26 PWM Module - - - - - - - - - - - - - - - - - - - - - - - - 29 Parallel Ports - - - - - - - - - - - - - - - - - - - - - - - - - 30 A/D converter - - - - - - - - - - - - - - - - - - - - - - - - 31 Serial Channels - - - - - - - - - - - - - - - - - - - - - - - 32 CAN Module - - - - - - - - - - - - - - - - - - - - - - - - - 35 Watchdog Timer - - - - - - - - - - - - - - - - - - - - - - - 35 Instruction Set Summary - - - - - - - - - - - - - - - - - - - 36 System Reset - - - - - - - - - - - - - - - - - - - - - - - - 39 Power Reduction Modes - - - - - - - - - - - - - - - - - - - 40 Special Function Register Overview - - - - - - - - - - - - - 41 ST10C167 datasheet 42 1708 01 3/4/98 2 PRELIMINARY DATA 20 20.1 20.2 20.3 20.3.1 Electrical Characteristics - - - - - - - - - - - - - - - - - - - 51 Absolute maximum ratings - - - - - - - - - - - - - - - - - - 51 Parameter interpretation - - - - - - - - - - - - - - - - - - - 51 DC characteristics - - - - - - - - - - - - - - - - - - - - - - 52 A/D converter characteristics - - - - - - - - - - - - - - - - - - - - - 55 20.4 20.4.1 20.4.2 20.4.3 20.4.4 20.4.5 20.4.6 20.4.7 20.4.8 20.4.9 20.4.10 20.4.11 20.4.12 AC characteristics - - - - - - - - - - - - - - - - - - - - - - 57 Definition of internal timing Clock generation modes Prescaler operation - - - Direct drive - - - - - - - Oscillator watchdog (OWD) Phase locked loop - - - Memory cycle variables - External clock drive XTAL1 Multiplexed bus - - - - - Demultiplexed bus - - - CLKOUT and READY - External bus arbitration - 57 59 59 60 60 61 62 63 64 71 78 80 21 22 Package Mechanical Data - - - - - - - - - - - - - - - - - - 83 Ordering Information - - - - - - - - - - - - - - - - - - - - - 83 ST10C167 datasheet 42 1708 01 3/4/98 3 PRELIMINARY DATA 1 Introduction 1 Introduction The ST10C167 is a derivative of the SGS THOMSON ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed RAM and clock generation via PLL. VDD XTAL1 XTAL2 RSTIN RSTOUT VAREF VAGND NMI EA READY ALE RD WR/WRL Port 5 16-bit VSS Port 0 16-bit Port 1 16-bit Port 2 16-bit ST10C167 Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit Figure 1 Logic symbol ST10C167 datasheet 42 1708 01 3/4/98 4 2 2 Pin Data P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ST10C167 datasheet Pin Data Figure 2 Pin Configuration (top view) 42 1708 01 PRELIMINARY DATA ST10C167 3/4/98 VAREF VAGND P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD VSS VDD P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO VSS VDD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VSS VDD P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 POH.7/AD15 POH.6/AD14 POH.5/AD13 POH.4/AD12 POH.3/AD11 POH.2/AD10 POH.1/AD9 VSS VDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 POH.0/AD8 POL.7/AD7 POL.6/AD6 POL.5/AD5 POL.4/AD4 POL.3/AD3 POL.2AD2 POL.A/AD1 POL.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23 A22/CAN_TxD A21/CAN_RxD P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VPP VSS VDD P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN 5 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I/O O ... O I O O I/O I/O ... I/O Pin Number Function P6.0 -P6.7 1-8 Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0CS0Chip Select 0 Output ......... P6.4CS4Chip Select 4 Output P6.5HOLDExternal Master Hold Request Input P6.6HLDAHold Acknowledge Output P6.7BREQBus Request Output Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0CC16IOCAPCOM2: CC16 Cap.-In/Comp.Out ......... P8.7CC23IOCAPCOM2: CC23 Cap.-In/Comp.Out 1 ... 5 6 7 8 P8.0 -P8.7 916 9 ... 16 Table 1 Pin description ST10C167 datasheet 42 1708 01 3/4/98 6 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I/O O ... O I/O ... I/O I I I I I I I I Pin Number Function P7.0 -P7.7 19 -26 Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0POUT0PWM Channel 0 Output ......... P7.3POUT3PWM Channel 3 Output P7.4CC28IOCAPCOM2: CC28 Cap.-In/Comp.Out ......... P7.7CC31IOCAPCOM2: CC31 Cap.-In/Comp.Out Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10T6EUDGPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11T5EUDGPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12T6INGPT2 Timer T6 Count Input P5.13T5INGPT2 Timer T5 Count Input P5.14T4EUDGPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15T2EUDGPT1 Timer T2 Ext.Up/Down Ctrl.Input 19 ... 22 23 ... 26 P5.0 -P5.15 27-3 6 39-4 4 39 40 41 42 43 44 Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 7 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I/O I/O ... I/O I/O I ... I/O I I Pin Number Function P2.0 -P2.15 47-5 4 57-6 4 Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0CC0IOCAPCOM: CC0 Cap.-In/Comp.Out ......... P2.7CC7IOCAPCOM: CC7 Cap.-In/Comp.Out P2.8CC8IOCAPCOM: CC8 Cap.-In/Comp.Out, EX0INFast External Interrupt 0 Input ......... P2.15CC15IOCAPCOM: CC15 Cap.-In/Comp.Out, EX7INFast External Interrupt 7 Input T7INCAPCOM2 Timer T7 Count Input 47 ... 54 57 ... 64 Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 8 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I/O I/O I/O I O I O I I I I I/O I/O I/O O O I/O O Pin Number Function P3.0P3.13, P3.15 65-7 0, 73-0 , 81 Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0T0INCAPCOM Timer T0 Count Input P3.1T6OUTGPT2 Timer T6 Toggle Latch Output P3.2CAPINGPT2 Register CAPREL Capture Input P3.3T3OUTGPT1 Timer T3 Toggle Latch Output P3.4T3EUDGPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5T4INGPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6T3INGPT1 Timer T3 Count/Gate Input P3.7T2INGPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8MRSTSSC Master-Rec./Slave-Transmit I/O P3.9MTSRSSC Master-Transmit/Slave-Rec. O/I P3.10TxD0ASC0 Clock/Data Output (Asyn./Syn.) P3.11RxD0ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12BHEExt. Memory High Byte Enable Signal, WRHExt. Memory High Byte Write Strobe P3.13SCLKSSC Master Clock Outp./Slave Cl. Inp. P3.15CLKOUTSystem Clock Output (=CPU Clock) 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 9 PRELIMINARY DATA 2 Pin Data Input (I) Output(O) I/O O O I O O O O O I O I Pin Number Symbol Function P4.0 -P4.7 85-9 2 Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0A16Least Significant Segment Addr. Line P4.5A21Segment Address Line, CAN_RxDCAN Receive Data Input P4.6A22Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7A23Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the ST10C167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. 85 90 91 92 RD 95 WR/WRL 96 READY/ READY 97 ALE 98 EA 99 Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 10 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I/O I/O I I I I I O Pin Number Function PORT0: P0L.0P0L.7, P0H.0P0H.7 100107, 108, 111117 PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width:8-bit16-bit P0L.0 - P0L.7:D0 - D7D0 - D7 P0H.0 - P0H.7:I/OD8 - D15 Multiplexed bus modes: Data Path Width:8-bit16-bit P0L.0 - P0L.7:AD0 - AD7AD0 - AD7 P0H.0 - P0H.7:A8 - A15AD8 - AD15 PORT1: P1L.0P1L.7, P1H.0P1H.7 118125 128135 PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4CC24IOCAPCOM2: CC24 Capture Input P1H.5CC25IOCAPCOM2: CC25 Capture Input P1H.6CC26IOCAPCOM2: CC26 Capture Input P1H.7CC27IOCAPCOM2: CC27 Capture Input XTAL1:Input to the oscillator amplifier and input to the internal clock generator XTAL2:Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. 132 133 134 135 XTAL1 138 XTAL2 137 Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 11 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) I O I - Pin Number Function RSTIN 140 Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10C167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10C167 to go into power down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the A/D converter. Reference ground for the A/D converter. Flash programming voltage. This pin accepts the programming voltage for ST10F167 derivatives with on-chip flash memory. It is used also as the timing pin for the return from powerdown circuit and power-up asynchronous reset. RSTOUT 141 NMI 142 VAREF VAGND VPP/RPD 37 38 84 VDD 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 Digital Supply Voltage: + 5 V during normal operation and idle mode. > 2.5 V during power down mode Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 12 PRELIMINARY DATA 2 Pin Data Symbol Input (I) Output(O) - Pin Number Function VSS 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 Digital Ground. Table 1 Pin description (Continued) ST10C167 datasheet 42 1708 01 3/4/98 13 PRELIMINARY DATA 3 Functional Description 3 Functional Description The architecture of the ST10C167 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10C167. 16 32KByte ROM for ST10C167 32KByte flash for ST10F167 ROMless for ST10R167 32 CPU-Core 16 Internal RAM 16 PEC Watchdog XRAM 16 OSC. Interrupt Controller 16 CAN Port 0 GPT1 CAPCOM2 External Bus Controller 10-Bit ADC CAPCOM1 16 ASC usart Port 1 PWM SSC 16 Port 2 8 Port 4 GPT2 16 8 BRG Port 3 15 BRG Port 7 8 Port 8 Port 6 8 Port 5 16 Figure 3 Block diagram ST10C167 datasheet 42 1708 01 3/4/98 14 PRELIMINARY DATA 4 Memory Organization 4 Memory Organization The memory space of the ST10C167 is configured in a Von Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. ROM: 32KBytes of on-chip ROM. IRAM: 2KByte of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. The register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) general purpose registers. XRAM: 2KByte of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is connected to the internal XBUS and is accessed like an external memory in 16-bit demultiplexed bus-mode without waitstate or read/write delay (80 ns access @ 25 MHz CPU clock). Byte and word access is allowed. The XRAM address range is 00'E000h - 00'E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10C167's system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. If bit XRAMEN is cleared, then any access in the address range 00'E000h - 00'E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. SFR/ESFR: 1024 bytes (2 * 512 bytes) of address space is reserved for the special function register areas. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. CAN: Address range 00'EF00h - 00'EFFFh is reserved for the CAN Module access. The CAN is enabled by setting XPEN bit 2 of the SYSCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (byte accesses are possible). Two waitstates give an access time of 160 ns @25 Mhz CPU clock. No tristate waitstate is used. Note If the CAN module is used, Port 4 can not be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5 MBytes (1 MByte per CS line) In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. ST10C167 datasheet 42 1708 01 3/4/98 15 PRELIMINARY DATA 5 Central Processing Unit (CPU) 5 Central Processing Unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10C167's instructions can be executed in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16 bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles.The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. CPU SP STKOV STKUN 32KByte ROM for ST10C167 128KByte Flash for ST10F167 ROMless for ST10R167 Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MLD Mul./Div.-HW Bit-Mask Gen. R15 16 General ALU 16-Bit Barrel-Shift Context Ptr R0 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. Purpose Registers Internal RAM 2KByte R15 32 16 R0 Figure 4 CPU block diagram The CPU uses an actual register context consisting of up to 16 wordwide GPRs physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. ST10C167 datasheet 42 1708 01 3/4/98 16 PRELIMINARY DATA 6 External Bus Controller 6 External Bus Controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: * 16-/18-/20-/24-bit addresses16-bit data, demultiplexed * 16-/18-/20-/24-bit addresses16-bit data, multiplexed * 16-/18-/20-/24-bit addresses8-bit data, multiplexed * 16-/18-/20-/24-bit addresses8-bit data, demultiplexed In demultiplexed bus modes addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to 4 independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. Port 4 outputs all 8 address lines if an address space of 16 MBytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. ST10C167 datasheet 42 1708 01 3/4/98 17 PRELIMINARY DATA 7 Interrupt System 7 Interrupt System The interrupt response time for internal program execution is from 200 ns to 480ns. The ST10C167 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The ST10C167 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible ST10C167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: ST10C167 datasheet 42 1708 01 3/4/98 18 PRELIMINARY DATA 7 Interrupt System Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h Trap Number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 32h 33h 34h 35h Table 2 Interrupt sources ST10C167 datasheet 42 1708 01 3/4/98 19 PRELIMINARY DATA 7 Interrupt System Source of Interrupt or PEC Service Request CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit Request Flag CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR Enable Flag CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE Interrupt Vector CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT Vector Location 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00E0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h Trap Number 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h 26h 27h 28h ADEIR S0TIR ADEIE S0TIE ADEINT S0TINT 00'00A4h 00'00A8h 29h 2Ah Table 2 Interrupt sources (Continued) ST10C167 datasheet 42 1708 01 3/4/98 20 PRELIMINARY DATA 7 Interrupt System Source of Interrupt or PEC Service Request ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 CAN Interface X-Peripheral Node X-Peripheral Node PLL Unlock Request Flag S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch Trap Number 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h Table 2 Interrupt sources (Continued) Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: ST10C167 datasheet 42 1708 01 3/4/98 21 PRELIMINARY DATA 7 Interrupt System Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priorit y Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch -3Ch] Any [00'0000h- 00'01FCh] in steps of 4h 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] Any [00h - 7Fh] Current CPU Priority I I I I I NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II RESET RESET RESET 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III Table 3 Exceptions or error conditions that can arise during run-time ST10C167 datasheet 42 1708 01 3/4/98 22 PRELIMINARY DATA 8 Capture/Compare (CAPCOM) Units 8 Capture/Compare (CAPCOM) Units The ST10C167 has two 16 channel CAPCOM units. They support generation and control of timing sequences on up to 32 channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each register has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/ compare register, specific actions will be taken based on the selected compare mode. ST10C167 datasheet 42 1708 01 3/4/98 23 PRELIMINARY DATA 8 Capture/Compare (CAPCOM) Units Compare Modes Mode 0 Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Mode 1 Mode 2 Mode 3 Double Register Mode Table 4 Compare modes The input frequencies fTx for Tx are determined as a function of the CPU clocks. The formulas are detailed in the user manual. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 25MHz CPU clock are listed in the table below. The numbers for the timer periods are based on a reload value of 0000H. Note that some numbers may be rounded to 3 significant figures. fCPU = 25MHz Pre-scaler for fCPU Input Frequency Resolution Period Timer Input Selection TxI 000B 8 001B 16 010B 32 011B 64 100B 128 101B 256 110B 512 111B 1024 3.125 MHz 320ns 21.0 ms 1.56 MHz 640ns 41.9 ms 781 kHz 1.28 s 83.9 ms 391 kHz 2.56 s 167 ms 195 kHz 5.12 s 336 ms 97.7 kHz 10.24 s 671 ms 48.8 kHz 20.48 s 1.34 s 24.4 kHz 40.96 s 2.68 s Table 5 CAPCOM timer input frequencies, resolution and periods ST10C167 datasheet 42 1708 01 3/4/98 24 PRELIMINARY DATA 9 General Purpose Timer Unit GPT1 9 General Purpose Timer Unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 9.1 GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 6 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode. fCPU = 25MHz Timer Input Selection T2I / T3I / T4I 000B 001B 16 010B 32 011B 64 100B 128 101B 256 110B 512 111B 1024 Pre-scaler factor Input Freq 8 3.125 MHz 320 ns 1.563 MHz 640 ns 781.3 kHz 128 ns 390.6 kHz 2.56 s 195.3 kHz 5.12 s 97.66 kHz 10.24 s 671 ms 48.83 kHz 20.48 s 1.34 s 24.41 kHz 40.96 s 2.68 s Resolution Period 21.0 ms 41.9 ms 83.9 ms 167 ms 336 ms Table 6 GPT1 timer input frequencies, resolution and periods ST10C167 datasheet 42 1708 01 3/4/98 25 PRELIMINARY DATA 9 General Purpose Timer Unit The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. GPT2 9.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. ST10C167 datasheet 42 1708 01 3/4/98 26 PRELIMINARY DATA 9 General Purpose Timer Unit GPT2 The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. Table 7 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. fCPU = 25MHz Timer Input Selection T5I / T6I 000B Pre-scaler factor Input Freq 4 001B 8 010B 16 011B 32 100B 64 101B 128 110B 256 111B 512 6.25 MHz 160ns 3.125 MHz 320 ns 1.563 MHz 640 ns 781.3 kHz 128 ns 390.6 kHz 2.56 s 167 ms 195.3 kHz 5.12 s 336 ms 97.66 kHz 10.24 s 671 ms 48.83 kHz 20.48 s 1.34 s Resolution Period 10.49 ms 21.0 ms 41.9 ms 83.9 ms Table 7 GPT2 timer input frequencies, resolution and period ST10C167 datasheet 42 1708 01 3/4/98 27 PRELIMINARY DATA 9 General Purpose Timer Unit GPT2 T2EUD U/D GPT1 Timer T2 2n n=3...10 Interrupt Request CPU Clock T2IN T2 Mode Control Reload Capture CPU Clock 2n n=3...10 T3EUD T3 Mode Control T3OUT GPT1 Timer T3 U/D T3OTL T3IN T4IN CPU Clock T4 Mode Control 2n n=3...10 Capture Reload Interrupt Request Interrupt Request GPT1 Timer T4 U/D T4EUD Figure 5 Block diagram of GPT1 T5EUD U/D CPU Clock T5IN 2n n=2...9 T5 Mode Con- GPT2 Timer T5 Clear Capture Interrupt Request CAPIN GPT2 CAPREL Interrupt Request Reload Interrupt Request T6IN CPU Clock 2n n=2...9 T6 Mode Con- Toggle FF GPT2 Timer T6 U/D T60TL T6OUT to CAPCOM Timers T6EUD Figure 6 Block diagram of GPT2 ST10C167 datasheet 42 1708 01 3/4/98 28 PRELIMINARY DATA 10 PWM Module GPT2 10 PWM Module The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests. Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64 Resolution 40ns 2.56ns Resolution 40ns 2.56ns 8-bit 97.66 KHz 1.526KHz 8-bit 48.82KHz 762.9Hz 10-bit 24.41KHz 381.5 Hz 10-bit 12.20KHz 190.7 Hz 12-bit 6.104KHz 95.37Hz 12-bit 3.05KHz 47.68Hz 14-bit 1.526KHz 23.84Hz 14-bit 762.9Hz 11.92Hz 16-bit 0.381KHz 5.96Hz 16-bit 190.7Hz 0Hz Table 8 PWM unit frequencies and resolution at 25MHz CPU clock Figure 7 Block diagram of PWM module ST10C167 datasheet 42 1708 01 3/4/98 29 PRELIMINARY DATA 11 Parallel Ports 11 Parallel Ports The ST10C167 provides up to 111 I/O lines organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. The standard output drivers of the ST10C167 have a drive capability of 8 mA. But in order to reduce chip consumption and also noise generated by level transition of output pins, the ST10C167 offers programmable output drivers on Port 2, Port 3, Port 7 and Port 8 that can be switched by software from 8 mA strength to 4 mA strength. The high byte of the PICON register is used to select the output buffer strength for each byte of the indicated ports, i.e. the 8-bit port P7 and P8 are controlled by one bit each while ports P2 and P3 are controlled by two bits each. Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. ST10C167 datasheet 42 1708 01 3/4/98 30 PRELIMINARY DATA 12 A/D converter 12 A/D converter A10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. Overrun error detection/protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10C167 supports four different conversion modes: Single channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result. Single channel continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention. Auto scan mode the analog levels on a pre-specified number of channels are sequentially sampled and converted. Auto scan continuous mode the number of pre-specified channels is repeatedly sampled and converted. Channel Injection Mode injects a channel into a running sequence without disturbing this sequence. The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. The following table shows the ADC unit conversion clock, sample clock and complete conversion times. Conversion clock tcc 0.48 s reserved 1.92 s 0.96 s Sample clock tsc 0.48 s reserved 7.68 s 7.68 s 42.32 s 28.88 s ADCTC 00 01 10 11 ADSTC 00 01 10 11 Complete conversion 7.76 s Table 9 ADC sample clock and complete conversion times ST10C167 datasheet 42 1708 01 3/4/98 31 PRELIMINARY DATA 13 Serial Channels The A/D converter provides automatic offset and linearity self calibration. The calibration operation is performed in two ways: * A full calibration sequence is performed after a reset and lasts 1.6 ms minimum (@ 25MHz CPU clock). During this time, the ADBSY flag is set to indicate the operation. Normal conversion can be performed during this time. The duration of the calibration sequence is then extended by the time consumed by the conversions. Note After a power-on reset, the total unadjusted error (TUE) of the ADC might be worse than +-2 LSB (max. +-4 LSB). During the full calibration sequence, the TUE is constantly improved until at the end of the cycle, TUE is within the specified limits of +-2 LSB. * One calibration cycle is performed after each conversion: each calibration cycle takes 4 ADC clock cycles. These operation cycles ensure constant updating of the ADC's accuracy, compensating changing operating conditions. 13 Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous/synchronous serial channel (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated baud rate generators set up all standard baud rates without oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. ASCO Supports full-duplex asynchronous communication up to 781.25 KBaud and half-duplex synchronous communication up to 5MBaud @ 25MHz system clock. For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. The table below lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate. S0BRS = `0', fCPU = 25MHz Baud Rate (Baud) 781250 Deviation Error 0.0% S0BRS = `1', fCPU = 25MHz Baud Rate (Baud) 520833 Reload Value Deviation Error Reload Value 0000H 0.0% 0000H Table 10 Commonly used baud rates by reload value and deviation errors ST10C167 datasheet 42 1708 01 3/4/98 32 PRELIMINARY DATA 13 Serial Channels S0BRS = `0', fCPU = 25MHz Baud Rate (Baud) 56000 38400 19200 9600 4800 2400 1200 600 95 Deviation Error +7.3%/ -0.4% +1.7%/ -3.1% +1.7%/ -0.8% +0.5%/ -0.8% +0.5%/ -0.1% +0.2%/ -0.1% +0.0%/ -0.1% +0.0%/ -0.1% +0.4%/ 0.4% S0BRS = `1', fCPU = 25MHz Baud Rate (Baud) 56000 38400 19200 9600 4800 2400 1200 600 75 63 Reload Value Deviation Error Reload Value 000CH / 000DH 0013H / 0014H 0027H / 0028H 0050H/ 0051H 00A1H / 00A2H 0144H / 0145H 028AH / 028BH 0515H / 0516H 1FFFH / 1FFFH +3.3%/ -7.0% +4.3%/ -3.1% +0.5%/ -3.1% +0.5%/ -1.4% +0.5%/ -0.5% +0.0%/ -0.5% +0.0%/ -0.2% +0.0%/ -0.1% +0.0%/ 0.0% +0.9%/ 0.9% 0008H / 0009H 000CH / 000DH 001AH / 001BH 0035H / 0036H 006BH / 006CH 00D8H / 00D9H 01B1H / 01B2H 0363H / 0364H 1B1FH / 1B20H 1FFFH / 1FFFH Table 10 Commonly used baud rates by reload value and deviation errors Note The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors. For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the ST10C167 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. ST10C167 datasheet 42 1708 01 3/4/98 33 PRELIMINARY DATA 13 Serial Channels SSCBR is the dual-function Baud Rate Generator/Reload register. The table below lists some possible baud rates against the required reload values and the resulting bit times for a 25MHz CPU clock. Baud Rate Reserved use a reload value > 0. 5MBaud 3.3MBaud 2.5MBaud 2MBaud 1MBaud 100KBaud 10KBaud 1KBaud 190.7Baud Bit Time --200ns 303ns 400ns 500ns 1s 10s 100s 1ms 5.2ms Reload Value 0000H 0001H 0002H 0004H 0005H 000BH 007CH 04E1H 30D3H FFFFH Table 11 Synchronous baud rate and reload values ST10C167 datasheet 42 1708 01 3/4/98 34 PRELIMINARY DATA 14 CAN Module 14 CAN Module The integrated CAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Provides full CAN functionality on up to 15 message objects. Message object 15 can be configured for basic CAN functionality. Both modes provide separate masks for acceptance filtering, allowing a number of identifiers in full CAN mode to be accepted and disregarding a number of identifiers in basic CAN mode. All message objects can be updated independentl from other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN module uses two pins to interface to a bus transceiver. 15 Watchdog Timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip's start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced The table below shows the watchdog time range for 25MHz CPU clock. Prescaler for fCPU 2 (WDTIN = `0') 20.48 s 5.24 ms 128 (WDTIN = `1') 1.31 ms 336 ms Reload value in WDTREL FFH 00H ST10C167 datasheet 42 1708 01 3/4/98 35 PRELIMINARY DATA 16 Instruction Set Summary 16 Instruction Set Summary The table below lists the instructions of the ST10C167. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual". Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 CMP(B) 2/4 Table 12 Instruction set summary ST10C167 datasheet 42 1708 01 3/4/98 36 PRELIMINARY DATA 16 Instruction Set Summary Mnemonic CMPD1/2 CMPI1/2 PRIOR Description Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Bytes 2/4 2/4 2 SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL 2 2 2 2/4 2/4 2/4 4 4 4 4 4 4 4 4 TRAP PUSH, POP SCXT 2 2 4 RET RETS 2 2 Table 12 Instruction set summary ST10C167 datasheet 42 1708 01 3/4/98 37 PRELIMINARY DATA 16 Instruction Set Summary Mnemonic RETP Description Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2 RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP 2 4 4 4 4 4 4 2 2 2/4 2/4 2 Table 12 Instruction set summary ST10C167 datasheet 42 1708 01 3/4/98 38 PRELIMINARY DATA 17 System Reset 17 System Reset The internal system reset function is invoked either by asserting a hardware reset signal on pin RSTIN (Hardware Reset Input), by the execution of the SRST instruction (Software Reset) or by an overflow of the watchdog timer. Whenever one of these conditions occurs, the microcontroller is reset into its predefined default state. The following type of reset are implemented on the ST10C167: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock signal on XTAL1, as it is not internally resynchronized. It immediately resets the microcontroller into its default reset state. This asynchronous reset is required upon power-up of the chip and may be used during catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before exiting the reset condition. Therefore, only the entry of the this hardware reset is asynchronous. Synchronous hardware reset (warm reset): A warm synchronous hardware reset is triggered when the reset input signal RSTIN is latched low and Vpp pin is high. The I/Os are immediately (asynchronously) set in high impedance, RSTOUT is driven low. After RSTIN negation is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. Then, the internal reset sequence starts for 1024 TCL (512 CPU clock cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 5 in SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. Note that after all reset sequence, bit BDRSTEN is cleared. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN becomes inactive. Software reset: The reset sequence can be triggered at any time by the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. As for a synchronous hardware reset, the reset sequence lasts 1024 TCL (512 CPU clock cycles), and drives the RSTIN pin low. Watchdog timer reset: When the watchdog timer is not disabled during the initialization or serviced regularly during program execution is will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle does not use READY, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. The watchdog reset cannot occur while the ST10C167 is in bootstrap loader mode. Bidirectional reset: This feature is enabled by bit 3 of the SYSCON register. The bidirectional reset makes the watchdog timer reset and software reset externally visible. It is active for the duration of an internal reset sequences caused by a watchdog timer reset and ST10C167 datasheet 42 1708 01 3/4/98 39 PRELIMINARY DATA 18 Power Reduction Modes software reset. This means that the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. The consequence is that during a watchdog timer reset or software reset, the behavior of the C167CR-4RM is equal to an external hardware reset. 18 Power Reduction Modes Two different power reduction modes are implemented on the ST10C167. Idle mode: The CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. Power Down mode: Clocking of all internal blocks is stopped, the contents of the internal RAM, however, are preserved through the voltage supplied via the VCC pins. The watchdog timer is stopped Two different power down modes are implemented: Protected power down mode: This is used in conjunction with an external power failure signal. The microcontroller enters the NMI trap routine which saves the internal state into RAM. After the internal state has been saved, the trap routine may set a flag or write a certain bit patterns into specific RAM locations and then execute the PWRDN instruction. If the NMI pin is still low at this time, power down mode will be entered, otherwise program execution continues. During power down the voltage at the VCC pins can be lowered to 2.5V conserving the contents of the internal RAM.The initialization routine (executed upon reset) can check the identification flag or bit pattern within RAM to determine whether the controller was initially switched on, or whether it was properly restarted from power down mode. Interruptible power down mode: When power down mode is entered, the CPU and peripheral clocks are frozen, and the oscillator and PLL are stopped. To exit power down mode with external interrupt, an EXxIN pin has to be asserted for at least 40 ns (x = 7...0). This signal enables the internal oscillator and PLL circuitry, and turns on the weak pull-down. If the Interrupt was enabled before entering power down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction. If the interrupt was disabled, the device executes the instruction following PWRDN instruction, and the Interrupt Request Flag remains set until it is cleared by software. ST10C167 datasheet 42 1708 01 3/4/98 40 PRELIMINARY DATA 19 Special Function Register Overview 19 Special Function Register Overview The following table lists all SFRs which are implemented in the ST10C167 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Physical address FF98h 8-bit address CCh Reset value 0000h Name ADCICb Description A/D converter end of conversion interrupt control reg A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D converter overrun error interrupt control reg Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX0IN Interrupt Control Register ADCONb ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEICb FFA0h FEA0h F0A0hE FE18h FE1Ah FE1Ch FE1Eh FF9Ah D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h BUSCON0b BUSCON1b BUSCON2b BUSCON3b BUSCON4b CAPREL CC8ICb FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FF88h 86h 8Ah 8Bh 8Ch 8Dh 25h C4h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 41 PRELIMINARY DATA 19 Special Function Register Overview Name CC0 CC0ICb CC1 CC1ICb CC2 CC2ICb CC3 CC3ICb CC4 CC4ICb CC5 CC5ICb CC6 CC6ICb CC7 CC7ICb CC8 CC8ICb CC9 CC9ICb CC10 CC10ICb CC11 CC11ICb Physical address FE80h FF78h FE82h FF7Ah FE84h FF7Ch FE86h FF7Eh FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h FE92h FF8Ah FE94h FF8Ch FE96h FF8Eh 8-bit address 40h BCh 41h BDh 42h BEh 43h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h 49h C5h 4Ah C6h 4Bh C7h Description CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Reg CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Reg CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Reg CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Reg CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Reg CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Reg CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Reg CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Reg CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Reg CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Reg CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Reg CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Reg Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 42 PRELIMINARY DATA 19 Special Function Register Overview Name CC12 CC12ICb CC13 CC13ICb CC14 CC14ICb CC15 CC15ICb CC16 CC16ICb CC17 CC17ICb CC18 CC18ICb CC19 CC19ICb CC20 CC20ICb CC21 CC21ICb CC22 CC22ICb CC23 CC23ICb Physical address FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h F160hE FE62h F162hE FE64h F164hE FE66h F166hE FE68h F168hE FE6Ah F16AhE FE6Ch F16ChE FE6Eh F16EhE 8-bit address 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h 35h B5h 36h B6h 37h B7h Description CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Reg CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Reg CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Reg CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Reg CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Reg CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Reg CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Reg CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Reg CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Reg CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Reg CAPCOM Register 22 CAPCOM Register 22 Interrupt Control Reg CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Reg Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 43 PRELIMINARY DATA 19 Special Function Register Overview Name CC24 CC24ICb CC25 CC25ICb CC26 CC26ICb CC27 CC27ICb CC28 CC28ICb CC29 CC29ICb CC30 CC30ICb CC31 CC31ICb CCM0b CCM1b CCM2b CCM3b CCM4b CCM5b CCM6b CCM7b Physical address FE70h F170hE FE72h F172hE FE74h F174hE FE76h F176hE FE78h F178hE FE7Ah F184hE FE7Ch F18ChE FE7Eh F194hE FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h 8-bit address 38h B8h 39h B9h 3Ah BAh 3Bh BBh 3Ch BCh 3Dh C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h Description CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Reg CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Reg CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Reg CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Reg CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Reg CAPCOM Register 29 CAPCOM Register 29 Interrupt Control Reg CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Reg CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Reg CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 44 PRELIMINARY DATA 19 Special Function Register Overview Name CP CRICb CSP DP0Lb DP0Hb DP1Lb DP1Hb DP2b DP3b DP4b DP6b DP7b DP8b DPP0 DPP1 DPP2 DPP3 EXICONb IDCHIP IDMANUF IDMEM IDPROG MDCb Physical address FE10h FF6Ah FE08h F100hE F102hE F104hE F106hE FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h F1C0hE F07ChE F07EhE F07AhE F078hE FF0Eh 8-bit address 08h B5h 04h 80h 81h 82h 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h E0h 3Eh 3Fh 3Dh 3Ch 87h Description CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Reg (read only) P0L Direction Control Register P0h Direction Control Register P1L Direction Control Register P1h Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register Device Identifier Register Manufacturer Identifier Register On-chip Memory Identifier Register Programming Voltage Identifier Register CPU Multiply Divide Control Register Reset value FC00h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 0000h 0001h 0002h 0003h 0000h 0A7h 0020h 3020h 9A40h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 45 PRELIMINARY DATA 19 Special Function Register Overview Name MDH MDL ODP2b ODP3b ODP6b ODP7b ODP8b ONES P0Lb P0Hb P1Lb P1Hb P2b P3b P4b P5b P6b P7b P8b PECC0 PECC1 PECC2 PECC3 Physical address FE0Ch FE0Eh F1C2hE F1C6hE F1CEhE F1D2hE F1D6hE FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h 8-bit address 06h 07h E1h E3h E7h E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h EAh 60h 61h 62h 63h Description CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) Port 7 Register (8 bits) Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register Reset value 0000h 0000h 0000h 0000h 00h 00h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh 00h 00h 00h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 46 PRELIMINARY DATA 19 Special Function Register Overview Name PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSWb PT0 PT1 PT2 PT3 PW0 PW1 PW2 PW3 PWMCON0b PWMCON1b PWMICb RP0Hb S0BG Physical address FEC8h FECAh FECCh FECEh F1C4hE F038hE F03AhE F03ChE F03EhE FF10h F030hE F032hE F034hE F036hE FE30h FE32h FE34h FE36h FF30h FF32h F17EhE F108hE FEB4h 8-bit address 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h 1Ah 1Bh 18h 19h 1Ah 1Bh 98h 99h BFh 84h 5Ah Description PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 PWM Module Period Register 3 CPU Program Status Word PWM Module Up/Down Counter 0 PWM Module Up/Down Counter 1 PWM Module Up/Down Counter 2 PWM Module Up/Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register System Start-up configuration reg (read only) Serial Channel 0 baud rate generator reload register Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 47 PRELIMINARY DATA 19 Special Function Register Overview Name S0CONb S0EICb S0RBUF S0RICb S0TBICb Physical address FFB0h FF70h FEB2h FF6Eh F19ChE FEB0h 8-bit address D8h B8h 59h B7h CEh Description Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Reg Serial Channel 0 receive buffer reg (read only) Serial Channel 0 receive interrupt control reg Serial Channel 0 transmit buffer interrupt control reg Serial Channel 0 transmit buffer register (write only) Serial Channel 0 transmit interrupt control reg CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Reg CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register Reset value 0000h 0000h XXh 0000h 0000h S0TBUF 58h 00h S0TICb SP SSCBR SSCCONb SSCEICb SSCRB SSCRICb SSCTB SSCTICb STKOV STKUN SYSCONb T0 T01CONb T0ICb T0REL FF6Ch FE12h F0B4hE FFB2h FF76h F0B2hE FF74h F0B0hE FF72h FE14h FE16h FF12h FE50h FF50h FF9Ch FE54h B6h 09h 5Ah D9h BBh 59h BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah 0000h FC00h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h FA00h FC00h 0xx0h1) 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 48 PRELIMINARY DATA 19 Special Function Register Overview Name T1 T1ICb T1REL T2 T2CONb T2ICb T3 T3CONb T3ICb T4 T4CONb T4ICb T5 T5CONb T5ICb T6 T6CONb T6ICb T7 T78CONb T7ICb T7REL T8 T8ICb Physical address FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h F050hE FF20h F17AhE F054hE F052hE F17ChE 8-bit address 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h 28h 90h BEh 2Ah 29h BFh Description CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name ST10C167 datasheet 42 1708 01 3/4/98 49 PRELIMINARY DATA 19 Special Function Register Overview Name T8REL TFRb WDT WDTCON XP0ICb XP1ICb XP2ICb XP3ICb ZEROSb Physical address F056hE FFACh FEAEh FFAEh F186hE F18EhE F196hE F19EhE FF1Ch 8-bit address 2Bh D6h 57h D7h C3h C7h CBh CFh 8Eh Description CAPCOM Timer 8 Reload Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL unlock Interrupt Control Register Constant Value 0's Register (read only) Reset value 0000h 0000h 0000h 000xh2) 0000h 0000h 0000h 0000h 0000h Table 13 Special function registers listed by name The Interrupt Control Registers XPnIC control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. 1 2 The system configuration is selected during reset. Bit WDTR indicates a watchdog timer triggered reset. ST10C167 datasheet 42 1708 01 3/4/98 50 PRELIMINARY DATA 20 Electrical Characteristics Absolute maximum ratings 20 Electrical Characteristics 20.1 Absolute maximum ratings * Ambient temperature under bias (TA): -40 to +125 C * Storage temperature (TST):- 65 to +150 C * Voltage on VDD pins with respect to ground (VSS): 0.5 to +6.5 V * Voltage on any pin with respect to ground (VSS): -0.3 toVDD +0.3 V * Input current on any pin during overload condition: -10 to +10 mA * Absolute sum of all input currents during overload condition:|100 mA| * Power dissipation:1.5 W Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN The parameters listed in the following tables represent the characteristics of the ST10C167 and its demands on the system. Where the ST10C167 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10C167, the symbol "SR" for System Requirement, is included in the "Symbol" column. ST10C167 datasheet 42 1708 01 3/4/98 51 PRELIMINARY DATA 20 Electrical Characteristics DC characteristics 20.3 DC characteristics VDD = 5 V 10%,VSS = 0 V, fCPU = 25 MHz, Reset active, TA = -40 to +125 C Limit Values Parameter Symbol min. Input low voltage VIL SR - 0.5 max. 0.2 VDD - 0.1 2.0 Uni t V Test Condition - Input low voltage (special threshold) Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) 1) VILSSR VIHSR - 0.5 V - 0.2 VDD + 0.9 0.6 VDD 0.7 VDD 0.8 VDD - 0.2 400 VDD + 0.5 V - VIH1SR VIH2SR VIHSSR VDD + 0.5 VDD + 0.5 VDD+ 0.5 V V V - - - HYS - mV - VOLCC - 0.45 V IOL = 2.4 mA VOL1CC VOHCC - 0.45 V IOL1 = 1.6 mA IOH = - 500 A IOH = -2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VDD 0 V < VIN < VDD 0.9 VDD 2.4 0.9 VDD 2.4 - - - V VOH1CC - V V A A Input leakage current (Port 5) Input leakage current (all other) IOZ1CC IOZ2CC 0.5 1 Table 14 DC characteristics ST10C167 datasheet 42 1708 01 3/4/98 52 PRELIMINARY DATA 20 Electrical Characteristics DC characteristics Limit Values Parameter Symbol min. Overload current RSTIN pull-up resistor 5) 4) max. 5 250 Uni t mA KO hm A A A A A A A A A pF Test Condition IOVSR RRSTCC 2) 3) 2) 3) 2) 3) 2) 3) - 50 5) 8) - Read/Write inactive current Read/Write active current ALE inactive current ALE active current 4) 4) 4) 4) IRWH IRWL IALEL IALEH IP6H IP6L - -500 40 - - -500 - -100 - - -40 - - 500 -40 - -10 - 20 10 VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz TA = 25 C RSTIN = VIL2 fCPU in [MHz] 6) Port 6 inactive current Port 6 active current 4) PORT0 configuration current 4) IP0H IP0L XTAL1 input current Pin capacitance 5) (digital inputs/outputs) Power supply current IIL CC CIOCC ICC - 20 + 5 * fCPU 20 + 2 * fCPU 100 mA Idle mode supply current IID - mA RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply current IPD - A VDD = 5.5 V 7) Table 14 DC characteristics 1 2 3 This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. ST10C167 datasheet 42 1708 01 3/4/98 53 PRELIMINARY DATA 20 Electrical Characteristics 4 DC characteristics This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 5 6 7 Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. 150 I [mA] ICCmax 100 ICCtyp IIDmax 50 IIDtyp 10 5 10 15 20 25 fCPU [MHz] Figure 8 Supply/idle current as a function of operating frequency ST10C167 datasheet 42 1708 01 3/4/98 54 PRELIMINARY DATA 20 Electrical Characteristics DC characteristics 20.3.1 A/D converter characteristics VDD = 5 V + 10%, VSS = 0 V, TA = -40 to +125 C 4.0 V < VAREF < VDD+0.1 V, VSS-0.1 V< VAGND < VSS+0.2 V Limit Values Parameter Symbol min. Analog input voltage range Sample time Conversion time VAINSR tSCC tCCC VAGND - - max. VAREF 2 tSC 14 tCC + tS + 4TCL 2 tCC /165 - 0.25 tS / 330 - 0.25 33 LSB KOhm V 1) 2) 4) 3) 4) Unit Test Condition Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance TUECC RAREFSR - - 5) tCC in [ns] 6) 7) RASRCSR - KOhm tS in [ns] 2) 7) CAINCC - pF 7) Table 15 A/D converter characteristics Sample time and conversion time of the ST10C167's ADC are programmable. The table below should be used to calculate the above timings. ADCON.15|14 (ADCTC) 00 01 10 11 ADCON.13|12 (ADSTC) 00 01 10 11 Conversion clock tCC TCL * 24 Reserved, do not use TCL * 96 TCL * 48 Sample clock tSC tCC tCC * 2 tCC * 4 tCC * 8 ST10C167 datasheet 42 1708 01 3/4/98 55 PRELIMINARY DATA 20 Electrical Characteristics 1 2 DC characteristics VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table above. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. This parameter is fixed by ADC control logic. TUE is tested at VAREF=5.0V, VAGND=0V, VCC=4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB . During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, guaranteed by design characterization. 3 4 5 6 7 ST10C167 datasheet 42 1708 01 3/4/98 56 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4 AC characteristics Test waveforms 2.4V 0.2VDD+0.9 Test Points 0.2VDD+0.9 0.45V 0.2VDD-0.1 0.2VDD-0.1 AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 9 Input output waveforms VOH VLoad +0.1V VLoad VLoad -0.1V VOH -0.1V Timing Reference Points VOL +0.1V VOL For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 10 Float waveforms 20.4.1 Definition of internal timing The internal operation of the ST10C167 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). The CPU clock signal can be generated by different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to ST10C167 datasheet 42 1708 01 3/4/98 57 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics generate fCPU. This influence must be regarded when calculating the timings for the ST10C167. The example for PLL operation shown in the figure above refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Phase locked loop operation fXTAL fCPU TCL TCL Direct Clock Drive fXTAL fCPU TCL TCL Prescaler Operation fXTAL fCPU TCL TCL Figure 11 Generation mechanisms for the CPU clock ST10C167 datasheet 42 1708 01 3/4/98 58 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.2 Clock generation modes The table below associates the combinations of these three bits with the respective clock generation mode. P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU Frequency fCPU = fXTAL * F FXTAL * 4 FXTAL * 3 FXTAL * 2 FXTAL * 5 FXTAL * 1 FXTAL * 1.5 FXTAL / 2 FXTAL * 2.5 External Clock Input Range 1) 2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.6 MHz 2 to 50 MHz 4 to 10 MHz CPU clock via prescaler Direct drive 2) Notes Default configuration 1 2 The external clock input range refers to a CPU clock range of 10...25 MHz. The maximum depends on the duty cycle of the external clock signal. 20.4.3 Prescaler operation When pins P0.15-13 (P0H.7-5) equal'001' during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL is running on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. ST10C167 datasheet 42 1708 01 3/4/98 59 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.4 Direct drive When pins P0.15-13 (P0H.7-5) equal'011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated by the following formula: TCL min = 1 f XTAL *DC min DC = duty cycle For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1 f XTAL Note The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL is running on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 20.4.5 Oscillator watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows: After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, the PLL is running on its free-running frequency, and increment the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU ST10C167 datasheet 42 1708 01 3/4/98 60 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. 20.4.6 Phase locked loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation D N: TCL min = TCL NOM * ( 1 - lD N l 100 ) D N = ( 4 - N 15 ) [ % ] where N = number of consecutive TCLs and 1 < N < 40. So for a period of 3 TCLs (i.e. N = 3): D 3 = 4 - 3 15 = 3.8% 3TCL min = 3TCL NOM x ( 1 - 3.8 100 ) = TCL NOM x 0.962 ( 57.72nsec@f CPU = 25MHz ) This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train ST10C167 datasheet 42 1708 01 3/4/98 61 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Max.jitter [%] This approximated formula is valid for 1 < N < 40 and 10MHz < fCPU < 25MHz. 4 3 2 1 2 4 8 16 32 N Figure 12 Approximated maximum PLL jitter 20.4.7 Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol tA tC tF Values TCL * ST10C167 datasheet 42 1708 01 3/4/98 62 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.8 External clock drive XTAL1 VDD = 5 V 10%,VSS = 0 V, TA = -40 to +125 C fCPU = fXTAL * N N = 1.5/2,/2.5/3/4/5 min 40 * N 103) 103) - - max 100 * N - - 103) 103) ns ns ns ns ns Unit fCPU = fXTAL Parameter Symbol min Oscillator period High time Low time Rise time Fall time tOSCSR t1SR t2SR t3SR t4SR 401) 183) 183) - - max 1000 - - 103) 103) fCPU = fXTAL / 2 min 202) 63) 63) - - max 500 - - 63) 63) 1 2 3 Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. The input clock signal must reach the defined levels VIL and VIH2. t3 t1 t4 VIH2 t2 VIL tOSC Figure 13 External clock drive XTAL1 ST10C167 datasheet 42 1708 01 3/4/98 63 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.9 Multiplexed bus VDD = 5 V 10%,VSS = 0 V, TA = -40 to +125 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25-MHz CPU clock without waitstates) Max. CPU Clock = 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) t5CC t6CC t7CC t8CC 10 + tA 4 + tA 10 + tA 10 + tA max. - - Variable CPU Clock 1/2TCL = 1 to 25MHz min. TCL - 10 + tA TCL - 16+ tA TCL - 10 + tA TCL - 10 + tA max. - - Unit ns ns ns ns ns ns ns ns ns ns 64 Parameter Symbol - - - - t9CC -10 + tA - -10 + tA - t10CC - 6 - 6 t11CC - 26 - TCL + 6 t12CC 30 + tC - 2TCL - 10 + tC 3TCL - 10 + tC - - t13CC 50 + tC - - t14SR - 20 + tC 2TCL - 20+ tC Table 16 Multiplexed bus characteristics ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics Parameter Symbol Max. CPU Clock = 25 MHz min. max. 40 + tC Variable CPU Clock 1/2TCL = 1 to 25MHz min. - max. 3TCL - 20+ tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 65 RD to valid data in (no RW-delay) ALE low to valid data in Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD t15SR - t16SR - 40 + tA + t C 50 + 2tA + tC - - t17SR - - t18SR t19SR 0 0 - 26 + tF - 2TCL - 14 + tF - Data valid to WR t22CC 20 + tC - 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA - Data hold after WR t23CC 26 + tF - - ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR ALE falling edge to Latched CS Latched CS low to Valid Data In Latched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) t25CC 26 + tF - - t27CC 26 + tF - - t38CC t39SR -4 - tA - 10 - tA 40 + tC + 2tA - 10 - tA 3TCL - 20 + tC + 2tA - t40CC 46 + tF 3TCL - 14 + tF TCL - 4 + tA t42CC 16 + tA - - Table 16 Multiplexed bus characteristics ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics Parameter Symbol Max. CPU Clock = 25 MHz min. max. - Variable CPU Clock 1/2TCL = 1 to 25MHz min. -4 + tA max. - Unit ns ns ns ns ns ns ns ns ns ns ns ns 66 ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS t43CC -4 + tA t44CC - 0 - 0 t45CC - 20 - TCL t46SR - 16 + tC - 2TCL - 24 + tC 3TCL - 24 + tC - t47SR - 36 + tC - t48CC 30 + tC - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14+ tC 0 - t49CC 50 + tC - - t50CC 26 + tC - - Data hold after RdCS Data float after RdCS t51SR t52SR 0 - - 20 + tF - 2TCL - 20 + tF - Address hold after RdCS, WrCS Data hold after WrCS t54CC 20 + tF - 2TCL - 20 + tF 2TCL - 20 + tF t56CC 20 + tF - - Table 16 Multiplexed bus characteristics ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t38 Latched CSx t16 t25 t39 t40 A23-A16 (A15-A8) BHE Unlatched CSx Read Cycle BUS t17 Address t6 t7 t18 Address t10 t14 t12 t46 t48 t51 t27 t54 t19 Data In t8 RD t42 RdCSx t44 t52 Write Cycle BUS Address t10 t23 Data Out t56 t22 t8 WR, WRL, WRH t42 WrCSx t44 t12 t50 t48 Figure 14 External memory cycle:multiplexed bus, with read/write delay, normal ALE ST10C167 datasheet 42 1708 01 3/4/98 67 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t38 t16 t25 t39 Latched CSx t40 A23-A16 (A15-A8) BHE Unlatched CSx Read Cycle BUS t17 Address t6 t7 t27 t54 t19 t18 Address t10 t14 t12 t46 t48 Data In t8 RD t42 RdCSx t44 t51 t52 Write Cycle BUS Address t10 Data Out t23 t56 t22 t8 WR, WRL, WRH t42 WrCSx t44 t12 t50 t48 Figure 15 External memory cycle:multiplexed bus, with read/write delay, ext'd ALE ST10C167 datasheet 42 1708 01 3/4/98 68 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t38 Latched CSx t16 t25 t39 t40 A23-A16 (A15-A8) BHE Unlatched CSx Read Cycle BUS t17 Address t6 t7 t18 Address t9 Data In t27 t54 t19 t11 RD t43 RdCSx t15 t13 t51 t52 t45 t47 t49 Write Cycle BUS Address t9 WR, WRL, WRH t43 WrCSx t49 t45 t23 Data Out t56 t11 t22 t13 t50 Figure 16 External memory cycle:multiplexed bus, no read/write delay, normal ALE ST10C167 datasheet 42 1708 01 3/4/98 69 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t38 t16 t25 t39 Latched CSx t40 A23-A16 (A15-A8) BHE Unlatched CSx Read Cycle BUS t17 Address t6 t7 t27 t54 t19 t18 Address Data In t9 RD t11 t15 t13 t51 t52 t43 RdCSx t45 t47 t49 Write Cycle BUS Address Data Out t23 t56 t9 WR, WRL, WRH t43 WrCSx t49 t45 t11 t22 t13 t50 Figure 17 External memory cycle:multiplexed bus, no read/write delay, extended ALE ST10C167 datasheet 42 1708 01 3/4/98 70 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.10 Demultiplexed bus VDD = 5 V 10%,VSS = 0 V, TA = -40 to +125 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Max. CPU Clock = 25MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in t5CC t6CC t8CC 10 + tA 4 + tA 10 + tA max. - - - Variable CPU Clock 1/2TCL = 1 to 25MHz min. TCL - 10+ tA TCL - 16+ tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - max. - - - Unit ns ns ns ns ns ns ns ns ns ns ns 71 Parameter Symb ol t9CC t12CC -10 + tA 30 + tC - - - - t13CC 50 + tC - - t14SR - 20 + tC 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - t15SR - 40 + tC - t16SR - 40 + tA + tC 50 + 2tA + tC - - Address/Unlatched CS to valid data in Data hold after RD rising edge t17SR - - t18SR 0 0 Table 17 Demultiplexed bus characteristics ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics Parameter min. Data float after RD rising edge (with RW-delay1)) t21SR - t20SR - max. 26 + tF min. - max. 2TCL - 14 + tF + 2tA 1) ns Data float after RD rising edge (no RW-delay1)) 10 + tF - TCL - 10 + tF + 2tA 1) ns Data valid to WR t22CC 20 + tC - 2TCL- 20 + tC TCL - 10+ tF -10 + tF 0 + tF - ns Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR2) ALE falling edge to Latched CS Latched CS low to Valid Data In Latched CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) t24CC t26CC t28CC 10 + tF -10 + tF 0 + tF - - - - ns ns - - ns t38CC t39SR -4 - tA - 10 - tA 40 + tC+ 2tA - -4 - tA - 10 - tA 3TCL - 20 + tC + 2tA - ns ns t41CC 6 + tF TCL - 14 + tF TCL - 4 + tA -4 + tA - ns t42CC t43CC t46SR 16 + tA -4 + tA - - - ns - - ns 16 + tC 2TCL - 24 + tC 3TCL - 24 + tC - ns t47SR - 36 + tC - ns t48CC 30 + tC - 2TCL - 10 + tC ns Table 17 Demultiplexed bus characteristics ST10C167 datasheet 42 1708 01 3/4/98 Unit 72 Symb ol Max. CPU Clock = 25MHz Variable CPU Clock 1/2TCL = 1 to 25MHz PRELIMINARY DATA 20 Electrical Characteristics AC characteristics Parameter min. RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS t49CC 50 + tC max. - min. 3TCL - 10 + tC 2TCL - 14 + tC 0 - max. - ns t50CC 26 + tC - - ns Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t51SR t53SR 0 - - 20 + tF - 2TCL - 20 + tF TCL - 20 + tF - ns ns t68SR - 0 + tF - ns t55CC t57CC -10 + tF 6 + tF - -10 + tF TCL - 14 + tF ns - - ns Table 17 Demultiplexed bus characteristics 1 RW-delay and tA refer to the next following bus cycle. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles ST10C167 datasheet 42 1708 01 3/4/98 Unit 73 Symb ol Max. CPU Clock = 25MHz Variable CPU Clock 1/2TCL = 1 to 25MHz PRELIMINARY DATA 20 Electrical Characteristics . AC characteristics t5 ALE t16 t26 t38 Latched CSx t39 t41 A23-A16 A15-A0 t17 Address t28 BHE nlatched CSx Read Cycle BUS (D15-D8) D7-D0 t6 t55 t20 t18 Data In t8 RD t14 t12 t51 t53 t42 RdCSx t46 t48 Write Cycle BUS (D15-D8) D7-D0 Data Out t24 t57 t8 t12 t42 t50 t48 t22 WR, WRL, WRH WrCSx Figure 18 External memory cycle: demultip bus, with read/write delay, normal ALE ST10C167 datasheet 42 1708 01 3/4/98 74 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t16 t38 t39 t26 t41 Latched CSx A23-A16 A15-A0 t17 Address t28 BHE Unlatched CSx Read Cycle BUS (D15-D8) D7-D0 t6 t55 t20 t18 Data In t8 RD t14 t12 t51 t53 t42 RdCSx t46 t48 Write Cycle BUS (D15-D8) D7-D0 Data Out t24 t57 t8 t12 t42 t50 t48 t22 WR, WRL, WRH WrCSx Figure 19 External memory cycle:demultiplexed bus, with read/write delay, ext'd ALE ST10C167 datasheet 42 1708 01 3/4/98 75 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t16 t26 t38 Latched CSx t39 t41 A23-A16 A15-A0 t17 Address t28 BHE Unlatched CSx Read Cycle BUS (D15-D8) D7-D0 t6 t55 t21 t18 Data In t9 t15 t43 t13 t47 t49 t51 t68 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 Data Out t24 t9 t57 t22 t13 t50 t49 WR, WRL, WRH t43 WrCSx Figure 20 External memory cycle: demultip bus, no read/write delay, normal ALE ST10C167 datasheet 42 1708 01 3/4/98 76 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics t5 ALE t16 t38 t39 t26 t41 Latched CSx A23-A16 A15-A0 t17 Address t28 BHE Unlatched CSx Read Cycle BUS (D15-D8) D7-D0 t6 t55 t21 t18 Data In t9 RD t15 t13 t51 t68 t43 RdCSx t47 t49 Write Cycle BUS (D15-D8) D7-D0 Data Out t24 t57 t9 t22 t13 t43 t50 t49 WR, WRL, WRH WrCSx Figure 21 External memory cycle:demultiplexed bus, no read/write delay, ext'd ALE ST10C167 datasheet 42 1708 01 3/4/98 77 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics 20.4.11 CLKOUT and READY VDD = 5 V 10%,VSS = 0 V, TA = -40 to +125 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Max. CPU Clock = 25MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Parameter Symbol Variable CPU Clock 1/2TCL = 1 to 25MHz min. 2TCL TCL - 6 TCL - 10 - - 0 + tA 14 max. 2TCL - - 4 4 10 + tA - Unit ns ns ns ns ns ns ns ns ns ns ns ns 78 max. 40 - - 4 4 10 + tA - t29CC t30CC t31CC t32CC t33CC t34CC t35SR t36SR t37SR t58SR 40 14 10 - - 0 + tA 14 4 - 4 - 54 - 2TCL + 14 - 14 - 14 - Asynchronous READY hold time 1) t59SR 4 - 4 - Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60SR 0 0 + 2tA + tC + tF 2) 0 TCL - 20 + 2tA + tC + tF 2) Table 18 CLKOUT and READY characteristics ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics 1 2 AC characteristics These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Running cycle 1) READY waitstate MUX/Tristate 6) t32 CLKOUT t33 t30 t34 t31 t29 ALE 7) Command RD, WR 2) t35 Sync t36 t35 3) t36 READY t58 Async 3) t59 3) t58 3) t59 t604) READY t37 5) see 6) Figure 22 CLKOUT and READY 1 2 3 4 5 Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order ST10C167 datasheet 42 1708 01 3/4/98 79 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here. 7 20.4.12 External bus arbitration VDD = 5 V 10%,VSS = 0 V, TA = -40 to +125 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Max. CPU Clock = 25MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive t61SR t62CC t63CC t64CC t65CC t66CC t67CC 20 max. - Variable CPU Clock 1/2TCL = 1 to 25MHz min. 20 max. - Unit ns ns ns ns ns ns ns 80 Parameter Symbol - 20 - 20 - 20 - 20 - -4 - -4 20 24 20 24 - -4 - -4 20 24 20 24 ST10C167 datasheet 42 1708 01 3/4/98 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ t64 3) 2) CSx (On P6.x) t66 Other Signals 1) Figure 23 External bus arbitration, releasing the bus 1 2 3 The ST10C167 will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. The CS outputs will be resistive high (pullup) after t64. ST10C167 datasheet 42 1708 01 3/4/98 81 PRELIMINARY DATA 20 Electrical Characteristics AC characteristics CLKOUT 2) t61 HOLD t62 HLDA t62 BREQ t62 1) t63 t65 CSx (On P6.x) t67 Other Signals Figure 24 External bus arbitration, (regaining the bus) 1 This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be disactivated without the ST10C167 requesting the bus. The next ST10C167 driven bus cycle may start here. 2 ST10C167 datasheet 42 1708 01 3/4/98 82 PRELIMINARY DATA 21 Package Mechanical Data 21 Package Mechanical Data Figure 25 Package Outline PQFP144 (28 x 28 mm) mm Dim min A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min), 7(max) 0.95 0.026 31.45 28.10 1.219 1.098 3.42 3.67 0.38 0.23 31.45 28.10 ty max 4.07 0.010 0.125 0.009 0.005 1.129 1.098 1.228 1.120 0.896 0.021.228 1.102 0.896 0.031 0.063 0.037 1.238 1.106 0.315 0.144 0.015 0.009 1.238 1.106 min ty max 0.106 inches Number of Pins N1 144 VR02061A 22 Ordering Information Salestype ST10C167-Q3 Temperature range -40C to 125C Package PQFP144 (28 x 28 mm) ST10C167 datasheet 42 1708 01 3/4/98 83 PRELIMINARY DATA Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A. ST10C167 datasheet 42 1708 01 3/4/98 84 |
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