View 56UW473_968912.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB56UW473EJN Series, HB56UW465EJN Series
4,194,304-word x 72-bit High Density Dynamic RAM Module 4,194,304-word x 64-bit High Density Dynamic RAM Module
ADE-203-724A (Z) Rev.1.0 Feb. 20, 1997 Description
The HB56UW473EJN, HB56UW465EJN belong to 8 Byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56UW473EJN is a 4M x 72 dynamic RAM module, mounted 18 pieces of 16-Mbit DRAM (HM51W17805) sealed in SOJ package and 1 pieces of serial EEPROM (24C02) for Presence Detect (PD). The HB56UW465EJN is a 4M x 64 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM51W17805) sealed in SOJ package and 1 pieces of serial EEPROM (24C02) for Presence Detect (PD). The HB56UW473EJN, HB56UW465EJN offer Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW473EJN, HB56UW465EJN is 168-pin socket type package (dual lead out). Therefore, the HB56UW473EJN, HB56UW465EJN make high density mounting possible without surface mount technology. The HB56UW473EJN, HB56UW465EJN provide common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 9.00 mm (Thickness) Lead pitch: 1.27 mm * Single 3.3 V (0.3 V) supply * High speed Access time: tRAC = 50/60/70ns (max) tCAC = 13/15/18ns (max) * Low power dissipation Active mode: 3.73/3.40/3.08 W (max) (HB56UW473EJN Series) 3.31/3.02/2.74 W (max) (HB56UW465EJN Series) Standby mode (TTL): 129.6 mW (max) (HB56UW473EJN Series) (TTL): 115.2 mW (max) (HB56UW465EJN Series) (CMOS): 9.72 mW (max) (L-version) (HB56UW473EJN Series) (CMOS): 8.64 mW (max) (L-version) (HB56UW465EJN Series)
HB56UW473EJN Series, HB56UW465EJN Series
* JEDEC standard outline unbuffered 8-byte DIMM * EDO page mode capability * Refresh period 2048 refresh cycles: 32 ms 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version)
Ordering Information
Type No. HB56UW473EJN-5 HB56UW473EJN-6 HB56UW473EJN-7 HB56UW473EJN-5L HB56UW473EJN-6L HB56UW473EJN-7L HB56UW465EJN-5 HB56UW465EJN-6 HB56UW465EJN-7 HB56UW465EJN-5L HB56UW465EJN-6L HB56UW465EJN-7L Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
2
HB56UW473EJN Series, HB56UW465EJN Series
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 (NC)* CB1 (NC)* VSS NC NC VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2
1 2
Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
Pin name VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC CB2 (NC)*
3
Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 (NC)* CB5 (NC)* VSS NC NC VCC NC CAS4 CAS5 RAS1 NC VSS A1 A3
5 6
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pin name VSS NC RAS3 CAS6 CAS7 NC VCC NC NC CB6 (NC)*7 CB7 (NC)*8 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62
CB3 (NC)*4 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30
3
HB56UW473EJN Series, HB56UW465EJN Series
Pin Arrangement (cont)
Pin No. 35 36 37 38 39 40 41 42 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Pin name A4 A6 A8 A10 NC VCC VCC NC CB0: CB1: CB2: CB3: CB4: CB5: CB6: CB7: Pin No. 77 78 79 80 81 82 83 84 Pin name DQ31 VSS NC NC NC SDA SCL VCC Pin No. 119 120 121 122 123 124 125 126 Pin name A5 A7 A9 NC NC VCC NC NC Pin No. 161 162 163 164 165 166 167 168 Pin name DQ63 VSS NC NC SA0 SA1 SA2 VCC
HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC: HB56UW473EJN, NC:
HB56UW465EJN HB56UW465EJN HB56UW465EJN HB56UW465EJN HB56UW465EJN HB56UW465EJN HB56UW465EJN HB56UW465EJN
4
HB56UW473EJN Series, HB56UW465EJN Series
Pin Description
Pin name A0 to A10 Function Address input Row address: Column address: Refresh address: DQ0 to DQ63 RAS0 to RAS3 CAS0 to CAS7 WE0, WE2 OE0, OE2 SDA SCL SA0 to SA2 CB0 to CB7* VCC VSS NC Note:
1
A0 to A10 A0 to A9 A0 to A10
Data-in/data-out Row address strobe Column address strobe Read/Write enable Output enable Serial data for PD Serial clock for PD Serial address for PD Check bit Power supply Ground No connection
1. This function is supported only HB56UW473EJN Series.
5
HB56UW473EJN Series, HB56UW465EJN Series
Serial PD Matrix*1
Byte number 0 1 2 3 4 5 6 Function described Number serial PD bytes Serial memory Bit7 0 0 Bit6 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Bit5 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit4 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 Bit3 1 1 0 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 Bit2 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 1 1 0 0 0 Bit0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 ECC None-parity Normal (15.625 s) Self refresh (62.5 s) Comments 13 256 bytes EDO 11 10 2 72 64 0 (+) 3.3 Volt
Fundamental memory type 0 Number of rows Number of columns Number of banks Data width HB56UW473EJN HB56UW465EJN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
7 8 9
Data width (continued) Voltage interface RAS access time 50 ns 60 ns 70 ns
10
CAS access time 13 ns 15 ns 18 ns
11
Error detection/corraction HB56UW473EJN HB56UW465EJN
12
Refresh period Refresh period (L-version)
Note:
1. Serial-PD data are not protected. 1: High level (Serial data) 0: Low level (Serial data)
6
HB56UW473EJN Series, HB56UW465EJN Series
Block Diagram (HB56UW473EJN)
RAS0 CAS0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O CASRAS WE OE I/O I/O I/O I/O D1 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D10 I/O I/O I/O RAS1 RAS2 CAS4 WE2 OE2 I/O CASRAS WE OE I/O I/O I/O I/O D9 I/O I/O I/O DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CAS6 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O CASRAS WE OE I/O I/O I/O I/O D4 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D13 I/O I/O I/O Serial PD SCL A0 SA0 A0 to A10 VCC VSS 0.22 F x 36 pcs D0 to D17 D0 to D17, U0 D0 to D17, U0 U0 A1 SA1 A2 SA2 SDA I/O CASRAS WE OE I/O I/O I/O I/O D3 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D12 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D2 I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D11 I/O I/O DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O CASRAS WE OE I/O I/O I/O I/O D8 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D17 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D7 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D16 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D6 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D15 I/O I/O I/O RAS3
I/O CASRAS WE OE I/O I/O I/O I/O D0 I/O I/O I/O
I/O CASRAS WE OE I/O I/O I/O I/O D5 I/O I/O I/O
I/O CASRAS WE OE I/O I/O I/O I/O D14 I/O I/O I/O
* D0 to D17 : HM51W17805 U0 : 24C02
Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collecter output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inactive "High" state.
7
HB56UW473EJN Series, HB56UW465EJN Series
Block Diagram (HB56UW465EJN)
RAS0 CAS0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O CASRAS WE OE I/O I/O I/O I/O D3 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D11 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D2 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D10 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D1 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D9 I/O I/O I/O RAS1 RAS2 CAS4 WE2 OE2 I/O CASRAS WE OE I/O I/O I/O I/O D8 I/O I/O I/O DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O CASRAS WE OE I/O I/O I/O I/O D7 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D15 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D6 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D14 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D5 I/O I/O I/O I/O CASRAS WE OE I/O I/O I/O I/O D13 I/O I/O I/O RAS3
I/O CASRAS WE OE I/O I/O I/O I/O D0 I/O I/O I/O
I/O CASRAS WE OE I/O I/O I/O I/O D4 I/O I/O I/O
I/O CASRAS WE OE I/O I/O I/O I/O D12 I/O I/O I/O
A0 to A10 VCC VSS 0.22 F x 32 pcs
D0 to D15 D0 to D15, U0 D0 to D15, U0 SCL A0
Serial PD U0 A1 SA1 A2 SA2 SDA
* D0 to D15 : HM51W17805 U0 : 24C02
SA0
Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collecter output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inactive "High" state.
8
HB56UW473EJN Series, HB56UW465EJN Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation (HB56UW473EJN) Power dissipation (HB56UW465EJN) Operating temperature Storage temperature Symbol VT VCC Iout Pt Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 18 16 0 to +70 -55 to +125 Unit V V mA W W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to V SS . VIH VIL Min 0 3.0 2.0 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC +0.3 0.8 Unit V V V V 1 1 1 Note
9
HB56UW473EJN Series, HB56UW465EJN Series
DC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3V, VSS = 0 V) (HB56UW473EJN)
50 ns Parameter Operating current Standby current 60 ns 70 ns Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 1035 -- 36 -- 945 -- 36 -- 855 mA 36 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4 2 1
--
18
--
18
--
18
mA
Standby current (L-version) RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
I CC2
--
2.7
--
2.7
--
2.7
mA
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
1035 -- 90 --
945 -- 90 --
855 mA 90 mA
1035 -- 945 -- 7.2 --
945 -- 855 -- 7.2 --
855 mA 810 mA 7.2 mA
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Self refresh mode current (L-version) Input leakage current
I CC11
--
4.5
--
4.5
--
4.5
mA
I LI
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
10
HB56UW473EJN Series, HB56UW465EJN Series
DC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3V, VSS = 0 V) (HB56UW465EJN)
50 ns Parameter Operating current Standby current 60 ns 70 ns Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 920 -- 32 -- 840 -- 32 -- 760 mA 32 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4 2 1
--
16
--
16
--
16
mA
Standby current (L-version) RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
I CC2
--
2.4
--
2.4
--
2.4
mA
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
920 -- 80 --
840 -- 80 --
760 mA 80 mA
920 -- 840 -- 6.4 --
840 -- 760 -- 6.4 --
760 mA 720 mA 6.4 mA
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Self refresh mode current (L-version) Input leakage current
I CC11
--
4
--
4
--
4
mA
I LI
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
11
HB56UW473EJN Series, HB56UW465EJN Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB56UW473EJN)
Parameter Input capacitance (Address) Input capacitance (RAS) Input capacitance (WE, OE ) Input capacitance (CAS) I/O capacitance (DQ, CB) Symbol CI! CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 110 55 90 48 27 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB56UW465EJN)
Parameter Input capacitance (Address) Input capacitance (RAS) Input capacitance (WE, OE ) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI! CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 100 48 76 34 20 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
12
HB56UW473EJN Series, HB56UW465EJN Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time OE to Din delay time OE delay time from Din CAS delay time from Din Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH 84 30 8 50 8 0 8 0 8 12 10 10 35 5 13 0 0 2 -- -- Max -- -- -- 60 ns Min 104 40 10 Max -- -- -- 70 ns Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 10 -- -- -- -- 37 25 -- -- -- -- -- -- 50 32 128 0 10 0 10 14 12 13 40 5 15 0 0 2 -- --
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 32 128 0 10 0 13 14 12 13 45 5 18 0 0 2 -- --
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 32 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 5 6 6 7 3 4
CAS to RAS precharge time t CRP t OED t DZO t DZC
Transition time (rise and fall) t T Refresh period (2,048 cycles) Refresh period (2,048 cycles) (L-version) t REF t REF
13
HB56UW473EJN Series, HB56UW465EJN Series
Read Cycle
50 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Symbol Min t RAC t CAC t AA t OEA t RCS -- -- -- -- 0 0 50 5 25 15 0 3 3 -- -- 13 3 -- -- 13 13 50 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- 13 13 -- -- 13 13 -- -- -- 60 ns Min -- -- -- -- 0 0 60 5 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- 70 ns Min -- -- -- -- 0 0 70 5 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 21
Read command hold time to t RCH CAS Read command hold time from RAS t RCHR
Read command hold time to t RRH RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR
Output buffer turn-off time to t OFR RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time t WEZ t WED t RDD t RNCD
14
HB56UW473EJN Series, HB56UW465EJN Series
Write Cycle
50 ns Parameter Write command setup time Write command hold time Write command pulse width Symbol Min t WCS t WCH t WP 0 8 8 8 8 0 8 Max -- -- -- -- -- -- -- 60 ns Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Write command to RAS lead t RWL time Write command to CAS lead t CWL time Data-in setup time Data-in hold time t DS t DH
Read-Modify-Write Cycle
50 ns Parameter Symbol Min 111 67 30 42 13 Max -- -- -- -- -- 60 ns Min 135 79 34 49 15 Max -- -- -- -- -- 70 ns Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Read-modify-write cycle time t RWC RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time WE t RWD t CWD t AWD t OEH
Refresh Cycle
50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) Symbol Min t CSR t CHR t WRP t WRH 5 8 0 8 5 Max -- -- -- -- -- 60 ns Min 5 10 0 10 5 Max -- -- -- -- -- 70 ns Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
RAS precharge to CAS hold t RPC time
15
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Cycle
50 ns Parameter EDO page mode cycle time Symbol Min t HPC 20 -- -- 30 3 8 5 30 Max -- 60 ns Min 25 Max -- 70 ns Min 30 Max -- Unit ns Notes 20 16 9, 17
EDO page mode RAS pulse t RASP width Access time from CAS precharge RAS hold time from CAS precharge Output data hole time from CAS low CAS hold time refferred OE CAS to OE setup time Read command hold time from CAS precharge t CPA t CPRH t DOH t COL t COP t RCHC
100000 -- 30 -- -- -- -- -- -- 35 3 10 5 35
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
9, 17
EDO Page Mode Read-Modify-Write Cycle
50 ns Parameter EDO page mode readmodify-write cycle time WE delay time from CAS precharge Symbol Min t HPRWC t CPW 57 45 Max -- -- 60 ns Min 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
Self Refresh Mode (L-version)
50 ns Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) Symbol Min t RASS t RPS 100 90 -50 Max -- -- -- 60 ns Min 100 110 -50 Max -- -- -- 70 ns Min 100 130 -50 Max -- -- -- Unit s ns ns Notes
CAS hold time (Self refresh) t CHS
16
HB56UW473EJN Series, HB56UW465EJN Series
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD tRAD (max) + tAA (max)- tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD , and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics onry; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); t OEH < tOEH, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and t OFF.
17
HB56UW473EJN Series, HB56UW465EJN Series
23. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 24. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 2048 of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
18
HB56UW473EJN Series, HB56UW465EJN Series
Timing Waveforms*27
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
19
HB56UW473EJN Series, HB56UW465EJN Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
20
HB56UW473EJN Series, HB56UW465EJN Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 21
HB56UW473EJN Series, HB56UW465EJN Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
22
HB56UW473EJN Series, HB56UW465EJN Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
CAS
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
23
HB56UW473EJN Series, HB56UW465EJN Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 24
HB56UW473EJN Series, HB56UW465EJN Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD
CAS
t CHR
t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column t RRH t RCH

WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t RCS
t RRH
t WRH t WRP
t WRP
tWRH
t WED t CDD t RDD
t OED
t OFF t OH
t OEZ t WEZ t OHO
t OFR t OHR
25
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Read Cycle
t RP t RASP tT CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
t CSH t CAS t RCHR
t CP
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
26
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
27
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
28
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD t CAS t CAS t HPRWC t CP t RSH t CAS
t CRP
CAS
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
29
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Mix Cycle (1)
t RP RAS tT CAS t RCD t WCS WE t ASC tRAH Row t WCH t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS
Din
t RASP t CRP tCAS tRSH t RCS tWP t RAL t CAH Column 4 t CAL t DS High-Z tOED t DH Din 3 tWED tRDD tCDD t RRH t RCH
t CP t CAS t CSH t CAS
t CP tCAS
t CP
tASR Address
tASC t CAH Column 3
tASC
Column 1
t DH Din 1

tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2
Dout 3
OE
Dout 4
30
HB56UW473EJN Series, HB56UW465EJN Series
EDO Page Mode Mix Cycle (2)
t RP t RASP
t RNCD
RAS
tT CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3 t CAL
Column 1 t CAL
t DS
Din
t DH Din 2
tRDD tCDD
High-Z
tOED
OE
tWED
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
31
HB56UW473EJN Series, HB56UW465EJN Series
Self Refresh Cycle (L-version)* 23, 24, 25, 26
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout 32
t WRH
, + & $
High-Z
HB56UW473EJN Series, HB56UW465EJN Series
Physical Outline
Unit: mm/inch
Front side 133.35 5.250 3.00 0.118 127.35 5.014 9.00 max 0.354 max
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C B 36.83 1.450 54.61 2.150 A 11.43 0.450
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.00 0.118
8.89 0.350
1.27 0.10 0.050 0.004
Back side 2 - 3.00 2 - 0.118
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Detail A
2.54 min 0.100 min
4.00 0.157
17.78 0.700
Detail B 1.27 0.050
0.25 max 0.010 max
Detail C 3.175 0.125 1.00 0.039
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 3.175 0.125 2.00 0.10 0.079 0.004
25.40 1.000
4.00 min 0.157 min
168
85
33
HB56UW473EJN Series, HB56UW465EJN Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
34
HB56UW473EJN Series, HB56UW465EJN Series
Revision Record
Rev. 1.0 Date Contents of Modification Drawn by Approved by Feb. 20, 1997 Initial issue
35

▲Up To Search▲

Price & Availability of 56UW473

	To Download 56UW473 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .