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Features
* * * * * * * * *
Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format (100) 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50 PECL/LVDS Compatible Clock Inputs Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output) LQFP144 Package Temperature Range: - 0C < TA < 70C (Commercial Grade) - -40C < TA < 85C (Industrial Grade) * 3-wire Serial Interface - 16-bit Data, 3-bit Address - 1:2 or 1:1 Output Demultiplexer Ratio Selection - Full or Partial Standby Mode - Analog Gain (1.5 dB) Digital Control - Input Clock Selection - Analog Input Switch Selection - Binary or Gray Logical Outputs - Synchronous Data Ready Reset - Data Ready Delay Adjustable on Both Channels - Interlacing Functions: Offset and Gain (Channel to Channel) Calibration Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel - Internal Static or Dynamic Built-In Test (BIT)
Dual 8-bit 500 Msps ADC
AT84AD004 Smart ADC Summary
Performance
* * * * * * * * * Low Power Consumption: 0.7W Per Channel Power Consumption in Standby Mode: 120 mW 1 GHz Full Power Input Bandwidth (-3 dB) SNR = 43 dB Typ (7.0 ENOB), THD = -53 dBc, SFDR = -55 dBc at Fs = 500 Msps Fin = 250 MHz 2-tone IMD3: -54 dBc (249 MHz, 5251 MHz) at 500 Msps DNL = 0.25 LSB, INL = 0.5 LSB Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration) Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration) Low Bit Error Rate (10-15) at 500 Msps
Application
* * * * Instrumentation Satellite Receivers Direct RF Down Conversion WLAN
5390AS-BDC-05/04
This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.
1
Description
The AT84AD004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 500 Msps and an input frequency bandwidth of 1 GHz. The dual concept, the integrated demultiplexer and the easy interleaving mode make this device user-friendly for all dual channel applications, such as direct RF conversion or data acquisition. The smart function of the 3-wire serial interface eliminates the need for external components, which are usually necessary for gain and offset tuning and setting of other parameters, leading to space and power reductions as well as system flexibility.
Functional Description
The AT84AD004 is a dual 8-bit 500 Msps ADC based on advanced high-speed BiCMOS technology. Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100). Two over-range bits are provided for the adjustment of the external gain control on each channel. A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments: * * * * * Analog input range adjustment (1.5 dB) with 8-bit data control using a 3-wire bus interface (steps of 0.18 dB) Analog input switch: both ADCs can convert the same analog input signal I or Q Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the output frequency on the data ready output signal Partial or full standby on channel I or channel Q Clock selection: - - - * * * * Two independent clocks: CLKI and CLKQ One master clock (CLKI) with the same phase for channel I and channel Q One master clock but with two phases (CLKI for channel I and CLKIB for channel Q)
ISA: Internal Settling Adjustment on channel I and channel Q FiSDA: Fine Sampling Delay Adjustment on channel Q Adjustable Data Ready Output Delay on both channels Test mode: decimation mode (by 16), Built-In Test
A calibration phase is provided to set the two DC offsets of channel I and channel Q close to code 127.5 and calibrate the two gains to achieve a maximum difference of 0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial interface. The AD84AD004 operates in fully differential mode from the analog inputs up to the digital outputs. The AD84AD004 features a full-power input bandwidth of 1 GHz.
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AT84AD004
5390AS-BDC-05/04
AT84AD004
Figure 1. Simplified Block Diagram
CLKI Clock Buffer DDRB Divider 2 to16 DRDA I
LVDS Clock Buffer
2
CLKIO
16 DoirI VINI VINIB Gain control I Calibration Gain/offset ISA I BIT Input switch INPUT MUX Gain control Q Calibration Gain/offset ISA Q & FiSDA DoirQ VINQ VINQB + S/H 8bit ADC Q DMUX 1: 2 or 1: 1 Q LVDS buffe r Q 3-wire Serial Interface 3WSI DMUX control 2 + S/H 8bit ADC I DMUX 1:2 or 1:1 I LVDS Buffer I
DOAI DOAIN DOBI DOBIN DOIRI DOIRIN
16 2
8
DMUX control Data Clock Ldn Mode DOIRQ DOIRQN DOAQ DOAQN DOBQ DOBQN
16 16
8
CLKQ Clock Buffer DDRB Divider 2 to 16 DRDA Q LVDS Clock Buffer 2 CLKQO
3
5390AS-BDC-05/04
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5390AS-BDC-05/04 0M

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