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| L4956 5A LOW DROP LINEAR REGULATOR SPLITTED SUPPLY VOLTAGE FOR IMPROVED EFFICIENCY: - VPW: 3V MIN. POWER SUPPLY VOLTAGE - VSIG: 4.5V MIN. SIGNAL SUPPLY VOLTAGE 5A OUTPUT CURRENT FAST LOAD TRANSIENT RESPONSE 0.75V TYP. DROP OUT VOLTAGE AT 5A INHIBIT WITH ZEROCURRENT COMSUMPTION POWER GOOD SHORT CIRCUIT PROTECTION THERMAL SHUTDOWN HEPTAWATT PACKAGE APPLICATIONS PENTIUMTM AND POWER PCTM SUPPLIES LOW COST SOLUTION FOR 3.3V TO 1.5V CONVERSION SUITABLE FOR APPLICATIONS WITH STAND BY FEATURE DESCRIPTION The L4956 is an adjustable monolithic linear regulator designed to satisfy very heavy load transient and efficient power conversion from 3.3V to 1.26V and lower, up to 5A. TYPICAL APPLICATION MULTIPOWER BCD TECHNOLOGY HEPTAWATT ORDERING NUMBER: L4956 Designed in BCDII technology, it uses a charge pump technique to have a proper internal N-channel gate drive. The signal supply voltage input VSIG can operate from 4.5V up to an absolute of 7V and the power supply voltage input VPW can opearte from 3V min to an absolute of 7V. An RDSON of 150mV gives a voltage drop of 750mV at 5A of load current. Very fast load transients and 1% of reference voltage precision makes this device suitable for supplying last micrprocessors generation and low voltage logics. The Heptawatt package enriches the device with auxiliary functions like power good and inhibit. INH VPW=3.3Vbus VPW VSIG 1 3 PG 6 7 OUT R1 5 4 GND D96IN374B VO VSIG= 5Vbus C1 C3 2 L4956 ADJ R2 C2 March 1998 1/8 L4956 ABSOLUTE MAXIMUM RATINGS Symbol VPW, VSIG Supply Input Voltage ADJ pin PG and INH pins PTOT Tst, Ti Power Dissipation @ Tamb = 50C Power Dissipation @ Tcase = 90C Storage Temperature Parameter Value 7 -0.3 to 4 0 to VSIG 2 15 -40 to +150 Unit V V V W W C PIN CONNECTION (Top view) 7 6 5 4 3 2 1 tab connected to pin 4 D96IN373 OUT PG ADJ GND INH VSIG VPW PIN FUNCTIONS No. 1 2 3 4 5 6 7 Name VPW VSIG INH GND ADJ PG OUT Function Unregulated power input voltage; this pin must be bypassed with a capacitor larger than 10F. Unregulated signal input voltage this pin has to be by passed with a minimum capacitor of 0.1F. TTL-CMOS input. A logic level on this input disable the device. An internal pull-down insures insures full functionally even if the pin is open. Ground. The output is connected directly to this terminal for 1.26V operation via divider for higher voltages. Open drain output, this pin is low when the output voltage is lower than 90%, otherwise is high. Regulated output voltage. A minimum bypass capacitor of 22F is required to insure stability. BLOCK DIAGRAM V PW 10F VSIG VSIG 2 VPW 1 V REF= 1.26V CURRENT LIMITATION CHARGE PUMP FOLDBACK PRE REGULATOR + - E/A BUFFER POWER DMOS 150m OUT 7 R1 ADJ 5 R2 V OUT 22F THERMAL SHUTDOWN INH 3 1.26V + 4 GND 6 PG 0.9VREF INHIBIT ACTIVE HIGH D96IN372A 2/8 L4956 THERMAL DATA Symbol Rth j-pins Rth j-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Shutdown Thermal Hysteresis Typ. Typ. Value 2.5 50 150 20 Unit C/W C/W C C ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise specified) Symbol VPW VSIG VOUT Parameter Power Operating Supply Voltage Signal Operating Supply Voltage Output Voltage (1) 0 < Tj < 125C; VPW = 3.3V 4.5V < VSIG < 6.5V; 0.1A < IO < 5A 3V < VPW < 5.5V; 4.5V< VSIG < 6.5V 0.1A < IO < 5A; 0 < Tj < 125C VOUT VOUT Line regulation (1) 3V < VPW < 5.5V; IO = 10mA 4.5V < VSIG < 6.5V VPW = 3.3V; VSIG = 5V 0.1A < IO < 5A IO = 5A IO = 5A, Tj = 125C 0 < Tj < 125C VO = 0V, 0 < Tj < 125C 0.1A < IO < 5A 4.5V < VSIG <6.5V INH = HIGH VSIG = 5V 0 < Tj < 125C 1.1 5.1 Test Condition Min. 3 4.5 1.240 1.224 1.260 1.260 0.5 1 0.75 1.1 6.3 1.8 1.5 100 1.26 0.2 5 0.9 x VOUT I6 = 4mA 0.1 0.2 0.4 10 3 150 1.42 Typ. Max. 6.5 6.5 1.280 1.296 3 5 1.1 1.5 7.5 Unit V V V V mV mV V V A A mA A V V A V V V Load regulation (1) Drop-out Voltage IO IQ Current Limiting Short Circuit Current Quiescent Current at pin VSIG Stand By Current at pin VSIG Inhibit Threshold Inhibit Histeresys Inhibit Bias Sink Current Power Good Threshold Power Good Saturation Power Good Histeresys (1) Output voltage connected to ADJ. 3/8 L4956 Figure 1. DC Operating Area. O utput C urrent [A] 8 7 6 5 4 3 2 D C O p e ra ting A rea Tc = 7 0 C P dm ax=2 2 W V pw > 3V V sig > 4.5 V T j = 1 25 C C u rre nt Lim ita ti o n Tc = 2 5 C P dm ax = 4 0 W Figure 2. Output Voltage Stability vs. Junction Temperature Vo ut [V ] 1 .2 8 1 .2 7 5 V pw = 3.3V V sig = 5V I out = 1 0m A R d son lim it P ow e r D issip a tio n L im it 1 .2 7 1 .2 6 5 1 .2 6 1 .2 5 5 1 .2 5 1 .2 4 5 1 0 0 1 2 3 4 5 6 (Vpw - Vout) [V ] 7 8 1 .2 4 -40 0 40 80 T j [C ] 12 0 160 Figure 3. Load Regulation. [m 5 4 3 2 1 O utput Voltage 0 -1 -2 -3 -4 -5 0 1 P u ls e d tec n iq u e h as b e e n u s e d V p w = 3.3 V V s i g = 5V Vo u t = Va d j T j = 2 5 C Figure 4. Dropout Voltage. 1 .2 5 [V] Vpw - Vout Voltage 1 T j = 1 2 5 C 0 .7 5 T j = 2 5 C 0 .5 Minimum Deviation Tj = -40 C 0 .2 5 P u ls ed te c hn iq u e h a s b e e n u s e d 2 3 I ou t [A ] 4 5 0 0 1 2 3 Io u t [A ] 4 5 6 Figure 5. Maximum Output Current vs. Junction Temperature O u tp u t C u rre nt [A ] 10 9 8 7 6 5 4 3 2 1 0 -4 0 -20 0 20 4 0 6 0 8 0 10 0 12 0 1 40 1 60 Tj [C ] P u ls e d te cn iq u e h a s b e e n u s e d (V p w -Vo u t) > 2 V Figure 6. Quiescent Current at pin VSIG vs. Junction Temperature. I q [m A ] 2 1 .8 1 .6 1 .4 1 .2 1 0 .8 0 .6 0 .4 -40 -20 0 40 6 0 8 0 1 00 120 14 0 1 60 T j [ C ] V S IG = 6 . 5 V I o u t = 1 0 m A to 5 A 3 V < V P W < 6 .5 V 20 4/8 L4956 Figure 7. Quiescent Current at pin VSIG vs. Signal Input Voltage. Iq [m A ] 3 2 .5 2 1 .5 1 0 .5 0 Io = 1 0 m A to T j = 2 5 C Figure 8. Stand-By Current at pin VSIG vs. Signal Input Voltage with INH = LOGIC HIGH I q [ A ] 1 50 5A 1 25 1 00 75 50 25 0 T j = 25 C 3 V < V P W < 6 .5 V 3 V < V P W < 6 .5 V 0 1 2 3 4 V S I G [V ] 5 6 7 4 4 .5 5 5 .5 6 V S IG [V ] 6 .5 7 Figure 9. Power Good Function V ADJ V OUT=VADJ (R1+R2)/R2 0.9 VADJ hyst = 200mV t PG Low High Low t D96IN364B Figure 10. Inhibit Function VINH Vref = 1.26V hyst = 200mV t regulator ON regulator OFF regulator ON D96IN365A t 5/8 L4956 LOAD TRANSIENT RESPONSE Figure 11. Figure 12. Vout 50mV/div CH1gnd Vout 50mV/div CH1gnd 5A 5A 0.5A CH2gnd Iout 2A/div t = 5s/div 0.5A CH2gnd Iout 2A/div t = 5s/div Figure 13. Test conditions: VPW = 3.3V; VSIG = 5; Vout = 1.5V; Load Transient from 0.5A to 5A; dlout = 20A/s; Tj = 25C dt Vout 50mV/div CH1gnd 5A 0.5A CH2gnd Iout 2A/div t = 100s/div Figure 14. Load transient test circuit. PG VIN=3.3V VPW VSIG=5V VSIG C1,C2 470F Panasonic HFQ 1 6 7 OUT R4 24 R5 126 C4 to C9 100F/10V AVX TPS 6 each C10 to C15 1F AVX X7R 6 each VOUT=1.5V 2 L4956 4 3 INH 5 ADJ C16 220nF GND D97IN593 6/8 L4956 HEPTAWATT PACKAGE MECHANICAL DATA DIM. A C D D1 E F F1 G G1 G2 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 Dia 3.65 2.6 15.1 6 2.8 5.08 3.85 0.144 10.05 16.97 14.92 21.54 22.62 3 15.8 6.6 0.102 0.594 0.236 0.110 0.200 0.152 2.41 4.91 7.49 2.54 5.08 7.62 2.4 1.2 0.35 0.6 MIN. mm TYP. MAX. 4.8 1.37 2.8 1.35 0.55 0.8 0.9 2.67 5.21 7.8 10.4 10.4 0.396 0.668 0.587 0.848 0.891 0.118 0.622 0.260 0.095 0.193 0.295 0.100 0.200 0.300 0.094 0.047 0.014 0.024 MIN. inch TYP. MAX. 0.189 0.054 0.110 0.053 0.022 0.031 0.035 0.105 0.205 0.307 0.409 0.409 7/8 L4956 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 8/8 |
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