View 3763_967550.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 16-Bit A/D Converter 1 MSPS S/(N+D): 90 dB Typ @ 250KHz 14-Bit D/A Converter Settling Time: 1 ms S/N: 92 dB Typ Two 80 MHz Amplifiers 30 V/ms Slew Rate Rail-to-Rail Input and Output Two Gain Setting Center Tapped Resistors Resistor Ratio Tracking: 2 ppm/C Unipolar Operation 132 mW Typical Power Dissipation APPLICATIONS Optical MEMS Mirror Control Industrial Process Control Data Acquistion Instrumentation Communication
VREF
1 MSPS 16/14 Bit Analog I/O Port AD15700
Functional Block Diagram
VDD_DAC DGND_DAC
14-BIT DAC
VOUT_DAC AGND_DAC
_______ CS_DAC DIN SCLK CONTROL LOGIC
14-BIT DATA LATCH
-IN1 +IN1 +VS1
SERIAL INPUT REGISTER
VOUT1 -VS1
COMMON
AD15700
RA1
1.5K
RB1
1.5K
REF REFGND IND(4R) INC(4R) INB(2R) INA(R) INGND VOUT2 4R 4R 2R R SWITCHED CAP DAC PARALLEL 16 INTERFACE CLOCK SAR ADC CONTROL LOGIC AND CALIBRATION CIRCUITRY SERIAL PORT SER/PAR BUSY DATA[15:0] _______ CS_ADC __ RD OB/2C BYTESWAP AVDD OVDD OGND RC1 RPAD1
GENERAL DESCRIPTION
The AD15700 is a precision component to interface analog input and output channels to a digital processor. It is ideal for area-limited applications that require maximum circuit density. The AD15700 contains the functionality of a 16-bit, 1 MSPS charge redistribution SAR analog-to-digital converter that operates from a 5 V power supply. The high-speed 16-bit sampling ADC incorporates a resistor input scaler which allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD15700 also contains a 14-bit, serial input, voltage output DAC that operates from a 5 V supply and has a settling time of 1 s. Two single or split supply voltage feedback amplifiers with rail-to-rail input and output characteristics featuring 80 MHz of small signal bandwidth and 10 V/C offset drift provide ADC and DAC buffering capability. The center tapped 3K resistors are precision resistor networks with 2 ppm/C ratio tracking that provide low gain drift when used for scaling.
+VS2 +IN2 -IN2 -VS2 PD RESET
1.5K 1.5K
RPAD2 ______ WARP CNVST IMPULSE
AGND_ADC
RA2 RB2 RC2
DVDD DGND ADC
The ADC, DAC and Amp functions are electrically isolated from each other to provide maximum design flexibility. Input and output signal conditioning circuits for the converters can be easily configured with short interconnects under the device at the board level. The AD15700 is available in a 10 mm Mini-BGA package.
REV. PrD 6/06/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA AD15700 16-BIT ADC ELECTRICAL CHARACTERISTICS
PARAMETER RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise Bipolar Zero Error 2 , TMIN to TMAX Bipolar Full-Scale Error2 , TMIN to T MAX Unipolar Zero Error2 , TMIN to TMAX Unipolar Full-Scale Error2 , TMIN to T MAX Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH I IL I IH CONDITION Min 16
(-40 C to +85 C, AVDD = DVDD = 5V, O VDD = 2.7 V TO 5.25 V, unless otherwise noted.)
Typ Max UNITS Bits
VIND - VINGND VINGND fIN = 100 kHz
4 REF, 0V to 4 REF, 2 REF (See Table I)
-0.1 74 See Table I
+0.5
V dB
In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode
1
0 0
1 1000 1 1.25 800 1.5 666
s kSPS ms s kSPS s kSPS
-2.5 16 0.7 5 V Range, Normal or Impulse Modes Other Range or Mode -45 0.1% -0.38 -0.18 -0.76 AVDD = 5 V 5% 9.5
+2.5
+45
LSB 1 Bits LSB LSB % of FSR % of FSR % of FSR % of FSR LSB
+0.38 +0.18 +0.76
FIN = 20 kHz 89 FIN = 250 kHz FIN = 250 kHz FIN = 20 kHz FIN = 250 kHz FIN = 20 kHz 88.5 FIN = 250 kHz, -60 dB Input
90 90 100 -100 -100 90 30 9.6
-96
dB 3 dB dB dB dB dB dB MHz
2 5 Full-Scale Step 250
ns ps rms ns
2.3 1 MSPS Throughput
2.5 200
3.0
V A
-0.3 +2.0 -1 -1
+0.8 DVDD+0.3 +1 +1
V V A A
-2-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
PARAMETER
DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current4 AVDD DVDD5 OVDD5 Power Dissipation5,6 I SINK= 1.6 mA I SOURCE= -570 A
CONDITION
Min
Typ
Max
UNITS
Parallel or Serial 16-Bit Conversion Results Available Immediately after Completed Conversion 0.4 OVDD-0.6
V V
4.75 4.75 2.7
5 5
5.25 5.25 5.25
V V V mA mA A mW W mW mW
666 kSPS Throughput7 100 SPS Throughput7 1 MSPS Throughput4
15 7.2 37 84 15 112
95 125 1
In Power-Down Mode8 TEMPERATURE RANGE Specified Performance
NOTES: 1. LSB means Least Significant Bit. With the 5 V input range, one LSB is 152.588 V. 2. These specifications do not include the error contribution from the external reference. 3. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 4. In warp mode. 5. Tested in parallel reading mode. 6. Tested with the 0 V to 5 V range and VIN - VINGND = 0 V. 7. In impulse mode. 8. With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND respectively.
TMIN to TMAX
-40
+85
C
Specifications subject to change without notice.
Table I. Analog Input Configuration Input Voltage Range 4 REF 2 REF REF 0 V to 4 REF 0 V to 2 REF 0 V to REF IND (4R) INC (4R)
INB (2R)
INGND INGND
VIN
INA (R)
REF REF REF INGND INGND
VIN
Input Impedance1
VIN VIN VIN VIN VIN VIN
INGND
VIN VIN VIN VIN VIN
1.63 k 948 711 948 711 Note 2
INGND
VIN VIN
NOTES:
1. Typical analog input impedance. 2. For this range the input is high impedance.
REV. PrD 6/06/02
-3-
PRELIMINARY TECHNICAL DATA AD15700 16-BIT ADC TIMING SPECIFICATIONS
Symbol
(-40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Min 5 1/1.25/1.5 Typ Max Unit ns s ns s
Refer to Figures 75 and 76 Convert Pulsewidth Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Warp Mode/Normal Mode/ Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/ Impulse Mode) Acquisition Time RESET Pulsewidth Refer to Figures 77,78, and 79 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figures 81 and 82 (Master Serial Interface Modes)2 CS_ADC LOW to SYNC Valid Delay CS_ADC LOW to Internal SCLK Valid Delay CS_ADC LOW to SDOUT Delay CNVST LOW to SYNC Delay (Read During Convert) (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay 3 Internal SCLK Period3 Internal SCLK HIGH3 Internal SCLK LOW3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SCLK Last Edge to SYNC Delay3 CS_ADC HIGH to SYNC HI-Z CS_ADC HIGH to Internal SCLK HI-Z CS_ADC HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert3 CNVST LOW to SYNC Asserted Delay Master Serial Read after Convert SYNC Deasserted to BUSY LOW Delay Refer to Figures 83 and 85 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW
t1 t2 t3 t4
Note 1 30 0.75/1/1.25
t5 t6 t7 t8 t9
2 10 0.75/1/1.25 1 10
ns ns s s ns
t10 t11 t12 t13 20 5
0.75/1/1.25
s ns ns ns
40 15
t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 4 25 15 9 4.5 2 3
10 10 10 25/275/525
ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns
40
10 10 10 See Table II 0.75/1/1.25 25
t31 t32 t33 t34 t35 t36 t37
5 3 5 5 25 10 10
16
ns ns ns ns ns ns ns
NOTES 1 In warp mode only,the maximum time between conversions is 1 ms,otherwise,there is no required maximum time. 2 In serial interface modes,the SYNC,SCLK,and SDOUT timings are defined with a maximum load CL of 10 pF;otherwise,the load is 60 pF maximum. 3 In serial master read during convert mode.See Table II. Specifications subject to change without notice.
-4-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700 16-BIT ADC TIMING SPECIFICATIONS (Continued)
Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY HIGH Width Maximum (Warp) BUSY HIGH Width Maximum (Normal) BUSY HIGH Width Maximum (Impulse) t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 0 0 4 25 40 15 9 4.5 2 3 1.5 1.75 2 0 1 20 50 70 25 24 22 4 60 2 2.25 2.5 1 0 20 100 140 50 49 22 30 140 3 3.25 3.5 1 1 20 200 280 100 99 22 89 300 5.25 5.5 5.75
Unit ns ns ns ns ns ns ns ns s s s
1 .6mA
IOL
TO OUTPUT PIN
1.4V C L 60 pF* 50 0mA IOH
NOTE * IN SER IAL INTER FACE MODES, THESYNC SCLK, AND , SDOUT TIMINGS AR D E EFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHER WISE, TH LOAD IS 60pF MAXIMUM. E
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10pF
2V 0 .8 V
t DEL AY
2V 0.8 V
t DELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timing
Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrD 6/06/02
-5-
PRELIMINARY TECHNICAL DATA AD15700 14-BIT DAC ELECTRICAL CHARACTERISTICS
PARAMETER STATIC PERFORMANCE Resolution Relative Accuracy, INL Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance 1 LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance Hysteresis Voltage REFERENCE Reference -3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance CONDITION
(TA= -40 C to +85 C, VDD_DAC = 5V, VREF = 2.5V, unless otherwise noted.)
Min
Typ
Max
UNITS
1 LSB = VREF/214 = 153V when VREF = 2.5 V Guaranteed Monotonic
14 0.15 0.15 -0.3 0.1 0.1 0.05 1.0 0.8 0 0.5
-1.75 0
Bits LSB LSB LSB ppm/C LSB ppm/C
0 To 1/2 LSB of FS, CL = 10 pF 1 LSB Change Around the Major Carry All 1s Loaded to DAC, VREF= 2.5 V Tolerance Typically 20% VDD 10%
VREF -1 LSB 1 10 .05 6.25 1.0
V s nV-s nV-s k LSB
2 9
VDD
V k
1.0 0.8 2.4 10 0.4
A V V pF V
All 1s Loaded All 0s Loaded, VREF= 1 V p-p at 100 kHz Code 0000H Code 3FFFH
1.3 1 92 75 120
MHz mV p-p dB pF pF
POWER REQUIREMENTS VDD IDD Power Dissipation
4.5 0.3 1.5
5.50 1.1 6.05
V mA mW
NOTE: 1. Reference input resistance is code-dependent, minimum at 2555H. Specifications subject to change without notice.
-6-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700 14-BIT DAC ELECTRICAL CHARACTERISTICS1,2
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit at TMIN, TMAX All Versions 25 40 20 20 15 15 35 20 15 0 30 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
(VDD = 5 V, 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted.)
Description SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time CS_DAC Low to SCLK High Setup CS_DAC High to SCLK High Setup SCLK High to CS_DAC Low Hold Time SCLK High to CS_DAC High Hold Time Data Setup Time Data Hold Time CS_DAC High Time Between Active Periods
NOTES Guaranteed by design.Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr =tf =5 ns (10%to 90%of +3 V and timed from a voltage level of +1.6 V).
1
Specifications subject to change without notice.
t1
SCLK
t6 t4
CS_DAC
t2
t3 t7
t5
t1 0 t8 t9
DIN
DB13
DB0
Figure 3. Timing Diagram
REV. PrD 6/06/02
-7-
PRELIMINARY TECHNICAL DATA AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS
PARAMETER DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise CONDITION G = +1, VO < 0.4 V p-p G = -1, VO = 2 V Step G = -1, VO = 2 V Step, CL = 10 pF
(+5 V Supply (TA = +25 C, VS= +5V, R L = 1 k to +2.5V, R F = 2.5 k , unless otherwise noted.))
Min
Typ
Max
UNITS
54 27
80 32 125
MHz V/s ns
fC = 1 MHz, VO = 2 V p-p, G = +2 fC = 100 kHz, VO = 2 V p-p, G = +2 f = 1 kHz f = 100 kHz f = 1 kHz R L = 1 k R L = 1 k
-62 -86 15 2.4 5 0.17 0.11
dBc dBc nV/ Hz pA/ Hz pA/ Hz % Degrees
Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current Input Offset Current Open Loop Gain
VCM = VCC/2; VOUT = 2.5 V TMIN to TMAX VCM = VCC/2; VOUT = 2.5 V VCM = VCC/2; VOUT = 2.5 V TMIN to TMAX VCM = VCC/2; VOUT = 1.5 V to 3.5 V TMIN to TMAX 76 74
1 6 5 0.45 50 82
6 10 1.2 2.0 350
mV mV V/C A A nA dB dB
INPUT CHARACTERISTICS Common-Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common-Mode Voltage Range Common-Mode Rejection Ratio Differential/Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing High Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio
VCM = 0 V to +5 V VCM = 0 V to +3.8 V
56 66
40 280 1.6 -0.5 to +5.5 -0.2 to +5.2 70 80 3.4
M k pF V V dB dB V
R L = 10 k R L = 1 k
+0.05 +4.95 +0.2 +4.8
Sourcing Sinking G = +2
+0.02 +4.98 +0.1 +4.9 15 28 -46 15
V V V V mA mA mA pF
+2.7 VS- = 0 V to -1 V or VS+ = +5 V to +6 V 75 800 86
+12 1400
V A dB
OPERATING TEMPERATURE RANGE Specifications subject to change without notice.
-40
+85
C
-8-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS
PARAMETER DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise CONDITION
(5 V Supply (TA = +25 C, VS= 5V, R L = 1 k to 0V, R F = 2.5 k , unless otherwise noted.))
Min
Typ
Max
UNITS
G = +1, VO < 0.4 V p-p G = -1, VO = 2 V Step G = -1, VO = 2 V Step, CL = 10 pF
54 30
80 35 125
MHz V/s ns
fC = 1 MHz, VO = 2 V p-p, G = +2 fC = 100 kHz, VO = 2 V p-p, G = +2 f = 1 kHz f = 100 kHz f = 1 kHz R L = 1 k R L = 1 k
-62 -86 15 2.4 5 0.15 0.15
dBc dBc nV/ Hz pA/
Hz
Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current Input Offset Current Open Loop Gain
pA/ Hz % Degrees
VCM = 0V; VOUT = 0V TMIN to TMAX VCM = 0V; VOUT = 0V VCM = 0V; VOUT = 0V TMIN to TMAX VCM = 0V; VOUT = 2V TMIN to TMAX 76 74
1 6 5 0.45 50 80
6 10 1.2 2.0 350
mV mV V/C mA mA nA dB dB
INPUT CHARACTERISTICS Common-Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common-Mode Voltage Range Common-Mode Rejection Ratio Differential/Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing High Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio
VCM = -5 V to +5 V VCM = -5 V to +3.5 V
60 66
40 280 1.6 -5.5 to +5.5 -5.2 to +5.2 80 90 3.4
M k pF V V dB dB V
R L = 10 k R L = 1 k
-4.94 +4.94 -4.7 +4.7
Sourcing Sinking G = +2
-4.98 +4.98 -4.85 +4.75 15 35 -50 15
V V V V mA mA mA pF
1.35 VS- = -5 V to -6 V or VS+ = +5 V to +6 V 76 900 86
6 1600
V A dB
OPERATING TEMPERATURE RANGE Specifications subject to change without notice.
-40
+85
C
REV. PrD 6/06/02
-9-
PRELIMINARY TECHNICAL DATA AD15700 RESISTOR DIVIDER ELECTRICAL CHARACTERISTICS
PARAMETER Resistance Temperature Coefficient of Resistance Resistance Ratio of Two Halves Resistance Ratio Tracking Power Dissipation NOTE:
1. At higher temperatures, linearly derate to 0 mW at 175C. Specifications subject to change without notice.
(@TA = 25 C, unless otherwise noted.)
Min 2.97 0.99
CONDITION
Typ
3.00 50 1.0
Max
3.03 1.01 2 2501
UNITS k ppm/C ppm/C mW
TA = +70C
AD15700 ABSOLUTE MAXIMUM RATINGS
Analog Inputs IND, INC, INB ................................... -11 V to +30 V INA, REF, INGND, REFGND, AGND ............................... -0.3 V to AVDD + 0.3 V ADC Ground Voltage Differences AGND_ADC, DGND_ADC, OGND ................. 0.3 V ADC Supply Voltages AVDD, DVDD, OVDD ....................................... 7 V AVDD to DVDD, AVDD to OVDD ..................... 7 V DVDD to OVDD .............................................. 7 V ADC Digital Inputs ......................-0.3 V to DVDD + 0.3 V VDD_DAC to AGND_DAC ........................ -0.3 V to +6 V DAC Digital Input Voltage to DGND_DAC .......................... -0.3V to DVDD +0.3 V VOUT_DAC to AGND_DAC ......... -0.3V to DVDD +0.3 V AGND_DAC to DGND_DAC .................. -0.3 V to +0.3 V
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DAC Input Current to Any DAC Pin Except Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Amplifier Supply Voltage (VS1, VS2) . . . . . . . . . . +12.6 V Amplifier Input Voltage (Common-Mode) . . . . VS 0.5 V Amplifier Differential Input Voltage . . . . . . . . . . . . 3.4 V Amplifier Output Short Circuit Duration . . . . . . . . . . . . Observe Power Derating Curves Resistor Instantaneous Voltage Drop . . . . . . . . . . . 50 V Internal Power Dissipation . . . . . (TJ MAX - TA)/ THETAJA Thermal Resistance THETAJA 10 mm CABGA . . . . . . . . . . . . . . . . . . . . . . . 42C/W Maximum Junction Temperature (TJ MAX) . . . . . . . 150C Operating Temperature Range . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . -65C to +150C Lead Temperature . . . . . . . . . . . . . . . . . . +225C, 15 sec
Ordering Information Temperature Range -40C to 85C 25C Package Description 144-BGA Evaluation Board Evaluation Kit*
Model AD15700BCA AD15700/PCB
ADSP-2191 EZ-KIT LiteTM ADSP-21535 EZ-KIT LiteTM ADSP-21160M EZ-KIT LiteTM ADSP-21161N EZ-KIT LiteTM
25C
* One of the DSP Evaluation Kits in required for operation of the AD15700/PCB Evaluation Board.
-10-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
ADC PIN FUNCTION DESCRIPTIONS Pin No.
H9, J8, J9,M12 M6 L7
Mnemonic
AGND_ADC AVDD BYTESWAP
Type
P P DI
Description
Analog Power Ground Pin Input Analog Power Pin. Nominally 5 V. Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Two's Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a two's complement output from its internal shift register. Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is HIGH, EXT/ is LOW and RDC/SDIN is LOW, which is the se rial master read DIVSCLK[0:1] after convert mode. These inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode.With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input and the external clock is gated by CS_ADC. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/ SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initia tion of the read sequence.When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.
L8
OB/ 2C
DI
M7
WARP
DI
L9
IMPULSE
DI
M8
SER/PAR
DI
M9, L10 M10, L11
DATA[0:1] DATA[2:3] or
DO DI/O
M11
DATA[4] or EXT/INT
DI/O
L12
DATA[5] or INVSYNC
DI/O
K11
DATA[6] or INVSCLK
K12
DATA[7] or RDC/SDIN
DI/O
REV. PrD 6/06/02
-11-
PRELIMINARY TECHNICAL DATA AD15700
J10 J11 J12 H10 H12 OGND OVDD DVDD DGND_ADC DATA[8] or SDOUT P P P P DO Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3.3 V). Digital Power. Nominally at 5 V. Digital Power Ground When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7671 provides the conversion result, MSB first, from its inter nal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH:If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must be Tied to Digital Ground. Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial output bus is enabled. CS_ADC is also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/ hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started.
H11
DATA[9] or SCLK
DI/O
G12
DATA[10] or SYNC
DO
G11
DATA[11] or RDERROR
DO
F12,F11, E12,E11 G10
DATA[12:15] BUSY
DO DO
G9 E10 K10
DGND_ADC RD CS_ADC
P DI DI
D12
RESET
DI
K9 E7
PD CNVST
DI DI
-12-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
H8 G5 H5 J7 J5, K5, L5, M5 AGND_ADC REF REFGND INGND INA, INB, INC, IND P AI AI P AI Must be Tied to Analog Ground. Reference Input Voltage. Reference Input Analog Ground. Analog Input Ground Analog Inputs. Refer to Table I for input range configuration.
DAC PIN FUNCTION DESCRIPTIONS Pin No. A6 A3,C3,C4 A2 B1 E1 E2 E3 C6 Mnemonic VOUT_DAC AGND_DAC VREF CS_DAC SCLK DIN DGND_DAC VDD_DAC Type AO P AI DI DI DI P P Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. This is the voltage reference input for the DAC. Connect to exter nal reference ranges from 2 V to VDD. This is an active low logic input signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V 10%. AMPLIFIER PIN FUNCTION DESCRIPTIONS Pin No. C9 (J1) A9 (G1) B12 (K4) A11 (F3) B10, B11 (G3, H3) Mnemonic +IN1(2) -IN1(2) VOUT1(2) +VS1(2) -VS1(2) Type AI AI AO P P Description Positive Input Voltage. Negative Input Voltage. Amplifier Output Voltage. Analog Positive Supply Voltage. Analog Negative Supply Voltage.
RESISTOR PIN FUNCTION DESCRIPTIONS Pin No. B9 (L4) A8 (M4) D9 (L1) A7 (M3) Mnemonic RA1(2) RB1(2) RC1(2) RPAD1(2) Type AI/O AI/O AI/O P Description Resistor End Terminal. Resistor Center Tap. Resistor End Terminal. Resistor Die Pad. Tie to Analog Ground. COMMON PIN FUNCTION DESCRIPTION Pin No. A1,A4,A5,A10,A12,B2-B8,C1, C2,C5,C7,C8,C10-C12,D1-D8, D10,D11,E4-E6,E8,E9,F1,F2, F4-F10,G2,G4,G6-G8,H1,H2, H4,H6,H7,J2-J4,J6,K1-K3, K6-K8,L2,L3,L6,M1,M2 Mnemonic COMMON Type P Description Common Floating Net Connecting 69 Pins. Not electrically connected within the module. Tie at least one of these pins to Analog Ground.
NOTES: AI = Analog Input. AI/O = Bidirectional Analog. DI = Digital Input. DI/O = Bidirectional Digital. DO = Digital Output. P= Power.
REV. PrD 6/06/02
-13-
PRELIMINARY TECHNICAL DATA AD15700
ADC DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Effective Number of Bits (ENOB)
Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale". The point used as "negative full scale" occurs 1/2 LSB before the first code transition."Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
A measurement of the resolution with a sine wave input. It is related to S/(N+D)by the following formula:
ENOB =((S/[N +D]dB - 1.76))/6.02)
and is expressed in bits.
Total Harmonic Distortion (THD)
The rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
Signal-to-Noise Ratio (SNR)
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value.It is often specified in terms of resolution for which no missing codes are guaranteed.
Full-Scale Error
The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels. Signal-to-(Noise + Distortion) Ratio (S/[N+D])
The last transition (from 011 ...10 to 011 ...11 in two 's complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.499886 V for the 2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
BIPOLAR ZERO ERROR
The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
Aperture Delay
The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
Unipolar Zero Error
A measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion.
Transient Response
In unipolar mode,the first transition should occur at a level 1/2 LSB above analog ground. The unipolar zero error is the deviation of the actual transition from that point.
Spurious Free Dynamic Range (SFDR)
The time required for the ADC to achieve its rated accuracy after a full-scale step function is applied to its input.
The difference,in decibels (dB),between the rms amplitude of the input signal and the peak spurious signal.
-14-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
DAC DEFINITION OF SPECIFICATIONS Relative Accuracy Digital-to-Analog Glitch Impulse
For the DAC relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in Figure 19.
Differential Nonlinearity
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in Figure 89.
Digital Feedthrough
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Figure 22 illustrates a typical DNL versus code plot.
Gain Error
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS_DAC is held high, while the CLK and DIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus,i.e.,from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 88.
Power Supply Rejection Ratio
Gain error is the difference between the actual and ideal analog output range,expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C.
Zero Code Error
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Powersupply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied by 10%.
Reference Feedthrough
Zero code error is a measure of the output error when zero code is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/C.
REV. PrD 6/06/02
-15-
PRELIMINARY TECHNICAL DATA AD15700
2.5 2.0 1.5 1.0 50
16-BIT A/D Converter Typical Performance Characteristics
60
NUMBER OF UNIT S
0 16 3 84 CODE 3 27 6 8 49 1 52
40
INL - LSB
0.5 0 - 0 .5 - 1 .0 - 1 .5
30
20
10 - 2 .0 - 2 .5 0 - 3 .0
- 2.7
- 2 .4
- 2 .1
- 1 .8
- 1 .5
- 1 .2
- 0 .9
- 0.6
NEGATIV E INL - LSB
Figure 4. Integral Nonlinearity vs Code
Figure 7. Typical Negative INL Distribution (314 Units)
1 .7 5 1 .5 0 1 .2 5
800 0 700 0 600 0 7029 703 9
1 .0 0
D NL - LSB
COUNTS
0 .7 5 0 .5 0 0 .2 5 0
500 0 400 0 300 0 200 0
- 0 .2 5 - 0 .5 0 - 0 .7 5 - 1 .0 0 0 16 3 8 4 32768 CODE 4 91 5 2 65 53 6 100 0 0 0 0 17
1297 98 6 25 0 0
7FFD 7FFE 7FFF 80 00 80 01 8 002 800 3 8 004 80 05 8005 CODE IN HEXA
Figure 5. Differential Nonlinearity vs Code
Figure 8. Histogram of 16,384 Conversions of a DC Input at the Code Transition
60
100 00 9 000
9503
50
8 000 7 000
NUMBER OF UNITS
40
30
COUNTS
6 000 5 000 4 000 3 296 3344
20 3 000 10 2 000 1 000 0 0 0 .3 0.6 0 .9 1 .2 1.5 POSITIVE INL - LSB 1.8 2 .1 2 .4 0 0 0 2 132
1 06
1
0
0
7FFC 7FFD 7FFE 7FFF 8 000 800 18 002 800 380 048 005 800 6 CODE IN HEXA
Figure 6. Typical Positive INL Distribution (314 Units)
Figure 9. Histogram of 16,384 Conversions of a DC Input at the Code Center
-16-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA 16-BIT A/D Converter Typical Performance Characteristics
0 - 20 FS = 1 MSPS f IN = 45.5322kHz SNR = 89 .45dB THD = - 100 .05dB SFDR = 100 .49dB SINAD = 8 9.1dB 96
AD15700
- 98
AMPLITUDE - dB of Full Scale
- 40 - 60
93 - 1 00 THD
- 80 - 1 00 - 1 20 - 1 40 - 1 60 - 1 80 0
90 SNR - 1 02 87
100
200 300 FR EQUENCY - kHz
40 0
500
84 - 55
- 35
- 15
5
25
45
65
85
- 1 04 1 05
TEMPER UR - C AT E
Figure 10. FFT Plot
Figure 13. SNR, THD vs Temperature
10 0
16.0
- 60 - 65 SFDR
11 0 10 5 10 0 95
95
15.5 SNR
- 70
SNR AND S/ [N+D] - dB
90 SINAD 85 ENOB 80
15.0
THD, HARMONICS - dB
- 75 - 80 - 85
ENOB - Bit s
14.5
85 - 90 - 95 - 1 00 - 1 05 - 11 0 3 RD HARMONIC 2ND HARMONIC T HD 80 75 70 65 60 10 FREQUENCY - k Hz 10 0
14.0
75
13.5
70 1 10 100 FREQUENCY - kHz
13.0 1 000
- 11 5 1
Figure 11. SNR, S/(N + D), and ENOB vs Frequency
Figure 14. THD, Harmonics, and SFDR vs Frequency
10 0
1 6.0
- 60 - 70
95
1 5.5 - 80 SNR
SNR AND S/ [N+D] - dB
THD, HARMONICS - d B
90 SINAD 85 ENOB 80
1 5.0
- 90 - 10 0 2 ND HA RMO NIC - 110 - 12 0 - 13 0 T HD
1 4.5
1 4.0
ENOB - Bit s
75
1 3.5 - 14 0
3 RD H ARM ONIC
70 1
10 1 00 FR EQUENCY - k Hz
1 3.0 100 0
- 15 0 - 60
- 50
- 40
- 30
- 20
-1
IN PUT LEV EL - dB
Figure 12. SNR vs Input Level
Figure 15. THD, Harmonics vs Input Level
REV. PrD 6/06/02
-17-
SFDR - dB
90
THD - dB
SNR - dB
PRELIMINARY TECHNICAL DATA AD15700
50
16-BIT A/D Converter Typical Performance Characteristics
1000
POWER-DOWN OPER ATING CUR RENTS - nA
900 800 700 600 500 400 300 200 100 0 - 55 OV DD AV D D DV DD
40
t 1 2 DELAY - ns
30
20
10
0 0 50 CL - p F 10 0 15 0
- 35
- 15
5
25
45
65
T EMPERAT URE - C
Figure 16. Typical Delay vs Load Capacitance CL
Figure 18. Power-Down Operating Currents vs Temperature
10 000 0
AVDD, W P NO M AR / R AL
10 000
DVDD W R /NO AL , A P RM
OPERAT ING CURRENTS - mA
10 00 100 10 0 0 .1
AVDD IMP LSE , U
DVD , IMP D ULSE OVD ALL M E D, OD S
0.0 1 0 .001 1
10
100
100 0
1 000 0
1000 00 10 000 0
SAMPLING RATE - SPS
Figure 17. Operating Currents vs Sample rate
-18-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA 14-BIT D/AConverter Typical Performance Characteristics
0.5 TA = 25C V DD = 5V V REF = 2.5V 0.25 0.25 0.5 TA = 25C VD D = 5V VR E F = 2.5V
AD15700
INL - LSB
0
DNL - LSB
0 2048 4096 6144 8192 10240 12288 14336 16384
0
-0.25
-0.5
-0.5 0
2048
4096
6144
8192
10240 12288 14336 16384
CODE - Decimal
CODE - Decimal
Figure 19. Integral Nonlinearity vs Code
Figure 22. Differential Nonlinearity vs Code
0.5 V DD = 5V V REF = 2.5V 0.25
0.5 VDD = 5V VREF = 2.5V 0.25
DNL - LSB
INL - LSB
0
0
-0.25
-0.25
-0.5 -60 -20 20 60 TEMPERATURE - C 100 140
-0.5 -60
-20
20 60 TEMPERATURE - C
100
140
Figure 20. Integral Nonlinearity vs Temperature
1.0 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1.0 INL VR E F = 2.5V TA = 25C DNL
Figure 23. Differential Nonlinearity vs Temperature
0.5 VD D = 5V TA = 25C DNL
LINEARITY ERROR - LSB
LINEARITY ERROR - LSB
0.25
0
INL
-0.25
-0.5 2 3 4 5 SUPPLY VOLTAGE - V 6 7
0
1
2
3
4
5
6
REFERENCE VOLTAGE
Figure 21. Linearity Error vs Supply Voltage
Figure 24. Linearity Error vs Reference Voltage
REV. PrD 6/06/02
-19-
PRELIMINARY TECHNICAL DATA AD15700
1.00 0.75 0.50 V DD = 5V V RE F = 2.5V
14-BIT D/AConverter Typical Performance Characteristics
0.75 VDD = 5V VREF = 2.5V
ZERO-CODE OFFSET ERROR - LSB
150
GAIN ERROR - LSB
0.25 0 -0.25 -0.5 0 -0.7 5 -1.0 -50 0 -25 0 25 50 75 100 125
0.50
0.25
TEMPERATURE - C
0 -50
-25
0
25 75 50 TEMPERATURE - C
100
125
150
Figure 25. Gain Error vs Temperature
250 VDD = 5V VLOGIC = 5V VREF = 2.5V
Figure 28. Zero-Code Error vs Temperature
450 TA = 25C 400
SUPPLY CURRENT - mA
SUPPLY CURRENT - mA
350
200
300
REFERENCE VOLTAGE VD D = 5V
SUPPLY VOLTAGE VR EF = 2.5V
250
200
150 -40
-20
0
20 40 60 TEMPERATURE - C
80
100
120
150 0
1
2
3 VOLTAGE - V
4
5
6
Figure 26. Supply Current vs Temperature
Figure 29. Supply Current vs Reference Voltage or Supply Voltage
400 VDD = 5V VREF = 2.5V
300 TA = 25C VD D = 5V VR EF = 2.5V
350
REFERENCE CURRENT - mA
TA = 25C
250
SUPPLY CURRENT - m A
200
300
150 UNIPOLAR MODE 100
250
200
50
150
0
1
2 3 DIGIT INPUT VOLTAGE - V AL
4
5
0 0
2048
4096
6144
8192
10240 12288 14336 16384
Figure 27. Supply Current vs Digital Input Voltage
Figure 30. Reference Current vs Code
-20-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA Amplifier Typical Performance Characteristics
800 600
AD15700
INPUT BIAS CURRENT - nA
400 200 0 -200 -400 -600 -800 VS = +2.7V V S = +5V VS = +10V
0
1
2
3 4 5 6 7 8 COMMON-MODE VOLTAGE - V
9
10
Figure 31. Typical VOS Distribution @ VS = 5V
Figure 34. Input Bias Current vs Common-Mode Voltage
0 2.5 -0.1 V S = +5V
OFFSET VOLTAGE - mV
2.3
OFFSET VOLTAGE - mV
-0.2
2.1 VS = +5V
-0.3
1.9 VS = 65V 1.7
-0.4
-0.5
-0.6 1.5 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE - 8C 60 70 80 90
0
0.5
1
1.5 2 2.5 3 3.5 4 COMMON-MODE VOLTAGE - V
4.5
5
Figure
32.
Input Offset Temperature
Voltage
vs
Figure 35. VOS vs Common-Mode Voltage
1 0.95 0.9 0.85
1000 950 6IS , VS = 65V
SUPPLY CURRENT/AMPLIFIER - mA
VS = +5V
900 850 800 750 +IS , V S = +2.7V 700 650 600 -40 -30 - 20 -10 +IS , VS = +5V
INPUT BIAS - mA
0.8 0.75 0.7 0.65 0.6 0.55 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 TEMPERATURE - 8C 70 80 90
0
10 20 30 40 50 TEMPERATURE - 8C
60
70 80
90
Figure 33. Input Bias Current vs Temperature
Figure 36. Supply Current vs Temperature
REV. PrD 6/06/02
-21-
PRELIMINARY TECHNICAL DATA AD15700
0 VC C = +2.7V 1 VC C = +10V 0.8 VIN VE E 0.6 VC C = +5V 0.4 VCC 2 VOUT RL OAD VC C
Amplifier Typical Performance Characteristics
1.2
DIFFERENCE FROM VC C - Volts
-0.5
-1
VC C = +5V VC C
-1.5 VCC = +10V -2 VIN VE E VC C 2 VOU T RLOA D
DIFFERENCE FROM V EE - Volts
0.2 V CC = +2.7V 0 100
-2.5 100
1k RL OAD - Ohms
10k
1k RL OAD - Ohms
10k
Figure 37. + Output Saturation Voltage vs RLOAD @ +85C
0
Figure 40. - Output Saturation Voltage vs RLOAD @ +85C
VC C = +2.7V
1.2 VCC VC C = +10V 0.8 VIN VE E 0.6 VCC = +5V 0.4 VCC 2 VO UT RL OA D
DIFFERENCE FROM V CC - Volts
-1
VC C = +5V VC C
-1.5 VCC = +10V -2 VIN VEE VC C 2 VOU T R OA D L
DIFFERENCE FROM V C C - Volts
10k
-0.5
1
0.2 VC C = +2.7V 0 100
-2.5 100
1k RL OAD - Ohms
1k RL OAD - Ohms
10k
Figure 38. + Output Saturation Voltage vs RLOAD @ +25C
0
Figure 41. - Output Saturation Voltage vs RLOAD @ +25C
VC C = +2.7V
1.2 VCC V CC = +10V 0.8 VIN VE E 0.6 VC C = +5V 0.4 VOUT RL OA D VCC 2
DIFFERENCE FROM V CC - Volts
-1
VC C = +5V VC C
-1.5 VCC = +10V -2 VIN VEE
VOU T RL OA D VC C 2
DIFFERENCE FROM V EE - Volts
10k
-0.5
1
0.2 V CC = +2.7V 0 100
-2.5 100
1k RL OAD - Ohms
1k RL OAD - Ohms
10k
Figure 39. + Output Saturation Voltage vs RLOAD @ -40C
Figure 42. - Output Saturation Voltage vs RLOAD @ -40C
-22-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA Amplifier Typical Performance Characteristics
110 105 100 -AOL 95 90 +AOL 85 80 75 70 65 60 0 2k 4k 6k RL OAD - Ohms 8k 10k -1.5 0.5 2.5 4.5 INPUT VOLTAGE - Volts 6.5 VS = +5V 500mV 1V
AD15700
INPUT BIAS CURRENT - m A
100
10
90
GAIN - dB
0 VS = +5V -10
10 0%
500mV
Figure 43. Open-Loop Gain (AOL) vs RLOAD
Figure 46. Differential Input Voltage 1-V Characteristics
86
0.05
DIFF GAIN - %
VS = +5V RL = 1kV 84 -AOL 82
0.00 -0.05 -0.10 -0.15
GAIN - dB
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
10th 11th
80
DIFF PHASE - Degrees
+AOL
0.10 0.05 0.00 -0.05 -0.10
78
76 -40 -30 -20 -10
0
10
20
30
40
50 60
70
80 90
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
10th 11th
TEMPERATURE - C
Figure 44.
Open-Loop Gain (A OL) vs Temperature
Figure
47.
Differential Gain @ VS = 5V; RL = 1k
and
Phase
110 RLOA D = 10k VS = +5V
100 V S = +5V
100
INPUT VOLTAGE NOISE - nV/ Hz
30 VOLTAGE NOISE 10
100
90
A OL - dB
RL OAD = 1k 80
10
3 CURRENT NOISE 1
1
70
60
0.1
50
0
0.5
1
1.5
2
2.5 3 VOU T - V
3.5
4
4.5
5
0.3 10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
Figure 45. Open-Loop Gain (AOL) vs VOUT
Figure 48. Input Voltage Noise vs Frequency
REV. PrD 6/06/02
-23-
INPUT CURRENT NOISE - pA/ Hz
PRELIMINARY TECHNICAL DATA AD15700
5 4 3 VS = +5V G = +1 RL = 1k 40 30 GAIN 20 10 0
Amplifier Typical Performance Characteristics
NORMALIZED GAIN - dB
2 1 0
PHASE - Degree
-1 -2 -3 -4 -5 0.1 1 10 FREQUENCY - MHz 100
-90 PHASE -135 -180 -225 0.3 1 10 FREQUENCY- MHz 100
-10 -20
Figure 49. Unity Gain, -3 dB Bandwidth
Figure 52. Open-Loop Frequency Response
3 2 1
-20 VS = +5V VIN = -16dBm +85C
TOTAL HARMONIC DISTORTION - dBc
-30 G = +1, RL = 2k TO -40 VCC 2
NORMALIZED GAIN - dB
0 +25C -1 -2 -3 -4 -5 VIN VS 2k VOU T 50
-40C
-50 2.5V p-p VS = +2.7V -60
1.3V p-p VS = +2.7V
2V p-p V S = +2.7V 4.8V p-p VS = +5V
-70
-80 0.1 1 10 FREQUENCY - MHz 100 1k 10k 100k 1M FUNDAMENTAL FREQUENCY - Hz 10M
Figure 50. Closed-Loop Gain vs Temperature
Figure 53. Total Harmonic Distortion vs Frequency; G=+1
-20
2
0
TOTAL HARMONIC DISTORT ION - dBc
1
VS = +2.7V RL + CL TO1.35V
V S = +5V RL + CL TO 2.5V VS = 65V
-30 -40 -50
CLOSED-LOOP GAIN - dB
G = +2 VS = +5V V CC RL = 1k TO 2
-1 -2 -3 -4 -5 -6 -7 -8 100k 1M 10M FREQUENCY - Hz G = +1 CL = 5pF RL = 1k
4.8V p-p -60 -70 4.6V p-p -80 4V p-p -90 1V p-p
100M
1k
10k 100k 1M FUNDAMENTAL FREQUENCY - Hz
10M
Figure 51. Closed-Loop Gain vs Supply Voltage
Figure 54. Total Harmonic Distortion vs Frequency; G=+2
-24-
REV. PrD 6/06/02
OPEN-LOOP GAIN - dB
PRELIMINARY TECHNICAL DATA Amplifier Typical Performance Characteristics
10 VS = 65V 0
AD15700
POWER SUPPLY REJECTION RAT IO - dB
8
-20
V S = +5V
-40
OUTPUT - V p-p
6 VS = +5V 4 VS = +2.7V 2
-60
-80
-100
-120 100 1k 10k 100k 1M FREQUENCY - Hz 10M 100M
0 1k
10k
100k FREQUENCY - Hz
1M
10M
Figure 55. Large Signal Response
Figure 58. PSRR vs Frequency
100 50 10
RBT = 50
5.5 4.5
VS = +5V RL = 10k TO 2.5V VIN = 6V p-p G = +1
ROUT - V
1V / Div
RBT RBT = 0 VOUT 0.1 1 10 FREQUENCY - MHz 100 200
3.5 2.5 1.5 0.5
1
0.1
-0.5
10s / Div
Figure 56. ROUT vs Frequency
Figure 59. Output Voltage
0 VS = +5V
COMMON-MODE REJECTION RATIO - dB
INPUT 5.5 4.5
-20
VS = +5V G = +1 INPUT = 650mV BEYOND RAILS
1V / Div
1k 10k 100k FREQUENCY - Hz 1M 10M
-40
3.5 2.5 1.5 0.5
-60
-80
- 0.5
-100 100
10s / Div
Figure 57. CMRR vs Frequency
Figure 60. Output Voltage Phase Reversal Behavior
REV. PrD 6/06/02
-25-
PRELIMINARY TECHNICAL DATA AD15700
RL T O +2.5V
Amplifier Typical Performance Characteristics
VS = +2.7V RL = 1k G = -1
2.85 2.35
500mV/Div
500mV/Div
1.85 1.35 0.85 0.35 RL TO 1.35V
RL TO GND 0 10s / Div
VS = +5V RL = 1kV G = -1
RL TO GND
10s / Div
Figure 61. Output Swing
Figure 63. Output Swing
3.1 2.9
G = +2 RF = RG = 2.5k RL = 2k CL = 5pF VS = +5V
2.56 2.54
G = +1 RF = 0 RL = 2k TO 2.5V CL = 5pF TO 2.5V V S = +5V
200mV/Div
2.7 2.5 2.3 2.1 1.9
20mV/Div
50ns /Div
2.52 2.50 2.48 2.46 2.44
50ns/ Div
Figure 62. 1 V Step Response
Figure 64. 100 mV Step Response
-26-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
CIRCUIT OPERATION TYPICAL CONNECTION DIAGRAM
The AD15700 contains precision components for interfacing analog I/O to a processor. Configuration for particular applications can be made with short external interconnects under the device.
Figure 65 shows how, using a minimum of external devices, the components within the AD15700 can be interconnected to form a complete analog interface to a processor. The circuit implements signal conditioning that includes buffering, filtering, and voltage scaling.
AD15700
ANALOG INPUT (0.2V TO 2REF) +IN2 -IN2 RA2 RB2 RC2 INA INB INC IND INGND ADR421 OR AD780 2.5V OR 3.0V 47 uF REF REF REFGND OP-AMP VOUT2 +VS2 -VS2 RESISTOR RPAD2 ADC SCLK ______ CNVST SDOUT BUSY DVDD RFS TFS RCLK TCLK +VS STATE MACHINE
C2 NOTE 2
DSP/uP
0.1 uF
ANALOG SUPPLY (5V) 0.1 uF AGND DIGITAL SUPPLY (3.3V OR 5V) 0.1 uF DGND 10
100 .1
OB/2C SER/PAR WARP RDC/SIN INVSCLK INVSYNC AVDD EXT/INT AGND_ADC DIVSCLK1 DIVSCLK0 DVDD IMPULSE _______ DGND_ADC CS_ADC __ RD OVDD BYTESWAP OGND RESET PD DAC VREF VDD_DAC DGND_DAC AGND_DAC VOUT_DAC RA1 RB1 RC1 +IN1 -IN1 SCLK _______ CS_DAC DIN
RESISTOR RPAD1 OP-AMP +VS1 -VS1 VOUT1 +VS 0.1 uF
C1 NOTE 1 ANALOG OUTPUT (0.2V TO 2REF)
NOTES:
1. C1 forms an R-C filter with the 6.25 k nominal output resistance of the DAC. 2. C2 forms part of the ADC input filter. See Analog Input Section.
Figure 65. Typical Connection Diagram
REV. PrD 6/06/02
-27-
PRELIMINARY TECHNICAL DATA AD15700
Analog Input Section Voltage Reference Input
Made up of a buffer-amplifier, an RC filter, and an ADC, the analog input circuit allows measurement of voltages ranging from 0.2 V to 2REF V. When placed in the 0V to REF input range, the circuit has the configuration shown in Figure 66.
ANALOG INPUT ADC 1.5K C2 277 60 pF
1.5K
The AD15700 uses an external 2.5 V or 3.0 V voltage reference. Because of the dynamic input impedance of the A/D and the code dependent impedance of the D/A, the reference inputs must be driven by a low impedance source. Decoupling consisting of a parallel combination of 47 F and 0.1 F capacitors is recommended. Suitable references include the ADR421 for 2.5 V output and the AD780 for selectable 2.5 V or 3.0 V output. Both of these feature low noise and low temperature drift.
Processor Interface
Figure 66. Analog Input Circuit
The filter is made up of one of the AD15700's internal centertapped resistors, an external capacitor C2, plus the ADC's internal resistance and capacitance. The transfer function of this filter is given by: H (s ) = 8 .11425 x10 6 1.62285 x 10 + 202 .288 s2C2 + s + 1 .21714 x 1010 sC2
7
With C2 set to 100 pF, the bandwidth is 1.2 MHz. Without C2, the bandwidth of the filter is 2.6 MHz. To utilize the ADC's maximum 9.6 MHz bandwith, the components external to the ADC are eliminated. In this case, the ADC is configured for its 0 to 2REF input range and the resulting equivalent input circuit is shown below in Figure 66A.
ANALOG INPUT 375 375 ADC 100 60 pF
The circuit in Figure 66 uses serial interfacing to minimize the number of signals that connect to the digital circuits. External logic such as a state machine is used to generate clocks and other timing signals for the interface. Ideally, the clocks supplied to the converters are discontinuous and operate at the maximum frequency supported by the converter and the processor. Discontinuous clocks that are quiet during critical times minimize degradation caused by voltage transients on the digital interface. It is best to keep the clocks quiet during ADC conversion and when the DAC output is sampled by the external system. Often, the processor cannot tolerate a discontinuous clock and therefore a separate continuous clock (or clocks) that is synchronous with the converter clocks must be generated. Separate clocks for the DAC and ADC are used to maximize the data transfer rate to each converter. The ADC operates at a maximum rate of 40 MHz while the DAC can operate up to 25 MHz.
Figure 66A. Analog Output Circuit Analog Output Section
The output circuitry consists of a DAC, RC filter, and an amplifier. The circuit uses the DAC's output resistance of 6.25 KW 20% to form a single-pole RC filter with an external capacitor C1. One of the AD15700's internal center-tapped resistors and one of its op-amps form an amplifier with a gain of two. The gain is used to bring the DAC's maximum range of REF volts up to 2REF volts.
DAC 6.25K ANALOG OUTPUT 1.5K
C1 1.5K
Figure 67. Analog Output Circuit
-28-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
IND INC INB INA R COMP INGND 65,536C SWB CNVST CONTROL LOGIC OUTPUT CODE 4R 4R 2R REF REFGND MSB 32,768C 16,384C 4C 2C C C BUSY LSB SWA
SWITCHES CONTROL
Figure 68. ADC Simplified Schematic ADC CIRCUIT INFORMATION
The ADC is a fast,low-power, single-supply, precise 16-bit analog-to-digital converter (ADC). It features different modes to optimize performances according to the applications. In Warp mode, it is capable of converting 1,000,000 samples per second (1 MSPS). The ADC provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipe-line or latency, making it ideal for multiple multiplexed channel applications. It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. The ADC can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic.
ADC CONVERTER OPERATION
and acquires the analog signal. Similarly, the "dummy" capacitor acquires the analog signal on INGND input. When the acquisition phase is complete, and the CNVST input goes or is low, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened first. The capacitor array and the "dummy" capacitor are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the output of the resistive scaler and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4. . .VREF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low.
Modes of Operation
The ADC is a successive-approximation analog-to-digital converter based on a charge redistribution DAC. Figure 69 shows the simplified schematic of the ADC. The input analog signal is first scaled down and level-shifted by the internal input resistive scaler which allows both unipolar ranges (0 V to 2.5 V,0 V to 5 V, and 0 to 10 V)and bipolar ranges (2.5V, 5 V, and 10 V). The output voltage range of the resistive scaler is always 0 V to 2.5 V. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional "LSB" capacitor. The comparator's negative input is connected to a "dummy" capacitor of the same value as the capacitive DAC array. During the acquisition phase,the common terminal of the array tied to the comparator 's positive input is connected to AGND via SWA. All independent switches are connected to the output of the resistive scaler. Thus, the capacitor array is used as a sampling capacitor
The ADC features three modes of operations, Warp, Normal, and Impulse. Each of these modes is more suitable for specific applications. The Warp mode allows the fastest conversion rate up to 1 MSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the ADC ideal for applications where both high accuracy and fast sample rate are required. The normal mode is the fastest mode (800 kSPS)without any limitation about the time
REV. PrD 6/06/02
-29-
PRELIMINARY TECHNICAL DATA AD15700
between conversions. This mode makes the ADC ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 666 kSPS. When operating at 100 SPS, for example, it typically consumes only 15W. This feature makes the ADC ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the ADC offers two output codings: straight binary and two's complement.The ideal transfer characteristic for the ADC is shown in Figure 69 and Table III.
ADC CODE - St raight Binar y
111...111 111...110 111...101
00 0...0 10 00 0...0 01 00 0...0 00 - FS - FS + 1 LSB + FS - 1 LSB +FS - 1.5 LSB ANALOG INPUT
- FS + 0.5 LSB
Figure 69. ADC Ideal Transfer Function
Table III. Output Codes and Ideal Input Voltages Digital Output Code (Hexa) Straight Two's Binary Complement 0 V to 2.5 V 38.15 V 2.499962 V 1.257038 V 1.25 V 1.249962 V 38.15 V 0V
Description Full-Scale Range Least Significant Bit FSR -1 LSB Midscale +1 LSB Midscale Midscale - 1 LSB -FSR +1 LSB -FSR
10 V 305.2 V 9.999695 V 305.2 V 0V -305.2 V -9.999695 V -10 V
5 V 152.6 V 4.999847 V 152.6 V 0V -152.6 V -4.999847 V -5 V
2.5 V 76.3 V 2.499924 V 76.3 V 0V -76.3 V -2.499924 V -2.5 V
Analog Input 0 V to 10 V 0 V to 5 V 152.6 V 76.3 V 9.999847 V 4.999924 V 5.000153 V 2.570076 V 5V 2.5 V 4.999847 V 2.499924 V 152.6 V 76.3 V 0V 0V
FFFF1 8001 8000 7FFF 0001 00002
7FFF1 0001 0000 FFFF 8001 80002
NOTES 1 This is also the code for an overrange analog input. 2 This is also the code for an underrange analog input.
-30-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
Analog Inputs
The ADC is specified to operate with six full-scale analog input ranges. Connections required for each of the four analog inputs, IND, INC, INB, INA, and the resulting full-scale ranges, are shown in Table I. The typical input impedance for each analog input range is also shown. Figure 70 shows a simplified analog input section of the ADC. The four resistors connected to the four analog inputs form a resistive scaler that scales down and shifts the analog input range to a common input range of 0 V to 2.5 V at the input of the switched capacitive ADC.
AVDD
as shown in Figure 71, which represents the typical CMRR over frequency. For instance, by using INGND to sense a remote signal ground, difference of ground potentials between the sensor and the local ADC ground are eliminated. During the acquisition phase for ac signals, the ADC behaves like a one-pole RC filter consisting of the equivalent resistance of the resistive scaler R/2 in series with R1 and CS. The resistor R1 is typically 100 and is a lumped component made up of some serial resistor and the on-resistance of the switches. The capacitor CS is typically 60 pF and is mainly the ADC sampling capacitor. This one-pole filter with a typical -3 dB cutoff frequency of 9.6 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs.
75
4R IND INC INB R INA CS 4 R 2R
70 65 R 1
CMRR - dB
60 55 50 45 40 35
R = 1.2 8k V
AGND
Figure 70. Simplified Analog Input
By connecting the four inputs INA, INB, INC, IND, to the input signal itself, the ground, or a 2.5V reference, other analog input ranges can be obtained. The diodes shown in Figure 70 provide ESD protection for the four analog inputs. The inputs INB, INC, IND, have a high voltage protection (-11 V to +30 V) to allow wide input voltage range. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including INA (0 V to 5 V). This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 120 mA maximum. For instance, when using the 0 V to 2.5 V input range, these conditions could eventually occur on the input INA when the input buffer's (U1) supplies are different from AVDD. In such case, an input buffer with a short-circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential signal between the output of the resistive scaler and INGND. Unlike other converters, the INGND input is sampled at the same time as the inputs. By using this differential input, small signals common to both inputs are rejected
1
10
100 FREQUEN CY - k Hz
1 000
Figure 71. Analog Input CMRR vs. Frequency
Except when using the 0 V to 2.5 V analog input voltage range, the ADC has to be driven by a very low impedance source to avoid gain errors. That can be done by using the driver amplifier. When using the 0 V to 2.5V analog input voltage range, the input impedance of the ADC is very high so the ADC can be driven directly by a low impedance source without gain error. That allows putting an external one-pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the ADC analog input circuit. However, the source impedance has to be kept low because it affects the ac performances,especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of total THD that can be tolerated. The THD degradation is a function of the source impedance and the maximum input frequency as shown in Figure 72.
REV. PrD 6/06/02
-31-
PRELIMINARY TECHNICAL DATA AD15700
- 70
- 80
R = 1 00 V
For instance, when using the 0 V to 5 V range, a driver like the AD15700's internal op-amp, with an equivalent input noise of 15 nV/Hz and configured as a buffer, followed by a 3.2 MHz RC filter, the SNR degrades by about 1.3 dB. * The driver needs to have a THD performance suitable to that of the ADC. Figure 72 gives the THD versus frequency that the driver should preferably exceed.
R = 11 V
TH D - dB
R= 50V - 90
- 1 00
Voltage Reference Input
- 1 10 0 1 00 FREQUENCY - kHz 10 0 0
Figure 72. THD vs. Analog Input Frequency and Input Resistance (0 V to 2.5 V Only) Driver Amplifier Choice
Although the ADC is easy to drive, the driver amplifier needs to meet at least the following requirements: * The driver amplifier and the ADC analog input circuit must be able, together, to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). * The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transi tion noise performance of the ADC. The noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used, and is then filtered by the ADC analog input circuit one-pole, lowpass filter made by (R/2 + R1) and CS. The SNR degradation due to the am plifier is:
The ADC uses an external 2.5 V voltage reference. The voltage reference input REF of the ADC has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. 47F is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: - The low-noise, low-temperature drift ADR421 or AD780 voltage references. - The low-power ADR291 voltage reference. - The low-cost AD1582 voltage reference. Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. For instance, a 15 ppm/C tempco of the reference changes the full scale by 1 LSB/C.
Scaler Reference Input (Bipolar Input Ranges)
where f-3 dB is the -3 dB input bandwidth in MHz of the ADC (9.6 MHz) or the cutoff frequency of the input filter if any used (0 V to 2.5 V range). N eN is the noise factor of the amplifier (1 if in buffer configu ration). is the equivalent input noise voltage of the op amp in nV/Hz.
When using the ADC with bipolar input ranges a buffer amplifier is required to isolate the REFIN pin from the signal dependent current in the AIN pin. A high-speed op amp can be used with a single 5 V power supply without degrading the performance of the ADC. The buffer must have good settling characteristics and provide low total noise within the input bandwidth of the ADC.
Power Supply
The ADC uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC
FSR is the full-scale span (i.e., 5 V for 2.5 V range).
-32-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
100000
filter from the analog supply. The ADC is independent of
POWER DISSIPATION - mW
WARP/ N ORMAL 10000
power supply sequencing and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 73.
75 70 65 60
1000
100
10 IMPULSE 1
PSRR - dB
0 .1 55 50 45 40 35 1 10 100 FREQUENCY - k Hz 1000 100 00 1 10 100 1000 SA MPLIN G RAT E - SPS 1 00 0 0 100000
Figure 74. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 73. PSRR vs. Frequency
Figure 75 shows the detailed timing diagrams of the conversion process. The ADC is controlled by the signal CNVST which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of
CS_ADC and RD signals.
t2 t1
CNVST
POWER DISSIPATION
In impulse mode, the ADC automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in Figure 74. This feature makes the ADC ideal for very low-power battery applications. This does not take into account the power, if any, dissipated by the input resistive scaler which depends on the input voltage range used and the analog input voltage even in power-down mode. There is no power dissipated when the 0 V to 2.5 V is used or when both the analog input voltage is 0 V and a unipolar range, 0 V to 5 V or 0 V to 10 V, is used. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V.
BUSY
t4 t3 t5 t6
CONVERT ACQUIRE CONVERT
MODE
ACQUIRE
t7
t8
Figure 75. Basic Conversion Timing
In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the ADC controls the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the ADC keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the ADC could sometimes run slightly faster then the guaranteed limits in the impulse mode of 666 kSPS. This feature does not exist in warp or normal modes.
REV. PrD 6/06/02
-33-
PRELIMINARY TECHNICAL DATA AD15700
Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. It is a good thing to shield the CNVST trace with ground and also to add a low value serial resistor (i.e., 50 W) termination close to the output of the component which drives this line. For applications where the SNR is critical, CNVST signal should have a very low jitter. Some solutions to achieve that is to use a dedicated oscillator for CNVST generation, or at least to clock it with a high-frequency low-jitter clock.
t9
RESET CS_ ADC = RD = 0
t1
CNVST
t 10
BUSY
t t3
DATA BUS
4
t 11
PREVIOUS CONVERSION DATA NEW DATA
Figure 77. Master Parallel Data Timing for Reading (Continuous Read) PARALLEL INTERFACE
BUSY
DATA
t8
CNVST
The ADC is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 79 and Figure 79. When the data is read during the conversion, however, it is recommended that it be read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry.
CS_ADC
Figure 76. RESET Timing
R D
DIGITAL INTERFACE
The ADC has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The ADC digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the ADC to the host system interface digital supply. Finally, by using the OB/2C input pin, both straight binary or two's complement coding can be used. The two signals CS_ADC and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS_ADC allows the selection of each ADC in multicircuits applications and is held low in a single ADC design. RD is generally used to enable the conversion result on the data bus.
BUSY
DATA BUS
CURRENT CONVER SION
t
12
t 13
Figure 78. Slave Parallel Data Timing for Reading (Read after Convert)
-34-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
CS_ADC = 0 CNVST, RD
t1
BUSY
t4 t3
DATA BUS
PREVIOUS CONVERSION
t1 2
t1 3
Figure 46. Slave Parallel Data Timing for Reading (Read during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 80, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is low. When BYTESWAP is high, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16 data bits can be read in 2 bytes on either D[15:8] or D[7:0].
CS_ ADC
RD
BYTE
PINS D[ 15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t 12
PINS D[ 7:0 ] HI-Z LOW BYTE
t12
HIGH BYTE
t 13
HI-Z
Figure 80. 8-Bit Parallel Interface
SERIAL INTERFACE
The ADC is configured to use the serial interface when the SER/PAR is held high. The ADC outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on SCLK pin. The output data is valid on both the rising and falling edge of the data clock.
REV. PrD 6/06/02
-35-
PRELIMINARY TECHNICAL DATA AD15700
MASTER SERIAL INTERFACE Internal Clock
The ADC is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. It also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on RDC/SDIN input, the data can be read after each conversion or during conversion. Figure 81 and Figure 82 show the detailed timing diagrams of these two modes. Usually, because the ADC is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used.
EXT / IN T = 0 CS_ ADC , RD
In read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimizes potential feedthrough between digital activity and the critical conversion decisions. In read-after-conversion mode, it should be noted that, unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width.
RDC/ SDIN = 0
IN VSC LK = IN VSYN C = 0
t3
CNV ST
BUSY
t 28 t t29 t
25 30
SYNC
t14 t 20
SCL K 1
t18 t 19 t21
2 3 14 15
t 24 t26
16
t 15 t
SDOUT X D15 D14 D2 D1 D0
27
t16
t 22
t 23
Figure 81. Master Serial Data Timing for Reading (Read after Convert)
EXT / INT = 0 CS_ AD C, RD
RDC/ SDIN = 1
INV SCL K = INVSYNC = 0
t1
CNV ST
t3
BUSY
t 17
SYN C
t 25 t 19 t 20 t 21
1 2 3 14 15 16
t 14
t 24
SCL K
t 15 t 18
t 26
t 27
D1 5 D1 4 D2 D1 D0
SDOUT
X
t 16
t 22
t 23
Figure 82. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
-36-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
EX T/ IN T = 1 CS _ A D C , R D IN V SCL K = 0 RD = 0
B US Y
t 35 t 36 t 37
SC L K 1 2 3 14 15 16 17 18
t31
SD OUT X D 15
t 32
D1 4 D1 3 D1 D0 X1 5 X1 4
t16
t 34
X1 5 X1 4 X1 3 X1 X0 Y1 5 Y1 4
S D IN
t 33
Figure 83. Slave Serial Data Timing for Reading (Read after Convert) SLAVESERIALINTERFACE External Clock
The ADC is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS_ADC and the data are output when both CS_ADC and RD are low. Thus, depending on CS_ADC, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 83 and Figure 85 show the detailed timing diagrams of these methods. While the ADC is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the ADC provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that is does not transition during the latter half of BUSY high.
External Discontinuous Clock Data Read after Conversion
falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process.Another advantage is to be able to read the data at any speed up to 40 MHz which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the ADC provides a "daisy chain" feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 84. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Hence, the MSB of the "upstream" converter just follows the LSB of the "downstream" converter on the next SCLK cycle.
BUSY OUT BUSY BUSY
AD157 00
#2 (UPS REAM) T RDC/ SDIN S DOUT CNVST CS_ADC SCLK
AD15 700
#1 (DOWNS REAM) T RDC/ SDIN SDOUT CNVST CS_A DC SCLK DATA OUT
Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 83 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS_ADC and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and
SCLK IN CS_ ADC IN CNVST IN
Figure 84. Two AD15700s in a Daisy-Chain Configuration
REV. PrD 6/06/02
-37-
PRELIMINARY TECHNICAL DATA AD15700
EXT/ INT = 1 CS_ A DC INV SCLK = 0 RD = 0
CNV ST
BUSY
t
3
t
SCLK
36
t 35 t 37
2 3 14 15 16
1
t31
SDOUT X D1 5
t
32
D1 4
D1 3
D1
D0
t16
Figure 85. Sl.ave Serial Data Timing for Reading (Read dPrevious Conversion during Convert) External Clock Data Read During Conversion SPI Interface (MC68HC11)
Figure 85 shows the detailed timing diagrams of this method. During a conversion, while both CS_ADC and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no "daisy chain" feature in this mode and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock of, at least 25 MHz, when impulse mode is used, 32 MHz when normal or 40 MHz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. That allows the use of a slower clock speed like 18 MHz in impulse mode, 21 MHz in normal mode and 26 MHz in warp mode.
MICROPROCESSOR INTERFACING
Figure 86 shows an interface diagram between the ADC and an SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the ADC acts as a slave device and data must be read after conversion. This mode also allows the "daisy chain" feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI interrupt enable (SPIE) = 1 by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register).
DVDD
AD1 5700*
SER/ PAR EXT/ INT CS ADC _ RD BUSY SDOUT SCLK INVSCLK CNVST IRQ
MC68 HC11*
M ISO/ SDI S CK I/ O POR T
The ADC is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The ADC is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general purpose serial port or I/ O ports on a microcontroller. A variety of external buffers can be used with the ADC to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the ADC with an SPI equipped microcontroller, the ADSP21065L and ADSP-218x signal processors.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 86. Interfacing the AD15700 to SPI Interface ADSP-21065L in Master Serial Interface
As shown in Figure 87, the AD15700s can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion at maximum speed transfer (DIVSCLK[0:1] both low).
-38-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
The ADC is configured for the internal clock mode (EXT/INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP21065L or by a frame output TFS of one serial port of the ADSP-21065L which can be used like a timer. The serial port on the ADSP-21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL) - see ADSP2106x SHARC User's Manual. Because the serial port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation.
DVDD
switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board.
AD1 5 7 0 0 *
SER/ P AR RDC/ SDIN RD EXT/ INT CS_ADC INVSYNC INVSCLK SYNC SDOUT SCLK CNVST RFS DR
ADSP-21 065L* SHARC (R)
The power supply lines to the AD15700 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supplies impedance presented to the AD15700 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 mF, should be placed on each power supplies pins AVDD, DVDD and OVDD close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 mF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD15700 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply available, to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. The AD15700's ADC has five different ground pins; INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances.
RCLK FLAGOR TFS
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 87. Interfacing to the ADSP-21065L Using the Serial Master Mode
APPLICATION HINTS Layout
The AD15700's ADC has very good immunity to noise on the power supplies as can be seen in Figure 73. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD15700 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD15700 , or, at least, as close as possible to the AD15700 . If the AD15700 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD15700. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the
REV. PrD 6/06/02
-39-
PRELIMINARY TECHNICAL DATA AD15700
TPC 88. Digital Feedthrough
TPC 90. Large Signal Settling Time
TPC 89. Digital-to-Analog Glitch Impulse DAC Circuit Information
TPC 91. Small Signal Settling Time
The DAC is a single, 14-bit, serial input, voltage output. It operates from a single supply ranging from 2.7 V to 5 V and consume typically 300 A with a supply of 5 V. Data is written to the devices in a 14-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, the parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V.
Digital-to-Analog Section
With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following equation.
The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 92. The four MSBs of the 14-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 10 bits of the
data word drive switches S0 to S9 of a 10-bit voltage mode R2R ladder network.
R R VOUT
where D is the decimal data word loaded to the DAC register and N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following.
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/16,384.
Serial Interface
2R
2R S0
2R S1
2R S9
2R E1
2R E2
2R E15
VREF
10-BIT R-2RLADDER
FOURMSBs DECODED INTO 15 EQUAL SEGMENTS
The DAC is controlled by a versatile 3-wire serial interface, which operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure 3. Input data is framed by the chip select input, CS_DAC. After a high-to-low transition on CS_DAC, data is shifted synchronously and
Figure 92. DAC Architecture
-40-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 14-bit words. After 14 data bits have been loaded into the serial input register, a low-to-high transition on CS_DAC transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS_DAC is low.
Unipolar Output Operation Output Amplifier Selection
In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have very low-offset voltage, (the DAC LSB is 152 V with a 2.5 V reference), to eliminate the need for output offset trims. Input bias current should also be very low as the bias current multiplied by the DAC output impedance (approximately 6K) will add to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, hence increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a faster effective settling time of the combined DAC and amplifier. Force Sense Buffer Amplifier Selection
The DAC is capable of driving unbuffered loads of 60 k. Unbuffered operation results in low-supply current, typically 300 mA, and a low-offset error. The DAC provides a unipolar
output swing ranging from 0 V to VREF. Figure 93 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table IV.
5V 2.5 V 10m F
0 .1m F
0.1 mF
S ERIA L I NT ERF AC E
VD D CS DIN SCL K
V R EFF *
V R EFS *
DAC
OU T OP AM P D GND AGND
UN IPOLAR OUT PUT
Figure 93. Unipolar Output
Table IV. Unipolar Code Table
These amplifiers can be single-supply or dual supplies, lownoise amplifiers. A low-output impedance at high frequencies is preferred as they need to be able to handle dynamic currents of up to 20 mA.
Reference and Ground
DAC Latch Contents
MSB LSB 11 1111 1111 1111 10 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 Analog Output VREF X (16383/16384) VREF X (8192/16384) = 1/2 VREF VREF X (1/16384) 0V
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation.
Unipolar Mode Worst-Case Output
As the input impedance is code-dependent, the reference pin should be driven from a low-impedance source. The DAC operates with a voltage reference ranging from 2 V to VDD. Although DAC's full-scale output voltage is determined by the reference, references below 2 V will result in reduced accuracy. Table IV outlines the analog output voltage for particular digital codes.
Power-On Reset
VOUT-UNI =
D x (VREF + VGE) + VZSE + INL 214
where VOUT -UNI = Unipolar Mode Worst-Case Output D VREF VGE VZSE INL = Decimal Code Loaded to DAC = Reference Voltage Applied to Part = Gain Error in Volts = Zero Scale Error in Volts = Integral Nonlinearity in Volts
The DAC has a power-on reset function to ensure the output is at a known state upon power-up. On power-up, the DAC register contains all zeros, until data is loaded from the serial register. However, the serial register is not cleared on powerup, so its contents are undefined. When loading data initially to the DAC, 14 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 14 bits are loaded, only the last 14 are kept, and if fewer than 14 are loaded, bits will remain from the previous word. If the DAC needs to be interfaced with data shorter than 14 bits, the data should be padded with zeros at the LSBs.
REV. PrD 6/06/02
-41-
PRELIMINARY TECHNICAL DATA AD15700
Power Supply and Reference Bypassing MICROWIRE to DAC Interface
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor.
MICROPROCESSOR INTERFACING
Figure 96 shows an interface between the DAC and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the DAC on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge.
Microprocessor interfacing to the DAC is via a serial bus that uses standard protocol compatible with DSP processors and micro- controllers. The communications channel requires a 3wire interface consisting of a clock signal, a data signal and a synchronization signal. The DAC requires a 14-bit data word with data valid on the rising edge of SCLK. The DAC update may be done automatically when all the data is clocked in.
ADSP-2101/ADSP-2103 to DAC Interface
MICROWIRE*
CS_DAC SO SCLK DIN SCLK
DAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 96. MICROWIRE to DAC Interface 80C51/80L51 to DAC Interface
Figure 94 shows a serial interface between the DAC and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT (Serial Port) transmit alternate framing mode. The ADSP-2101/ADSP-2103 is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-Bit Word Length. The first 2 bits are DON'T CARE as DAC will keep the last 14 bits. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Because of the edges-triggered difference, an inverter is required at the SCLKs between the DSP and the DAC.
ADSP-2101/ ADSP-2103*
TF S DT SC LK C S_DAC D IN SC LK
A serial interface between the DAC and the 80C51/80L51 microcontroller is shown in Figure 97. TxD of the microcontroller drives the SCLK of the DAC, while RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS_DAC.
80C51/ 80L51*
P3.3 RxD TxD
CS_DAC DAC DIN SCLK
DAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
*AD DIT ION AL PINS OMI TT ED F OR CL AR ITY.
Figure 97. 80C51/80L51 to DAC Interface
Figure 94. ADSP-2101/ADSP-2103 to DAC Interface 68HC11 to DAC Interface
Figure 95 shows a serial interface between the DAC and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines SDIN. CS signal is driven from one of the port lines The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK.
The 80C51/80L51 provides the LSB first, while the DAC expects the MSB of the 14-bit word first. Care should be taken to ensure the transmit routine takes this into account. Usually it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the DAC. Also, 80C51 outputs 2 byte words/16 bits data, thus the first two bits, after rearrangement, should be DON'T CARE as they will be dropped from the DAC's 14-bit word. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/ 80L51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS_DAC input signal to the DAC, so P3.3 should be brought low at the beginning of the 16-bit write cycle 2 x 8 bit words and held low until the 16-bit 2 x 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be DON'T CARE.
PC6
68HC11/ 68L11*
PC7 MOSI SCK
CS_DAC DIN SCLK
DAC
*ADDITIONAL PINS OMITTED FO CLARITY R .
Figure 95. 68HC11/68L11 to DAC Interface
-42-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
APPLICATIONS Optocoupler interface Decoding Multiple DACs
The digital inputs of the DAC are Schmitttriggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from the controller via optocouplers. Figure 98 illustrates such an interface.
5V REGULATOR POW ER 10mF
The CS_DAC pin of the DAC can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS_DAC signal at any one time. The DAC addressed will be determined by the decoder. There will be some digital feedthrough from the digital input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 99 shows a typical circuit.
DAC CS_DAC DIN DIN VD D SCLK VOU T
0.1mF SCLK
VD D 10kV SCLK SCLK
VD D
VD D
ENABLE
EN DECODER
DAC CS_DAC DIN SCLK DGND DAC CS_DAC VOU T VOU T
DAC
10kV CS CS_DAC VOU T
CODED ADDRESS
VD D 10kV DIN DIN GND
DIN SCLK
DAC CS_DAC V OU T
Figure 98. DAC in an Optocoupler Interface
DIN SCLK
Figure 99. Addressing Multiple DACs
REV. PrD 6/06/02
-43-
PRELIMINARY TECHNICAL DATA AD15700
AMPLIFIER THEORY OF OPERATION
The amplifiers are single and dual versions of high speed, low power voltage feedback amplifiers featuring an innovative architecture that maximizes the dynamic range capability on the inputs and outputs. Linear input common-mode range exceeds either supply voltage by 200 mV, and the amplifiers show no phase reversal up to 500 mV beyond supply. The output swings to within 20 mV of either supply when driving a light load; 300 mV when driving up to 5 mA. The amplifier provides an impressive 80 MHz bandwidth when used as a follower and 30 V/ms slew rate at only 800 mA supply current. Careful design allows the amplifier to operate with a supply voltage as low as 2.7 volts.
Input Stage Operation
Switching to the NPN pair as the common-mode voltage is driven beyond 1 V within the positive supply allows the amplifier to provide useful operation for signals at either end of the supply voltage range and eliminates the possibility of phase reversal for input signals up to 500 mV beyond either power supply. Offset voltage will also change to reflect the offset of the input pair in control. The transition region is small, on the order of 180 mV. These sudden changes in the dc parameters of the input stage can produce glitches that will adversely affect distortion.
Overdriving the Input Stage
Sustained input differential voltages greater than 3.4 volts should be avoided as the input transistors may be damaged. Input clamp diodes are recommended if the possibility of this condition exists. The voltages at the collectors of the input pairs are set to 200 mV from the power supply rails. This allows the amplifier to remain in linear operation for input voltages up to 500 mV beyond the supply voltages. Driving the input common-mode voltage beyond that point will forward bias the collector junction of the input transistor, resulting in phase reversal. Sustaining this condition for any length of time should be avoided as it is easy to exceed the maximum allowed input differential voltage when the amplifier is in phase reversal.
A simplified schematic of the input stage appears in Figure 100. For common-mode voltages up to 1.1 volts within the positive supply, (0 V to 3.9 V on a single 5 V supply) tail current I2 flows through the PNP differential pair, Q13 and Q17. Q5 is cut off; no bias current is routed to the parallel NPN differential pair Q2 and Q3. As the common-mode voltage is driven within 1.1 V of the positive supply, Q5 turns on and routes the tail current away from the PNP pair and to the NPN pair. During this transition region, the amplifier's input current will change magnitude and direction. Reusing the same tail current ensures that the input stage has the same transconductance (which determines the amplifier's gain and bandwidth) in both regions of operation.
VC C R1 2kV I3 25 mA R2 2 kV
Q9 1. 1V R5 5 0kV Q5 V IP V IN
I2 9 0mA
Q3 R6 85 0V Q1 3 R7 85 0V R8 85 0V Q17
Q2 1 Q8 R9 850V 4
Q6
Q 10 1 Q7 4 I4 25 mA OU T PUT S TAGE , C OM MON-M ODE F EED BAC K Q 11 4
Q1 4 4 1 Q 15 Q16 1
I1 5m A
VE E
Q18
Q4
R3 2 kV
R4 2k V
Figure 100. Simplified Schematic of Input Stage
-44-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
Output Stage, Open-Loop Gain and Distortion vs. Clearance from Power Supply Output Overdrive Recovery
The amplifier features a rail-to-rail output stage. The output transistors operate as common emitter amplifiers, providing the
output drive current as well as a large portion of the amplifier's open-loop gain.
I1 25mA Q4 2 Q51 I2 2 5mA Q4 7
Output overdrive of an amplifier occurs when the amplifier attempts to drive the output voltage to a level outside its normal range. After the overdrive condition is removed, the amplifier must recover to normal operation in a reasonable amount of time. As shown in Figure 102, the amplifier recovers within 100 ns from negative overdrive and within 80 ns from positive overdrive.
R F = RG = 2kV RG V IN RF VOU RL T
DIFFERENTIAL DRIVE FROM IN PU T STAGE Q20 Q21
Q37
Q38 Q6 8 C9 5p F
50 V
R 29 3 00V Q27 Q43 Q48 C5 1 .5p F VOUT
I4 25m A Q50
Q4 9 I5 25 mA Q44 1V
VS = 62 .5V VIN = 62 .5 V R L = +1kV T O GN D
100ns
Figure 102. Overdrive Recovery Figure 101. Output Stage Simplified Schematic Driving Capacitive Loads
The output voltage limit depends on how much current the output transistors are required to source or sink. For applications with very low drive requirements (a unity gain follower driving another amplifier input, for instance), the amplifier typically swings within 20 mV of either voltage supply. As the required current load increases, the saturation output voltage will increase linearly as ILOAD x RC, where ILOAD is the required load current and RC is the output transistor collector resistance. For the amplifier, the collector resistances for both output transistors are typically 25. As the current load exceeds the rated output current of 15 mA, the amount of base drive current required to drive the output transistor into saturation will reach its limit, and the amplifier's output swing will rapidly decrease. The open-loop gain of the amplifier decreases approximately linearly with load resistance and also depends on the output voltage. Open-loop gain stays constant to within 250 mV of the positive power supply, 150 mV of the negative power supply and then decreases as the output transistors are driven further into
saturation.
Capacitive loads interact with an amplifier's output impedance to create an extra delay in the feedback path. This reduces circuit
stability, and can cause unwanted ringing and oscillation. A given value of capacitance causes much less ringing when the amplifier is used with a higher noise gain.
The capacitive load drive of the amplifier can be increased by adding a low valued resistor in series with the capacitive load. Introducing a series resistor tends to isolate the capacitive load from the feedback loop, thereby, diminishing its influence. Figure 103 shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor at lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the rolloff of the series resistor and capacitive load.
1000 VS = +5V 200mV STEP WITH 30% OVERSHOOT RS = 5
CAPACITIVE LOAD - pF
The distortion performance of the amplifiers differs from conventional amplifiers. Typically an amplifier's distortion performance degrades as the output voltage amplitude increases. Used as a unity gain follower, the amplifier output will exhibit more distortion in the peak output voltage region around VCC 0.7 V. This unusual distortion characteristic is caused by the input stage architecture and is discussed in detail in the section covering "Input Stage Operation".
RS = 0
100
RS = 20V RS = 20 RG RS = 0, 5 RF RS VOUT CL 1
10
0
1
2 3 CLOSED-LOOP GAIN - V/V
4
5
Figure 103. Capacitive Load Drive vs. Closed-Loop Gain
REV. PrD 6/06/02
-45-
PRELIMINARY TECHNICAL DATA AD15700
High Performance Single Supply Line Driver
Even though the amplifier swings close to both rails, the amplifier has optimum distortion performance when the signal has a common-mode level half way between the supplies and when there is about 500 mV of headroom to each rail. If low distortion is required in single supply applications for signals that swing close to ground, an emitter follower circuit can be used at the amplifier output.
+5V 10F
100 90
2V
10 0 %
50mV
0.5V
1s
0.1F 3 49.9 2 4 OP-A MP 2.49k 2.49k 49.9 200 49.9 VOU T 7 6 2N3904
+9dBm
V IN
Figure 105. Output Signal Swing of Low Distortion Line Driver at 500 kHz
Figure 104. Low Distortion Line Driver for Single Supply Ground Referenced Signals
Figure 104 shows the amplifier configured as a single supply gain-of-2 line driver. With the output driving a back terminated 50 W line, the overall gain from VIN to VOUT is unity. In addition to minimizing reflections, the 50 back termination resistor protects the transistor from damage if the cable is short circuited. The emitter follower, which is inside the feedback loop, ensures that the output voltage from the amplifier stays about 700 mV above ground. Using this circuit, very low distortion is attainable even when the output signal swings to within 50 mV of ground. The circuit was tested at 500 kHz and 2 MHz. Figures 105 and 106 show the output signal swing and frequency spectrum at 500 kHz. At this frequency, the output signal (at VOUT), which has a peak-to-peak swing of 1.95 V (50 mV to 2 V), has a THD of -68 dB (SFDR =
-77 dB).
VERTICAL SCALE 10dB/Div
START 0Hz
STOP 5MHz
Figure 106. THD of Low Distortion Line Driver at 500 kHz
1.5V
1 00 90
10 0%
50mV
0.2V
200ns
Figures 107 and 108 show the output signal swing and frequency spectrum at 2 MHz. As expected, there is some degradation in signal quality at the higher frequency. When the output signal has a peak-to-peak swing of 1.45 V (swinging from 50 mV to 1.5 V), the THD is -55 dB (SFDR = -60 dB). This circuit could also be used to drive the analog input of a single supply high speed ADC whose input voltage range is referenced to ground (e.g., 0 V to 2 V or 0 V to 4 V). In this case, a back termination resistor is not necessary (assuming a short physical distance from transistor to ADC), so the emitter of the external transistor would be connected directly to the ADC input. The available output voltage swing of the circuit would, therefore be doubled.
Figure 107. Output Signal Swing of Low Distortion Line Driver at 2 MHz
+7 d Bm
VE RTIC AL SC AL E 10 d B/Di v
S TAR T 0H z
S TOP 2 0M H z
Figure 108. THD of Low Distortion Line Driver at 2 MHz
-46-
REV. PrD 6/06/02
PRELIMINARY TECHNICAL DATA AD15700
AD15700 Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A
COMMON
VREF
AGND DAC
COMMON
COMMON
VOUT
RPAD1
RB1
-IN1
COMMON
+VS1
COMMON
A
B
CS DAC
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
RA1
-VS1
-VS1
VOUT1
B
C
COMMON
COMMON
AGND DAC
AGND DAC
COMMON
VDD DAC
COMMON
COMMON
+IN1
COMMON
COMMON
COMMON
C
D
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
RC1
COMMON
COMMON
RESET
D
E
SCLK
DIN
DGND DAC
COMMON
COMMON
COMMON
CNVST
COMMON
COMMON
RD
D15
D14
E
F
COMMON
COMMON
+VS2
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
D13
D12
F
G
-IN2
COMMON
-VS2
COMMON
REF
COMMON
COMMON
COMMON
TEST1
BUSY
D11 RDERROR
D10 SYNC
G
H
COMMON
COMMON
-VS2
COMMON
REFGND
COMMON
COMMON
TEST0
AGND ADC
DGND ADC
D9 SCLK
D8 SDOUT
H
J
+IN2
COMMON
COMMON
COMMON
INA
COMMON
INGND
AGND ADC
AGND ADC
OGND
OVDD
DVDD
J
K
COMMON
COMMON
COMMON
VOUT2
INB
COMMON
COMMON
COMMON
PD
CS ADC
D6 INVSCLK
D7 RDC/SDIN
K
L
RC2
COMMON
COMMON
RA2
INC
COMMON
BYTE SWAP
OB/2C
IMPULSE
D1
D3 DIVSCLK1
D5 INVSYNC
L
M
COMMON
COMMON
RPAD2
RB2
IND
AVDD
WARP
SER /PAR
D0
D2 DIVSCLK0
D4 EXT/INT
AGND ADC
M
1
2
3
4
5
6
7
8
9
10
11
12
REV. PrD 6/06/02
-47-
PRELIMINARY TECHNICAL DATA AD15700
Outline Dimensions
Dimensions shown in millimeters
Tolerances: .xx = .05mm .xxx = .03mm
-48-
REV. PrD 6/06/02

▲Up To Search▲

Price & Availability of 3763

	To Download 3763 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .