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| a PERFORMANCE FEATURES Dual Channel, 215MSPS minimum sample rate SNR = 65 dB @ Fin up to 65MHz at 215MSPS ENOB of 10.3 @ Fin up to 65MHz at 215MSPS (-1dBFs) SFDR = -80dBc @ Fin up to 65MHz at 215MSPS (-1dBFs) Input VSWR 1.1:1 to Nyquist Gain Flatness up to Nyquist: < 0.1dB LVDS Digital Output Data 400MHz Full Power Analog Bandwidth Power dissipation = 1.3W typical at 215MSPS per channel 1.5V Input voltage range Output data format option Data Sync input and Data Clock output provided Interleaved or parallel data output option APPLICATIONS Wireless and Wired Broadband Communications - Wideband carrier frequency systems - Cable Modem Reverse Path Communications Test Equipment Radar and Satellite sub-systems Dual Channel, 12-Bit 215MSPS A/D Converter AD10235 PRODUCT DESCRIPTION The AD10235 is a dual 12-bit analog-to-digital converter with a transformer coupled analog input and features low cost, low power, small size and ease of use. The product operates up to 215MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier systems. The AD10235 requires a +3.3V supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are Low Voltage Differential Signal (LVDS) compatible. Separate digital output power supply pins support fexible output data formats. An output data format select option of two's complement or offset binary is supported. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10235 is available in a 40sq-mm, 729-lead PBGA package. PRODUCT HIGHLIGHTS 1. 2. 3. Guaranteed sample rate of 215MSPS. Input signal conditioning included with full power bandwidth to 400MHz Optimized for IF Sampling. FUNCTIONAL BLOCK DIAGRAM -1- Rev Pr. A This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. AD10235 TARGET SPECIFICATIONS T Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error REFERENCE OUT (VREF) ANALOG INPUT (AIN, AIN) Input Voltage Range (AIN-AIN)1 Input Resistance Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate1 Minimum Conversion Rate1 Encode Pulse Width High (t EH) 1 Encode Pulse Width Low(t EL ) 1 Temp Test Level (DC Specifications (AV DD = 3.3V, DrVDD = 3.3V; TMIN=-40 C , MAX=+85 C, Fin=-0.5dBFS, LVDS Output Mode ) AD10235AB Typical 12 Min Max Units Full +25C +25C +25C +25C I I I I I Guaranteed tbd tbd 1 1.5 mV %FS LSB LSB Full Full Full V V V tbd tbd 1.235 ppm/C ppm/C V Full Full Full V V V .766 50 5 V pF Full Full Full Full I V V V 215 40 2 2 MSPS MSPS nS nS ENCODE AND DIGITAL I/O INPUTS (ENC, ENC) Differential Input Voltage 1 Input Resistance Input Capacitance LOGIC INPUTS (S1,S5) Logic `1' voltage Logic `0' voltage Input Resistance Input Capacitance LOGIC OUTPUTS (LVDSMode)2 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding POWER SUPPLY Supply Voltages AVDD DrVDD Supply Current Total I ANALOG (AVDD=3.3V) Total I DIGITAL (DrVDD=3.3V) POWER SUPPLY REJECTION TOTAL POWER DISSIPATION Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV IV 0.2 5.5 4 2.0 .8 30 4 247 1.125 Two's comp or Binary V pF V V pF mV V 454 1.375 Full Full Full Full Full Full V V V V V V 3.0 3.0 3.3 3.3 640 110 tbd 2.5 3.6 3.6 V V mA mA mV/V W Rev Pr. A -2- AD10235 TARGET SPECIFICATIONS (AC Specifications 1 (AVDD = 3.3V, DrVDD = 3.3V; ENCODE = 215MHz; Internal voltage reference, LVDS Output Mode ) Test Level AD10235AB Typical Parameter DYNAMIC PERFORMANCE SNR Analog Input 10MHz @ -0.5dBFS 65MHz 100MHz 240MHz SINAD Analog Input @ -0.5dBFS Temp Min Max Units 25C 25C 25C 25C I I V V 65.5 65 64 60 dB dB dB dB 10MHz 65MHz 100MHz 240MHz 25C 25C 25C 25C I I V V 65 64.5 63.4 TBD dB dB dB dB Spurious Free Dynamic Range Analog Input 10MHz @ -0.5dBFS 65MHz 100MHz 240MHz Two-tone Intermodulation Distortion (IMD) f IN = 29.3MHz; fIN = 30.3MHz f IN = 150MHz; fIN = 151MHz f IN = 250MHz; fIN = 251MHz Analog Input Bandwidth OUTPUT Parameters in LVDS Mode 3 Valid Time (t V) Propagation Delay (t PD) Rise Time (t R) (20% to 80%) FallTime (t F) (20% to 80%) DCO Propagation Delay (t CPD) Data to DCO Skew (t PD - t CPD) Pipeline Latency Aperture Delay (t A) Aperture Uncertainty (Jitter, t J) 25C 25C 25C 25C I I V V 82 80 76 59 dBc dBc dBc dBc 25C 25C 25C 25C V V V V tbd tbd tbd 400 dBc dBc dBc MHz Full Full 25C 25C Full Full Full 25C 25C IV I V V VI IV VI V V tbd 3.9 .5 .5 2.9 1 14 tbd 0.25 ns ns ns ns ns ns Cycles ps ps rms NOTES 1. All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode (ENCODE and ENCODE > 200mV. 2. Digital Output Logic Levels: DrVDD = 3.3V, CLOAD= 5pF. 3. LVDS R1 = 100 ohms. LVDS Output Swing Set Resistor = 3.4K. -3- Rev Pr. A AD10235 Table 1. AD10235 Output Select Coding 1 S1 Data Format Select)2 S5 (Full Scale Adjust) Mode 1 0 X X X X 1 0 2's Compliment Offset Binary 1.533 Vpp Single- Ended Full Scale -> .766 Vpp differential Full Scale -> 1.533Vpp differential Notes: 1 S1- S5 all have 30K resistive pulldowns on chip 2 S1 Pin is independent of S5 and sets output coding for both states of S5 3 For CMOS output requirements, consult the factory. Pin Configuration Rev Pr. A -4- AD10235 -5- Rev Pr. A AD10235 ABSOLUTE MAXIMUM RATINGS AVDD, DRVDD ................................................................... 4V Analog Inputs ..................................... -0.5 V to AVDD + 0.5V Digital Inputs .................................. -0.5 V to DRVDD + 0.5V REFIN Inputs ...................................... -0.5V to AVDD +0.5V Digital Output Current ...................................................20 mA Operating Temperature ................................ -55C to + 125C Storage Temperature ..................................... -65C to +150C Maximum Junction Temperature ................................... 150C Maximum Case Temperature .......................................... 150C JA2 ....................................................................................................... 25C/W, 32C/W Notes 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical JA2 = 32C/W (heat slug not soldered), Typical JA2 = 25C/W (heat slug soldered), for multilayered board in still air. EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Caution: ESD (electrostatic discharge) senstive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10230 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PLANNED GRADES Model AD10235AB AD10235/PCB Temperature Range -40C to 85C (Ambient) Package Description 40 sq-mm 729 lead PBGA Evaluation Board with AD10235AB Rev Pr. A -6- AD10235 PIN FUNCTION DESCRIPTIONS LVDS Mode Name DNC S5X Function in LVDS Mode Do not connect Full Scale Adjust pin: High = fullscale is 0.766 Vp-p differential Low = fullscale is 1.533 Vp-p differential Not used - tie to ground Test pin - Tie to ground. Output Mode select. Tie to +3.3V Data format select. Low = Two's compliment, High = Binary 3.3V analog supply (3.0V to 3.6V) Analog ground 1.235 Reference I/O - function dependent on REFSENSE Analog input - true Analog input - compliment Data sync (input) - true. Not used in LVDS mode. Tie LOW. Data sync (input) - compliment. Not used in LVDS mode. Tie HIGH. Clock input - true. (LVPECL levels) Clock input - compliment. (LVPECL levels) 3.3V digital output supply (3.0V to 3.6V) Digital Ground D0 complement output bit (LSB) (LVDS Levels) D0 true output bit (LSB) (LVDS Levels) D1 complement output bit (LSB) (LVDS Levels) D1 true output bit (LSB) (LVDS Levels) D2 complement output bit (LSB) (LVDS Levels) D2 true output bit (LSB) (LVDS Levels) D3 complement output bit (LSB) (LVDS Levels) D3 true output bit (LSB) (LVDS Levels) D4 complement output bit (LSB) (LVDS Levels) D4 true output bit (LSB) (LVDS Levels) Data Clock output - compliment (LVDS Levels) Data Clock output - true (LVDS Levels) D5 complement output bit (LSB) (LVDS Levels) D5 true output bit (LSB) (LVDS Levels) D6 complement output bit (LSB) (LVDS Levels) D6 true output bit (LSB) (LVDS Levels) D7 complement output bit (LSB) (LVDS Levels) D7 true output bit (LSB) (LVDS Levels) D8 complement output bit (LSB) (LVDS Levels) D8 true output bit (LSB) (LVDS Levels) D9 complement output bit (LSB) (LVDS Levels) D9 true output bit (LSB) (LVDS Levels) D10 complement output bit (LSB) (LVDS Levels) D10 true output bit (LSB) (LVDS Levels) D11 complement output bit (LVDS Levels) MSB D11 true output bit (LVDS Levels) MSB Overrange complement output bit (LVDS Levels) Overrange true output bit (LVDS Levels) S4X S3X S2X S1X LVDSBIASX +3.3VAX AGNDX REFX AINXAINX+ DSX+ DSXENCX ENCX DrVDD DGNDX D0X D0X D1X D1X D2X D2X D3X D3X D4X D4X DCO_X DCO_X D5X D5X D6X D6X D7X D7X D8X D8X D9X D9X D10X D10X D11X D11X ORX ORX Notes: X= (A) Channel A or (B) Channel B -7- Rev Pr. A AD10235 LVDS Mode Pin Configuration (PCB Footprint) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA S1A S3A S4A NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB B AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA S1A S3A S4A NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB REF_B REF_B C AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA REF_A LVDS BIASA S2A S5A NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB LVDS BIASB LVDS BIASB D AGNDA AGNDA AGNDA AGNDA AGNDA AINA- AGNDA AINA+ AGNDA REF_A LVDS BIASA S2A S5A NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AINB- AGNDB AINB+ AGNDB S1B S1B E AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB S2B S2B F AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB S3B S3B G AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB S4B S4B H AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA NC AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB S5B S5B J +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB K +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA +3.3VAA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB +3.3VAB L AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB M AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB N AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB P AGNDA AGNDA +3.3VAA +3.3VAA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB +3.3VAB +3.3VAB AGNDB AGNDB R AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB T AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB U AGNDA AGNDA ENCA ENCA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB ENCB ENCB AGNDB AGNDB V AGNDA AGNDA ENCA ENCA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB ENCB ENCB AGNDB AGNDB W AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB Y AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AGNDB AA NC NC NC NC DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB ORB ORB ORB ORB AB NC NC D0A D0A DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB D11B D11B D11B D11B AC D0A D0A D1A D1A DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDA DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB DGNDB D10B D10B D10B D10B AD D1A D1A D3A D4A DCO_A D5A D6A D7A D8A D9A D10A D11A ORA +3.3VDIGB NC NC D0B D1B D2B D3B D4B DCO_B D5B D6B D7B D9B D9B AE D2A D2A D3A D4A DCO_A D5A D6A D7A D8A D9A D10A D11A ORA +3.3VDIGB NC NCB D0B D1B D2B D3B D4B DCO_B D5B D6B D7B D9B D9B AF D2A D2A D3A D4A DCO_A D5A D6A D7A D8A D9A D10A D11A ORA +3.3VDIGA NC D0B D1B D2B D3B D4B DC0_B D5B D6B D7B D8B D8B D8B AG +3.3VDIGA +3.3VDIGA D3A D4A DCO_A D5A D6A D7A D8A D9A D10A D11A ORA +3.3VDIGA NC D0B D1B D2B D3B D4B DC0_B D5B D6B D7B D8B +3.3VDIGB +3.3VDIGB Rev Pr. A -8- AD10235 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperature Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated from the measured SNR based on the equation: SNRMEASURED -1.76 dB 6.02 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). ENOB = ENCODE Pulsewidth / Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing t ENCH in text. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: V2Fullscale rms = 10 log Z Input .001 PowerFullscale Gain Error Gain error is the difference between the measured and ideal full scale input voltage range of the ADC. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propogation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. -9- Rev Pr. A AD10235 APPLICATION NOTES THEORY OF OPERATION The AD10235 architecture is optimized for high speed and ease of use. The analog inputs drive a wide-bandwidth, high performance transformer circuit, which drives the A/D converter. A unique termination scheme (patent pending) is employed to enhance the input bandwidth. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are standard LVDS (ANSI644 compatible). USING THE AD10235 ENCODE Input Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. An A/D converter's track/hold circuit is essentially a mixer, combining any noise, distortion, or timing jitter on the clock with the desired signal prior to the A/D conversion circuit. For that reason, considerable care has been taken in the design of the ENCODE input of the AD10235, and the user is advised to give commensurate thought to the clock source. The AD10235 has an internal clock duty cycle stabilization circuit that locks onto the rising edge of ENCODE (falling edge of ENCODE if driven differentially), and optimizes timing internally. This allows for a wide range in input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern, and is not reduced by the internal stabilization circuit. This circuit is always on, and cannot be disabled by the user. The ENCODE and ENCODE inputs are internally biased to 1.5V (nominal), and support either differential or singleended signals. For best dynamic performance, a differential signal is recommended. Good performance can be achieved by using an MC10EL16 to drive the encode inputs and provide single-ended to differential converion, as illustrated in figure below. inputs are self-biased by an on-chip resistor divider to a nominal 2.8V. (See Equivalent Circuits section TBD.) Special care was taken in the design of the Analog Input section of the AD10235 to prevent damage and corruption of data when the input is overdriven. Digital Outputs The AD10235 has been designed to provide LVDS digital outputs. This allows for higher-speed operation while reducing the amount of digital noise coupled into the analog section of the system. CMOS output versions of this device are available. Consult the factory for more information. LVDS outputs are available when S2=VDD and a 3.4K RSET resistor is placed at pin 7 (LVDSBIAS). This resistor sets the current at each output equal to a nominal 3.5mA (1.2V/RSET). A 100 ohm differential termination resistor placed at the LVDS receiver inputs results in a nominal 350mV voltage swing at the termination of the line. When operating in LVDS mode, the output supply must be at a DC potential that is greater than or equal to the analog supply level (AVDD) using the same power supply for both pins, using an inductor for noise isolation if necessary. Clock Outputs (DCO, DCO) Clock output signals are derived from ENCODE and are available off-chip at DCO and DCO. These clocks can facilitate data latching and other downstream timing functions, providing a low skew clocking solution (see timing diagram). The capacitave loading on these signals should not exceed 5pF, limiting the transient currents associated with such high speed conversion signals. Note that a 100 ohm differential termination resistor is required at the receiver for proper LVDS operation. Voltage Reference A stable and accurate 1.25 V voltage reference is built into the AD10235 (VREF). An external reference is not required. 1 F PECL GATE AD10235 ENCODE ENCODE 1 F 510 510 Driving Encode with EL16 Analog Input The analog input is a differentially ac-coupled high performance 1:1 transformer with an input impedance of 50 . The nominal full scale input is 1.533 Vp-p. For best dynamic performance, impedances at AIN and AIN are matched. The analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. The wideband transformer is used to provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog -10- Rev Pr. A AD10235 OUTLINE DIMENSIONS dimensions shown in mm -11- Rev Pr. A |
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