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Features
* USB 2.0 Full Speed Host/Function Processor
- Real-time Host/Function Switching Capability - Internal USB and System Interface Controllers - 32-bit Generic System Processor Interface with DMA - Separate Tx and Rx Buffers for Host and Function Operations - In-System Software Upgrade Autonomous USB Host Operation without System Processor Intervention - Device Enumeration - USB Protocol Management - Bus Bandwidth Reclamation - Status Handling - Control, Bulk, Interrupt and Isochronous Transfers Full-speed Function Controller - 1 Bi-directional Control Endpoint - 6 Programmable (Packet Size and Endpoint type) Endpoints Supporting Interrupt, Bulk and Isochronous Transfers - Automatic Retry for Non-isochronous End-points Integrated USB Firmware - Easy-to-use, ANSI C Compliant API for USB Device Driver Development - Embedded, OS Agnostic USB Host Stack - Embedded System Interface Driver - Embedded USB Hub Driver 6 Mhz Operation 3.3/1.8V Operation 100-pin LQFP Packages
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USB 2.0 Full-Speed Host/Function Processor AT43USB370 Summary
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Overview
Atmel's AT43USB370 is a USB 2.0 compliant, dual role, full speed Host/Function processor designed specifically to enable point-to-point USB connectivity for embedded devices. It features integrated USB host stack, system interface drivers, on-chip USB hardware, 32-bit generic system processor interface with DMA support, and on-the-fly host/function switching capability. The on-chip USB hardware features USB transceiver, serial interface engine (SIE), SIE controller and SOF generation block. It supports the physical and data link layer of the USB protocol whereas the USB transaction layer is implemented in firmware. In host mode, the integrated USB firmware consists of the USB host stack running on the USB controller and the system interface driver resident on the system interface controller. The USB host stack provides complete USB protocol management including d ev ic e en um era tio n, tran sa ct io n ma n ag e me nt, sch e du ling a n d fram e management, and bus reclamation. The system interface driver serves as an interface between the USB host stack and the applications resident on the external system processor. It handles all of the high-level data flow management during a USB transaction. Together, the USB host stack and the system interface driver deliver complete USB host operations autonomously, without the intervention of the system processor.
Rev. 3340BS-USB-4/14/03
1
The AT43USB370 communicates with the external system processor through its generic 32-bit system processor interface. This system interface features 2 Kbytes of FIFO and a DMA engine designed to ensure maximum bus utilization. The automatic USB retry mechanism built into the AT43USB370 further minimizes data traffic across the system interface. As a function, the AT43USB370 operates in full speed mode. It supports one control endpoint and a maximum of six programmable (max packet size and endpoint type) endpoints. The internal USB controller runs the function firmware that manages USB enumeration and data flow control without system processor intervention. Developing application specific USB device drivers requires the use of a small set of high level, ANSI C compliant APIs (system interface APIs) that provides communication between the system processor and the AT43USB370. The encapsulation of USB operations into this small set of APIs leads to unprecedented ease in device driver development and RTOS support. The AT43USB370, with its highly integrated USB hardware/firmware architecture, not only hides the complexity of the traditional USB design, but also frees system resources from being burdened by timing critical USB activities. It is an ideal solution for point-to-point USB connectivity in the resource constrained embedded environment.
Pin Configuration
Figure 1. AT43USB370 100-Lead TQFP
D0 D1 D2 D3 D4 D5 D6 D7 VSS D8 D9 D10 D11 VCC D12 D13 D14 D15 NC VDD18 VSS D16 D17 D18 D19
A7 A6 A5 A4 A3 A2 A1 A0 CS_N OE_N SELECT INTR_IN INTR_OUT VDD VSS VSS VDD18 PROG MORE READY DONE BUSY WAIT_N WE_N DREQ_N
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS D20 D21 D22 D23 VDD D24 D25 D26 D27 VSS D28 D29 D30 D31 VDD18 VSS NC NC SCAN_EN RCV_DATA DCLK TRST_N VSS VDD
2
AT43USB370
3340BS-USB-4/14/03
DACK_N VSS BT MT VDD TP0 TP1 CLK_SEL VSS XTAL1 XTAL2 VDD LFT VSS DP DM TP2 TP3 RPD_EN RPU_EN RESET_N TCK TMS TDI TDO
AT43USB370
Pin Assignment
Table 1. Pin Assignment for the AT43USB370
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal A7 A6 A5 A4 A3 A2 A1 A0 CS_N OE_N SELECT INTR_IN INTR_OUT VDD VSS VSS VDD18 PROG MORE READY DONE BUSY WAIT_N WE_N DREQ_N DACK_N VSS BT MT VDD TP0 TP1 CLK_SEL VSS Type Input Input Input Input Input Input Input Input Input Input Input Input Output Power Supply/Gnd Power Supply/Gnd Power Supply/Gnd Power Supply/Gnd Input Input Output Input Output Output Input Output Input Power Supply/Gnd Input Input Power Supply/Gnd Input Output Input Power Supply/Gnd Pin # 35 36 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Signal XTAL1 XTAL2 XTAL2 VDD LFT VSS DP DM TP2 TP3 RPD_EN RPU_EN RESET_N TCK TMS TDI TDO VDD VSS TRST_N DCLK RCV_DATA SCAN_EN NC NC VSS VDD18 D31 D30 D29 D28 VSS D27 D26 Type Input Output Output Power Supply/Gnd Input Power Supply/Gnd Bi-directional Bi-directional Input Input Output Output Input Input Input Input Output Power Supply/Gnd Power Supply/Gnd Input Output Output Input Not Connected Not Connected Power Supply/Gnd Power Supply/Gnd Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Gnd Bi-directional Bi-directional Pin # 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal D25 D24 VDD D23 D22 D21 D20 VSS D19 D18 D17 D16 VSS VDD18 NC D15 D14 D13 D12 VCC D11 D10 D9 D8 VSS D7 D6 D5 D4 D3 D2 D1 D0 Type Bi-directional Bi-directional Power Supply/Gnd Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Gnd Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Gnd Power Supply/Gnd Not Connected Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Gnd Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Gnd Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional
3
3340BS-USB-4/14/03
Pin Description
Table 2. Pin Description for the AT43USB370
Pin Name A[7:0] CS_N OE_N SELECT INTR_IN INTR_OUT VCC VDD VSS VDD18 PROG MORE READY DONE BUSY WAIT_N WE_N DREQ_N DACK_N BT MT TP0 TP1 TP2 TP3 CLK_SEL XTAL1 XTAL2 LFT DP DM RPD_EN Type Input Input Input Input Input Output Power Supply/Gnd Power Supply/Gnd Power Supply/Gnd Power Supply/Gnd Input Input Output Input Output Output Input Output Input Input Input Input Output Input Input Input Input Output Input Bi-directional Bi-directional Output Description ADDRESS BUS - System Address Bus (Least Significant Byte only) CHIP_SELECT - from System Processor. Active Low OUTPUT_ENABLE - from System Processor. Active Low PROCESSOR_SELECT - from System Processor - used to select between USBC and SIC when PROG is active. Active High Interrupt to AT43USB370 - from System Processor. Active High Interrupt from AT43USB370 - to System Processor. Active High 3.3V Power Net 3.3V Power Supply Ground 1.8V Power Supply - Bus interface IO pads PROGRAM_LOAD_ENABLE - from System Processor - set program mode to USBC and SIC. Active High. PIO Mode Handshake signal from System Processor. Active High PIO Mode Handshake signal to System Processor. Active High PIO Mode Handshake signal from System Processor. Active High BUSY - to System Processor - indicates the AT43USB370 cannot accept external interrupts. Active High WAIT - to System Processor. Active Low WRITE_ENABLE - from System Processor. Active Low DMA Request - to System Processor. Active Low DMA Acknowledge - from System Processor. Active Low BIST- Test Signal Memory - Test Signal Test Pin 0 Test Pin 1 Test Pin 2 Test Pin 3 External/PLL Clock Selection - Low selects crystal-PLL clock source while a High uses XTAL1, bypassing PLL. Oscillator Input - Input to the inverting oscillator amplifier. Oscillator Output - Output of the inverting oscillator amplifier. PLL Loop Filter D+ (USB Line) D- (USB Line) Pull Down Enable
4
AT43USB370
3340BS-USB-4/14/03
AT43USB370
Table 2. Pin Description for the AT43USB370 (Continued)
Pin Name RPU_EN RESET_N TCK TMS TDI TDO TRST_N DCLK RCV_DATA SCAN_EN NC D[31:0] Type Output Input Input Input Input Output Input Output Output Input - Bi-directional Description Pull Up Enable RESET - for AT43USB370. Active Low JTAG Clock JTAG Mode Select JTAG Serial Data IN JTAG Serial Data OUT JTAG Reset - Active Low Test Pin Test Pin Test Pin-Scan Control Not Connected System Data Bus
Block Diagram
Figure 2. AT43USB370 Hardware
USB Controller (USBC)
Control & Status Registers
System Interface Controller (SIC)
SIE Controller
USB Transceiver
D+ D-
System Processor Interface FIFOs DMA
Control Address Data
SIE
5
3340BS-USB-4/14/03
Figure 3. AT43USB370 Architecture
System Processor
Mass Storage
Applications USB Class Device Drivers HID Printer
Other USB Devices
Operating System AT43USB370 System Interface APIs
Embedded, OS Agnostic USB Firmware
System Interface Driver
API Manager Data Trasport Service Descriptor Management
USB Host Stack
Device Enumeration Transaction Management Frame Scheduling Status Handling HUB Driver
Hard Disk
Printer
Keyboard
USB Hub
Development Support
The AT43USB370 is supported by the AT43DK370, a complete development kit. The AT43DK370 includes a reference design board with an ARM7 system processor, the USB 2.0 compliant host stack and system interface firmware, sample application code and the complete documentation (PCB layout, schematics, BOM, etc.). The "USB Clinic", an Atmel USB software debugging utility is included in the development kit.
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AT43USB370
3340BS-USB-4/14/03
AT43USB370
Packaging Information
100 Pin - LQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 1.35 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM - - 1.40 16.00 14.00 16.00 14.00 - - - 0.50 TYP MAX 1.60 0.15 1.45 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum.
E1 B C L e
04/29/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 100AA, 100-lead, 14 x 14 mm Body Size, 1.4 mm Body Thickness, 0.5 mm Lead Pitch, Low Profile Quad Flat Pack (LQFP) DRAWING NO. 100AA REV. C
R
7
3340BS-USB-4/14/03
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Printed on recycled paper.
3340BS-USB-4/14/03 xM

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