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M
* * * * * PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 PIC16F84A
PIC16F8X
Pin Diagram
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
EEPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
PIC16F8X
1.0
PROGRAMMING THE PIC16F8X
The PIC16F8X is programmed using a serial method. The serial mode will allow the PIC16F8X to be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16F8X devices in all packages.
1.1
Hardware Requirements
The PIC16F8X requires one programmable power supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V. Both supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC16F8X allows programming of user program memory, data memory, special locations used for ID, and the configuration word.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F8X
During Programming Pin Name RB6 RB7 MCLR VDD VSS Function CLOCK DATA VTEST MODE VDD VSS Pin Type I I/O P* P P Clock input Data input/output Program Mode Select Power Supply Ground Pin Description
Legend: I = Input, O = Output, P = Power *In the PIC16F8X, the programming high voltage is internally generated. To activate the programming mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current.
(c) 1998 Microchip Technology Inc.
DS30262B-page 1
PIC16F8X
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
2.2
ID Locations
The user memory space extends from 0x0000 to 0x1FFF (8K), of which 1K (0x0000 - 0x03FF) is physically implemented. In actual implementation the onchip user program memory is accessed by the lower 10-bits of the PC, with the upper 3-bits of the PC ignored. Therefore if the PC is greater than 0x3FF, it will wrap around and address a location within the physically implemented memory. (See Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a `1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode as described in Section 2.3. In the configuration memory space, 0x2000-0x200F are physically implemented. However, only locations 0x2000 through 0x2007 are available. Other locations are reserved. Locations beyond 0x200F will physically access user memory. (See Figure 2-1).
A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in an unscrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where `bbbb' is ID information. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-2. To understand the scrambling mechanism after code protection, refer to Section 4.0.
DS30262B-page 2
(c) 1998 Microchip Technology Inc.
PIC16F8X
FIGURE 2-1: PROGRAM MEMORY MAPPING
0.5 KW 0 1FF 3FF 400 Implemented 1 KW Implemented
Not Implemented
Not Implemented
1FFF 2000
ID Location ID Location ID Location ID Location Reserved Reserved Reserved Configuration Word
Implemented
Implemented
2000 2001 2002 2003 2004 2005 2006 2007
2008
Not Implemented
Not Implemented
3FFF
(c) 1998 Microchip Technology Inc.
DS30262B-page 3
PIC16F8X
2.3 Program/Verify Mode
The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 and RB7 are Schmitt Trigger Inputs in this mode. Note: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). The commands that are available are: 2.3.1.1 LOAD CONFIGURATION
The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). The normal sequence for programming is to use the load data command to set a value to be written at the selected address. Issue the begin programming command followed by read data command to verify, and then increment the address. 2.3.1 SERIAL PROGRAM/VERIFY OPERATION
The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specifications) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first.
After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits in a "data word," as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL).
DS30262B-page 4
(c) 1998 Microchip Technology Inc.
PIC16F8X
2.3.1.2 LOAD DATA FOR PROGRAM MEMORY After receiving this command, the chip will load in a 14bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1.
TABLE 2-1:
COMMAND MAPPING FOR PIC16F83/CR83/F84/CR84
Command Mapping (MSB ... LSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0, data (14), 0 0, data (14), 0 Data 0, data (14), 0 0, data (14), 0 0, data (14), 0
Load Configuration Load Data for Program Memory Read Data from Program Memory Increment Address Begin Programming Load Data for Data Memory Read Data from Data Memory Bulk Erase Program Memory Bulk Erase Data Memory
TABLE 2-2:
COMMAND MAPPING FOR PIC16F84A
Command Mapping (MSB ... LSB) X X X X 0 0 X X X X X X X X 0 1 X X X X 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0, data (14), 0 0, data (14), 0 Data 0, data (14), 0 0, data (14), 0 0, data (14), 0
Load Configuration Load Data for Program Memory Read Data from Program Memory Increment Address Begin Erase Programming Cycle Begin Programming Only Cycle Load Data for Data Memory Read Data from Data Memory Bulk Erase Program Memory Bulk Erase Data Memory
(c) 1998 Microchip Technology Inc.
DS30262B-page 5
PIC16F8X
FIGURE 2-2: PROGRAM FLOW CHART - PIC16F8X PROGRAM MEMORY
Start
Set VDD = VDDp
Program Cycle
Read Data Command
Increment Address Command No
Data Correct? Yes All Locations Done? Yes Verify all Locations @ VDDmin @ VDD min.
No
Report Programming Failure
Program Cycle Load Data Command
Begin Programming Command
Data Correct? Yes Verify all Locations @ VDDmax @ VDD max.
No
Report Verify Error @ VDDmin @ VDD min.
Wait 10 ms
Data Correct? Yes Done
No
Report Verify Error @ VDDmax @ VDD max.
DS30262B-page 6
(c) 1998 Microchip Technology Inc.
PIC16F8X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16F8X CONFIGURATION MEMORY
Start
Load Configuration Command
No
Program ID Location?
Yes
Program Cycle
Read Data Command
Increment Address Command
Report Programming Failure
No
Data Correct Yes
No
Address = 0x2004 Yes Increment Address Command
Increment Address Command
Increment Address Command
Program Cycle (Config. Word)
VDDmax Set VDD = VDD max.
Report Program Config. Word Error No Done Yes Data Correct?
No
Data Correct? Yes
Read Data Command
VDDmin Set VDD = VDD min. Read Data Command
(c) 1998 Microchip Technology Inc.
DS30262B-page 7
PIC16F8X
2.3.1.3 LOAD DATA FOR DATA MEMORY 2.3.1.8 BEGIN PROGRAMMING After receiving this command, the chip will load in a 14bit "data word" when 16 cycles are applied. However, the data memory is only 8-bits wide, and thus only the first 8-bits of data after the start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly. The data memory contains 64 words. Only the lower 8-bits of the PC are decoded by the data memory, and therefore if the PC is greater than 0x3F, it will wrap around and address a location within the physically implemented memory. 2.3.1.4 READ DATA FROM PROGRAM MEMORY A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes a write. The user must allow for program cycle time for programming to complete. No "end programming" command is required. This command is similar to the ERASE/PROGRAM CYCLE command, except that a word erase is not done. It is recommended that a bulk erase be performed before starting a series of programming only cycles. 2.3.1.9 BULK ERASE PROGRAM MEMORY
After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.3.1.5 READ DATA FROM DATA MEMORY
After this command is performed, the next program command will erase the entire program memory. To perform a bulk erase of the program memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase User Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase.
After receiving this command, the chip will transmit data bits out of the data memory starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8bits wide, and therefore, only the first 8-bits that are output are actual data. 2.3.1.6 INCREMENT ADDRESS
If the address is pointing to the test program memory (0x2000 - 0x200F), then both the user memory and the test memory will be erased. The configuration word will not be erased, even if the address is pointing to location 0x2007. Note: If the device is code-protected (PIC16F84A), the BULK ERASE command will not work. BULK ERASE DATA MEMORY
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.1.7 BEGIN ERASE/PROGRAM CYCLE
2.3.1.10
To perform a bulk erase of the data memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase Data Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. Note: All BULK ERASE operations must take place at 4.5 to 5.5 VDD range.
A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes an erase before write. The user must allow for both erase and programming cycle times for programming to complete. No "end programming" command is required.
DS30262B-page 8
(c) 1998 Microchip Technology Inc.
PIC16F8X
2.4 Programming Algorithm Requires Variable VDD
The PIC16F8X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin. as well as VDDmax. Verification at VDDmin. guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (See Table 5-1). VDDP = VCC range required during programming. VDDmin. = minimum operating VDD spec for the part. VDDmax.= maximum operating VDD spec for the part. Programmers must verify the PIC16F8X at its specified VDD max. and VDDmin levels. Since Microchip may introduce future versions of the PIC16F8X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
(c) 1998 Microchip Technology Inc.
DS30262B-page 9
PIC16F8X
3.0 CONFIGURATION WORD
3.1 Device ID Word
The PIC16F8X has five configuration bits. These bits can be set (reads `0') or left unchanged (reads `1') to select various device configurations. The device ID word for the PIC16F84A is located at 2006h.
TABLE 3-1:
Device ID Value Device Dev PIC16F84A 00 0101 010 Rev 0 0000
FIGURE 3-1:
Bit Number: PIC16F83/ F84/F84A PIC16CR83/ CR84
CONFIGURATION WORD BIT MAP
12
CP CP
13
CP CP
11
CP CP
10
CP CP
9
CP CP
8
CP CP
7
CP DP
6
CP CP
5
CP CP
4
CP CP
3
PWRTE PWRTE
2
WDTE WDTE
1
FOSC1 FOSC1
0
FOSC0 FOSC0
bit 4-13: CP, Code Protection Configuration Bits 1 = code protection off 0 = code protection on bit 7: PIC16CR83/CR84 only DP, Data Memory Code Protection Bit 1 = code protection off 0 = data memory is code protected PWRTE, Power Up Timer Enable Configuration Bit 1 = Power up timer disabled 0 = Power up timer enabled WDTE, WDT Enable Configuration Bits 1 = WDT enabled 0 = WDT disabled FOSC<1:0>, Oscillator Selection Configuration Bits 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator
bit 3:
bit 2:
bit 1-0
DS30262B-page 10
(c) 1998 Microchip Technology Inc.
PIC16F8X
4.0 CODE PROTECTION
Procedure to disable code protect: a) b) c) d) e) f) g) h) Execute load configuration (with a `1' in bit 4, code protect). Increment to configuration word location (0x2007) Execute command (000001) Execute command (000111) Execute `Begin Programming' (001000) Wait 10 ms Execute command (000001) Execute command (000111) For PIC16F8X devices, once code protection is enabled, all program memory locations read all 0's. The ID locations and the configuration word read out in an unscrambled fashion. Further programming is disabled for the entire program memory as well as data memory. It is possible to program the ID locations and the configuration word.
4.1
Disabling Code-Protection
It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (code protect bit = 1) using this procedure; however, all data within the program memory and the data memory will be erased when this procedure is executed, and thus, the security of the data or code is not compromised.
4.2
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F8X, the EEPROM data memory should also be embedded in the hex file (see Section 5.1). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
PIC16F83
CONFIGURATION WORD
To code protect: 000000000XXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] PIC16CR83 To code protect: 000000000XXX Program Memory Segment Configuration Word (0x2007) All memory R/W in Protected Mode Read Unscrambled Read All 0's for Program Memory, Read All 1's for Data Memory Write Disabled Read Unscrambled R/W in Unprotected Mode Read Unscrambled Read Unscrambled, Data Memory Write Enabled Read Unscrambled R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
ID Locations [0x2000 : 0x2003]
(c) 1998 Microchip Technology Inc.
DS30262B-page 11
PIC16F8X
PIC16CR84 To code protect: 000000000XXX Program Memory Segment Configuration Word (0x2007) All memory R/W in Protected Mode Read Unscrambled Read All 0's for Program Memory, Read All 1's for Data Memory Write Disabled Read Unscrambled R/W in Unprotected Mode Read Unscrambled Read Unscrambled, Data Memory Write Enabled Read Unscrambled
ID Locations [0x2000 : 0x2003] PIC16F84 To code protect: 000000000XXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] PIC16F84A To code protect: 000000000XXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003]
R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled
R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled
R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Legend: X = Don't care
DS30262B-page 12
(c) 1998 Microchip Technology Inc.
PIC16F8X
4.3
4.3.1
CHECKSUM COMPUTATION
CHECKSUM
The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
Checksum is calculated by reading the contents of the PIC16F8X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16F8X. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F8X devices is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable)
TABLE 4-2:
CHECKSUM COMPUTATION
Code Protect OFF ON OFF ON OFF ON OFF ON OFF ON Checksum* SUM[0x000:0x1FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID Blank Value 0x3DFF 0x3E0E 0x3DFF 0x3E0E 0x3BFF 0x3C0E 0x3BFF 0x3C0E 0x3BFF 0x3C0E 0x25E6 at 0 and max address 0x09CD 0x09DC 0x09CD 0x09DC 0x07CD 0x07DC 0x07CD 0x07DC 0x07CD 0x07DC
Device PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 PIC16F84A
Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
(c) 1998 Microchip Technology Inc.
DS30262B-page 13
PIC16F8X
5.0
5.1
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
Embedding Data EEPROM Contents in Hex File
The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write data EEPROM contents to a hex file along with program memory information and fuse information. The 64 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage is one data byte per address location, LSB aligned.
TABLE 5-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
+10C TA +40C, unless otherwise stated, (25C is recommended) 4.5V VDD 5.5V, unless otherwise stated. Characteristic Supply voltage during programming Supply voltage during verify High voltage on MCLR for test mode entry Supply current (from VDD) during program/verify Supply current from VIHH (on MCLR) (RB6, RB7) input high level (RB6, RB7) input low level MCLR (test mode selection) MCLR rise time (VSS to VHH) for test mode entry RB6, RB7 setup time (before pattern setup time) Data in setup time before clock Data in hold time after clock Data input not driven to next clock input (delay required between command/data or command/command) Delay between clock to clock of next command or data Clock to data out valid (during read data) RB <7:6> hold time after MCLR Erase cycle time Program cycle time 100 100 100 1.0 0.8 VDD 0.2 VDD 8.0 Min. 4.5 VDDmin 12 Typ. 5.0 Max. 5.5 VDDmax 14.0 50 200 Units V V V mA A V V s ns ns ns s Schmitt Trigger input Schmitt Trigger input Note 1 Note 2 Conditions/ Comments
Standard Operating Conditions Operating Temperature: Operating Voltage: Paramet er No. Sym. VDDP VDDV VIHH IDDP IHH VIH1 VIL1 P1 P2 P3 P4 P5 TvHHR Tset0 Tset1 Thld1 Tdly1
P6 P7 P8
Tdly2 Tdly3 Thld0
1.0 80 100 10 10
s ns ns ms ms
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
DS30262B-page 14
(c) 1998 Microchip Technology Inc.
PIC16F8X
FIGURE 5-1:
VIHH MCLR P2 1 RB6 (CLOCK) RB7 (DATA) P8 100ns 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
LOAD DATA COMMAND (PROGRAM/VERIFY)
0 P3
1
100ns 0
0
0
0 P5 1s min.
0 P3 P4
0
P4 100ns min. Reset
} }
} }
Program/Verify Test Mode
100ns min.
FIGURE 5-2:
VIHH MCLR P2 RB6 (CLOCK) RB7 (DATA)
READ DATA COMMAND (PROGRAM/VERIFY)
100ns 1 P8 100ns 1 P4 P3 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
0
0
0
0
0 P5 1s min.
P7
} }
100ns min. RB7 = output RB7 input
Reset
Program/Verify Test Mode
FIGURE 5-3:
MCLR
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1 2 3 4 5 6 1s min. 1 Next Command 2
RB6 (CLOCK) RB7 (DATA)
0
1
1
0
0
0 P5
0
0
P3 P4
1s min.
Program/Verify Test Mode
Reset
} }
100ns min
(c) 1998 Microchip Technology Inc.
DS30262B-page 15
M
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Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 5/98, Microchip Technology Incorporated, USA.
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30262B-page 16
(c) 1998 Microchip Technology Inc.

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