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SP5054
2.6GHz 3-Wire BUS Controlled Synthesiser
DS3048
ISSUE 3.4
May 1996
The SP5054 is a single-chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5055, allowing the design of one tuner with either I 2C bus or 3-wire bus format, depending on which device is inserted. The SP5054, when used with a satellite varactor tuner, forms a complete phase locked loop tuning system. The circuit consists of a divide-by-16 prescaler with its own preamplifier and a 14/15-bit programmable divider controlled by a serially-loaded data register. Four independently programmable open-collector outputs are included. The device has four modes of operation, selected by the Mode Select input; these modes are summarised in Table1. The comparison frequencies are obtained by the division of the output of a 4MHz crystal controlled on-chip oscillator. The phase comparator has a charge pump output with an output amplifier stage around which feedback may be applied. Only one external transistor is required for varactor line driving.
Ordering Information
SP5054 KG DPAS (18-lead plastic package) SP5054S KG MPAS (16-lead miniature plastic package)
CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2 PORT P1
1 2 3 4
18 17 16 15
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC NC NC LOCK ENABLE
Features * Complete 2*6GHz Single Chip System * 62*5kHz, 100kHz and 125kHz Step Size * * * * * * * * * Low Power Consumption (325mW Typ.) Programming Compatible with Toshiba TD6380, TD6381 and TD6382 * Pin Compatible with SP5055 * Low Radiation Varactor Drive Amplifier Disable Charge Pump Disable Single Port 18/19 Bit Serial Data Entry Four Controllable Outputs ESD Protection
5 SP5054 14 6 7 8 9 13 12 11 10
DP18
CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2
1
16
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC LOCK ENABLE
* See notes on pin compatibility
Normal ESD handling precautions should be observed
SP5054S
8
9
PORT P1
Applications * Satellite TV * High IF Cable Tuning Systems
Figure 1 - Pin connections - top view
MP16
SP5054
Electrical Characteristics
TAMB = 220C to 180C, VCC = 14*5V to 15*5V. Frequency standard = 4MHz. All pin connections refer to DP package. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Pin Min. Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Input capacitance High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current Clock inout hysteresis Clock rate Data set up time, t2 Data hold time, t3 Enable set up time, t1 Enable hold time, t5 Clock-to-enable time, t4 Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain Oscillator temperature stability Oscillator stability with supply voltage Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance Ports and Lock Output Sink current Port leakage current Varactor drive amplifier disable Charge pump disable 10 2 2 40 2400 14 15,16 Typ. 65 50 100 50 2 3 0 VCC 0*7 1 5 2250 700 2700 0*4 0*5 300 600 300 600 300 6150 65 5 1 6400 2 2 200 ppm/C ppm/V Parallel resonant crystal (note 1) mV p-p Nominal spread = 615% Max. 80 400 400 VCC = 5V mA mVrms 500MHz to 2*6GHz sinewave mVrms 120MHz and 500MHz, see Fig. 6 pF V V A A A A A V MHz ns ns ns ns ns A nA mV/s mA Units Conditions
15,16
4,5,10 4,5,10 4,5,10 5 4,10 3 3 5 5 4 4 10 10 10 1 1 18
VIN = 5*5V, VCC = 5*5V VIN = 0V, VCC = 5*5V VIN = 0V, VCC = 5*5V VIN = 5*5V, VCC = 5*5V VIN = 0V, VCC = 5*5V
See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 V pin 1 = 2*0V V pin 1 = 2*0V At collector of external transistor V pin 18 = 0*7V I pin 18 = 100A
6-9,11 6-9 10 4
10 10 2350 2350
mA A A A
VOUT = 0*7V VOUT = 13*2V VIN < 0V VIN < 0V
NOTE 1. The maximum resistance quoted refers to all conditions, including start-up.
2
SP5054
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V Parameter SP5054 Supply voltage RF input voltage Port voltage 14 15,16 6-9 6-9 15,16 1,18 2 4,5,10 Pin SP5054S 12 13,14 6-9 6-9 13-14 1,16 2 4,5,10 20*3 20*3 20*3 20*3 20*3 20*3 255 Min. 20*3 Value Max. 7 2*5 14 6 VCC 10*3 VCC 10*3 VCC 10*3 VCC 10*3 1150 1150 78 24 111 41 484 V V p-p V V V V V V C C C/W C/W C/W C/W mW With VCC applied Port in off state Port in on state Units Conditions
Prescaler DC offset Loop amplifier DC offset Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature DP18 thermal resistance, chip-to-ambient DP18 thermal resistance, chip-to-case MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption at 5*5V
j1 j 0.5 j2
j 0.2 j5
0
2*6GHz
0.2
0.5
1
2
5
2j 5 2j 0.2
S11 ZO = 50
2j 0.5 2j 1
2j 2
FREQUENCY MARKER STEP = 500MHz
Figure 2 - Typical input impedance
3
SP5054
VCC RF IN RF IN
PRE AMP
416 PRESCALER
14/15 BIT PROGRAMMABLE DIVIDER
FPD
PHASE COMP F
FCOMP
REFERENCE DIVIDER 4512/640/1024
OSC 4MHz
CRYSTAL
CLOCK DATA ENABLE MODE SELECT DATA INPUT INTERFACE
DATA CLOCK MODE SELECT
CHARGE PUMP 14/15 BIT DIVIDER RATIO LATCH CHARGE PUMP DRIVE OUTPUT
CONTROL OUTPUT BUFFER CP DIS VA DIS
LOCK DETECT
VEE
P4 P3 P2 P1 PORTS
LOCK
Figure 3 - Block diagram of SP5054
Mode 3 2 1 0
Mode Select input voltage 0*925VCC to VCC 0*675VCC to 0*825V CC Open circuit 0V to 0*325 VCC
Programmable divider bit length 14 15 15 15
Reference divider ratio 512 512 1024 640
Frequency step size (kHz) * 125 125 62*5 100
Maximum operating frequency (GHz) * 2*0479 2*5 2*0479 2*5
Table 1 - SP5054 modes of operation. * Frequencies stated apply when using a 4MHz crystal.
Functional Description
The SP5054 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard Data, Clock and Enable three-wire data bus. The data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the Enable, so giving improved fine tune facility for digital AFC etc. The data sequence and timing follows the format shown in Fig. 4. The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of this divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domain to the internally generated comparison frequency, FCOMP. FCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used is generally 4MHz, which gives an FCOMP of 3*90625/6*25/ 7*8125kHz and, when multiplied back up to the synthesised LO, gives a minimum step size of 62*5/100/125kHz, respectively. The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The SP5054 contains an improved lock detect circuit which generates a flag when the loop has attained lock. `In lock' is indicated by high impedance state. The SP5054 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least 10mA. These outputs are set by the remaining four bits within the normal data word.
Notes on pin compatibility
The SP5054 may be used in SP5055 applications which require 3-wire bus as opposed to I2C bus data format. In SP5055 applications where the reference crystal is grounded to pin 3, a small modification is required to ground the crystal as shown in Fig. 5. Appropriate connections must also be made to the Mode Select input (see Table 1). In Mode 3, The SP5054 is programming compatible with the Toshiba TD6380, in Modes 0 and 2 with the TD6381 and in Mode 1 with the TD6382.
4
SP5054
CLOCK
ENABLE
DATA (MODE 3)
217
P1
216
P2
215
P3
214
P4
213
MSB
212
22
21
20
LSB
DATA (MODES 0, 1, 2)
218
P1
217
P2
216
P3
215
P4
CLOCK
ENABLE
DATA t1 = ENABLE SET-UP TIME t2 = DATA SET-UP TIME t3 = DATA HOLD TIME t4 = CLOCK-TO ENABLE TIME t5 = ENABLE HOLD TIME
t1 t4 t2 t3 t5
Figure 4 - Data format and timing

FREQUENCY DATA LSB = 125kHz (MODE 2) 62*5kHz (MODE 1) 100kHz (MODE 0)

FREQUENCY DATA (LSB = 125kHz)
214
MSB
213
22
21
20
LSB
5
SP5054
130V
22k 15V 47n 180n 10k 22k 4MHz CRYSTAL 18p 1 2 MODE DATA CLOCK P4 3 4 18 17 1n 16 15 1n 2N3904 0*1 47k VT
112V
VARACTOR DRIVE
10n
OSCILLATOR OUTPUT
5 SP5054 14 6 7 8 9 13 12 11 10 LOCK ENABLE
SATELLITE TUNER
CONTROL MICRO
P3 P2 P1
Figure 5 - Typical application (fSTEP = 125kHz)
400
VIN (mV RMS INTO 50 )
150
OPERATING WINDOW
100
50
120
1000
2000 FREQUENCY (MHz)
2600
3000
Figure 6 - Typical input sensitivity
6
SP5054
VREF
VCC
550
550
CHARGE PUMP
RF INPUTS 170 DRIVE OUTPUT
RF input
Loop amplifier
INPUT
CLOCK
Enable and data inputs
Clock input
VCC PORT
MODE SELECT CRYSTAL
Reference oscillator
Output ports P1-P4
Mode select input
Figure 7 - SP5054 input/output interface circuits
7
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