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Ordering number : EN4742
CMOS LSI
LC72P32
One-Time Programmable ROM Single-Chip PLL Plus Microcontroller
Overview
The LC72P32 is a version of the LC7232N single-chip PLL plus microcontroller product that provides an 8 Kbyte (4096 words x 16 bits) one-time programmable ROM on chip. The LC72P32 has identical functions and the same pin assignment and packaging as the LC7232N, which is a mask ROM product. The LC72P32 can contribute to bringing up the first production run of a new product quickly and to reducing the switchover period when specifications change.
Sanyo PROM Writing Service
Sanyo provides custom PROM writing, printing, screening and read-back testing (for fee) services for our one-time programmable ROM microcontroller products. Contact your Sanyo sales representative for pricing and other details.
Package Dimensions
unit: mm 3044B-QFP80A
[LC72P32]
Features
* Option selection according to PROM data The LC7232N optional functions can be specified with PROM data. This allows mass-production products to be tested and evaluated. * On-chip 8 Kbyte (4096 words x 16 bits) PROM This is a one-time programmable 8 Kbyte (4096 words x 16 bits) ROM. * Packaging and pin assignments are identical to those of the LC7232N mask ROM version, i.e., these products are pin compatible.
SANYO: QIP80A
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
93098HA (OT) /93094TH (OT) B8-0763 No. 4742-1/16
LC72P32
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topg Tstg HOLD, INT, RES, ADI, SNS, and the G port Inputs other than VIN1 H port Outputs other than VOUT1 D and H port pins E and F port pins B and C port pins S1 to S28 and I port pins Topg = -30 to +70C Conditions Ratings -0.3 to +6.5 -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to 5 0 to 3 0 to 1 0 to 1 400 -30 to +70 -45 to +125 Unit V V V V V mA mA mA mA mW C C
Output voltage
Note: This IC has reduced resistance to damage from static discharges and therefore requires special care in handling.
Allowable Operating Ranges at Ta = -30 to +70C, VDD = 4.0 to 5.5 V
Ratings Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 VIH2 Input high level voltage VIH3 VIH4 VIH5 VIH6 VIL1 VIL2 VIL3 Input low level voltage VIL4 VIL5 VIL6 VIL7 fIN1 fIN2 fIN3 Input frequency fIN4 fIN5 fIN6 fIN7 fIN8 VIN1 VIN2 Input amplitude VIN3 VIN4, 5 VIN6, 7 Input voltage range VIN8 Conditions CPU and PLL operating CPU operating Memory hold G port RES, INT, HOLD SNS A port E and F ports LCTR (period measurement), VDD1 G port RES, INT SNS A port E and F port LCTR (period measurement), VDD1 HOLD XIN FMIN, VIN2, VDD1 FMIN, VIN3, VDD1 AMIN (L), VIN4, VDD1 AMIN (H), VIN5, VDD1 HCTR, VIN6, VDD1 LCTR (frequency measurement), VIN7 and VDD1 LCTR (period), VIH6, VIL6 and VDD1 XIN FMIN FMIN AMIN LCTR, HCTR ADI min 4.5 4.0 1.3 0.7 VDD 0.8 VDD 2.5 0.6 VDD 0.7 VDD 0.8 VDD 0 0 0 0 0 0 0 4.0 10 10 0.5 2.0 0.4 100 1 0.50 0.10 0.15 0.10 0.10 0 4.5 typ max 5.5 5.5 5.5 8.0 8.0 8.0 VDD VDD VDD 0.3 VDD 0.2 VDD 1.3 0.2 VDD 0.3 VDD 0.2 VDD 0.4 VDD 5.0 130 150 10 40 12 500 20 x 103 1.5 1.5 1.5 1.5 1.5 VDD Unit V V V V V V V V V V V V V V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms Vrms Vrms V
No. 4742-2/16
LC72P32 Electrical Characteristics for the Allowable Operating Ranges
Ratings Parameter Hysteresis Reject pulse width Power-down detection voltage Symbol VH PREJ VDET IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIL1 Input low level current IIL2 IIL3 IIL4 Input floating voltage Pull-down resistance Output high level off leakage current Output low level off leakage current VIF RPD IOFFH1 IOFFH2 IOFFH3 IOFFL1 IOFFL2 VOH1 VOH2 VOH3 Output high level voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 Output low level voltage VOL4 VOL5 VOL6 VOL7 VOL8 Output middle level voltage A/D conversion error IDD1 IDD2 IDD3 Current drain IDD4 VM1 HOLD, INT, RES, ADI, SNS, and the G port: VI = 5.5 V A, E and F ports: E and F ports output off, A port with no RPD: VI = VDD XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V A port: with RPD: VI = VDD = 5.0 V INT, HOLD, RES, ADI, SNS, and the G port: VI = VSS A, E and F ports: E and F ports output off, A port with no RPD: VI = VSS XIN: VIN = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS A port: with RPD A port: with RPD, VDD = 5.0 V EO1, EO2: VO = VDD B, C, D, E, F, and I ports: VO = VDD H port: VO = 13 V EO1, EO2: VO = VSS B, C, D, E, F, and I ports: VO = VSS B and C ports: IO = -1 mA E and F ports: IO = -1 mA EO1, EO2: IO = -500 A XOUT: IO = -200 A S1 to S28 and I port: IO = -0.1 mA D port: IO = -5 mA COM1, COM2: IO = -25 A B and C ports: IO = 50 A E and F ports: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S28 and I port: IO = 0.1 mA D port: IO = 5 mA COM1, COM2: IO = 25 A H port: IO = 5 mA COM1, COM2: VDD = 5.0 V, IO = 20 A ADI, VDD1 VDD1, fIN2 = 130 MHz VDD = 5.0 V, PLL stopped, CT = 2.67 s (HOLD mode, Figure 1) VDD = 5.0 V, PLL stopped, CT = 13.33 s (HOLD mode, Figure 1) VDD = 5.0 V, PLL stopped, CT = 40.00 s (HOLD mode, Figure 1) VDD = 5.5 V, oscillator stopped, Ta = 25C (BACKUP mode, Figure 2) VDD = 2.5 V, oscillator stopped, Ta = 25C (BACKUP mode, Figure 2) 0.3 (150 ) 0.75 2.0 -1/2 15 2.7 1.7 1.5 5 1 2.5 0.5 VDD - 2.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 0.75 0.5 VDD - 0.5 1.0 VDD - 0.3 2.0 1.0 1.0 1.0 1.0 1.0 0.75 (400 ) 2.0 3.0 1/2 20 VDD - 1.0 0.01 75 100 0.01 2.0 4.0 5.0 10 2.0 4.0 5.0 10 50 3.0 3.0 15 30 0.05 VDD 200 10 3.0 5.0 10 3.0 VDD - 0.5 Conditions LCTR (period), RES, INT SNS 3.0 3.5 min 0.1 VDD 50 4.0 3.0 3.0 15 30 typ max Unit V s V A A A A A A A A A V k nA A A nA A V V V V V V V V V V V V V V V V LSB mA mA mA mA A A
IDD5
No. 4742-3/16
LC72P32 Test Circuits
Note: With PB to PF, PH and PI all open. Note that output mode is selected for PE and PF.
Figure 1 IDD2 to IDD4 in HOLD Mode
Note: With PA to PI, S1 to S24, COM1 and COM2 open.
Figure 2 IDD5 in BACKUP Mode
No. 4742-4/16
LC72P32 Pin Functions
Pin Pin No. Function I/O Circuit type PROM mode function
Low threshold type dedicated input port PA0 PA1 PA2 PA3 35 34 33 32 These pins can be used, for example, for key data acquisition. Built-in pull-down resistors can be specified as an option. This option is in 4-pin units, and cannot be specified for individual pins. Input through these pins is disabled in BACKUP mode. PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 30 29 28 27 26 25 24 23 Dedicated output ports Since the output transistor impedances are unbalanced CMOS, these pins can be effectively used for functions such as key scan timing. These pins go to the output highimpedance state in BACKUP mode. These pins go to the low level during a reset, i.e., when the RES pin is low. Output Input
PD0 PD1 PD2 PD3
22 21 20 19
Dedicated output port These are normal CMOS outputs. These pins go to the output high-impedance state in BACKUP mode. These pins go to the low level during a reset, i.e., when the RES pin is low.
I/O port PE0 PE1 PE2 PE3 18 17 16 15 These pins are switched between input and output as follows. Once an input instruction (IN, TPT, or TPF) is executed, these pins latch in the input mode. Once an output instruction (OUT, SPB, or RPB) is executed, they latch in the output mode. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACKUP mode these pins go to the input mode with input disabled. I/O I/O port PF0 PF1 PF2 PF3 14 13 12 11 These pins are switched between input and output by the FPC instruction. The I/O states of this port can be specified for individual pins. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACKUP mode these pins go to the input mode with input disabled. Data I/O PE0: D0 PE1: D1 PE2: D2 PE3: D3 PF0: D4 PF1: D5 PF2: D6 PF3: D7
PG0 PG1
6 5 Dedicated input port Input through these pins is disabled in BACKUP mode.
PROM control signal inputs PG0: CE PG1: OE Input
PG2 PG3
4 3
Continued on next page. No. 4742-5/16
LC72P32
Continued from preceding page.
Pin Pin No. Function I/O Circuit type PROM mode function
Dedicated output port PH0 PH1 PH2 PH3 10 9 8 7 Since these pins are high breakdown voltage n-channel transistor open-drain outputs, they can be effectively used for functions such as band power supply switching. Note that PH2 and PH3 also function as the DAC1 and DAC2 outputs. These pins go to the high impedance state during a reset, i.e., when the RES pin is low, and in BACKUP mode.
Output
Dedicated output port While these pins have a CMOS output circuit structure, they can be switched to function as LCD drivers. Their function is switched by the SS and RS instructions. These pins cannot be switched individually. The LCD driver function is selected and a segment off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACKUP mode. Note that when the general-purpose port use option is specified, these pins output the contents of IPORT when LPC is 1, and the contents of the general-purpose output port LATCH when LPC is 0. Output
PI0/S25 PI1/S26 PI2/S27 PI3/S28
39 38 37 36
Address input S1 to S14 63 to 50 LCD driver segment outputs A frame frequency of 100 Hz and a 1/2 duty, 1/2 bias drive type are used. A segment off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACKUP mode. S15 to S24 49 to 40 The use of these pins as general-purpose output ports can be specified as an option. Output I/O S: A0 to S14: A13
LCD driver common outputs COM1 COM2 65 64 A 1/2 duty, 1/2 bias drive type is used. The output when power is first applied or when RES is low is identical to the normal operating mode output. These pins are held at the low level in BACKUP mode. Output
FM VCO (local oscillator) input FMIN 74 The input must be capacitor-coupled. The input frequency range is from 10 to 130 MHz. AM VCO (local oscillator) input The input should be capacitor-coupled. AMIN 75 The band supported by this pin can be selected using the PLL instruction. High (2 to 40 MHz) SW Low (0.5 to 10 MHz) LW and MW Input
Continued on next page. No. 4742-6/16
LC72P32
Continued from preceding page.
Pin Pin No. Universal counter input The input should be capacitor-coupled. HCTR 70 The input frequency range is from 0.4 to 12 MHz. This input can be effectively used for FM IF or AM IF counting. Universal counter input The input should be capacitor-coupled for input frequencies in the range 100 to 150 kHz. Capacitor coupling is not required for input frequencies from 1 to 20 Hz. This input can be effectively used for AM IF counting. Input Function I/O Circuit type PROM mode function
LCTR
71
A/D converter input ADI 69 A 1.28 ms period is required for a 6-bit sequential comparison conversion. The full scale input is ((63/96) * VDD) for a data value of 3FH. Input
Interrupt request input INT 66 An interrupt is generated when the INTEN flag is set (by an SS instruction) and a falling edge is input. Input
EO1 EO2
77 78
Reference frequency and programmable divisor phase comparison error outputs Charge pump circuits are built in. EO1 and EO2 are the same. Output
SNS
72
Input pin used to determine if a power outage has occurred in BACK UP mode This pin can also be used as a normal input port.
Input
Input pin used to force the LC72E32 to HOLD mode HOLD 67 The LC72E32 goes to HOLD mode when the HOLDEN flag is set (by an SS instruction) and the HOLD input goes low. A high breakdown voltage circuit is used so that this input can be used in conjunction with the normal power switch. Input
System reset input RES 68 This signal should be held low for 75 ms after power is first applied to effect a power-up reset. The reset starts when a low level has been input for at least six reference clock cycles. Input
XIN XOUT
1 80
Crystal oscillator connections (4.5 MHz) A feedback resistor is built in.
Input Output
TEST1 TEST2
79 2
LSI test pins. These pins must be connected to VSS. Programming voltage Vpp
VDD VSS
31, 73
Power supply + connections. Both pins must be connected.
76
Power supply - connection.
No. 4742-7/16
LC72P32 Option
No. 1 Description WDT (watchdog timer) inclusion selection Selections WDT included No WDT Pull-down resistors included No pull-down resistors 2.67 s 3 Cycle time selection 13.33 s 40.00 s 4 LCD port/general-purpose port selection LCD ports General-purpose output ports
2
Port A pull-down resistor inclusion selection
Usage Notes The LC72P32 is provided for use in early production runs of products designed for the LC7232N. Please keep the following points in mind when using this product. 1. Differences between the LC72P32 and the LC7232N
Parameter Operating temperature (Topr) Operation immediately following power on Input type of the A port immediately following power on* Output type of the S1 to S28 outputs immediately following power on* Power-down detection voltage (VDET) IDD2 -30 to +70 C After the 75 ms power-on reset period, the LSI internal option settings are set up during a period of about 1 ms. After that operation completes, program execution starts with the program counter set to location 0. No pull-down resistors LC72P32 -40 to +85C After the 75 ms power-on reset period, program execution starts with the program counter set to location 0. Pull-down resistors are included or not according to the option specifications. These pins function as either LCD ports or generalpurpose output ports according to the option specifications. Minimum: 2.7 V Typical: 3.0 V Maximum: 3.3 V Conditions: VDD2, PLL stopped CT = 2.67 s (HOLD mode, Figure 1) Typical: 1.5 mA Conditions: VDD2, PLL stopped CT = 13.33 s (HOLD mode, Figure 1) Typical: 1.0 mA Conditions: VDD2, PLL stopped CT = 40.00 s (HOLD mode, Figure 1) Typical: 0.7 mA These are LSI test pins and must be either left open or connected to VSS. Conditions: CPU operating Minimum: 3.5 V LC7232N
LCD ports Minimum: 3.0 V Typical 3.5 V Maximum: 4.0 V Conditions: VDD = 5.0 V, PLL stopped CT = 2.67 s (HOLD mode, Figure 1) Typical: 2.7 mA Conditions: VDD = 5.0 V, PLL stopped CT = 13.33 s (HOLD mode, Figure 1) Typical: 1.7 mA Conditions: VDD = 5.0 V, PLL stopped CT = 40.00 s (HOLD mode, Figure 1) Typical: 1.5 mA These are LSI test pins and must be connected to VSS. Conditions: CPU operating Minimum: 4.0 V
Current drain
IDD3
IDD4
The TEST1 and TEST2 pins Supply voltage VDD2
Note: * This refers to the option setup time of about 1 ms that occurs following the period of about 75 ms from power application.
2. PLA and options The LC72P32 uses locations 2000H to 201FH as program memory for PLA pattern specification, and locations 2020H to 2033H for option specification. This option specification allows the LC72P32 to support option setups identical to those available with the LC7232N.
No. 4742-8/16
LC72P32 * LC72P32 Option Types
Symbol WDT Option Type WDT (watchdog timer) inclusion selection Selections WDT included No WDT Pull-down resistors included No pull-down resistors 2.67 s CTIM Cycle time selection 13.33 s 40.00 s LCDP LCD port/general-purpose port selection LCD ports General-purpose output ports
APPDN
A port pull-down resistor inclusion selection
Note that these options are not determined until the option setting period of about 1 ms, which follows a period of about 75 ms from power application, has passed. 3. Use of the mass-produced unit printed circuit board When using the printed circuit board for the massed produced end product with the LC72P32, be sure to connect the TEST1 and TEST2 pins to VSS and be sure to connect both pins 31 and 73 (the VDD pins) to the plus side of the power supply. 4. PROM address space
5. Notes on ordering ROM when using Sanyo's (for fee) PROM writing service * When ordering one-time programmable and mask ROM versions at the same time The customer must provide a PROM to which the mask ROM version program and option data have been written. The customer must also provide ordering forms for both the mask ROM version and one-time programmable version products. * When ordering only one-time programmable versions The customer must provide a PROM to which the one-time programmable version program and option data have been written. The customer must also provide ordering forms for the one-time programmable version product.
No. 4742-9/16
LC72P32 6. Conditions prior to mounting * Use the procedure below for mounting unwritten PROM products.
* When Sanyo's (for fee) PROM writing service is used
Note: Due to the structure of microcontrollers with built-in one-time programmable PROM (unwritten PROM products), complete testing prior to shipment is not possible. Thus there are cases where the writing yield may be lower.
Usage Techniques 1. Writing the built-in PROM The following two techniques can be used to write the LC72P32's built-in PROM. * Using a general-purpose EPROM programmer If a general-purpose EPROM programmer is used, the built-in PROM can be written by using a dedicated writing adapter available from Sanyo (product name: LC72E32 ADAPTER FOR EPROM PROGRAMMER). Note that the 27512 (Vpp = 12.5 V) Intel fast writing method should be used, and the address range should be set to locations 0 to 2033H. * Using the RE32 in-circuit emulator If the RE32 in-circuit emulator is used, the built-in PROM can be written by using a dedicated writing adapter available from Sanyo (product name: LC72E32 ADAPTER FOR RE32). Use the PGOTP command to write data to the PROM.
No. 4742-10/16
LC72P32 2. Dedicated writing adapter There are two writing adapters available for use with the LC72P32. These adapters are not interchangeable and each adapter must be used only for its intended purpose.
Note: The two writing adapters have essentially identical external appearances. General-purpose EPROM programmer adapter: Product name: LC72E32 Adapter for EPROM Programmer Product code: NDK-DC-001-A RE32 in-circuit emulator adapter: Product name: LC72E32 Adapter for RE32 Product code: NDK-DC-003-A
No. 4742-11/16
LC72P32 Pin Assignment
No. 4742-12/16
LC72P32 Block Diagram
No. 4742-13/16
LC72P32 LC72P32 Instruction Table Abbreviations: ADDR: Program memory address [12 bits] b: Borrow B: Bank number [2 bits] C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank 0) Rn: Register number [4 bits] ( ): Contents of register or memory ( )n: Contents of bit N of register or memory
Instruction Group Operand Mnemonic 1st AD ADS Addition instructions AC ACS AI AIS AIC AICS SU SUS SB r r r r M M M M r r r 2nd M M M M I I I I M M M Add M to r Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equals M Skip if r is greater than or equal to M Skip if M equal to I Skip if M is greater than or equal to I r (r) + (M) r (r) + (M) skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I skip if carry M (M) + I + C M (M) + I + C skip if carry r (r) - (M) r (r) - (M) skip if borrow r (r) - (M) - b r (r) - (M) - b skip if borrow M (M) - I M (M) - I skip if borrow M (M) - I - b M (M) - I - b skip if borrow r-M skip if zero r-M skip if not borrow (r) (M) M-I skip if zero M-I skip if not borrow (M) I Function Operation D15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 DH DH DH DH DH DH DH DH DH DH DH 7654 DL DL DL DL DL DL DL DL DL DL DL 3 2 1 D0 Rn Rn Rn Rn I I I I Rn Rn Rn Machine code
Subtraction instructions
SBS SI SIS SIB
r M M M
M I I I
0 0 0 0
1 1 1 1
1 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
DH DH DH DH
DL DL DL DL
Rn I I I
SIBS
M
I
0
1
1
1
1
1
DH
DL
I
Comparison instructions
SEQ
r
M
0
0
0
0
0
1
DH
DL
Rn
SGE
r
M
0
0
0
0
1
1
DH
DL
Rn
SEQI
M
I
0
0
1
1
0
1
DH
DL
I
SGEI
M
I
0
0
1
1
1
1
DH
DL
I
Continued on next page. No. 4742-14/16
LC72P32
Continued from preceding page.
Instruction Group Operand Mnemonic 1st AND OR EXL LD ST Transfer instructions MVRD M M r r M r 2nd I I M M r M AND I with M OR I with M Exclusive OR M with r Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Load M to PLL registers Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt N Test timer F/F then skip if it has not been set Test unlock F/F then skip if it has not been set Set status register Reset status register Test status register true Test status register false M (M) M (M) r (r) r (M) M (r) [DH, Rn] (M) I I (M) Function Operation D15 14 13 12 11 10 9 8 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 DH DH DH DH DH DH 7654 DL DL DL DL DL DL 3 2 1 D0 I I Rn Rn Rn Rn Machine code
Logical operation instructions
MVRS
M
r
M [DH, Rn] [DH, DL1] [DH, DL2] MI PLL r PLL DATA if M (N) = all "1", then skip if M (N) = all "0", then skip PC ADDR PC ADDR Stack (PC) + I PC Stack PC Stack if timer F/F = "0", then skip if UL F/F = "0", then skip (Status register 1) N1 (Status register 1) N0 if (Status register 2) N = all "1", then skip if (Status register 2) N = all "0", then skip
1
0
0
0
1
1
DH
DL
Rn
MVSR MVI PLL
M1 M M
M2 I r
1 1 1
0 0 0
0 0 0
1 1 1
0 0 1
0 1 0
DH DH DH
DL1 DL DL
DL2 I Rn
Bit test instructions
TMT
M
N
1
0
1
0
0
1
DH
DL
N
TMF JMP CAL RT RTI TTM
M
N
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 0 0
0 1 0 1 1 1
1
1
DH
DL ADDR (12 bits) ADDR (12 bits)
N
Jump and subroutine call instructions
ADDR ADDR
0 0 0
1 1 1
00 01 10
0000 0000 0000
000 000 N
0 0
F/F test instructions
TUL
N
1
1
0
1
0
1
11
0000
N
Status register instructions
SS RS TST TSF
N N N N
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
00 01 10 11
0000 0000 0000 0000
N N N N
Bank switching instructions
BANK
B
Select bank
BANK B
1
1
0
1
0
0
B
0000
000
0
Continued on next page. No. 4742-15/16
LC72P32
Continued from preceding page.
Instruction Group Operand Mnemonic 1st LCD LCP I/O instructions IN OUT SPB RPB TPT M M M M P P P 2nd I I P P N N N Output segment pattern to LCD digit direct Output segment pattern to LCD digit through PLA Input port data to M Output contents of M to port Set port bits Reset port bits Test port bits, then skip if all bits specified are true Test port bits, then skip if all bits specified are false Set I to UCCW1 LCD (DIGIT) M LCD (DIGIT) PLA M M (Port (P)) (Port (P)) M (Port (P)) N 1 (Port (P)) N 0 if (Port (P)) N = all "1", then skip if (Port (P)) N = all "0", then skip Function Operation D15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DH DH DH DH 00 01 10 7654 DL DL DL DL P P P 3 2 1 D0 DIGIT DIGIT P P N N N Machine code
TPF Universal counter instructions
P
N
1
1
1
1
1
1
11
P
N
UCS
I
UCCW1 I
0
0
0
0
0
0
01
0000
I
UCC FPC CKSTP DAC NOP
I N
Set I to UCCW2 F port I/O control Clock stop
UCCW2 I FPC latch N Stop clock if HOLD = 0 DAreg DAC DATA
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 1 1 0 0
0 0 0 0 0
0 0 0 0 0
11 00 01 10 00
0000 0000 0000 0000 0000
I N 000 I 000 0 0
Other instructions
I
Load M to D/A registers No operation
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. PS. No. 4742-16/16

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