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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
PM7390
CONFIGURING THE PM7390 S/UNI MACH 48
PRELIMINARY ISSUE 2: FEBRUARY 2001
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
PUBLIC REVISION HISTORY Issue No. 1 2 Issue Date Oct 2000 Jan 2001 Details of Change Document Created 1. Added Section 7: "TCL Code examples". 2. Section 6.1.11, Table 42: Change RCAS/TCAS Enable to all timeslots per the data sheet 3. Tables 34, 35, 36, 41, 54, 55, 56, 57, 92, 93,94,96 97: Changed headings from UL3/PL3 to ATM/POS to clarify functions. 4. Table 94 and Table 96: Corrected entries for POS and ATM traffic 5. Section 5.10: Added note that SIRP must be enabled for correct operation of the device 6. Section 6.3.5: Modified STS-1 example SDQ block pointer configuration to allow for dynamic reconfiguration to STS-3c. 7. Section 6.4.5: Modified SDQ block pointer configuration to allow for dynamic reconfiguration to STS-3c. 8. Section 6.4.6, Table 94: Corrected DS3 HDLC entries for offset 02 to 0x403 from 0x402 to allow bit swapping which is required for bit synchronous HDLC. 9. Section 6.4.7, Table 96: Corrected DS3 HDLC entries for offset 03 to 0x7 from 0x3 to allow bit swapping which is required for bit synchronous HDLC. 10. Added Section 5.7.1: "FIFO Arrangement in the SDQs"
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
CONTENTS 1 2 3 4 5 DEFINITIONS .......................................................................................... 1 SCOPE .................................................................................................... 2 OVERVIEW.............................................................................................. 3 REFERENCES......................................................................................... 4 REGISTER SETUP.................................................................................. 5 5.1 WRITING AND READING INDIRECT REGISTERS ..................... 6 5.1.1 WRITING INDIRECT REGISTERS .................................... 6 5.1.2 READING INDIRECT REGISTERS.................................... 6 5.2 5.3 5.4 5.5 5.6 5.7 VALID CHANNEL ASSIGNMENTS ............................................... 6 CONFIGURATION REGISTER ..................................................... 9 TIMESLOT CONFIGURATION.................................................... 10 SERIAL TELECOMBUS ...............................................................11 RXPHY AND TXPHY SETUP ...................................................... 13 SCALABLE DATA QUEUE (SDQ) ............................................... 14 5.7.1 FIFO ARRANGEMENT IN THE SDQS ............................. 15 5.7.2 DATA/BUFFER AVAILABLE THRESHOLD ...................... 16 5.8 5.9 5.10 5.11 5.12 6 RECEIVE CELL AND FRAME PROCESSOR (RCFP + RTDP) .. 17 TRANSMIT CELL AND FRAME PROCESSOR (TCFP + TTDP) 19 SONET/SDH INBAND ERROR REPORT PROCESSOR ........... 21 RECEIVE CHANNEL ASSIGNER (RCAS).................................. 22 TRANSMIT CHANNEL ASSIGNER (TCAS)................................ 23
EXAMPLES............................................................................................ 24
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
6.1
EXAMPLE 1: SINGLE PHY, STS-48C......................................... 24 6.1.1 SET CONFIGURATION REGISTER................................. 25 6.1.2 SET TIMESLOT AND DELAY REGISTERS (STS-48C) ... 25 6.1.3 SET SERIAL TELECOMBUS REGISTERS...................... 25 6.1.4 RXPHY CALENDAR (STS-48C/STM-16C) ...................... 27 6.1.5 SCALABLE DATA QUEUE (STS48C/STM-16C) .............. 27 6.1.6 RECEIVE CELL AND FRAME PROCESSOR (STS48C) . 28 6.1.7 TRANSMIT CELL AND FRAME PROCESSOR (STS48C)28 6.1.8 RECEIVE CHANNEL ASSIGNER (STS48C).................... 29 6.1.9 TRANSMIT CHANNEL ASSIGNER (STS48C/STM-16C). 30 6.1.10 SONET/SDH INBAND ERROR REPORT PROCESSOR. 30 6.1.11 ENABLE BLOCKS (STS48C/STM-16C)........................... 30
6.2
EXAMPLE 2: 16 X STS-3C CHANNELS..................................... 32 6.2.1 SET CONFIGURATION REGISTER................................. 33 6.2.2 SET TIMESLOT AND DELAY REGISTERS (16 X STS-3C) .......................................................................................... 33 6.2.3 SET SERIAL TELECOMBUS REGISTERS (STS-3C)...... 34 6.2.4 SET UP RXPHY CALENDAR (16 X STS-3C)................... 34 6.2.5 SCALABLE DATA QUEUE (16 X STS-3C) ....................... 35 6.2.6 RECEIVE TIMESLICE DATACOM PROCESSOR............ 37 6.2.7 TRANSMIT TIMESLICE DATACOM PROCESSOR ......... 38 6.2.8 RECEIVE CHANNEL ASSIGNER (16 X STS-3C) ............ 39 6.2.9 TRANSMIT CHANNEL ASSIGNER (16 X STS-3C).......... 40 6.2.10 SONET/SDH INBAND ERROR PROCESSOR (16 X STS3C).................................................................................... 41
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CONFIGURING THE PM7390 S/UNI MACH48
6.2.11 ENABLE BLOCKS (16 X STS-3C) ................................... 42 6.3 EXAMPLE 3: 48 X STS-1............................................................ 43 6.3.1 SET CONFIGURATION REGISTER................................. 44 6.3.2 SET TIMESLOT AND DELAY REGISTERS (48 X STS-1) 44 6.3.3 SET SERIAL TELECOMBUS REGISTERS...................... 45 6.3.4 SET UP RXPHY CALENDAR ........................................... 45 6.3.5 SCALABLE DATA QUEUE (48 X STS-1).......................... 46 6.3.6 RECEIVE TIMESLICE DATACOM PROCESSOR............ 49 6.3.7 TRANSMIT TIMESLICE DATACOM PROCESSOR ......... 50 6.3.8 RECEIVE CHANNEL ASSIGNER..................................... 50 6.3.9 TRANSMIT CHANNEL ASSIGNER .................................. 51 6.3.10 SONET/SDH INBAND ERROR PROCESSOR (48 X STS-1)52 6.3.11 ENABLE BLOCKS (48 X STS-1) ...................................... 53 6.4 EXAMPLE 4: 25 PHYS/ MIXED RATE ....................................... 54 6.4.1 SET CONFIGURATION REGISTER................................. 55 6.4.2 SET TIMESLOT AND DELAY REGISTERS (MIXED)....... 55 6.4.3 SET SERIAL TELECOMBUS REGISTERS...................... 56 6.4.4 SET UP RXPHY CALENDAR (MIXED RATE) .................. 56 6.4.5 SET UP SDQ (MIXED RATE) ........................................... 57 6.4.6 RECEIVE CELL AND FRAME PROCESSOR .................. 59 6.4.7 TRANSMIT CELL AND FRAME PROCESSOR................ 60 6.4.8 RECEIVE CHANNEL ASSIGNER..................................... 62 6.4.9 TRANSMIT CHANNEL ASSIGNER .................................. 65 6.4.10 DS-3 SETUP .................................................................... 67
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
6.4.11 SONET/SDH INBAND ERROR PROCESSOR (MIXED RATE) ............................................................................... 68 6.4.12 ENABLE BLOCKS (MIXED RATE)................................... 70 7 TCL EXAMPLE CODE ........................................................................... 71 7.1 7.2 7.3 7.4 GENERAL TCL PROCEDURES ................................................. 71 EXAMPLE 1: 1 X STS-48C ATM PL3.......................................... 75 EXAMPLE 2: 16 X STS-3C ATM PL3.......................................... 79 EXAMPLE 3: 48 X STS-1 ATM PL3 ............................................ 86
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
LIST OF FIGURES FIGURE 1 - BANK 0 SDQ FIFO ARRANGEMENT ......................................... 15 FIGURE 2 - MACH48 STS-48C EXAMPLE..................................................... 24 FIGURE 3 - MACH48 STS-3C EXAMPLE....................................................... 32 FIGURE 4 - MACH48 STS-1 EXAMPLE ......................................................... 43 FIGURE 5 - MIXED RATE EXAMPLE ............................................................. 54
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 S/UNI MACH48 LEGAL CHANNEL MAPPINGS.............................. 7 CONFIGURATION REGISTER........................................................ 9 TIMESLOT CONFIGURATION REGISTERS................................. 10 T8TE + R8TD BASE ADDRESSES ................................................11 T8TE REGISTERS .........................................................................11 R8TD REGISTERS........................................................................ 12 RXPHY REGISTERS ..................................................................... 13 TXPHY REGISTERS ..................................................................... 13 RXSDQ REGISTERS..................................................................... 14
TABLE 10 TXSDQ REGISTERS ..................................................................... 14 TABLE 11 RXSDQ DT SETTINGS PER FIFO ................................................ 16 TABLE 12 TXSDQ BT/DT SETTINGS PER FIFO........................................... 16 TABLE 13 RCFP + RTDP BASE ADDRESSES .............................................. 17 TABLE 14 RTDP REGISTERS........................................................................ 17 TABLE 15 RCFP REGISTERS........................................................................ 17 TABLE 16 TCFP + TDFP BASE ADDRESSES............................................... 19 TABLE 17 TCFP REGISTERS ........................................................................ 19 TABLE 18 TTDP REGISTERS ........................................................................ 20 TABLE 19 SIRP BASE ADDRESSES ............................................................. 21 TABLE 20 SIRP REGISTERS ......................................................................... 21 TABLE 21 RCAS BASE ADDRESSES............................................................ 22 TABLE 22 RCAS REGISTERS ...................................................................... 22
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
TABLE 23 TCAS BASE ADDRESSES ............................................................ 23 TABLE 24 TCAS REGISTERS........................................................................ 23 TABLE 25 CONFIG REGISTER (STS-48C), S-TCB....................................... 25 TABLE 26 CONFIG REGISTER (STS-48C), DLOOP ..................................... 25 TABLE 27 RX S-TCB SYNCHRONIZATION DELAY ...................................... 25 TABLE 28 MISCELLANEOUS REGISTER 0012H.......................................... 25 TABLE 29 S-TCB REGISTER SETUP ............................................................ 26 TABLE 30 R8TDX ANALOG CONTROL SETTING (REV1)............................ 26 TABLE 31 S-TCB DIAGNOSTIC LOOPBACK ................................................ 26 TABLE 32 CALENDAR LENGTH VALUE (1 X STS-48C) ............................... 27 TABLE 33 EXAMPLE SDQ ENTRY SETUP FOR PHYID 0(STS-48C)........... 27 TABLE 34 SDQ REGISTER SETUP (STS-48C)............................................. 28 TABLE 35 RCFP0 REGISTER (STS-48C)...................................................... 28 TABLE 36 TCFP0 REGISTER (STS-48C) ...................................................... 29 TABLE 37 RCAS REGISTER SETUP (STS-48C)........................................... 29 TABLE 38 RCAS LOOPBACK (STS-48C) ...................................................... 29 TABLE 39 TCAS REGISTER SETUP (STS-48C) ........................................... 30 TABLE 40 STS-48C SIRP SETUP .................................................................. 30 TABLE 41 PROVISIONING RCFP/TCFP BLOCKS ........................................ 30 TABLE 42 ENABLING RCAS/TCAS BLOCKS................................................ 31 TABLE 43 ENABLING RXSDQ/TXSDQ BLOCKS .......................................... 31 TABLE 44 ENABLING RXPHY/TXPHY BLOCKS ........................................... 31 TABLE 45 CONFIG REGISTER (16 X STS-3C), S-TCB ................................ 33 TABLE 46 CONFIG REGISTER (16 X STS-3C), DLOOP............................... 33
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
TABLE 47 TIMESLOT REGISTERS (16 X STS-3C)....................................... 33 TABLE 48 RX S-TCB SYNCHRONIZATION DELAY ...................................... 33 TABLE 49 MISCELLANEOUS REGISTER 0012H.......................................... 33 TABLE 50 CALENDAR REGISTER VALUES (16 X STS-3C)......................... 34 TABLE 51 RXPHY CALENDAR (16 X STS-3C).............................................. 34 TABLE 52 FIFO SETUP (16 X STS-3C) ......................................................... 35 TABLE 53 EXAMPLE SDQ ENTRY SETUP FOR PHYID 14(16 X STS-3C)... 36 TABLE 54 SDQ REGISTER SETUP FOR PHYID 14 STS-3C ENTRY........... 37 TABLE 55 RTDP REGISTER SETUP (16 X STS-3C)..................................... 37 TABLE 56 TTDP REGISTER SETUP (16 X STS-3C) ..................................... 38 TABLE 57 TTDP REGISTER SETUP FOR PHYID 26 STS-3C ENTRY ......... 39 TABLE 58 RCAS REGISTER SETUP (16 X STS-3C) .................................... 40 TABLE 59 RCAS LOOPBACK SETTINGS (16 X STS-3C)............................. 40 TABLE 60 TCAS CONFIGURATION REGISTERS (16 X STS-3C) ................ 40 TABLE 61 - 16 X STS-3C SIRP CONFIGURATION........................................ 41 TABLE 62 ENABLING RCAS/TCAS BLOCKS................................................ 42 TABLE 63 ENABLING RXSDQ/TXSDQ BLOCKS .......................................... 42 TABLE 64 ENABLING RXPHY/TXPHY BLOCKS ........................................... 42 TABLE 65 CONFIG REGISTER (48 X STS-1), S-TCB ................................... 44 TABLE 66 CONFIG REGISTER (48 X STS-1), DLOOP ................................. 44 TABLE 67 TIMESLOT REGISTERS (48 X STS-1) ......................................... 44 TABLE 68 RX S-TCB SYNCHRONIZATION DELAY ...................................... 44 TABLE 69 MISCELLANEOUS REGISTER 0012H.......................................... 44 TABLE 70 CALENDAR LENGTH REGISTER (48 X STS-1)........................... 45
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
TABLE 71 - RXPHY CALENDAR SETUP (48 X STS-1) ................................. 45 TABLE 72 48 X STS-1 FIFO SETUP .............................................................. 46 TABLE 73 - EXAMPLE SDQ ENTRY SETUP FOR PHYID 36(48 X STS-1) ... 48 TABLE 74 SDQ REGISTER SETUP FOR PHYID 36 STS-1 ENTRY ............. 48 TABLE 75 RTDP REGISTER SETUP (48 X STS-1) ....................................... 49 TABLE 76 RCAS REGISTER SETUP (48 X STS-1)....................................... 51 TABLE 77 RCAS BASE REGISTER VALUES FOR LOOPBACK(48 X STS-1)51 TABLE 78 TCAS CONFIGURATION REGISTERS (48 X STS-1) ................... 52 TABLE 79 - 48 X STS-1 SIRP CONFIGURATION .......................................... 52 TABLE 80 ENABLING RCAS/TCAS BLOCKS................................................ 53 TABLE 81 ENABLING RXSDQ/TXSDQ BLOCKS .......................................... 53 TABLE 82 ENABLING RXPHY/TXPHY BLOCKS ........................................... 53 TABLE 83 CONFIG REGISTER (MIXED RATE), S-TCB ................................ 55 TABLE 84 CONFIG REGISTER (MIXED RATE), DLOOP .............................. 55 TABLE 85 MIXED RATE TIMESLOT REGISTERS......................................... 55 TABLE 86 RX S-TCB SYNCHRONIZATION DELAY ...................................... 56 TABLE 87 MISCELLANEOUS REGISTER 0012H.......................................... 56 TABLE 88 CALENDAR LENGTH REGISTER (MIXED RATE)........................ 56 TABLE 89 RXPHY CALENDAR SETUP (MIXED RATE) ................................ 56 TABLE 90 25 X MIXED RATE EXAMPLE FIFO SETUP ................................. 57 TABLE 91 EXAMPLE SDQ ENTRY SETUP FOR PHYID 12 (STS-12C)........ 58 TABLE 92 SDQ REGISTER SETUP FOR PHYID 12 STS-12C ENTRY......... 59 TABLE 93 RCFP1 REGISTER (STS-12C)...................................................... 59 TABLE 94 RTDP REGISTER SETUP (6 X STS-3C, 9 X STS-1, 9 X DS3)..... 59
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
TABLE 95 TCFP REGISTER SETUP (MIXED RATE) .................................... 60 TABLE 96 TTDP REGISTER SETUP (MIXED RATE) .................................... 61 TABLE 97 TTDP REGISTER SETUP FOR PHYID 37 STS-1 ENTRY............ 62 TABLE 98 RCAS0 REGISTER SETUP........................................................... 62 TABLE 99 RCAS1 REGISTER SETUP........................................................... 62 TABLE 100 RCAS2 REGISTER SETUP........................................................... 63 TABLE 101 RCAS3 REGISTER SETUP........................................................... 64 TABLE 102 SETTINGS FOR LOOPBACK........................................................ 64 TABLE 103 TCAS0 REGISTER SETUP ........................................................... 65 TABLE 104 TCAS1 REGISTER SETUP ........................................................... 65 TABLE 105 TCAS2 REGISTER SETUP ........................................................... 66 TABLE 106 TCAS3 REGISTER SETUP ........................................................... 66 TABLE 107 DS-3 CHANNEL ARRANGEMENT................................................ 67 TABLE 108 DS-3 REGISTER SETUP .............................................................. 67 TABLE 109 DS3 PLCP REGISTER SETUP ..................................................... 67 TABLE 110 - MIXED RATE SIRP1 SETUP....................................................... 68 TABLE 111 - MIXED RATE SIRP2 SETUP....................................................... 68 TABLE 112 - MIXED RATE SIRP3 SETUP....................................................... 68 TABLE 113 - MIXED RATE SIRP4 SETUP....................................................... 69 TABLE 114 ENABLING RCAS/TCAS BLOCKS................................................ 70 TABLE 115 ENABLING RXSDQ/TXSDQ BLOCKS .......................................... 70 TABLE 116 ENABLING RXPHY/TXPHY BLOCKS ........................................... 70
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
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DEFINITIONS RCAS TCAS RXPHY TXPHY RXSDQ TXSDQ RCFP TCFP RTDP TTDP T8TE R8TD SPLR SPLT Receive Channel Assigner Transmit Channel Assigner Receive UL3/PL3 Physical Layer Interface Transmit UL3/PL3 Physical Layer Interface Receive Scalable Data Queue Transmit Scalable Data Queue Receive Cell and Frame Processor (STS-12c/STS-48c) Transmit Cell and Frame Processor (STS-12c/STS-48c) Receive Timeslice Datacom Processor (STS-3c/STS-1/DS-3) Transmit Timeslice Datacom Processor (STS-3c/STS-1/DS-3) Transmit 8B/10B Telecombus Encoder Receive 8B/10B Telecombus Decoder SMDS PLCP Layer Receiver SMDS PLCP Layer Transmitter
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
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SCOPE This document is intended as an introductory guide for hardware engineers to configure the S/UNI MACH48 device on a register access level.
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OVERVIEW The S/UNI MACH48 is an ATM and packet processor capable of processing data streams from STS-48/STM-16 with STS-1/STM-0/DS3 granularity for a total aggregate bandwidth of 2.488 Gbps. From the line side, the Serial (S-TCB) or Parallel Telecombus (P-TCB) interface takes SONET/SDH framed data and extracts ATM cells or POS packets for transmission onto a UL3/PL3 bus. The MACH48 can extract any combination of cells and packets. Towards the line side, the MACH48 maps cells and packets received from the UL3/PL3 bus into SONET/SDH frames. The SONET/SDH frames are then transmitted via the Parallel or Serial Telecombus. This document outlines several basic setup examples involving channels of various bandwidths using either ATM or POS traffic. The following combinations are illustrated: * * * * 1 PHY: 16 PHYS: 48 PHYS: 25 PHYS: 9 x DS3 1 x STS-48c/STM16 x STS-3c/STM-1 48 x STS-1/STM-0 1 x STS-12c/STM-4, 6 x STS-3c/STM-1, 9 x STS-1/STM-0,
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
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REFERENCES 1. PMC-1990823, S/UNI MACH48 Data Sheet Issue 3, May 2000.
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
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REGISTER SETUP The MACH48 can be set up in the following order: * * * * * * * * * * Configuration Register Timeslot Configuration Telecombus RXPHY Calendar Scalable Data Queue (SDQ) Receive Cell and Frame Processor (RCFP + RTDP) Transmit Cell and Frame Processor (TCFP + TTDP) SONET/SDH Inband Error Report Processor(SIRP) Receive Channel Assigner (RCAS) Transmit Channel Assigner (TCAS)
The following sections highlight registers of interest with specific reference to a particular setup configuration. Not all registers are necessarily listed.
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
5.1
Writing and Reading Indirect Registers
5.1.1 Writing Indirect Registers Several blocks in the S/UNI MACH48 use indirect registers. The algorithm for writing to an indirect register is illustrated below: 1. 2. 3. Poll the BUSY bit that is in the Indirect Address register that is to be written until it reads 0. Write the appropriate indirect data and/or indirect configuration registers Write the Indirect Register Address last with the RWB bit set to 0. This will initiate the write to that specific PHYID.
5.1.2 Reading Indirect Registers To initiate a read from an indirect register, do the following: 1. 2. 3. Write the Indirect Address Register with the desired PHYID and the RWB bit set to 1. This will initiate the read. Poll the BUSY bit that is in the base address of the register that is to be written until it reads 0. Read the appropriate indirect data and/or indirect configuration registers.
Note: The indirect data and configuration registers should not be read except during a indirect read as they will be indeterminate values.
5.2
Valid Channel Assignments The S/UNI MACH48 can service up to 48 PHYs of different bandwidths for a total of 2.488Gbps. The granularity of the channelization is STS-1/STM-0. Though the data streams can be channelized into virtually any combination of bandwidths, certain guidelines must be followed to ensure correct operation of the device. Specified channel assignments require specific FIFO and timeslot associations. The table below shows the different legal channel mappings. The three righmost columns are associated with example 4 in this document. Items in bold indicate the valid mappings for that example. Note that in the example, no lower bandwidth channel occupies a timeslot that is used by a higher
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
bandwidth channel (e.g. STS-3c E and F must occupy timeslots 0,4,8 and 2,6,10 respectively while the other STS-1/DS-3 channels may occupy the timeslots that remain). Table 1
Channel PHYID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
S/UNI MACH48 Legal Channel Mappings
STS-48c STM-16c a a a a a a a a a a a a a a a a a a a a a a a a a a a a STS-12c STM-4c a a a a a a a a a a a a b b b b b b b b b b b b c c c c STS-3c STM-1 a b c d a b c d a b c d e f g h e f g h e f g h I j k l STS-1 STM-0/ DS3 a b c d e f g h I j k l m n o p q r s t u v w x y z aa ab Mixed Example STS-3c A STS-3c B STS-3c C STS-3c D STS-3c A STS-3c B STS-3c C STS-3c D STS-3c A STS-3c B STS-3c C STS-3c D STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A STS-12c A DS-3 A DS-3 B STS-1 A STS-1 B FIFO NUM 0 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 21 22 23 24 25 26 27 32 33 34 35 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 Timeslot
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
Channel PHYID 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
STS-48c STM-16c a a a a a a a a a a a a a a a a a a a a
STS-12c STM-4c c c c c c c c c d d d d d d d d d d d d
STS-3c STM-1 I j k l I j k l m n o p m n o p m n o p
STS-1 STM-0/ DS3 ac ad ae af ag ah ai aj ak al am an ao ap aq ar as at au av
Mixed Example STS-1 C DS-3 C DS-3 D STS-1 D DS-3 E STS-1 E DS-3 F STS-1 F STS-3c E STS-1 G STS-3c F DS-3 G STS-3c E STS-1 H STS-3c F DS-3 H STS-3c E STS-1 I STS-3c F DS-3 I
FIFO NUM 36 37 38 39 40 41 42 43 48 49 50 51 52 53 54 55 56 57 58 59
Timeslot
4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
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5.3
Configuration Register The Configuration register controls global reset and loopback functions. Table 2
0001h
Configuration Register
DESCRIPTION S/UNI MACH48 Master Reset, Configuration, and Global Digital Loopback
Register Address
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5.4
Timeslot Configuration These registers set up the system side timeslots. See Table 9 and 11 in the S/UNI MACH 48 Data Sheet for valid timeslot mappings. Table 3
0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh
Timeslot Configuration Registers
DESCRIPTION Receive Timeslot Configuration #1 Receive Timeslot Configuration #2 Receive Timeslot Configuration #3 Receive Timeslot Configuration #4 Receive Timeslot Configuration #5 Receive Timeslot Configuration #6 Transmit Timeslot Configuration #1 Transmit Timeslot Configuration #2 Transmit Timeslot Configuration #3 Transmit Timeslot Configuration #4 Transmit Timeslot Configuration #5 Transmit Timeslot Configuration #6
Register Address
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5.5
Serial Telecombus The Telecombus registers are only used when the line side Serial Telecombus is enabled. The base address for each Telecombus link is as follows: Table 4
1860h 1868h 1870h 1878h 1880h 1888h 1890h 1898h 1820h 1828h 1830h 1838h 1840h 1848h 1850h 1858h
T8TE + R8TD Base Addresses
LINK TWRK[1] TWRK[2] TWRK[3] TWRK[4] TPROT[1] TPROT[2] TPROT[3] TPROT[4] RWRK[1] RWRK[2] RWRK[3] RWRK[4] RPROT[1] RPROT[2] RPROT[3] RPROT[4]
Base Address(T8TE)
Table 5
T8TE+00h T8TE+01h T8TE+02h T8TE+03h T8TE+04h T8TE+05h T8TE+06h
T8TE Registers
DESCRIPTION T8TE Control and Status T8TE Interrupt Status T8TE Telecombus Mode #1 T8TE Telecombus Mode #2 T8TE Test Pattern T8TE Analog Control T8TE DTB Bus
Register Address
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Table 6
R8TD+00h R8TD +01h R8TD +02h R8TD +03h R8TD +04h
R8TD Registers
DESCRIPTION R8TD Control and Status Interrupt Status Line Code Violation Count Analog Control 1 Analog Control 2
Register Address
Note: Proper operation of the MACH48 device requires RT8D + 03h Analog Control 1 to be written with CC34h.
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5.6
RXPHY and TXPHY Setup The RXPHY and TXPHY registers can be used for the PL3 or UL3 Receive interface. In PL3 mode, the RXPHY registers are used to set up the calendar attributes and burst size. Table 7
0040h 0041h 0042h 0043h 0044h 0045h 0046h
RXPHY Registers
DESCRIPTION RXPHY Configuration RXPHY Interrupt Status RXPHY Interrupt Enable RXPHY Indirect Burst Size RXPHY Calendar Length RXPHY Calendar Indirect Address Data RXPHY Data Type Field
Register Address
Table 8
0048h 0049h 004Ah 004Bh
TXPHY Registers
DESCRIPTION TXPHY Configuration TXPHY Interrupt Status TXPHY Interrupt Enable TXPHY Data Type Field
Register Address
The TPAHOLD bit in the TXPHY register (0048h) is explained in section 15.8.2 of the S/UNI MACH48 Data Sheet. It is set to 0 for all of the examples except the 48 x STS-1 example.
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5.7
Scalable Data Queue (SDQ) The SDQ registers are used to set up Receive and Transmit SDQ attributes. Table 9
0050h 0051h 0053h 0054h 0055h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh
RXSDQ Registers
DESCRIPTION RXSDQ FIFO Reset RXSDQ FIFO Interrupt Enable RXSDQ FIFO Overflow Port and Interrupt Indication RXSDQ FIFO EOP Error Port and Interrupt Indication RXSDQ FIFO SOP Error Port and Interrupt Indication RXSDQ FIFO Indirect Address RXSDQ FIFO Indirect Configuration RXSDQ FIFO Indirect Data Available Threshold RXSDQ FIFO Indirect Cells and Packets Count RXSDQ FIFO Cells and Packets Accepted Aggregate Count (LSB) RXSDQ FIFO Cells and Packets Accepted Aggregate Count (MSB) RXSDQ FIFO Cells and Packets Dropped Aggregate Count
Register Address
Table 10
0060h 0061h 0063h 0064h 0065h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh
TXSDQ Registers
DESCRIPTION TXSDQ FIFO Reset TXSDQ FIFO Interrupt Enable TXSDQ FIFO Overflow Port and Interrupt Indication TXSDQ FIFO EOP Error Port and Interrupt Indication TXSDQ FIFO SOP Error Port and Interrupt Indication TXSDQ FIFO Indirect Address TXSDQ FIFO Indirect Configuration TXSDQ FIFO Indirect Data Available Threshold TXSDQ FIFO Indirect Cells and Packets Count TXSDQ FIFO Cells and Packets Accepted Aggregate Count (LSB) TXSDQ FIFO Cells and Packets Accepted Aggregate Count (MSB) TXSDQ FIFO Cells and Packets Dropped Aggregate Count
Register Address
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5.7.1 FIFO Arrangement in the SDQs The figure below shows the bank 0 SDQ that would service PHY 0 for STS-12c, PHYs 0-3 for STS-3c and PHYs 0 to 11 for STS-1. If the PHYs are to be dynamically reconfigured, then the FIFOs must arranged such that only those being reconfigured will be affected. A way to do this is to locate STS-1 FIFOs next to their corresponding members for a larger bandwidth FIFO. As an example, STS-3c channel (phyid) 0 is comprised of timeslots 1, 5 and 9 in STS12 stream 0. If these were STS-1 channels, they would correspond to channels 0, 4 and 8, respectively. When the STS-1 channels are aggregated into the STS-3c, the STS-1 FIFOs can be absorbed to create a single FIFO. In order to do this, the three STS-1 FIFOs must be located consecutively. Figure 1 - Bank 0 SDQ FIFO Arrangement
Bank 0 SDQ
BLK PTR BLK PTR BLK PTR 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 16 Block FIFO (STS-1/DS3) 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 PHY ID PHY ID PHY ID 0 4 8 0x06 1 5 9 192 Block FIFO (STS-48c/STS-12c) 2 48 Block FIFO (STS-3c) 0x0C 2 6 10 0x12 3 7 11
0
0x00
0 48 Block FIFO (STS-3c)
0x00
1 48 Block FIFO (STS-3c)
3 48 Block FIFO (STS-3c)
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5.7.2 Data/Buffer Available Threshold The Data Available Threshold and Buffer Available Threshold parameters are explained in Section 14.15 and 14.16 of the S/UNI MACH48 Data Sheet. The equation below outlines the criteria for setting BT and DT.
(DT[7..0] +1) + (BT[4..0] < FIFO SIZE
For the RXSDQ the DT setting is linked to the BURST SIZE with the following criteria.
(BT[4..0] +1) It is important to note that for UL3, DT[7..0], BT[4..0] and BURST SIZE are set to 0003h (4 blocks= 1 ATM cell) for all FIFO sizes. Table 11
Mode UL3
RXSDQ DT Settings per FIFO
Bandwidth STS-48c/STS-12c STS-3c STS-1 Fifo Size 192 48 16 192 48 16 DT(7..0) 3 3 3 95 23 7 BURST SIZE 3 3 3 3 3 3
PL3
STS-48c/STS-12c STS-3c STS-1
It is recommended that the DT setting for the TXSDQ be 1/2 to 2/3 the size of the FIFO. In the examples the values used are 1/2 the size of the FIFO when in PL3 mode. Table 12
Mode UL3
TXSDQ BT/DT Settings per FIFO
Bandwidth STS-48c/STS-12c STS-12c STS-1 Fifo Size 192 192 16 192 48 16 BT(4..0) 3 3 3 7 7 7 DT(7..0) 3 3 3 95 23 7
PL3
STS-48c/STS-12c STS-3c STS-1
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5.8
Receive Cell and Frame Processor (RCFP + RTDP) There are two types of Receive Cell and Frame Processor blocks, RCFP (Receive Cell and Frame Processor) and RTDP (Receive Timeslice Datacom Processor). The RCFP blocks are used for STS-12c/STM-4c and STS-48c/STM16c channels while the RTDP blocks are used for STS-3c/STM-1, STS-1/STM-0, and DS-3 bandwidth channels. Table 13
0070h 0080h 0090h 00A0h 00F0h 0110h 0130h 0150h
RCFP + RTDP Base Addresses
DESCRIPTION RCFP Configuration #1 (RCFP0_BASE) RCFP Configuration #2 (RCFP1_BASE) RCFP Configuration #3 (RCFP2_BASE) RCFP Configuration #4 (RCFP3_BASE) RTDP Indirect Channel Select #1 (RTDP0_BASE) RTDP Indirect Channel Select #2 (RTDP1_BASE) RTDP Indirect Channel Select #3 (RTDP2_BASE) RTDP Indirect Channel Select #4 (RTDP3_BASE)
Register Address
Table 14
RTDP Registers
DESCRIPTION RTDP Indirect Configuration RTDP Indirect Minimum Packet Length and Bit Order RTDP Indirect Maximum Packet Length RTDP Indirect LCD Count Threshold RTDP Indirect Idle Cell Header and Mask
Register Address RTDP_BASEx + 01h RTDP_BASEx + 02h RTDP_BASEx + 03h RTDP_BASEx + 04h RTDP_BASEx + 05h (x=1 to 4)
Table 15
RCFP Registers
DESCRIPTION RCFP Interrupt Enable RCFP Interrupt Indication and Status RCFP Minimum Packet Length
Register Address RCFP_BASEx + 01h RCFP_BASEx + 02h RCFP_BASEx + 03h
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Register Address RCFP_BASEx + 04h RCFP_BASEx + 05h RCFP_BASEx + 06h RCFP_BASEx + 07h RCFP_BASEx + 08h RCFP_BASEx + 09h RCFP_BASEx + 0Ah RCFP_BASEx + 0Bh RCFP_BASEx + 0Ch RCFP_BASEx + 0Dh RCFP_BASEx + 0Eh RCFP_BASEx + 0Fh (x=1 to 4)
DESCRIPTION RCFP Maximum Packet Length RCFP LCD Count Threshold RCFP Idle Cell Header and Mask RCFP Receive Byte/Idle Cell Counter (LSB) RCFP Receive Byte/Idle Cell Counter RCFP Receive Byte/Idle Cell Counter (MSB) RCFP Packet/Cell Counter (LSB) RCFP Packet/Cell Counter (MSB) RCFP Receive Erred FCS/HCS Counter RCFP Receive Aborted Packet Counter RCFP Receive Minimum Length Packet Error Counter RCFP Receive Maximum Length Packet Error Counter
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5.9
Transmit Cell and Frame Processor (TCFP + TTDP) Like the Receive side, the Transmit side has two types of cell and frame processor blocks. The Transmit Cell and Frame Processor (TCFP) is used to process STS-12c/STM-4c and STS-48c/STM-16c data streams. The Transmit Timeslice Datacom Processor (TTDP) is used to process STS-3c/STM-1 and lower bandwidths. Table 16
00B0h 00C0h 00D0h 00E0h 0170h 0180h 0190h 01A0h
TCFP + TDFP Base Addresses
DESCRIPTION TCFP Configuration #1 TCFP Configuration #2 TCFP Configuration #3 TCFP Configuration #4 TTDP Indirect Channel Select #1 TTDP Indirect Channel Select #2 TTDP Indirect Channel Select #3 TTDP Indirect Channel Select #4
Register Address
Table 17
TCFP Registers
DESCRIPTION TCFP Interrupt Indication TCFP Idle/Unassigned ATM Cell Header TCFP Diagnostics TCFP Transmit Cell/Packet Counter (LSB) TCFP Transmit Cell/Packet Counter (MSB) TCFP Transmit Byte Counter (LSB) TCFP Transmit Byte Counter TCFP Transmit Byte Counter (MSB) TCFP Aborted Packet Counter
Register Address TCFPx_BASE+01h TCFPx_BASE+02h TCFPx_BASE+03h TCFPx_BASE+04h TCFPx_BASE+05h TCFPx_BASE+06h TCFPx_BASE+07h TCFPx_BASE+08h TCFPx_BASE+09h x = 1 to 4
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Table 18
TTDP Registers
DESCRIPTION TTDP Indirect Configuration TTDP Indirect Idle/Unassigned ATM Cell Header TTDP Indirect Diagnostics TTDP Indirect Transmit Cell/Packet Counter (LSB) TTDP Indirect Transmit Cell/Packet Counter (MSB) TTDP Indirect Transmit Byte Counter (LSB) TTDP Indirect Transmit Byte Counter (MSB) TTDP Indirect Aborted Packet Counter TTDP CRC Error Mask TTDP Interrupt Enable 1 TTDP Interrupt Enable 2 TTDP Interrupt 1 TTDP Interrupt 2 TTDP Transmit Off
Register Address TTDPx_BASE+01h TTDPx_BASE+02h TTDPx_BASE+03h TTDPx_BASE+04h TTDPx_BASE+05h TTDPx_BASE+06h TTDPx_BASE+07h TTDPx_BASE+08h TTDPx_BASE+09h TTDPx_BASE+0Ah TTDPx_BASE+0Bh TTDPx_BASE+0Ch TTDPx_BASE+0Dh TTDPx_BASE+0Eh x = 1 to 4
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5.10
SONET/SDH Inband Error Report Processor The SONET/SDH Inband Error Report Processor (SIRP) maps remote error indications (REI, RDI) from the G1 byte of the receive SONET Path Overhead into the transmit SONET Path Overhead. It is important to note that the SIRP must be enabled for all provisioned channels in order for the S/UNI MACH48 to function correctly. When the SIRP is enabled the J1 byte is passed correctly to the downstream blocks. Table 19
14C0h 14D0h 14E0h 14F0h
SIRP Base Addresses
DESCRIPTION SIRP1_BASE SIRP2_BASE SIRP3_BASE SIRP4_BASE
Register Address
Table 20
SIRP Registers
DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration SIRP Timeslot #4 Configuration SIRP Timeslot #5 Configuration SIRP Timeslot #6 Configuration SIRP Timeslot #7 Configuration SIRP Timeslot #8 Configuration SIRP Timeslot #9 Configuration SIRP Timeslot #A Configuration SIRP Timeslot #B Configuration SIRP LCD RDI Value Register
Register Address SIRPx_BASE + 00h SIRPx_BASE + 01h SIRPx_BASE + 02h SIRPx_BASE + 03h SIRPx_BASE + 04h SIRPx_BASE + 05h SIRPx_BASE + 06h SIRPx_BASE + 07h SIRPx_BASE + 08h SIRPx_BASE + 09h SIRPx_BASE + 0Ah SIRPx_BASE + 0Bh SIRPx_BASE + 0Ch x = 1 to 4
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5.11
Receive Channel Assigner (RCAS) The Receive Channel Assigner groups STS-1/STM-0 timeslots into channels. A more detailed description of its operation can be found in the S/UNI MACH48 Data Sheet, Section 11.13. The RCAS registers are directly accessed and use the following registers. Table 21
01B0h 01C0h 01D0h 01E0h
RCAS Base Addresses
DESCRIPTION RCAS_BASE #1 RCAS_BASE #2 RCAS_BASE #3 RCAS_BASE #4
Register Address (RCAS12)
Table 22
RCAS12+00 RCAS12+01
RCAS Registers
DESCRIPTION RCAS Channel Disable RCAS Channel Loopback Enable RCAS Timeslot Configuration #0-11
Register Address
RCAS12+(02-0D)
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5.12
Transmit Channel Assigner (TCAS) The Transmit Channel Assigner maps channel numbers from the UL3/PL3 interface into the STS-1 timeslots. The TCAS registers are directly accessed and use the following registers. Table 23
01F0h 0200h 0210h 0220h
TCAS Base Addresses
DESCRIPTION TCAS_BASE #1 TCAS_BASE #2 TCAS_BASE #3 TCAS_BASE #4
Register Address
Table 24
TCAS12+00h
TCAS Registers
DESCRIPTION TCAS Channel Configuration TCAS Timeslot Configuration #0-11
Register Address
TCAS12+(02h-0Dh)
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6 6.1
EXAMPLES Example 1: Single PHY, STS-48c In this example, the MACH48 device is configured to receive a single PHY STS48c. The example sets up Serial Telecombus mode and allows the choice of either UL3 or PL3 mode. Figure 2 - MACH48 STS-48c Example
UL3/PL3 INTERFACE
70-104 Mbps 32 BIT BUS
S/UNI-
(R)
PM7390-BI CB924102A M9845
MACH48
TRAFFIC ATM POS
TRAFFIC 1 x STS-48c/STM-16c
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6.1.1 Set Configuration Register Table 25
ADDRESS 0001h
Config Register (STS-48c), S-TCB
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 015Ch PL3 VALUE 01DCh
Table 26
ADDRESS 0001h
Config Register (STS-48c), DLOOP
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 015Eh PL3 VALUE 01DCh
6.1.2 Set Timeslot and Delay Registers (STS-48c) For STS-48c/STM-16c, the timeslot registers are ignored. Set the RJ0DLY, this value will need to be modified if the S-TCB is used, depending on the system configuration. Table 27
ADDRESS 0011h
RX S-TCB Synchronization Delay
DESCRIPTION Receive Serial Telecombus Syncronization Delay VALUE 807Fh
Set the IWTI, IPTI,OPTI and OWTI modes in the Miscellaneous Register to STS48c mode. Table 28
0012h
Miscellaneous Register 0012h
DESCRIPTION Miscellaneous VALUE 80FAh
ADDRESS
Note: This is the default value at startup 6.1.3 Set Serial Telecombus Registers For Serial Telecombus Mode, set up the working and protect links for High Order Path Termination (HPT) mode. Set TMODEx[1..0] => 01 for HPT mode.
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Table 29
S-TCB Register Setup
DESCRIPTION T8TE1 Telecombus Mode #1 T8TE1 Telecombus Mode #2 T8TE2 Telecombus Mode #1 T8TE2 Telecombus Mode #2 T8TE3 Telecombus Mode #1 T8TE3 Telecombus Mode #2 T8TE4 Telecombus Mode #1 T8TE4 Telecombus Mode #2 T8TE5 Telecombus Mode #1 T8TE5 Telecombus Mode #2 T8TE6 Telecombus Mode #1 T8TE6 Telecombus Mode #2 T8TE7 Telecombus Mode #1 T8TE7 Telecombus Mode #2 T8TE8 Telecombus Mode #1 T8TE8 Telecombus Mode #2 VALUE 5555h 0055h 5555h 0055h 555h 0055h 5555h 0055h 5555h 0055h 5555h 0055h 5555h 0055h 5555h 0055h
ADDRESS T8TE1_BASE (1860h) + 0002h T8TE1_BASE (1860h) + 0003h T8TE2_BASE (1868h) + 0002h T8TE2_BASE (1868h) + 0003h T8TE3_BASE (1870h) + 0002h T8TE3_BASE (1870h) + 0003h T8TE4_BASE (1878h) + 0002h T8TE4_BASE (1878h) + 0003h T8TE5_BASE (1880h) + 0002h T8TE5_BASE (1880h) + 0003h T8TE6_BASE (1888h) + 0002h T8TE6_BASE (1888h) + 0003h T8TE7_BASE (1890h) + 0002h T8TE7_BASE (1890h) + 0003h T8TE8_BASE (1898h) + 0002h T8TE8_BASE (1898h) + 0003h
The following register must also be set in the S/UNI MACH48 for proper operation. Table 30
ADDRESS R8TDx_BASE+03h (x=1 to 8)
R8TDx Analog Control Setting
DESCRIPTION R8TDx Analog Control 1 VALUE CC34h
For loopback (Serial Telecombus Diagnostic loopback), the loopback bits must be set. The DLBEN bits are located in the R8TD blocks. Table 31
ADDRESS R8TD1_BASE (1820h) R8TD2_BASE (1828h) R8TD3_BASE (1830h)
S-TCB Diagnostic Loopback
DESCRIPTION R8TD1 Control and Status R8TD2 Control and Status R8TD3 Control and Status VALUE 8000h 8000h 8000h
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ADDRESS R8TD4_BASE (1838h) R8TD5_BASE (1840h) R8TD6_BASE (1848h) R8TD7_BASE (1850h) R8TD8_BASE (1858h)
DESCRIPTION R8TD4 Control and Status R8TD5 Control and Status R8TD6 Control and Status R8TD7 Control and Status R8TD8 Control and Status
VALUE 8000h 8000h 8000h 8000h 8000h
6.1.4 RXPHY Calendar (STS-48c/STM-16c) For the STS-48c example, there is only one entry in the calendar when the POS mode is selected. The calendar length requires a direct write while the calendar entry requires an indirect register write. Table 32
ADDRESS 0044h
Calendar Length Value (1 x STS-48c)
DESCRIPTION RXPHY Calendar Length VALUE 0000h
An example write for a calendar entry is illustrated below: 1. Poll the BUSY bit in register 0045h: Bit 15.
2. When BUSY bit is 0, write 0 to CALENDAR ADDRESS[6..0] and CALENDAR DATA[5..0] and CONFIG_RWB in register 0045h. The TXPHY is set up in a similar manner. 6.1.5 Scalable Data Queue (STS48c/STM-16c) Both the RXSDQ and the TXSDQ are set up in a similar manner. For the STS48c example there is only one entry in the SDQ. The entry will have the following attributes. Table 33
Description PHYID FIFO NUMBER FIFO BLOCK SIZE
Example SDQ Entry Setup for PHYID 0(STS-48c)
Value(DEC) 0 0 3 Value (BIN) 000000b 000000b 11b Register 0058h 0059h 0059h Note PHYID for the STS-48c channel Associates a FIFO# with a PHYID A Block size of 192 (as per Data Sheet Section 14)
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Description DATA AVAILABLE THRESHOLD
Value(DEC) 3 or 95
Value (BIN) 00000011b or 01011111b
Register 005A
Note = 3 for ATM and variable for POS depending on required burst size, in this example=95.
These values are written to the RXSDQ in the following order: 1. 2. 3. Poll the BUSY bit in register 0058h until it reads 0. Write the data to the addresses as shown in Table 34. Write the Indirect Register Address with the RWB bit set to 0 and the PHYID. This will initiate the write of the indirect data registers.
Writing to the TXSDQ is done in the same manner. Table 34
ADDRESS 0059h 005Ah 0069h 006Ah
SDQ Register Setup (STS-48c)
DESCRIPTION RXSDQ FIFO Indirect Configuration RXSDQ FIFO Indirect Data AvailableThreshold TXSDQ FIFO Indirect Configuration TXSDQ FIFO Inidrect Data/Buffer Available Threshold ATM 80C0h 0303h 80C0h 0303h POS C0C0h 0703h C0C0h 5F07h
6.1.6 Receive Cell and Frame Processor (STS48c) In STS-48c/STM-4c mode, only the least significant RCFP base address is used (0070h). The RTDP blocks are not used. Note, at this point the processor is not provisioned. This will be done after all other registers are set. Table 35
ADDRESS 0070h
RCFP0 Register (STS-48c)
DESCRIPTION RCFP Configuration Register #1 ATM 0110h POS 0510h
6.1.7 Transmit Cell and Frame Processor (STS48c) The TCFP is set up identically to the RCFP.
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Table 36
ADDRESS 00B0h
TCFP0 Register (STS-48c)
DESCRIPTION TCFP Configuration Register #1 ATM 0080h POS 0180h
6.1.8 Receive Channel Assigner (STS48c) Set the Timeslot mode and provision each channel (0 to 11). The data sheet stipulates that if the MACH48 is set up for STS-48c, all timeslots should be provisioned and enabled for channel 0. For this example: TsxMode = 000 for STS-12c/STM-4c
TSx_PROV is set to 1 The registers should be written as follows: Table 37 RCAS Register Setup (STS-48c)
ADDRESS RCAS0_BASE (0x01B0h) + (0002h+x) RCAS1_BASE (0x01C0h) + (0002h+x) RCAS2_BASE (0x01D0h) + (0002h+x) RCAS3_BASE (0x01E0h) + (0002h+x) x = 0h to Bh DESCRIPTION RCAS0 Timeslot Configuration #0-11 RCAS1 Timeslot Configuration #0-11 RCAS2 Timeslot Configuration #0-11 RCAS3 Timeslot Configuration #0-11 VALUE 0010h 0010h 0010h 0010h
If channel based diagnostic loopback is required, the following registers should be written: Table 38 RCAS Loopback (STS-48c)
ADDRESS RCAS0_BASE (0x01B0h) + (0001h) RCAS1_BASE (0x01C0h) + (0001h) RCAS2_BASE (0x01D0h) + (0001h) RCAS3_BASE (0x01E0h) + (0001h) DESCRIPTION RCAS0 Channel Loopback Enable RCAS1 Channel Loopback Enable RCAS2 Channel Loopback Enable RCAS3 Channel Loopback Enable VALUE 1001h 1001h 1001h 1001h
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CONFIGURING THE PM7390 S/UNI MACH48
6.1.9 Transmit Channel Assigner (STS48c/STM-16c) Set the Timeslot mode and provision each channel (0 to 11). Like the RCAS, all timeslots should be provisioned and enabled for channel 0. For this example: TsxMode = 000 for STS-12c/STM-4c
TSx_PROV is set to 1 The registers should be written as follows: Table 39 TCAS Register Setup (STS-48c)
DESCRIPTION TCAS0 Timeslot Configuration #0-11 VALUE 0010h
ADDRESS TCAS0_BASE (0x01F0h) + (0002h+x) where x = 0 to Bh TCAS1_BASE (0x0200h) + (0002h+x) where x = 0 to Bh TCAS2_BASE (0x0210h) + (0002h+x) where x = 0 to Bh TCAS3_BASE (0x0220h) + (0002h+x) where x = 0 to Bh
TCAS1 Timeslot Configuration #0-11
0010h
TCAS2 Timeslot Configuration #0-11
0010h
TCAS3 Timeslot Configuration #0-11
0010h
6.1.10 SONET/SDH Inband Error Report Processor For the STS-48c example, only the SIRP1_BASE is provisioned. Table 40
ADDRESS SIRP1_BASE+00h
STS-48c SIRP Setup
DESCRIPTION SIRP Timeslot Configuration #0 VALUE 0007h
6.1.11 Enable Blocks (STS48c/STM-16c) Once all of the registers are set up as required, the blocks can be enabled. Table 41
ADDRESS 0070h
Provisioning RCFP/TCFP Blocks
DESCRIPTION RCFP Configuration Register ATM 0111h POS 0511h
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CONFIGURING THE PM7390 S/UNI MACH48
00B0h
TCFP Configuration Register
0081h
0181h
In the STS-48c mode, all of the channels are provisioned and enabled. Table 42
ADDRESS RCAS0_BASE RCAS1_BASE RCAS2_BASE RCAS3_BASE TCAS0_BASE TCAS1_BASE TCAS2_BASE TCAS3_BASE
Enabling RCAS/TCAS Blocks
DESCRIPTION RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
The SDQ FIFO are enable as follows: Table 43
ADDRESS 0050h 0060h
Enabling RXSDQ/TXSDQ Blocks
DESCRIPTION RXSDQ FIFO Reset TXSDQ FIFO Reset VALUE 0000h 0000h
The RXPHY and TXPHY is enabled. For the STS-48c mode, TPAHOLD is set to 0 since the FIFO size is large (192 blocks). Table 44
ADDRESS 0040h 0048h
Enabling RXPHY/TXPHY Blocks
DESCRIPTION RXPHY Configuration TXPHY Configuration UL3 VALUE 0000h 0000h PL3 VALUE 0000h 0040h
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6.2
Example 2: 16 x STS-3c Channels In this example, the MACH48 is setup up to have 16 STS-3c PHYs. The PHYS are numbered from 0 to 3, 12 to 15, 24 to 27, and 36 to 39. Figure 3 - MACH48 STS-3c Example
UL3/PL3 INTERFACE 4 x STS-12 LINKS TRAFFIC 16 x STS-3c/STM-1
70-104 Mbps 32 BIT BUS
S/UNI-
(R)
PM7390-BI CB924102A M9845
MACH48
TRAFFIC ATM POS
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6.2.1 Set Configuration Register The setup is for Serial Telecombus and either UL3 or PL3 Table 45
ADDRESS 0001h
Config Register (16 x STS-3c), S-TCB
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0150h PL3 VALUE 01D0h
For Diagnostic loopback, the register is set up as follows: Table 46
ADDRESS 0001h
Config Register (16 x STS-3c), DLOOP
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0152h PL3 VALUE 01D2h
6.2.2 Set Timeslot and Delay Registers (16 x STS-3c) Table 47
ADDRESS 0002h-000Dh
Timeslot Registers (16 x STS-3c)
DESCRIPTION RX/TX Timeslot Configuration #0-11 VALUE 5555h
Set the RJ0DLY, this value will need to be modified depending on the system configuration. Table 48
ADDRESS 0011h
RX S-TCB Synchronization Delay
DESCRIPTION Receive Serial Telecombus Synchronization Delay VALUE 007Fh
Set the IWTI, IPTI, OPTI and OWTI modes in the Miscellaneous Register to bypass. Table 49
ADDRESS 0012h
Miscellaneous Register 0012h
DESCRIPTION Miscellaneous VALUE 8055h
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6.2.3 Set Serial Telecombus Registers (STS-3c) Similarly to Example 1, the MACH48 is set up in Serial Telecombus Mode. Set up the working and protect links for High Order Path Termination (HPT) mode. The R8TDx +03h must also be set to CC34h. Set TMODEx[1..0] => 01 for HPT mode. 6.2.4 Set Up RXPHY Calendar (16 x STS-3c) For this example, there are 48 entries in the calendar when POS mode is selected. Table 50
ADDRESS 0044h
Calendar Register Values (16 x STS-3c)
DESCRIPTION RXPHY Calendar Length VALUE 002Fh
Table 51
Calendar Entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RXPHY Calendar (16 x STS-3c)
Channel # Calendar Entry 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 Channel # Calendar Entry 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 Channel #
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An example write to calendar entry 15 is illustrated below: 1. Poll the BUSY bit in register 0045h: Bit 15.
2. When BUSY bit is 0, write 15 to CALENDAR ADDRESS[6..0] and 39 to CALENDAR DATA[5..0] and CONFIG_RWB in register 0045h. (0F27h) 6.2.5 Scalable Data Queue (16 x STS-3c) Both the RXSDQ and TXSDQ should be set up according to the following table. Table 52
Channel # PHYID[5:0] BW
FIFO Setup (16 x STS-3c)
Size (Block) Size (Cell) FIFO_BS [1:0] Bank FIFO# [5:0] Block_PTR [4:0] (hex)
0 1 2 3 12 13 14 15 24 25 26 27 36 37 38 39 STS-3c 48 12 2 3 STS-3c 48 12 2 2 STS-3c 48 12 2 1 STS-3c 48 12 2 0
0 1 2 3 16 17 18 19 32 33 34 35 48 49 50 51
00 06 0C 12 00 06 0C 12 00 06 0C 12 00 06 0C 12
The following is an example of how an SDQ entry is performed. The table below shows the required parameters used to set up the PHYID = 14 entry in Table 52.
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Table 53
Description PHYID FIFO NUMBER
Example SDQ Entry Setup for PHYID 14(16 x STS-3c)
Value(DEC) 14 17 2 Value (BIN) 00000Eb 010001b 10b Register 0058h 0059h 0059h Note PHYID for the STS-3c channel Associates a FIFO# with a PHYID A Block size of 48 (as per Data Sheet Section 14)
FIFO BLOCK SIZE
DATA AVAILABLE THRESHOLD
3 or 23
00000011b or 00100011b
005A
= 3 for ATM and variable for POS depending on required burst size, in this example=23.
These values are written to the RXSDQ in the following order: 1. 2. 3. Poll the BUSY bit in register 0058h until it reads 0. Write the data to the addresses as shown in Table 54. Write the Indirect Register Address with the RWB bit set to 0 and the PHYID. This will initiate the write of the indirect data registers.
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Writing to the TXSDQ is done in the same manner. Table 54
ADDRESS 0059h 005Ah 0069h 006Ah
SDQ Register Setup for PHYID 14 STS-3c Entry
DESCRIPTION RXSDQ FIFO Indirect Configuration RXSDQ FIFO Indirect Data AvailableThreshold TXSDQ FIFO Indirect Configuration TXSDQ FIFO Inidrect Data Available Threshold ATM VALUE 928Ch 0303h 928Ch 0303h POS VALUE D28Ch 0703h D28Ch 2307h
6.2.6 Receive Timeslice Datacom Processor In this example (16 x STS-3c), the RCFP blocks are not used. The table below shows the values that are to be written into the RTDP indirect registers for each of the 16 channels used. RTDP_BASE + 01h: Enable Channel, Select POS/ATM, STRIP_SEL = 1. RTDP_BASE + (02h - 05h) are set to default values. Table 55
Channel # PHYID[5:0]
RTDP Register Setup (16 x STS-3c)
RTDP BASE POS 01 ATM 02 OFFSET 03 04 05
0 1 2 3 12 13 14 15 24 25 26 27 0130h 0511 0111 0402 0300 0168 01FF 0110h 0511 0111 0402 0300 0168 01FF 00F0h 0511 0111 0402 0300 0168 01FF
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Channel # PHYID[5:0] 36 37 38 39
RTDP BASE 01 02
OFFSET 03 04 05
0150h
0511h
0111h
0402h
0300h
0168h
01FFh
The example below will write the RTDP setup for PHYID = 27. 1. 2. Poll the BUSY bit in register: 0130h until it reads 0. Write the above indirect registers except the Indirect Address Register.
3. Write the Indirect Register Address (0130h) last with the RWB bit set to 0 and the CHAN[3..0] set to 3 (0003h). This will initiate the write to Channel 3 which corresponds to PHYID.= 27 in the third RTDP block.
6.2.7 Transmit Timeslice Datacom Processor Similarly to the RTDP, the TTDP is set up as follows. Table 56
Channel # PHYID[5:0]
TTDP Register Setup (16 x STS-3c)
TTDP BASE POS 01h ATM OFFSET 02h 03h
0 1 2 3 12 13 14 15 24 25 26 0190 0301 0101 016A 0003 0180 0301 0101 016A 0003 0170 0301 0101 016A 0003
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Channel # PHYID[5:0]
TTDP BASE POS 01h ATM
OFFSET 02h 03h
27 36 37 38 39 01A0 0301 0101 016A 0003
The following is an example of how an TTDP entry is performed. The table below shows the required register values to set up the PHYID = 26 entry in Table 56. Table 57
ADDRESS TTDP2_BASE + 00h TTDP2_BASE + 01h TTDP2_BASE + 02h TTDP2_BASE + 03h
TTDP Register Setup for PHYID 26 STS-3c Entry
DESCRIPTION TTDP Indirect Channel Select TTDP Indirect Configuration TTDP Indirect Idle/Unassigned ATM Cell Header TTDP Indirect Diagnostics ATM VALUE 0002h 0101h 016Ah 0003h POS VALUE 0002h 0301h 016Ah 0003h
1. 2.
Poll the BUSY bit in register: 0190h until it reads 0. Write the above indirect registers except the Indirect Address Register.
3. Write the Indirect Register Address (0190h) last with the RWB bit set to 0 and the CHAN[3..0] set to 2 (0002h). This will initiate the write to Channel 2 which corresponds to PHYID= 26 in the third RTDP block.
6.2.8 Receive Channel Assigner (16 x STS-3c) For this example: TsxMode = 001 for STS-3c/STM-1
TSx_PROV is set to 1 The registers should be written as follows to each RCAS base address.
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Table 58
ADDRESS
RCAS Register Setup (16 x STS-3c)
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11 VALUE 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h
RCAS_BASE + 0002h RCAS_BASE + 0003h RCAS_BASE + 0004h RCAS_BASE + 0005h RCAS_BASE + 0006h RCAS_BASE + 0007h RCAS_BASE + 0008h RCAS_BASE + 0009h RCAS_BASE + 000Ah RCAS_BASE + 000Bh RCAS_BASE + 000Ch RCAS_BASE + 000Dh
If channel based diagnostic loopback is required, the following registers should be written: Table 59 RCAS Loopback Settings (16 x STS-3c)
ADDRESS RCAS0_BASE (0x01B0h) + (0001h) RCAS1_BASE (0x01C0h) + (0001h) RCAS2_BASE (0x01D0h) + (0001h) RCAS3_BASE (0x01E0h) + (0001h) DESCRIPTION RCAS0 Channel Loopback Enable RCAS1 Channel Loopback Enable RCAS2 Channel Loopback Enable RCAS3 Channel Loopback Enable VALUE 000Fh 000Fh 000Fh 000Fh
6.2.9 Transmit Channel Assigner (16 x STS-3c) Set the Timeslot mode and provision each channel (0 to 11). TsxMode = 001 for STS-3c/STM-1,TSx_PROV is set to 1 Therefore the registers should be written as follows: Table 60
ADDRESS TCAS_BASE + 0002h
TCAS Configuration Registers (16 x STS-3c)
DESCRIPTION TCAS Timeslot Configuration #0 VALUE 0030h
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ADDRESS TCAS_BASE + 0003h TCAS_BASE + 0004h TCAS_BASE + 0005h TCAS_BASE + 0006h TCAS_BASE + 0007h TCAS_BASE + 0008h TCAS_BASE + 0009h TCAS_BASE + 000Ah TCAS_BASE + 000Bh TCAS_BASE + 000Ch TCAS_BASE + 000Dh
DESCRIPTION TCAS Timeslot Configuration #1 TCAS Timeslot Configuration #2 TCAS Timeslot Configuration #3 TCAS Timeslot Configuration #4 TCAS Timeslot Configuration #5 TCAS Timeslot Configuration #6 TCAS Timeslot Configuration #7 TCAS Timeslot Configuration #8 TCAS Timeslot Configuration #9 TCAS Timeslot Configuration #10 TCAS Timeslot Configuration #11
VALUE 0031h 0032h 0033h 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h
6.2.10 SONET/SDH Inband Error Processor (16 x STS-3c) For the 16 x STS-3c example, only the first four timeslots of each SIRP are provisioned. Table 61 - 16 x STS-3c SIRP Configuration
ADDRESS SIRPx_BASE + 00h SIRPx_BASE + 01h SIRPx_BASE + 02h SIRPx_BASE + 03h x= 1 to 4 DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration VALUE 0001h 0001h 0001h 0001h
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6.2.11 Enable Blocks (16 x STS-3c) Once all of the registers are set up as required, the blocks can be enabled. Table 62
ADDRESS RCAS0_BASE RCAS1_BASE RCAS2_BASE RCAS3_BASE TCAS0_BASE TCAS1_BASE TCAS2_BASE TCAS3_BASE
Enabling RCAS/TCAS Blocks
DESCRIPTION RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration VALUE 0FF0h 0FF0h 0FF0h 0FF0h 0FF0h 0FF0h 0FF0h 0FF0h
Table 63
ADDRESS 0050h 0060h
Enabling RXSDQ/TXSDQ Blocks
DESCRIPTION RXSDQ FIFO Reset TXSDQ FIFO Reset VALUE 0000h 0000h
Table 64
ADDRESS 0040h 0048h
Enabling RXPHY/TXPHY Blocks
DESCRIPTION RXPHY Configuration TXPHY Configuration UL3 VALUE 0000h 0000h PL3 VALUE 0000h 0040h
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6.3
Example 3: 48 x STS-1 In this example, the MACH48 is setup up to have 48 PHYs, each at STS-1/STM0 bandwidth. The PHYS are numbered from 0 to 47. Figure 4 - MACH48 STS-1 Example
UL3/PL3 INTERFACE
70-104 Mbps 32 BIT BUS
S/UNI-
(R)
PM7390-BI CB924102A M9845
MACH48
TRAFFIC ATM POS
48 x STS-1/STM-0
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4 x STS-12 LINKS TRAFFIC
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6.3.1 Set Configuration Register The setup is for Serial Telecombus and either UL3 or PL3 Table 65
ADDRESS 0001h
Config Register (48 x STS-1), S-TCB
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0150h PL3 VALUE 01D0h
For Diagnostic loopback, the register is set up as follows: Table 66
ADDRESS 0001h
Config Register (48 x STS-1), DLOOP
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0152h PL3 VALUE 01D2h
6.3.2 Set Timeslot and Delay Registers (48 x STS-1) Both the RX and TX Timeslot configuration registers are written with the same values. Table 67
ADDRESS 0002h-000Dh
Timeslot Registers (48 x STS-1)
DESCRIPTION RX/TX Timeslot Configuration VALUE AAAAh
Set the RJ0DLY, this value will need to be modified depending on the system configuration. Table 68
ADDRESS 0011h
RX S-TCB Synchronization Delay
DESCRIPTION Receive Serial Telcombus Synchronization Delay VALUE 007Fh
Set the IWTI, IPTI,OPTI and OWTI modes in the Miscellaneous Register bypass mode. Table 69
ADDRESS 0012h
Miscellaneous Register 0012h
DESCRIPTION Miscellaneous VALUE 8055h
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6.3.3 Set Serial Telecombus Registers Similarly to Example 1, Section 6.1.3 the MACH48 is set up in Serial Telecombus Mode. Set up the working and protect links for High Order Path Termination (HPT) mode. The R8TDx +03h must also be set to CC34h. Set TMODEx[1..0] => 01 for HPT mode.
6.3.4 Set Up RXPHY Calendar The Calendar for this example has a length of 48. Each channel from 0 to 47 is polled with a uniform probability of being selected. Table 70
ADDRESS 0044h
Calendar Length Register (48 x STS-1)
DESCRIPTION RXPHY Calendar Length VALUE 002Fh
The table can be set up as follows: Table 71
Calendar Entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 12 24 36 1 13 25 37 2 14 26 38 3 15
- RXPHY Calendar Setup (48 x STS-1)
Channel # Calendar Entry 16 17 18 19 20 21 22 23 24 25 26 27 28 29 4 16 28 40 5 17 29 41 6 18 30 42 7 19 Channel # Calendar Entry 32 33 34 35 36 37 38 39 40 41 42 43 44 45 8 20 32 44 9 21 33 45 10 22 34 46 11 23 Channel #
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Calendar Entry 14 15
Channel #
Calendar Entry
Channel #
Calendar Entry
Channel #
27 39
30 31
31 43
46 47
35 47
6.3.5 Scalable Data Queue (48 x STS-1) Both the RXSDQ and TXSDQ are set up according to the following table. The block pointers are arranged such that any reconfiguration to a higher bandwidth channel will not affect unintended channels. Table 72
Channel # PHYID[5:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 STS-1 16 4 1 1 STS-1 16 4 1 1 STS-1 16 4 1 0 BW
48 x STS-1 FIFO Setup
Size (Block) Size (Cell) FIFO_BS [1:0] Bank FIFO# [5:0] 0 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 21 22 23 Block_PTR [4:0] 00 06 0C 12 02 08 0E 14 04 0A 10 16 00 06 0C 12 02 08 0E 14
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Channel # PHYID[5:0] 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
BW
Size (Block)
Size (Cell)
FIFO_BS [1:0]
Bank
FIFO# [5:0] 24 25 26 27 32 33 34 35 36
Block_PTR [4:0] 04 0A 10 16 00 06 0C 12 02 08 0E 14 04 0A 10 16 00 06 0C 12 02 08 0E 14 04 0A 10 16
STS-1
16
4
1
2
37 38 39 40 41 42 43 48 49 50 51 52
STS-1
16
4
1
3
53 54 55 56 57 58 59
The table below shows the required parameters used to set up the PHYID = 36 entry in Table 72.
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Table 73
Description PHYID FIFO NUMBER
- Example SDQ Entry Setup for PHYID 36(48 x STS-1)
Value(DEC) 36 48 1 Value (BIN) 100100b 110000b 01b Register 0058h 0059h 0059h Note PHYID for the STS-1 channel Associates a FIFO# with a PHYID A Block size of 48 (as per Data Sheet Section 14)
FIFO BLOCK SIZE
DATA AVAILABLE THRESHOLD
3 or 7
00000011b or 00000111b
005A
= 3 for ATM and variable for POS depending on required burst size, in this example=7.
These values are written to the RXSDQ in the following order: 1. 2. 3. Poll the BUSY bit in register 0058h until it reads 0. Write the data to the addresses as shown in Table 74. Write the Indirect Register Address with the RWB bit set to 0 and the PHYID. This will initiate the write of the indirect data registers.
Writing to the TXSDQ is done in the same manner. Table 74
ADDRESS 0059h 005Ah 0069h 006Ah
SDQ Register Setup for PHYID 36 STS-1 Entry
DESCRIPTION RXSDQ FIFO Indirect Configuration RXSDQ FIFO Indirect Data AvailableThreshold TXSDQ FIFO Indirect Configuration TXSDQ FIFO Inidrect Data Available Threshold ATM VALUE B040h 0303h B040h 0303h POS VALUE F040h 0703h F040h 0707h
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6.3.6 Receive Timeslice Datacom Processor The RTDP is set up according to the following table. Table 75
Channel # PHYID[5:0]
RTDP Register Setup (48 x STS-1)
RTDP BASE POS 01 ATM 02 OFFSET 03 04 05
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0130h 0511h 0111h 0402h 0300h 0168h 01FFh 0110h 0511h 0111h 0402h 0300h 0168h 01FFh 00F0h 0511h 0111h 0402h 0300h 0168h 01FFh
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Channel # PHYID[5:0]
RTDP BASE POS 01 ATM 02
OFFSET 03 04 05
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0150H 0511h 0111h 0402h 0300 0168h 01FFh 0130h 0511h 0111h 0402h 0300h 0168h 01FFh
6.3.7 Transmit Timeslice Datacom Processor The TTDP is set up identically to the RTDP above. 6.3.8 Receive Channel Assigner TSxMode = 010 for STS-1/STM-0, TSx_PROV is set to 1 The registers should be written as follows for each RCAS block:
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Table 76
ADDRESS
RCAS Register Setup (48 x STS-1)
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11 VALUE 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh
RCAS_BASE + 0002h RCAS_BASE + 0003h RCAS_BASE + 0004h RCAS_BASE + 0005h RCAS_BASE + 0006h RCAS_BASE + 0007h RCAS_BASE + 0008h RCAS_BASE + 0009h RCAS_BASE + 000Ah RCAS_BASE + 000Bh RCAS_BASE + 000Ch RCAS_BASE + 000Dh
If channel based diagnostic loopback is required, the following registers should be written: Table 77 RCAS Base Register Values for Loopback(48 x STS-1)
ADDRESS RCAS0_BASE (0x01B0h) + (0001h) RCAS1_BASE (0x01C0h) + (0001h) RCAS2_BASE (0x01D0h) + (0001h) RCAS3_BASE (0x01E0h) + (0001h) DESCRIPTION RCAS0 Channel Loopback Enable RCAS1 Channel Loopback Enable RCAS2 Channel Loopback Enable RCAS3 Channel Loopback Enable VALUE 0FFFh 0FFFh 0FFFh 0FFFh
6.3.9 Transmit Channel Assigner Set the Timeslot mode and provision each channel. TSxMode = 010 for STS-1/STM-0, TSx_PROV is set to 1 The registers are written as follows:
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Table 78
TCAS Configuration Registers (48 x STS-1)
ADDRESS DESCRIPTION TCAS Timeslot Configuration #0 TCAS Timeslot Configuration #1 TCAS Timeslot Configuration #2 TCAS Timeslot Configuration #3 TCAS Timeslot Configuration #4 TCAS Timeslot Configuration #5 TCAS Timeslot Configuration #6 TCAS Timeslot Configuration #7 TCAS Timeslot Configuration #8 TCAS Timeslot Configuration #9 TCAS Timeslot Configuration #10 TCAS Timeslot Configuration #11 VALUE 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh
TCAS_BASE + 0002h TCAS_BASE + 0003h TCAS_BASE + 0004h TCAS_BASE + 0005h TCAS_BASE + 0006h TCAS_BASE + 0007h TCAS_BASE + 0008h TCAS_BASE + 0009h TCAS_BASE + 000Ah TCAS_BASE + 000Bh TCAS_BASE + 000Ch TCAS_BASE + 000Dh
6.3.10 SONET/SDH Inband Error Processor (48 x STS-1) For the 48 x STS-1 example, all 48 timeslots are provisioned. Table 79 - 48 x STS-1 SIRP Configuration
ADDRESS SIRPx_BASE + 00h SIRPx_BASE + 01h SIRPx_BASE + 02h SIRPx_BASE + 03h SIRPx_BASE + 04h SIRPx_BASE + 05h SIRPx_BASE + 06h SIRPx_BASE + 07h SIRPx_BASE + 08h SIRPx_BASE + 09h SIRPx_BASE + 0Ah SIRPx_BASE + 0Bh x= 1 to 4 DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration SIRP Timeslot #4 Configuration SIRP Timeslot #5 Configuration SIRP Timeslot #6 Configuration SIRP Timeslot #7 Configuration SIRP Timeslot #8 Configuration SIRP Timeslot #9 Configuration SIRP Timeslot #A Configuration SIRP Timeslot #B Configuration VALUE 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h
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6.3.11 Enable Blocks (48 x STS-1) Once all of the registers are set up as required, the blocks can be enabled. Table 80
ADDRESS RCAS0_BASE RCAS1_BASE RCAS2_BASE RCAS3_BASE TCAS0_BASE TCAS1_BASE TCAS2_BASE TCAS3_BASE
Enabling RCAS/TCAS Blocks
DESCRIPTION RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Table 81
ADDRESS 0050h 0060h
Enabling RXSDQ/TXSDQ Blocks
DESCRIPTION RXSDQ FIFO Reset TXSDQ FIFO Reset VALUE 0000h 0000h
For this example, TPAHOLD = 1. Table 82
ADDRESS 0040h 0048h
Enabling RXPHY/TXPHY Blocks
DESCRIPTION RXPHY Configuration TXPHY Configuration UL3 VALUE 0000h 0000h PL3 VALUE 0000h 00C0h
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6.4
Example 4: 25 PHYs/ Mixed Rate This example shows how mixed rate channels can be implemented. Figure 5 - Mixed Rate Example
UL3/PL3 INTERFACE
70-104 Mbps 32 BIT BUS
S/UNI-
(R)
PM7390-BI CB92410 2A M9845
MACH48
TRAFFIC ATM POS
1 x STS-12c/STM-3 6 x STS-3c/STM-1 9 x STS-1 9 x DS-3
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4 x STS-12 LINKS TRAFFIC
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6.4.1 Set Configuration Register The setup is for Serial Telecombus and either UL3 or PL3 Table 83
ADDRESS 0001h
Config Register (Mixed Rate), S-TCB
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0150h PL3 VALUE 01D0h
For Diagnostic loopback, the register is set up as follows: Table 84
ADDRESS 0001h
Config Register (Mixed Rate), DLOOP
DESCRIPTION Master Reset, Configuration and Global Digital Loopback UL3 VALUE 0152h PL3 VALUE 01D2h
6.4.2 Set Timeslot and Delay Registers (Mixed) The timeslot registers are set up according to their bandwidth. Table 85
ADDRESS 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh
Mixed Rate Timeslot Registers
DESCRIPTION Receive Timeslot Configuration #1 Receive Timeslot Configuration #2 Receive Timeslot Configuration #3 Receive Timeslot Configuration #4 Receive Timeslot Configuration #5 Receive Timeslot Configuration #6 Transmit Timeslot Configuration #1 Transmit Timeslot Configuration #2 Transmit Timeslot Configuration #3 Transmit Timeslot Configuration #4 Transmit Timeslot Configuration #5 Transmit Timeslot Configuration #6 VALUE 5555h 0055h 0000h AAAAh 99AAh 9999h 5555h 0055h 0000h AAAAh 99AAh 9999h
Set the RJ0DLY, this value will need to be modified depending on the system configuration.
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Table 86
ADDRESS 0011h
RX S-TCB Synchronization Delay
DESCRIPTION Receive Serial Telcombus Synchronization Delay VALUE 007Fh
Set the IWTI, IPTI, OPTI and OWTI modes in the Miscellaneous Register to bypass. Table 87
ADDRESS 0012h
Miscellaneous Register 0012h
DESCRIPTION Miscellaneous VALUE 8055h
6.4.3 Set Serial Telecombus Registers Similarly to Example 1, Section 6.1.3, the MACH48 is set up in Serial Telecombus Mode. Set up the working and protect links for High Order Path Termination (HPT) mode. The R8TDx +03h must also be set to CC34h. Set TMODEx[1..0] => 01 for HPT mode.
6.4.4 Set Up RXPHY Calendar (Mixed Rate) The calendar length for this example is 48 entries. Table 88
ADDRESS 0044h
Calendar Length Register (Mixed Rate)
DESCRIPTION RXPHY Calendar Length VALUE 002Fh
The table is set up such that it creates a weighted probability of servicing a channel depending on its bandwidth. The table below shows one possible implementation. Table 89
Calendar Entry 0 1 12 0
RXPHY Calendar Setup (Mixed Rate)
Channel # Calendar Entry 16 17 12 0 Channel # Calendar Entry 32 33 12 0 Channel #
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Calendar Entry 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel #
Calendar Entry
Channel #
Calendar Entry
Channel #
1 2 12 3 36 38 12 24 25 26 12 27 28 29
18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 12 3 36 38 12 30 31 32 12 33 34 35
34 35 36 37 38 39 40 41 42 43 44 45 46 47
1 2 12 3 36 38 12 37 39 41 12 43 45 47
6.4.5 Set Up SDQ (Mixed Rate) The table below shows how this example is set up with respect to FIFO block sizes. Table 90
Channel # PHYID[5:0]
25 x Mixed Rate Example FIFO Setup
BW Size (Block) Size (Cell) FIFO_BS [1:0] Bank FIFO# [5:0] Block_PTR [4:0] (hex)
0 1 2 3 12 24 25 26 STS-12c DS-3 DS-3 STS-1 16 4 1 2 192 48 3 1 STS-3c 48 12 2 0
0 1 2 3 16 32 33 34
00 06 0C 12 00 00 06 0C
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Channel # PHYID[5:0]
BW
Size (Block)
Size (Cell)
FIFO_BS [1:0]
Bank
FIFO# [5:0]
Block_PTR [4:0] (hex)
27 28 29 30 31 32 33 34 35 36 37 38 39 41 43 45 47
STS-1 STS-1 DS-3 DS-3 STS-1 DS-3 STS-1 DS-3 STS-1 STS-3c STS-1 STS-3c DS-3 STS-1 DS-3 STS-1 DS-3 16 4 1 3 48 16 48 12 4 12 2 1 2 3 3 3 16 4 1 2
35 36 37 38 39 40 41 42 43 48 49 50 51 53 55 57 59
12 02 08 0E 14 04 0A 10 16 00 06 0C 12 08 14 0A 16
The following is an example of how an SDQ entry is performed for a STS-12c connection. The table below shows the required register parameters to set up the PHYID = 12 FIFO. Table 91
Description PHYID FIFO NUMBER FIFO BLOCK SIZE
Example SDQ Entry Setup for PHYID 12 (STS-12c)
Value(DEC) 12 16 3 Value (BIN) 001100b 010000b 11b Register 0058h 0059h 0059h Note PHYID for the STS-12c channel Associates a FIFO# with a PHYID A Block size of 192 (as per Data Sheet Section 14)
DATA AVAILABLE THRESHOLD
3 or 95
00000011b or 01011111b
005A
= 3 for UL3 and variable for PL3 depending on required burst size, in this example=95.
These values are written to the RXSDQ in the following order: 1. Poll the BUSY bit in register 0058h until it reads 0.
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2. 3.
Write the data to the addresses as shown in Table 92. Write the Indirect Register Address with the RWB bit set to 0 and the PHYID. This will initiate the write of the indirect data registers.
Writing to the TXSDQ is done in the same manner. Table 92
ADDRESS 0059h 005Ah 0069h 006Ah
SDQ Register Setup for PHYID 12 STS-12c Entry
DESCRIPTION RXSDQ FIFO Indirect Configuration RXSDQ FIFO Indirect Data AvailableThreshold TXSDQ FIFO Indirect Configuration TXSDQ FIFO Inidrect Data Available Threshold ATM VALUE 90C0h 0303h 90C0h 0303h POS VALUE D0C0h 0703h D0C0h 5F07h
6.4.6 Receive Cell and Frame Processor Channel 12 is setup as an STS-12c/STM-4 data stream. Table 93
ADDRESS 0080h
RCFP1 Register (STS-12c)
DESCRIPTION RCFP Configuration Register #1 ATM VALUE 0111h POS VALUE 0511h
The remaining channels are set up according to the table below. Table 94
Channel # PHYID[5:0]
RTDP Register Setup (6 x STS-3c, 9 x STS-1, 9 x DS3)
RTDP BASE POS 01 ATM 02 OFFSET 03 04 05
0 1 2 3 12 24 25 26 0130h N/A N/A 0D11h N/A 0511h N/A N/A 0111h N/A 0403h 0402h 0300h 0168h 01FFh N/A N/A N/A 00F0h 0511h 0111h 0402h 0300h 0168h 01FFh
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Channel # PHYID[5:0]
RTDP BASE POS 01 ATM 0111h 02
OFFSET 03 04 05
27 28 29 30 31 32 33 34 35 36 37 38 39 41 43 45 47 0150h N/A 0511h N/A 0D11h 0111h 0111h 0111h N/A 0403h 0402h 0300h 0168h 01FFh 0511h 0111h 0130h 0511h
N/A 0511h N/A 0511h 0D11h 0511h
0111h 0402h 0111h 0111h 0111h N/A 0111h 0403h 0402h 0300h 0168h 01FFh
6.4.7 Transmit Cell and Frame Processor Similarly to the RCFP, the TCFP is used to set up Channel 12. Table 95
ADDRESS TCFP1_BASE + 00h
TCFP Register Setup (Mixed Rate)
DESCRIPTION TCFP1 Configuration VALUE 0181h
The TTDP is set up according to the table below.
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Table 96
Channel # PHYID[5:0]
TTDP Register Setup (Mixed Rate)
TTDP BASE POS 01h ATM OFFSET 02h 03h
0 1 2 3 12 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 41 43 45 47 01A0h N/A 0301h N/A 0701h N/A 0007h 0101h 016Ah 0003h 0301h 0190h N/A 0301h N/A 0301h 0701h 0301h N/A 0101h 0007h 0003h 0101h 016Ah 0003h 0301h N/A N/A 0701h N/A N/A N/A N/A N/A 0007h 0170h 0301h 0101h 016Ah 0003h
The following is an example of how a TTDP entry is performed. The table below shows the required register values to set up the PHYID = 37 entry in Table 96.
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Table 97
ADDRESS
TTDP Register Setup for PHYID 37 STS-1 Entry
DESCRIPTION TTDP Indirect Channel Select TTDP Indirect Configuration TTDP Indirect Idle/Unassigned ATM Cell Header TTDP Indirect Diagnostics ATM VALUE 0001h 0101h 016Ah 0003h POS VALUE 0001h 0301h 016Ah 0003h
TTDP2_BASE + 00h TTDP2_BASE + 01h TTDP2_BASE + 02h TTDP2_BASE + 03h
6.4.8 Receive Channel Assigner TSxMode = 001 for STS-3c/STM-1, TSx_PROV is set to 1 The registers should be written as follows for the RCAS0 block: Table 98
ADDRESS RCAS0_BASE + 0002h RCAS0_BASE + 0003h RCAS0_BASE + 0004h RCAS0_BASE + 0005h RCAS0_BASE + 0006h RCAS0_BASE + 0007h RCAS0_BASE + 0008h RCAS0_BASE + 0009h RCAS0_BASE + 000Ah RCAS0_BASE + 000Bh RCAS0_BASE + 000Ch RCAS0_BASE + 000Dh
RCAS0 Register Setup
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11 VALUE 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h
TsxMode = 000 for STS-12c/STM-4, TSx_PROV is set to 1 The registers should be written as follows for the RCAS1 block: Table 99
ADDRESS RCAS1_BASE + 0002h RCAS1_BASE + 0003h RCAS1_BASE + 0004h
RCAS1 Register Setup
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 VALUE 0010h 0010h 0010h
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ADDRESS RCAS1_BASE + 0005h RCAS1_BASE + 0006h RCAS1_BASE + 0007h RCAS1_BASE + 0008h RCAS1_BASE + 0009h RCAS1_BASE + 000Ah RCAS1_BASE + 000Bh RCAS1_BASE + 000Ch RCAS1_BASE + 000Dh
DESCRIPTION RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11
VALUE 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h
TSxMode = 011 for DS3 HDLC TSxMode = 100 for DS3 Direct Mapped ATM TSxMode = 010 for STS-1/STM-0 TSx_PROV is set to 1 The registers should be written as follows for the RCAS2 block: Table 100
ADDRESS RCAS2_BASE + 0002h RCAS2_BASE + 0003h RCAS2_BASE + 0004h RCAS2_BASE + 0005h RCAS2_BASE + 0006h RCAS2_BASE + 0007h RCAS2_BASE + 0008h RCAS2_BASE + 0009h RCAS2_BASE + 000Ah RCAS2_BASE + 000Bh RCAS2_BASE + 000Ch RCAS2_BASE + 000Dh
RCAS2 Register Setup
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11 VALUE 0070h 0091h 0052h 0053h 0054h 00B5h 00B6h 0057h 0098h 0059h 007Ah 005Bh
TSxMode = 010 for STS-1/STM-0
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TSxMode = 101 for DS3 PLCP ATM TSx_PROV is set to 1 The registers should be written as follows for the RCAS3 block: Table 101
ADDRESS RCAS3_BASE + 0002h RCAS3_BASE + 0003h RCAS3_BASE + 0004h RCAS3_BASE + 0005h RCAS3_BASE + 0006h RCAS3_BASE + 0007h RCAS3_BASE + 0008h RCAS3_BASE + 0009h RCAS3_BASE + 000Ah RCAS3_BASE + 000Bh RCAS3_BASE + 000Ch RCAS3_BASE + 000Dh
RCAS3 Register Setup
DESCRIPTION RCAS Timeslot Configuration #0 RCAS Timeslot Configuration #1 RCAS Timeslot Configuration #2 RCAS Timeslot Configuration #3 RCAS Timeslot Configuration #4 RCAS Timeslot Configuration #5 RCAS Timeslot Configuration #6 RCAS Timeslot Configuration #7 RCAS Timeslot Configuration #8 RCAS Timeslot Configuration #9 RCAS Timeslot Configuration #10 RCAS Timeslot Configuration #11 VALUE 0030h 0051h 0032h 00B3h 0030h 0055h 0032h 0097h 0030h 0059h 0032h 007Bh
If channel based diagnostic loopback is required, the following registers should be written: Table 102 Settings for Loopback
DESCRIPTION RCAS0 Channel Loopback Enable RCAS1 Channel Loopback Enable RCAS2 Channel Loopback Enable RCAS3 Channel Loopback Enable VALUE 000Fh 1001h 0FFFh 0AAFh
ADDRESS RCAS0_BASE (0x01B0h) + (0001h) RCAS1_BASE (0x01C0h) + (0001h) RCAS2_BASE (0x01D0h) + (0001h) RCAS3_BASE (0x01E0h) + (0001h)
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6.4.9 Transmit Channel Assigner The TCAS registers should be setup identically to the RCAS registers. Table 103 TCAS0 Register Setup
DESCRIPTION TCAS0 Configuration #0 TCAS0 Configuration #1 TCAS0 Configuration #2 TCAS0 Configuration #3 TCAS0 Configuration #4 TCAS0 Configuration #5 TCAS0 Configuration #6 TCAS0 Configuration #7 TCAS0 Configuration #8 TCAS0 Configuration #9 TCAS0 Configuration #10 TCAS0 Configuration #11 VALUE 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h 0030h 0031h 0032h 0033h
ADDRESS TCAS0_BASE + 0002h TCAS0_BASE + 0003h TCAS0_BASE + 0004h TCAS0_BASE + 0005h TCAS0_BASE + 0006h TCAS0_BASE + 0007h TCAS0_BASE + 0008h TCAS0_BASE + 0009h TCAS0_BASE + 000Ah TCAS0_BASE + 000Bh TCAS0_BASE + 000Ch TCAS0_BASE + 000Dh
Table 104
TCAS1 Register Setup
DESCRIPTION TCAS1 Configuration #0 TCAS1 Configuration #1 TCAS1 Configuration #2 TCAS1 Configuration #3 TCAS1 Configuration #4 TCAS1 Configuration #5 TCAS1 Configuration #6 TCAS1 Configuration #7 TCAS1 Configuration #8 TCAS1 Configuration #9 TCAS1 Configuration #10 TCAS1 Configuration #11 VALUE 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h
ADDRESS TCAS1_BASE + 0002h TCAS1_BASE + 0003h TCAS1_BASE + 0004h TCAS1_BASE + 0005h TCAS1_BASE + 0006h TCAS1_BASE + 0007h TCAS1_BASE + 0008h TCAS1_BASE + 0009h TCAS1_BASE + 000Ah TCAS1_BASE + 000Bh TCAS1_BASE + 000Ch TCAS1_BASE + 000Dh
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Table 105
TCAS2 Register Setup
DESCRIPTION TCAS2 Configuration #0 TCAS2 Configuration #1 TCAS2 Configuration #2 TCAS2 Configuration #3 TCAS2 Configuration #4 TCAS2 Configuration #5 TCAS2 Configuration #6 TCAS2 Configuration #7 TCAS2 Configuration #8 TCAS2 Configuration #9 TCAS2 Configuration #10 TCAS2 Configuration #11 VALUE 0070h 0091h 0052h 0053h 0054h 00B5h 00B6h 0057h 0098h 0059h 007Ah 005Bh
ADDRESS TCAS2_BASE + 0002h TCAS2_BASE + 0003h TCAS2_BASE + 0004h TCAS2_BASE + 0005h TCAS2_BASE + 0006h TCAS2_BASE + 0007h TCAS2_BASE + 0008h TCAS2_BASE + 0009h TCAS2_BASE + 000Ah TCAS2_BASE + 000Bh TCAS2_BASE + 000Ch TCAS2_BASE + 000Dh
Table 106
TCAS3 Register Setup
DESCRIPTION TCAS3 Configuration #0 TCAS3 Configuration #1 TCAS3 Configuration #2 TCAS3 Configuration #3 TCAS3 Configuration #4 TCAS3 Configuration #5 TCAS3 Configuration #6 TCAS3 Configuration #7 TCAS3 Configuration #8 TCAS3 Configuration #9 TCAS3 Configuration #10 TCAS3 Configuration #11 VALUE 0030h 0051h 0032h 00B3h 0030h 0055h 0032h 0097h 0030h 0059h 0032h 007Bh
ADDRESS TCAS3_BASE + 0002h TCAS3_BASE + 0003h TCAS3_BASE + 0004h TCAS3_BASE + 0005h TCAS3_BASE + 0006h TCAS3_BASE + 0007h TCAS3_BASE + 0008h TCAS3_BASE + 0009h TCAS3_BASE + 000Ah TCAS3_BASE + 000Bh TCAS3_BASE + 000Ch TCAS3_BASE + 000Dh
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6.4.10 DS-3 Setup The DS-3 channels are setup as follows: Table 107 DS-3 Channel Arrangement
CHANNEL 24 25 29 30 32 34 39 45 47 TYPE DS-3 HDLC DS-3 Direct Mapped ATM DS-3 PLCP ATM DS-3 PLCP ATM DS-3 Direct Mapped ATM DS-3 HDLC DS-3 PLCP ATM DS-3 Direct Mapped ATM DS-3 HDLC DS3_BASE 0B30h 0B90h 0D10h 0D70h 0E90h 0EF0h 10D0h 13D0h 13D0h Timeslot Location 9,1 10,1 10,2 11,2 9,3 11,3 16,1 14,3 16,3
In order to set up the channels in the above manner, the following registers must be written. Table 108 DS-3 Register Setup
DESCRIPTION DS3 FRMR Configuration DS3 TRAN Configuration VALUE 0089h 0001h
ADDRESS DS3_BASE + 08h DS3_BASE + 0Ch
For the PLCP ATM Channels, the following registers are written. Table 109 DS3 PLCP Register Setup
DESCRIPTION SPLR Configuration SPLT Configuration VALUE 0004h 0004h
ADDRESS DS3_BASE DS3_BASE + 04Ch
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6.4.11 SONET/SDH Inband Error Processor (Mixed Rate) The SIRP1 is setup for 4 x STS-3c connections. Table 110 - Mixed Rate SIRP1 Setup
DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration VALUE 0007h 0007h 0007h 0007h
ADDRESS SIRP1_BASE + 00h SIRP1_BASE + 01h SIRP1_BASE + 02h SIRP1_BASE + 03h
The SIRP2 is set up for one STS-12c connection Table 111 - Mixed Rate SIRP2 Setup
DESCRIPTION SIRP Timeslot #0 Configuration VALUE 0007h
ADDRESS SIRP2_BASE + 00h
The SIRP3 is set up for 12 x STS-1/DS-3 Connections. Table 112 - Mixed Rate SIRP3 Setup
DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration SIRP Timeslot #4 Configuration SIRP Timeslot #5 Configuration SIRP Timeslot #6 Configuration SIRP Timeslot #7 Configuration SIRP Timeslot #8 Configuration SIRP Timeslot #9 Configuration SIRP Timeslot #A Configuration SIRP Timeslot #B Configuration VALUE 00071h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h
ADDRESS SIRP3_BASE + 00h SIRP3_BASE + 01h SIRP3_BASE + 02h SIRP3_BASE + 03h SIRP3_BASE + 04h SIRP3_BASE + 05h SIRP3_BASE + 06h SIRP3_BASE + 07h SIRP3_BASE + 08h SIRP3_BASE + 09h SIRP3_BASE + 0Ah SIRP3_BASE + 0Bh
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PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
The SIRP4 is set up for 2 x STS-3c and 6 x STS-1/DS-3 connections. Table 113 - Mixed Rate SIRP4 Setup
DESCRIPTION SIRP Timeslot #0 Configuration SIRP Timeslot #1 Configuration SIRP Timeslot #2 Configuration SIRP Timeslot #3 Configuration SIRP Timeslot #6 Configuration SIRP Timeslot #7 Configuration SIRP Timeslot #9 Configuration SIRP Timeslot #11 Configuration VALUE 0007h 0007h 0007h 0007h 0007h 0007h 0007h 0007h
ADDRESS SIRP1_BASE + 00h SIRP1_BASE + 01h SIRP1_BASE + 02h SIRP1_BASE + 03h SIRP1_BASE + 05h SIRP1_BASE + 07h SIRP1_BASE + 09h SIRP1_BASE + 0Bh
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
6.4.12 Enable Blocks (Mixed Rate) Once all of the registers are set up as required, the blocks can be enabled. Table 114
ADDRESS RCAS0_BASE RCAS1_BASE RCAS2_BASE RCAS3_BASE TCAS0_BASE TCAS1_BASE TCAS2_BASE TCAS3_BASE
Enabling RCAS/TCAS Blocks
DESCRIPTION RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable RCAS12 Channel Disable TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration TCAS12 Channel Configuration VALUE 0FF0h 0FFEh 0000h 0F00h 0FF0h 0FFEh 0000h 0F00h
Table 115
ADDRESS 0050h 0060h
Enabling RXSDQ/TXSDQ Blocks
DESCRIPTION RXSDQ FIFO Reset TXSDQ FIFO Reset VALUE 0000h 0000h
Table 116
ADDRESS 0040h 0048h
Enabling RXPHY/TXPHY Blocks
DESCRIPTION RXPHY Configuration TXPHY Configuration UL3 VALUE 0000h 0000h PL3 VALUE 0000h 0040h
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
7
TCL EXAMPLE CODE The following code fragments are tcl scripts used with the S/UNI MACH48 Reference Design. They demonstrate the configurations outlined in this document. This code was used on the CHESS reference design that incorporates a SPECTRA-2488 or SPECTRA-4x155, a TBS, a TSE and the S/UNI MACH48.
7.1
General Tcl Procedures The following Tcl procedures are examples of indirect reads and writes used in configuration examples, sections 7.2-7.4.
############################################################## #PROC WAITONBUSY: This procedure will wait for a specified bit #to go to a value of one before returning. ############################################################## proc waitOnBusy {iSlot xAddress xBusyBitMask} { set busyBit 1 while {$busyBit} { set busyBit [read $iSlot $xAddress] set busyBit [expr {$busyBit & $xBusyBitMask}] } } ############################################################## #PROC SDQSETUP: This procedure will write values to the SDQ #indirect registers. ############################################################## proc sdqSetup {iSlot iSdqOffset iPhyID iFifoNum iBlockPtr iFifoBS iPosSelect iEnable iDT iBT} { #puts "Wait for the busy bit" waitOnBusy $iSlot [expr {$iSdqOffset + 0x0008}] 0x8000 set tempSdqData [expr { 0x0000 + ($iEnable << 15) + ($iPosSelect << 14) + ($iFifoNum << 8) + ($iFifoBS << 6) + ($iBlockPtr) } ] #puts [format "Writing %x to %x + 0x0009" $tempSdqData $iSdqOffset] write $iSlot [expr {$iSdqOffset + 0x0009}] $tempSdqData
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
set tempSdqData [expr { 0x0000 + ($iDT << 8) + ($iBT) } ] #puts [format "Writing %x to %x + 0x000A" $tempSdqData $iSdqOffset] write $iSlot [expr {$iSdqOffset + 0x000A}] $tempSdqData set tempSdqData [expr { 0x0000 + ($iPhyID) } ] #puts [format "Writing %x to %x + 0x0008" $tempSdqData $iSdqOffset] write $iSlot [expr {$iSdqOffset + 0x0008}] $tempSdqData } ############################################################## #PROC RTDPSETUP: This procedure will write values to the RTDP #indirect registers. ############################################################## proc rtdpSetup {iSlot iPhyID xReg1 xReg2 xReg3 xReg4 xReg5} { global RTDP0_BASE RTDP1_BASE RTDP2_BASE RTDP3_BASE if {$iPhyID < 12} { set rtdpOffset $RTDP0_BASE } elseif {$iPhyID < 24} { set rtdpOffset $RTDP1_BASE } elseif {$iPhyID < 36} { set rtdpOffset $RTDP2_BASE } else { set rtdpOffset $RTDP3_BASE } #Wait for the busy bit waitOnBusy $iSlot $rtdpOffset 0x8000 write write write write write write } $iSlot $iSlot $iSlot $iSlot $iSlot $iSlot [expr {$rtdpOffset + 0x0001}] $xReg1 [expr {$rtdpOffset + 0x0002}] $xReg2 [expr {$rtdpOffset + 0x0003}] $xReg3 [expr {$rtdpOffset + 0x0004}] $xReg4 [expr {$rtdpOffset + 0x0005}] $xReg5 $rtdpOffset [expr {int([expr {fmod($iPhyID,12)}])}]
############################################################## #PROC TTDPSETUP: This procedure will write values to the TTDP #indirect registers. ############################################################## proc ttdpSetup {iSlot iPhyID xReg1 xReg2 xReg3} { global TTDP0_BASE TTDP1_BASE TTDP2_BASE TTDP3_BASE if {$iPhyID < 12} { set ttdpOffset $TTDP0_BASE
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
} elseif {$iPhyID < 24} { set ttdpOffset $TTDP1_BASE } elseif {$iPhyID < 36} { set ttdpOffset $TTDP2_BASE } else { set ttdpOffset $TTDP3_BASE } #Wait for the busy bit waitOnBusy $iSlot $ttdpOffset 0x8000 write write write write } $iSlot $iSlot $iSlot $iSlot [expr {$ttdpOffset + 0x0001}] $xReg1 [expr {$ttdpOffset + 0x0002}] $xReg2 [expr {$ttdpOffset + 0x0003}] $xReg3 $ttdpOffset [expr {int([expr {fmod($iPhyID,12)}])}]
##################################################################### #PROC SETRXPHYCALENTRY: This procedure will write an indirect calendar #entry. ##################################################################### proc setRxphyCalEntry {iSlot iCalPos iChan} { global RXPHY_BASE # Wait for the busy bit waitOnBusy $iSlot [expr {$RXPHY_BASE + 0x0005}] 0x8000 write $iSlot [expr {$RXPHY_BASE + 0x0005}] [expr {$iChan + ($iCalPos << 8)}] } ##################################################################### #PROC RXPHYCALREPORT: This procedure will output the current data #written to the calendar. ##################################################################### proc RxphyCalReport {iSlot} { global RXPHY_BASE set numEntries [expr {[read $iSlot [expr {$RXPHY_BASE + 0x0004}]] & 0x007F}] puts [format "Calendar Size = %d" $numEntries] for {set i 0} {$i < ($numEntries+1)} {incr i 1} { # Wait for the busy bit waitOnBusy $iSlot [expr {$RXPHY_BASE + 0x0005}] 0x8000 write $iSlot [expr {$RXPHY_BASE + 0x0005}] [expr {($i << 8) + 0x0080}] # Wait for the busy bit waitOnBusy $iSlot [expr {$RXPHY_BASE + 0x0005}] 0x8000 set rxphyTempData [read $iSlot [expr {$RXPHY_BASE + 0x0005}]] set calAddr [expr {($rxphyTempData & 0x7F00) >> 8}]
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
set calData [expr {($rxphyTempData & 0x003F)}] puts [format "Rxphy calendar addr %d contains channel %d" $calAddr $calData ] } } ###################################################################### #PROC MACHINIT: This Procedure will write the required default values #to the MACH48 ###################################################################### proc MACHinit {iSlot} { global WT8TE0_BASE WT8TE1_BASE WT8TE2_BASE WT8TE3_BASE global PT8TE0_BASE PT8TE1_BASE PT8TE2_BASE PT8TE3_BASE global WR8TD0_BASE WR8TD1_BASE WR8TD2_BASE WR8TD3_BASE global PR8TD0_BASE PR8TD1_BASE PR8TD2_BASE PR8TD3_BASE puts "Initializing MACH" # Set the T8TE's to run in HPT mode set mode 0x5555 set mode2 0x0055 write $iSlot [expr {$WT8TE0_BASE + 0x0002}] write $iSlot [expr {$WT8TE0_BASE + 0x0003}] write $iSlot [expr {$WT8TE1_BASE + 0x0002}] write $iSlot [expr {$WT8TE1_BASE + 0x0003}] write $iSlot [expr {$WT8TE2_BASE + 0x0002}] write $iSlot [expr {$WT8TE2_BASE + 0x0003}] write $iSlot [expr {$WT8TE3_BASE + 0x0002}] write $iSlot [expr {$WT8TE3_BASE + 0x0003}] write $iSlot [expr {$PT8TE0_BASE + 0x0002}] write $iSlot [expr {$PT8TE0_BASE + 0x0003}] write $iSlot [expr {$PT8TE1_BASE + 0x0002}] write $iSlot [expr {$PT8TE1_BASE + 0x0003}] write $iSlot [expr {$PT8TE2_BASE + 0x0002}] write $iSlot [expr {$PT8TE2_BASE + 0x0003}] write $iSlot [expr {$PT8TE3_BASE + 0x0002}] write $iSlot [expr {$PT8TE3_BASE + 0x0003}] #Analog patches write $iSlot [expr write $iSlot [expr write $iSlot [expr write $iSlot [expr write $iSlot [expr write $iSlot [expr write $iSlot [expr write $iSlot [expr }
$mode $mode2 $mode $mode2 $mode $mode2 $mode $mode2 $mode $mode2 $mode $mode2 $mode $mode2 $mode $mode2
{$WR8TD0_BASE {$WR8TD1_BASE {$WR8TD2_BASE {$WR8TD3_BASE {$PR8TD0_BASE {$PR8TD1_BASE {$PR8TD2_BASE {$PR8TD3_BASE
+ + + + + + + +
0x3}] 0x3}] 0x3}] 0x3}] 0x3}] 0x3}] 0x3}] 0x3}]
0xCC34 0xCC34 0xCC34 0xCC34 0xCC34 0xCC34 0xCC34 0xCC34
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
7.2
Example 1: 1 x STS-48c ATM PL3
############################################################ #SETUP MACH ############################################################ #Take MACH out of Reset write mach48 0x1 0x3dc #SET TO HPT MODE, DEFAULT FIX MACHinit mach48 #Set TSI to STS-48c mode #IT IS DEFAULT ############################################################ #SETUP THE TCFP #ONLY THE FIRST BLOCK NEEDS TO BE SET UP puts "setting up TCFP" write mach48 0xb0 0x0c3 ############################################################ #SETUP THE TCAS puts "Setting up TCAS" write mach48 0x1f2 0x0010 write mach48 0x1f3 0x0010 write mach48 0x1f4 0x0010 write mach48 0x1f5 0x0010 write mach48 0x1f6 0x0010 write mach48 0x1f7 0x0010 write mach48 0x1f8 0x0010 write mach48 0x1f9 0x0010 write mach48 0x1fa 0x0010 write mach48 0x1fb 0x0010 write mach48 0x1fc 0x0010 write mach48 0x1fd 0x0010 write write write write write write write mach48 mach48 mach48 mach48 mach48 mach48 mach48 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write write write write write write write write write write write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x209 0x20a 0x20b 0x20c 0x20d 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21a 0x21b 0x21c 0x21d 0x222 0x223 0x224 0x225 0x226 0x227 0x228 0x229 0x22a 0x22b 0x22c 0x22d
0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010
############################################################ #SETUP THE RXPHY #Set the Calendar Length- ONLY ONE PHY - STS-48c write mach48 0x44 0 setRxphyCalEntry mach48 0 0 ############################################################ #SETUP THE SDQ's puts "setting up SDQ's" # iSlot iSdqOffset iPhyID iFifoNum iBlockPtr iFifoBS iPosSelect iEnable iDT iBT sdqSetup mach48 0x50 0 0 0 3 0 1 3 3 sdqSetup mach48 0x60 0 0 0 3 0 1 3 3
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
############################################################ #SETUP THE RCFP - FOR ATM TRAFFIC, POS = 0x041b #ONLY THE FIRST BLOCK NEEDS TO BE SET UP puts "setting up RCFP" write mach48 0x70 0x011b ############################################################ #SETUP THE RCAS puts "Setting up RCAS" write mach48 0x1b2 0x0010 write mach48 0x1b3 0x0010 write mach48 0x1b4 0x0010 write mach48 0x1b5 0x0010 write mach48 0x1b6 0x0010 write mach48 0x1b7 0x0010 write mach48 0x1b8 0x0010 write mach48 0x1b9 0x0010 write mach48 0x1ba 0x0010 write mach48 0x1bb 0x0010 write mach48 0x1bc 0x0010 write mach48 0x1bd 0x0010 write mach48 0x1c2 0x0010 write mach48 0x1c3 0x0010 write mach48 0x1c4 0x0010 write mach48 0x1c5 0x0010 write mach48 0x1c6 0x0010 write mach48 0x1c7 0x0010 write mach48 0x1c8 0x0010 write mach48 0x1c9 0x0010 write mach48 0x1ca 0x0010 write mach48 0x1cb 0x0010 write mach48 0x1cc 0x0010 write mach48 0x1cd 0x0010 write mach48 0x1d2 0x0010 write mach48 0x1d3 0x0010 write mach48 0x1d4 0x0010 write mach48 0x1d5 0x0010 write mach48 0x1d6 0x0010 write mach48 0x1d7 0x0010 write mach48 0x1d8 0x0010 write mach48 0x1d9 0x0010 write mach48 0x1da 0x0010 write mach48 0x1db 0x0010 write mach48 0x1dc 0x0010 write mach48 0x1dd 0x0010 write mach48 0x1e2 0x0010 write mach48 0x1e3 0x0010
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x1e4 0x1e5 0x1e6 0x1e7 0x1e8 0x1e9 0x1ea 0x1eb 0x1ec 0x1ed
0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010 0x0010
############################################################ #SETUP THE SIRP write mach48 0x14c0 0x0007 ############################################################ #ENABLE the BLOCKS puts "Enabling Blocks" #Enable SDQs write mach48 0x60 0 write mach48 0x50 0 #Enable TXPHY, RXPHY write mach48 0x48 0x40 write mach48 0x40 0 puts "Enable RCAS" write mach48 0x1b0 0 write mach48 0x1c0 0 write mach48 0x1d0 0 write mach48 0x1e0 0 ############################################################ TSEinit mapTSE3 tse1 portEnable4 portEnable5 ############################################################ #SETUP THE DELAYS FOR THE SYSTEM after 1000 write mach48 0x11 127 write mach48 0x13 30 write tse1 0x40 60 write tbs5 0x5 127 #Center the FIFOs for the LVDS Links center puts "Enabling TCAS"
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
after write write write write
1000 mach48 mach48 mach48 mach48
0x1f0 0x200 0x210 0x220
0 0 0 0
7.3
Example 2: 16 x STS-3c ATM PL3
#Sets HPT mode and enables R8TDs MACHinit mach48 #Take the MACH out of reset. Set RHPP_EN,SEREN,DLOOP,POSL3,RWSEL_EN write mach48 0x1 0x3d0 #Set TSI into BYPASS mode write mach48 0x12 0x8055 #Setup TTDP on Chan 0-3,12-15,24-27,36-39 puts "setting up TTDP" ttdpSetup mach48 0 0x0185 0x016A 0x0003 ttdpSetup mach48 1 0x0185 0x016A 0x0003 ttdpSetup mach48 2 0x0185 0x016A 0x0003 ttdpSetup mach48 3 0x0185 0x016A 0x0003 ttdpSetup mach48 12 0x0185 0x016A 0x0003 ttdpSetup mach48 13 0x0185 0x016A 0x0003 ttdpSetup mach48 14 0x0185 0x016A 0x0003 ttdpSetup mach48 15 0x0185 0x016A 0x0003 ttdpSetup mach48 24 0x0185 0x016A 0x0003 ttdpSetup mach48 25 0x0185 0x016A 0x0003 ttdpSetup mach48 26 0x0185 0x016A 0x0003 ttdpSetup mach48 27 0x0185 0x016A 0x0003 ttdpSetup mach48 36 0x0185 0x016A 0x0003 ttdpSetup mach48 37 0x0185 0x016A 0x0003 ttdpSetup mach48 38 0x0185 0x016A 0x0003 ttdpSetup mach48 39 0x0185 0x016A 0x0003
#Setup TCAS_0 for 4xSTS-3c channels puts "setting up TCAS" write mach48 0x1f2 0x0030 write mach48 0x1f3 0x0031 write mach48 0x1f4 0x0032 write mach48 0x1f5 0x0033 write mach48 0x1f6 0x0030 write mach48 0x1f7 0x0031 write mach48 0x1f8 0x0032 write mach48 0x1f9 0x0033
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x1fa 0x1fb 0x1fc 0x1fd 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20a 0x20b 0x20c 0x20d 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21a 0x21b 0x21c 0x21d 0x222 0x223 0x224 0x225 0x226 0x227 0x228 0x229 0x22a 0x22b 0x22c 0x22d
0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033
################################################################ puts "Setting up RXPHY Calendar "
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
# Set the calendar length to 48 write mach48 0x0044 0x002F setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 0 12 24 36 1 13 25 37 2 14 26
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry
mach48 mach48 mach48 mach48 mach48
43 44 45 46 47
38 3 15 27 39
################################################################ ################################################################ puts "Setting up the SDQ" # iSlot iSdqOffset iPhyID iFifoNum iBlockPtr iFifoBS iPosSelect iEnable iDT iBT # sdqSetup mach48 0x50 0 0 0 2 0 1 3 3 sdqSetup mach48 0x50 1 1 6 2 0 1 3 3 sdqSetup mach48 0x50 2 2 12 2 0 1 3 3 sdqSetup mach48 0x50 3 3 18 2 0 1 3 3 sdqSetup mach48 0x50 12 0 0 2 0 1 3 3 sdqSetup mach48 0x50 13 1 6 2 0 1 3 3 sdqSetup mach48 0x50 14 2 12 2 0 1 3 3 sdqSetup mach48 0x50 15 3 18 2 0 1 3 3 sdqSetup mach48 0x50 24 0 0 2 0 1 3 3 sdqSetup mach48 0x50 25 1 6 2 0 1 3 3 sdqSetup mach48 0x50 26 2 12 2 0 1 3 3 sdqSetup mach48 0x50 27 3 18 2 0 1 3 3 sdqSetup mach48 0x50 36 0 0 2 0 1 3 3 sdqSetup mach48 0x50 37 1 6 2 0 1 3 3 sdqSetup mach48 0x50 38 2 12 2 0 1 3 3 sdqSetup mach48 0x50 39 3 18 2 0 1 3 3
################################################################# sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0 1 2 3 12 13 14 15 24 25 26 27 36 37 38 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 0 6 12 18 0 6 12 18 0 6 12 18 0 6 12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
sdqSetup mach48 0x60 39 3 18 2 0 1 3 3 ################################################################# #Setup RTDP on Chan 0-3 puts "Setting up RTDP" rtdpSetup mach48 0 0x011b rtdpSetup mach48 1 0x011b rtdpSetup mach48 2 0x011b rtdpSetup mach48 3 0x011b rtdpSetup mach48 12 0x011b rtdpSetup mach48 13 0x011b rtdpSetup mach48 14 0x011b rtdpSetup mach48 15 0x011b rtdpSetup mach48 24 0x011b rtdpSetup mach48 25 0x011b rtdpSetup mach48 26 0x011b rtdpSetup mach48 27 0x011b rtdpSetup mach48 36 0x011b rtdpSetup mach48 37 0x011b rtdpSetup mach48 38 0x011b rtdpSetup mach48 39 0x011b
0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402
0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300
0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168
0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF
#Receive Timeslot Registers (0x0002->0x0007) puts "Setting up timeslot registers" write mach48 0x0002 0x5555 write mach48 0x0003 0x5555 write mach48 0x0004 0x5555 write mach48 0x0005 0x5555 write mach48 0x0006 0x5555 write mach48 0x0007 0x5555 #Transmit Timeslot Registers (0x0008->0x000D) write mach48 0x0008 0x5555 write mach48 0x0009 0x5555 write mach48 0x000a 0x5555 write mach48 0x000b 0x5555 write mach48 0x000c 0x5555 write mach48 0x000d 0x5555 #Setup RCAS_0 for 4xSTS-3c channels puts "Setting up RCAS" write mach48 0x1b2 0x0030 write mach48 0x1b3 0x0031 write mach48 0x1b4 0x0032 write mach48 0x1b5 0x0033 write mach48 0x1b6 0x0030 write mach48 0x1b7 0x0031
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PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x1b8 0x1b9 0x1ba 0x1bb 0x1bc 0x1bd 0x1c2 0x1c3 0x1c4 0x1c5 0x1c6 0x1c7 0x1c8 0x1c9 0x1ca 0x1cb 0x1cc 0x1cd 0x1d2 0x1d3 0x1d4 0x1d5 0x1d6 0x1d7 0x1d8 0x1d9 0x1da 0x1db 0x1dc 0x1dd 0x1e2 0x1e3 0x1e4 0x1e5 0x1e6 0x1e7 0x1e8 0x1e9 0x1ea 0x1eb 0x1ec 0x1ed
0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033 0x0030 0x0031 0x0032 0x0033
puts "Setting up the SIRP"
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
84
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x14c0 0x14c1 0x14c2 0x14c3 0x14d0 0x14d1 0x14d2 0x14d3 0x14e0 0x14e1 0x14e2 0x14e3 0x14f0 0x14f1 0x14f2 0x14f3
0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007
#Set up RHPP write mach48 write mach48 write mach48 write mach48
for STS-3c Traffic 0x1602 0xf 0x1682 0xf 0x1702 0xf 0x1782 0xf
#Enable BLOCKS:TCAS,RCAS puts "Enable TX,RX SDQs" write mach48 0x60 0 write mach48 0x50 0 puts "Enable TX,RX Phys" write mach48 0x48 0x0040 write mach48 0x40 0 puts "Enabling RCAS" write mach48 0x1b0 0xff0 write mach48 0x1c0 0xff0 write mach48 0x1d0 0xff0 write mach48 0x1e0 0xff0 TSEinit mapTSE3 tse1 portEnable4 portEnable5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
85
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
#Setup Delays for the system puts "setting up system delays" write mach48 0x11 127 write mach48 0x13 30 write tse1 0x40 60 write tbs5 0x5 127 center puts "Enabling TCAS" write mach48 0x1f0 0xff0 write mach48 0x200 0xff0 write mach48 0x210 0xff0 write mach48 0x220 0xff0
7.4
Example 3: 48 x STS-1 ATM PL3
#This script will set the MACH48 up in 48 x STS-1 mode.
#Sets HPT mode and enables R8TDs MACHinit mach48 #Take the MACH out of reset. Set RHPP_EN,SEREN,POSL3,RWSEL_EN write mach48 0x1 0x3d0 #Set TSI into BYPASS mode write mach48 0x12 0x8055 #Setup TTDP puts "setting up ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48 ttdpSetup mach48
TTDP" 0 0x0185 1 0x0185 2 0x0185 3 0x0185 4 0x0185 5 0x0185 6 0x0185 7 0x0185 8 0x0185 9 0x0185 10 0x0185 11 0x0185
0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A
0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003
ttdpSetup mach48 12
0x0185 0x016A 0x0003
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
86
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup ttdpSetup
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185 0x0185
0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A 0x016A
0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003 0x0003
############################################################## #SETUP THE TRANSMIT CHANNEL ASSIGNER #Setup TCAS for 48xSTS-1 channels puts "setting up TCAS_0" write mach48 0x1f2 0x0050 write mach48 0x1f3 0x0051 write mach48 0x1f4 0x0052 write mach48 0x1f5 0x0053
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
87
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x1f6 0x1f7 0x1f8 0x1f9 0x1fa 0x1fb 0x1fc 0x1fd
0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005a 0x005b
puts "setting up TCAS_1" write mach48 0x202 0x0050 write mach48 0x203 0x0051 write mach48 0x204 0x0052 write mach48 0x205 0x0053 write mach48 0x206 0x0054 write mach48 0x207 0x0055 write mach48 0x208 0x0056 write mach48 0x209 0x0057 write mach48 0x20a 0x0058 write mach48 0x20b 0x0059 write mach48 0x20c 0x005a write mach48 0x20d 0x005b puts "setting up TCAS_2" write mach48 0x212 0x0050 write mach48 0x213 0x0051 write mach48 0x214 0x0052 write mach48 0x215 0x0053 write mach48 0x216 0x0054 write mach48 0x217 0x0055 write mach48 0x218 0x0056 write mach48 0x219 0x0057 write mach48 0x21a 0x0058 write mach48 0x21b 0x0059 write mach48 0x21c 0x005a write mach48 0x21d 0x005b puts "setting up TCAS_3" write mach48 0x222 0x0050 write mach48 0x223 0x0051 write mach48 0x224 0x0052 write mach48 0x225 0x0053 write mach48 0x226 0x0054 write mach48 0x227 0x0055 write mach48 0x228 0x0056 write mach48 0x229 0x0057 write mach48 0x22a 0x0058
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
88
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write mach48 0x22b 0x0059 write mach48 0x22c 0x005a write mach48 0x22d 0x005b ################################################################ puts "Setting up RXPHY Calendar " # Set the calendar length to 48 write mach48 0x0044 47 setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 4 16 28 40 5 17 29 41 6 18 30 42 7 19 31 43 8 20 32 44 9
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
89
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry setRxphyCalEntry
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
37 38 39 40 41 42 43 44 45 46 47
21 33 45 10 22 34 46 11 23 35 47
################################################################ ################################################################ puts "Setting up the SDQ" # iSlot iSdqOffset iPhyID iFifoNum iBlockPtr iFifoBS iPosSelect iEnable iDT iBT #RXSDQ sdqSetup mach48 0x50 0 0 0 1 0 1 3 3 sdqSetup mach48 0x50 1 1 6 1 0 1 3 3 sdqSetup mach48 0x50 2 2 12 1 0 1 3 3 sdqSetup mach48 0x50 3 3 18 1 0 1 3 3 sdqSetup mach48 0x50 4 4 2 1 0 1 3 3 sdqSetup mach48 0x50 5 5 8 1 0 1 3 3 sdqSetup mach48 0x50 6 6 14 1 0 1 3 3 sdqSetup mach48 0x50 7 7 20 1 0 1 3 3 sdqSetup mach48 0x50 8 8 4 1 0 1 3 3 sdqSetup mach48 0x50 9 9 10 1 0 1 3 3 sdqSetup mach48 0x50 10 10 16 1 0 1 3 3 sdqSetup mach48 0x50 11 11 22 1 0 1 3 3 sdqSetup mach48 0x50 12 16 0 1 0 1 3 3 sdqSetup mach48 0x50 13 17 6 1 0 1 3 3 sdqSetup mach48 0x50 14 18 12 1 0 1 3 3 sdqSetup mach48 0x50 15 19 18 1 0 1 3 3 sdqSetup mach48 0x50 16 20 2 1 0 1 3 3 sdqSetup mach48 0x50 17 21 8 1 0 1 3 3 sdqSetup mach48 0x50 18 22 14 1 0 1 3 3 sdqSetup mach48 0x50 19 23 20 1 0 1 3 3 sdqSetup mach48 0x50 20 24 4 1 0 1 3 3 sdqSetup mach48 0x50 21 25 10 1 0 1 3 3 sdqSetup mach48 0x50 22 26 16 1 0 1 3 3 sdqSetup mach48 0x50 23 27 22 1 0 1 3 3 sdqSetup mach48 0x50 24 32 0 1 0 1 3 3 sdqSetup mach48 0x50 25 33 6 1 0 1 3 3 sdqSetup mach48 0x50 26 34 12 1 0 1 3 3 sdqSetup mach48 0x50 27 35 18 1 0 1 3 3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
90
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
36 37 38 39 40 41 42 43 48 49 50 51 52 53 54 55 56 57 58 59
2 8 14 20 4 10 16 22 0 6 12 18 2 8 14 20 4 10 16 22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
################################################################# # iSlot iSdqOffset iPhyID iFifoNum iBlockPtr iFifoBS iPosSelect #iEnable iDT iBT #TXSDQ sdqSetup mach48 0x60 0 0 0 1 0 1 3 3 sdqSetup mach48 0x60 1 1 6 1 0 1 3 3 sdqSetup mach48 0x60 2 2 12 1 0 1 3 3 sdqSetup mach48 0x60 3 3 18 1 0 1 3 3 sdqSetup mach48 0x60 4 4 2 1 0 1 3 3 sdqSetup mach48 0x60 5 5 8 1 0 1 3 3 sdqSetup mach48 0x60 6 6 14 1 0 1 3 3 sdqSetup mach48 0x60 7 7 20 1 0 1 3 3 sdqSetup mach48 0x60 8 8 4 1 0 1 3 3 sdqSetup mach48 0x60 9 9 10 1 0 1 3 3 sdqSetup mach48 0x60 10 10 16 1 0 1 3 3 sdqSetup mach48 0x60 11 11 22 1 0 1 3 3 sdqSetup mach48 0x60 12 16 0 1 0 1 3 3 sdqSetup mach48 0x60 13 17 6 1 0 1 3 3 sdqSetup mach48 0x60 14 18 12 1 0 1 3 3 sdqSetup mach48 0x60 15 19 18 1 0 1 3 3 sdqSetup mach48 0x60 16 20 2 1 0 1 3 3 sdqSetup mach48 0x60 17 21 8 1 0 1 3 3 sdqSetup mach48 0x60 18 22 14 1 0 1 3 3 sdqSetup mach48 0x60 19 23 20 1 0 1 3 3 sdqSetup mach48 0x60 20 24 4 1 0 1 3 3 sdqSetup mach48 0x60 21 25 10 1 0 1 3 3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
91
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup sdqSetup
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
26 27 32 33 34 35 36 37 38 39 40 41 42 43 48 49 50 51 52 53 54 55 56 57 58 59
16 22 0 6 12 18 2 8 14 20 4 10 16 22 0 6 12 18 2 8 14 20 4 10 16 22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
################################################################# #Setup RTDP on Chan 0-11,12-23,24-35,36-47 puts "Setting up RTDP" rtdpSetup mach48 0 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 1 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 2 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 3 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 4 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 5 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 6 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 7 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 8 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 9 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 10 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup mach48 11 0x011b 0x0402 0x0300 0x0168 0x01FF rtdpSetup rtdpSetup rtdpSetup rtdpSetup mach48 mach48 mach48 mach48 12 13 14 15 0x011b 0x011b 0x011b 0x011b 0x0402 0x0402 0x0402 0x0402 0x0300 0x0300 0x0300 0x0300 0x0168 0x0168 0x0168 0x0168 0x01FF 0x01FF 0x01FF 0x01FF
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
92
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup rtdpSetup
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b 0x011b
0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402 0x0402
0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300 0x0300
0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168 0x0168
0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF 0x01FF
####################################################### #Receive Timeslot Registers (0x0002->0x0007) puts "Setting up timeslot registers" write mach48 0x0002 0xaaaa write mach48 0x0003 0xaaaa write mach48 0x0004 0xaaaa write mach48 0x0005 0xaaaa write mach48 0x0006 0xaaaa write mach48 0x0007 0xaaaa #Transmit Timeslot Registers (0x0008->0x000D) write mach48 0x0008 0xaaaa
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
93
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write mach48 0x0009 0xaaaa write mach48 0x000a 0xaaaa write mach48 0x000b 0xaaaa write mach48 0x000c 0xaaaa write mach48 0x000d 0xaaaa ################################################## #Setup RCAS for 48xSTS-1 channels puts "Setting up RCAS_0" write mach48 0x1b2 0x0050 write mach48 0x1b3 0x0051 write mach48 0x1b4 0x0052 write mach48 0x1b5 0x0053 write mach48 0x1b6 0x0054 write mach48 0x1b7 0x0055 write mach48 0x1b8 0x0056 write mach48 0x1b9 0x0057 write mach48 0x1ba 0x0058 write mach48 0x1bb 0x0059 write mach48 0x1bc 0x005a write mach48 0x1bd 0x005b puts "Setting up RCAS_1" write mach48 0x1c2 0x0050 write mach48 0x1c3 0x0051 write mach48 0x1c4 0x0052 write mach48 0x1c5 0x0053 write mach48 0x1c6 0x0054 write mach48 0x1c7 0x0055 write mach48 0x1c8 0x0056 write mach48 0x1c9 0x0057 write mach48 0x1ca 0x0058 write mach48 0x1cb 0x0059 write mach48 0x1cc 0x005a write mach48 0x1cd 0x005b puts "Setting up RCAS_2" write mach48 0x1d2 0x0050 write mach48 0x1d3 0x0051 write mach48 0x1d4 0x0052 write mach48 0x1d5 0x0053 write mach48 0x1d6 0x0054 write mach48 0x1d7 0x0055 write mach48 0x1d8 0x0056 write mach48 0x1d9 0x0057 write mach48 0x1da 0x0058 write mach48 0x1db 0x0059 write mach48 0x1dc 0x005a write mach48 0x1dd 0x005b puts "Setting up RCAS_3"
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
94
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write mach48 0x1e2 0x0050 write mach48 0x1e3 0x0051 write mach48 0x1e4 0x0052 write mach48 0x1e5 0x0053 write mach48 0x1e6 0x0054 write mach48 0x1e7 0x0055 write mach48 0x1e8 0x0056 write mach48 0x1e9 0x0057 write mach48 0x1ea 0x0058 write mach48 0x1eb 0x0059 write mach48 0x1ec 0x005a write mach48 0x1ed 0x005b ################################################### puts "Setting up the SIRP" write mach48 0x14c0 0x0007 write mach48 0x14c1 0x0007 write mach48 0x14c2 0x0007 write mach48 0x14c3 0x0007 write mach48 0x14c4 0x0007 write mach48 0x14c5 0x0007 write mach48 0x14c6 0x0007 write mach48 0x14c7 0x0007 write mach48 0x14c8 0x0007 write mach48 0x14c9 0x0007 write mach48 0x14ca 0x0007 write mach48 0x14cb 0x0007 write write write write write write write write write write write write write write write write write write write mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 0x14d0 0x14d1 0x14d2 0x14d3 0x14d4 0x14d5 0x14d6 0x14d7 0x14d8 0x14d9 0x14da 0x14db 0x14e0 0x14e1 0x14e2 0x14e3 0x14e4 0x14e5 0x14e6 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
95
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write write write write write write write write write write write write write write
mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48 mach48
0x14e7 0x14e8 0x14e9 0x14ea 0x14eb 0x14f0 0x14f1 0x14f2 0x14f3 0x14f4 0x14f5 0x14f6 0x14f7 0x14f8 0x14f9 0x14fa 0x14fb
0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007 0x0007
############################################# #Enable BLOCKS:SDQs,PHYs,RCAS puts "Enable TX,RX SDQs" write mach48 0x60 0 write mach48 0x50 0 puts "Enable TX,RX Phys" write mach48 0x48 0x00c0 write mach48 0x40 0 puts "Enabling RCAS" write mach48 0x1b0 0 write mach48 0x1c0 0 write mach48 0x1d0 0 write mach48 0x1e0 0 ##################################################### TSEinit mapTSE3 tse1 portEnable4 portEnable5 #################################################### #Setup Delays for the system puts "setting up system delays" after 1000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
96
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
write write write write center
mach48 0x11 127 mach48 0x13 30 tse1 0x40 60 tbs5 0x5 127
#Turn off frame pulse in MACH and SP155 puts "Switching off SP155 and MACH FP" write fpga 0x40 0 puts "Enabling TCAS" after 1000 write mach48 0x1f0 0 write mach48 0x200 0 write mach48 0x210 0 write mach48 0x220 0 delay
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
97
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
98
PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2
PM7390 S/UNI MACH48
CONFIGURING THE PM7390 S/UNI MACH48
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2001532 (P2) ref PMC-1990823(P3) Issue date: Oct 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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