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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
PM5313/PM5363
SPECTRA-622 WITH-TUPP-PLUS-622
REFERENCE DESIGN
PRELIMINARY ISSUE 2: DECEMBER 1999
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 1 2 Issue Date Aug. 1999 Dec. 1999 Details of Change Document created. Document revised to reflect changes made to the schematic for revision of reference design. A section was added containing VHDL code for the FPGA as well as a more detailed description of the FPGA. The following changes were made to the schematic: -Addition of serial EPROM for programming of the FPGA. -Modified reference oscillator circuitry to accommodate PECL reference Oscillator, as well as HCMOS/TTL Oscillator. -Modified reset circuitry. -Corrected several minor schematic errors
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
CONTENTS 1 2 3 4 5 6 7 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES .................................................................... 5 BLOCK DIAGRAM ................................................................................... 7 FUNCTIONAL DESCRIPTION................................................................. 8 7.1 7.2 7.3 PM5313 SPECTRA-622................................................................ 9 PM5363 TUPP-PLUS-622............................................................. 9 FPGA ...........................................................................................11 7.3.1 STS-12 ADD DROP MUX FPGA .......................................11 7.3.2 77.76 MHZ TELECOM BUS INTERFACE FPGA ............. 21 7.4 7.5 BUFFERS.................................................................................... 22 PLX TECHNOLOGY 9050 PCI BRIDGE ..................................... 22 7.5.1 SERIAL EEPROM ............................................................ 22 7.6 7.7 7.8 7.9 8 REFERENCE CLOCKS .............................................................. 25 POWER....................................................................................... 25 TELECOM BUS........................................................................... 25 MECHANICAL FORM FACTOR .................................................. 25
IMPLEMENTATION DESCRIPTION ...................................................... 34 8.1 8.2 ROOT DRAWING, SHEET 1 ....................................................... 34 OPTICS _REFCLK_BLOCK, SHEET 2....................................... 34
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
8.3 8.4 8.5 8.6 9 10
SPECTRA_622 _BLOCK, SHEET 3 & 4 ..................................... 35 TUPP_622_BLOCK, SHEETS 5, & 6.......................................... 35 FPGA BLOCK SHEET, 7............................................................. 36 SYS_INTERFACE , SHEET 8, 9, & 10........................................ 37
SCHEMATICS AND LAYOUT ................................................................ 38 BILL OF MATERIAL ............................................................................... 39
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
LIST OF FIGURES FIGURE 1 STS-12 ADM IN A UPSR SONET RING NETWORK ....................... 5 FIGURE 2 STS-12 ADD DROP MUX ................................................................ 6 FIGURE 3 REFERENCE DESIGN BLOCK DIAGRAM. .................................... 7 FIGURE 4 STS-12 ADD DROP MUX FPGA.....................................................11 FIGURE 5 77.76 MHZ TELECOM BUS FPGA................................................ 21
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 EEPROM CONTENTS................................................................... 23 J3 PIN ASSIGNMENT.................................................................... 26 J5 PIN ASSIGNMENT.................................................................... 27 J3 AND J5 SIGNAL DESCRIPTION............................................... 28 FPGA CONFIGURATION JUMPER SETTINGS ............................ 36 BILL OF MATERIALS..................................................................... 39
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
1
DEFINITIONS LOS Loss of signal. When a SONET receiver detects an all-zeros pattern for 10 microseconds or longer, this constitutes a LOS failure. It indicates that the upstream transmitter has failed. This condition is cleared when two consecutive valid frames are received. Loss of frame. The absence of valid framing pattern for 3 milliseconds leads to a LOF failure condition. This is cleared when two consecutive valid A1/A2 framing patterns are received. Alarm indication signal. This condition can occur in response to one of the conditions above. The SONET signal format provides AISs for the line (AIS-L), STS Path (AIS-P), and VT Path (AIS-V) layers. Line remote defect indication. A signal returned to the transmitting Line Terminating Equipment (LTE) upon receipt of an AIS code or detection of an incoming line defect at the receiving LTE. The SONET signal format provides RDIs for the line (RDI-L), STS Path (RDI-P), and VT Path. Signal Degrade. A "soft failure" condition resulting from the Line BER exceeding a pre-selected threshold. Bit Error Rate Signal Fail. A "hard failure" condition detected on the incoming OC-N signal.
LOF
AIS
RDI
SD BER SF
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
2
FEATURES * * 33 MHz CompactPCI (cPCI) interface. Implements STS-12 Add-Drop MUX and STS-12 terminal MUX using the PM5313 SPECTRA-622 OC-12 SONET/SDH payload extractor aligner and the TUPP-PLUS-622 SONET/SDH tributary unit payload processor. OC-12 line side interface can accommodate both 5 Volt and 3.3 Volt Optical transceivers. 3.3 Volt CMOS telecom bus interface to the TUPP-PLUS-622 system drop bus and to the SPECTRA-622 system add bus. * Telecom bus can be configured to operate in either the single STS-12 (STM-4) at 77.76 MHz or as four STS-3s (STM-1) at 19.44 MHz.
* *
* *
3.3 Volt CMOS DS3 interface to the SPECTRA-622 drop and add bus. Custom FPGA to provides data throughput and APS functions for the STS-12 add-drop MUX application. * * * Can be programmed via the cPCI bus or through XCHECKER port. R/W registers for configuration of Add-Drop MUX and APS control and monitor. Interfaces to SPECTRA-622 receive and transmit overhead and alarm signals for custom applications.
*
Low cost 77.76 MHz reference uses a standard fundamental mode, inexpensive crystal or standard HCMOS/TTL oscillator. * * 77.76 MHz reference clock can be supplied by onboard oscillator or by external source.
*
PLL clock drivers for the 19.44 MHz and 77.76 MHz system clocks.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
3 * * *
APPLICATIONS Tributary pointer processing and performance monitoring. SONET/SDH Add Drop Multiplexers - STS-12 (STM-4/AU-3), STS-12 (STM-4/AU-4) or STS12c (STM-4-4c) SONET/SDH Terminal Multiplexers. - STS-12 (STM-4/AU-3), STS-12 (STM-4/AU-4) or STS12c (STM-4-4c)
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
4
REFERENCES 1. PCI Industrial Computers Manufacturers Group (PICMG), "CompactPCI Specification 2.0 R 2.1", Wakefield MA, September 1997. 2. PMC-Sierra Inc., PMC-981162, "SONET/SDH Payload Extractor/Aligner for 622 Mbits/s", November 1998, Issue 1. 3. PMC-Sierra Inc. , PMC-981421, "SONET/SDH Tributary Unit Payload Processor For 622 Mbit/s Interfaces", December 1998, Issue 1. 4. American National Standard for Telecommunications (ANSI) Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, and formats, "T1.105-1995", New York, NY, October 27, 1995
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
5
APPLICATION EXAMPLES The SPECTRA-622 WITH TUPP-PLUS-622 reference design can be used in conjunction with the TEMUX reference design to implement an STS-12 Add Drop MUX in a Unidirectional Path Switched Ring (UPSR) as shown in Fig. 1 below or as an STS-12 Terminal MUX in a point to point network. Figure 1 STS-12 ADM in a UPSR SONET Ring Network
STS-12 ADM
TEMUX Reference Design
Drop
Add
SONET NODE
OC-12
SPECTRA-622 With TUPP-Plus622 Reference Design
SPECTRA-622 With TUPP-Plus622 Reference Design
SONET NODE
Drop
TEMUX Reference Design
Add
STS-12 ADM
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
When used as an add Drop MUX the SPECTRA-622 would be configured to operate in the quad Add/Drop bus interface STS-3 (STM-1) mode and TUPPPLUS-622 would be configured in the STS-3 (STM-1) mode with the telecom bus clocked at 19.44 MHz. The FPGA would be configured to loop-back the throughput STS-1s from the drop bus to the add bus and perform APS related functions. When configured to implement a Terminal MUX, the SPECTRA-622 WITH TUPP-PLUS-622 reference design would be configured as an ADM with all traffic dropped. Figure 2 STS-12 Add Drop MUX
OC-12
19.44 MHZ CLK
LREFCLK Drop TX
RX
Drop
Drop
Ring Ctrl. Spectra-622/ TUPP+622 Ref. Design 19.44 MHz CLK
Ring Ctrl.
19.44 MHz CLK Spectra-622/ TUPP+622 Ref. Design Ring Ctrl. TEMUX
CPCI Proccessor Card
Ring Ctrl.
Add TX
Add RX Add
OC-12
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
6
BLOCK DIAGRAM Figure 3 Reference Design Block Diagram.
DD DC1J1V1 DPL DDP 32 4 4 4 32 4 4 DD DC1J1V1 DPL DDP DTPL DTV5 GSCLK_FP ADDR DATA 52 52
PM5363 TUPP+622
SCLK / HSCLK
4 4 4
DCK / ACK ODL HP5208
OC-12
PM5313 Spectra-622
32 4 4 4
FPGA XC4028XL
CLK AD AC1J1V1 APL ADP REF_OUT REF_TTL EXT_REF SCLK ADDR DATA 44 LAC1 4
AD AC1J1V1 APL 77.77MHz PECL OSC. ADP REFCLK ADDR DATA
B U F F E R S
44 4
T E L E C O M B U S
EXT REF
TTL/PECL
8
14 3.3/2.5V Regulators PLX Tech 9050 PCI Bridge Controller 32 32
C P C I
77.76 MHz HCMOS/TTL REF/SCLK OSC.
ROBO Clocks (19.44/77.76 MHz)
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
7
FUNCTIONAL DESCRIPTION The PM5313 SPECTRA-622 takes the OC-12 SONET/SDH serial bit stream from the HP5208 optical transceiver and recovers clock, data and processes section, line, and path overhead. The telecom drop bus from the SPECTRA-622 interfaces directly to the input side of the PM5363 TUPP-PLUS-622. The TUPPPLUS-622 will perform tributary processing and frame alignment on the SONET/SDH STS-12 byte serial data stream. The TUPP-PLUS-622 will output a frame aligned single STS-12 (STM-4) clocked at 77.76 MHz or a quad STS-3 (STM-1) clocked at 19.44 MHz and this will be clocked into the FPGA. When the SPECTRA-622 WITH TUPP reference design is configured to implement an add drop MUX, both TUPP-PLUS-622 and the SPECTRA-622 will be configured to operate in the Quad STS-3 (STM-1) mode. The payload will be clocked into the FPGA from the TUPP-PLUS-622 drop bus output on the rising edge of the 19.44 MHz clock . The entire payload will be clocked out of the FPGA onto the telecom interface (J4, J5) drop side. Traffic to be inserted into the payload will be clocked into the FPGA from the telecom interface add side on the rising edge of 19.44 MHz clock and inserted into the appropriate STS-12 time slot along with the throughput data. The aggregate data will be clocked out of the FPGA onto the SPECTRA-622 add bus on the rising edge of the 19.44 MHz clock. All of the drop bus signals including the system clocks can be tristated to accommodate APS switching. The management software should initiate a switch if the SPECTRA-622 detects one of the following conditions: * * Signal Degrade: soft failure condition caused by line BER exceeding a SD threshold. Signal Fail: hard failure caused by LOS, LOF, line AIS, or by Line BER exceeding a SF threshold.
Once one of the above conditions has been detected by the SPECTRA-622, path AIS will be sent to the upstream node, (SPECTRA-622 WITH TUPP-PLUS622 reference design) and a switch will be initiated. When the SPECTRA-622 WITH TUPP-PLUS-622 reference design is configured to operate in the single STS-12 (STM-4) mode. The TUPP telecom drop bus will be clocked directly through the FPGA on the rising edge of a 77.76 MHz system clock, onto the telecom bus interface connector (J4 & J5). Add bus signals will be clocked in from the same interface connector (J4 & J5), directly through the FPGA, onto the SPECTRA-622 add bus, on the rising edge of the 77.76 MHz system clock.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
7.1
PM5313 SPECTRA-622 The PM5313 SPECTRA-622 is a PMC Sierra standard product that implements an STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) SONET/SDH payload extractor aligner. The SPECTRA-622 receives SONET/SDH streams using a 622 Mbit/s bit serial interface, recovers clock, data and processes section, line and path overhead. The SPECTRA-622 performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section line, and path bit interleaved parity (B1, B2, and B3), accumulating error counts at each level for performance monitoring purposes. The SPECTRA-622 interprets the received payload pointers (H1, H2) and extracts the SPE. The SPE will be available on the telecom drop bus as either a single STS-12 (STM-4) at 77.76 MHz or four STS-3s (STM-1) at 19.44 MHz. The SPECTRA-622 transmits SONET/SDH streams using a bit serial interface. The SPECTRA-622 synthesizes the transmit clock from a 77.76 MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line and path bit interleaved parity codes (B1,B2,B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) are also inserted. The SPECTRA-622 also generates the payload pointers (H1, H2) and inserts the SPE from the telecom add bus. The telecom drop bus can be configured as a single STS-12 (STM-4) at 77.76 MHz or four STS-3s (STM-1) at 19.44 MHz. The SPECTRA-622 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL compatible inputs and TTL/CMOS compatible outputs. High speed inputs and outputs support 3.3 Volt and 5.0 Volt PECL. A standard 5 signal JTAG test port for boundary scan board test purposes is provided and a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Both the microprocessor and the JTAG interface are 5 Volt tolerant. The SPECTRA-622 is available in a 520 pin Super BGA package and is guaranteed to operate over the industrial temperature range (-40C to +85C).
7.2
PM5363 TUPP-PLUS-622 The PM5363 TUPP-PLUS-622 is a SONET/SDH Tributary Unit Payload Unit Processor for 622 Mbit/s interfaces. The payload processor aligns and monitors the performance of all SONET virtual tributaries (VTs) or SDH tributary units (TUS). The TUPP-PLUS-622 provides many SONET/SDH maintenance and performance functions.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
The TUPP-PLUS-622 telecom bus can be configured as a single STS-12 (STMs 4) at 77.76 MHz or four STS-3 (STM-1) at 19.44 MHz. The TUPP-PLUS-622 is implemented in low power, +2.5 Volt core and +3.3 Volt I/O, CMOS technology. It has TTL compatible inputs and TTL/CMOS compatible outputs. High speed inputs and outputs support 3.3 Volt and 5.0 Volt PECL. A standard 5 signal JTAG test port for boundary scan board test purposes is provided and a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Both the microprocessor and the JTAG interface are 5 Volt tolerant. The TUPP-622 is available in a 304 pin Super BGA package and is guaranteed to operate over the industrial temperature range (-40C to +85C).
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
7.3
FPGA
7.3.1 STS-12 Add Drop MUX FPGA Figure 4
DTV5[4:1] DTPL[4:1] DC1J1V1[4:1] DPL[4:1] DD[31:0] DDP[4:1] AC1J1V1[1] APL[1] AD[7:0] ADP[1] [1] [1] [7:0] [1] [2] [2] [15:8] [2] [3] [3] [23:16] [3] [4] [4] [31:24] [4] [1] [1]
STS-12 Add Drop MUX FPGA
DTV5[4:1] DTPL[4:1] DC1J1V1[4:1] DPL[4:1] DD[31:0] DDP[4:1]
I / O R E G I S T E R S
M U X
I / O R E G I S T E R S
AC1J1V1[1] APL[1] AD[7:0] ADP[1] AC1J1V1[2] APL[2] AD[15:8] ADP[2] AC1J1V1[3] APL[3] AD[23:16] ADP[3]
AC1J1V1[2] APL[2] AD[15:8] ADP[2]
M U X
AC1J1V1[3] APL[3] AD[23:16] ADP[3]
M U X
AC1J1V1[4] APL[4] AD[31:24] ADP[4] C SCLK_ROBO
AC1J1V1[4]
M U X
C
APL[4] AD[31:24] ADP[4]
Time Slice and MUX control logic PLX_CLK D[7:0] A[3:0] TOH TOHCLK RRCPFP RRCPDAT RRCPCLK TRCPFP TRCPCLK TRCPDAT ROBO_FS INTB_TUPP INTB_SPECTRA INTB INTB_LED SCLK REFCLK_OUT 77 MHz CLK
0[2:0] 2[2:0] 3[2:0] 4[3] 4[2] 4[1] Microprocessor 4[0] interface 4[1:0] 1[2:0]
LAC1[4:1] DBUS_EN
CUSTOM LOGIC
L A T C H
INT_BLOCK
REFCLK_BLOCK
M U X
4
M U X
EXT_REF
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
The main function of the STS-12 Add Drop MUX FPGA is to provide data throughput on a STS-1 basis and insert data on the add bus on a STS-1 basis. In this application the telecom bus will be operating in the Quad STS-3 mode. As shown in Fig. 4 above, the FPGA will consist of the following blocks: 22 bit 2:1 MUXs, microprocessor interface, time slice and MUX control logic, reference clock, and some additional, general purpose glue logic. The I/O registers simply latch the data in on the rising edge of the 19.44 MHz clock and clock the data out on the rising edge of the clock. The MUX block consist of four 22 bit 2:1 MUXs and I/O latches. The I/O latches are on the add bus inputs only, and delay the data by two clock cycles to provide proper alignment of the inserted STS-1s and the throughput data. The microprocessor interface provides 8 bit R/W interface to the PLX-9050 local side and contains 5 R/W registers. Read access is a standard asychronous peripheral interface (Intel mode) and the write accesses are synchronous to the PLX 33 MHz clock. The INT_block monitors the interrupt signals from both the SPECTRA-622 and the TUPP-Plus-622. If either of these two interrupts occur, INTB will be low until the respective interrupt is cleared. The state of both interrupts is latched in a register, on the rising edge of the system clock, and can be read by the microprocessor interface at 0x05 as described in table xx below. INTB_LED is a buffered version of INTB and can be used to drive an LED.
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SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Register 0x05: INTERRUPT Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function unused unused unused unused unused unused INT_TUPP INT_SPECTRA Default 0 0 0 0 0 0 0 0
INT_SPECTRA: INT_SPECTRA indicates the status of the SPECTR-622's interrupt pin and INT_TUPP INT_SPECTRA indicates the status of the SPECTR-622's interrupt pin and The Refclk_block contains the logic necessary to select between the external, 77.76 MHz line side reference and the on board HCMOS/TTL 77.76 MHz reference. As well as generating 19.44 and 77.76 MHz system clocks from the 77.76 MHz reference. Rfclk_block registers are described in table 2 below.
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SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Register 0x04: Rfclk Bit Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REFINT: The REFINT bit selects the source for the 77.76 MHz reference clock. When REFINT is set high, the reference clock will be source from the on board oscillator. When REFINT is set low, the reference clock source will be external. SCLKSEL: The SCLKSEL bit selects the clock frequency of the SCLK output. When the SCLKSEL is set high, SCLK is nominally 19.44 MHz. When SCLK is set low, SCLK is nominally 77.76 MHz. ROBOFS: The ROBOFS bit selects the clock frequency of the ROBO clock devices. When the ROBOFS is set high, the ROBO clocks are nominally 77.76MHz. When ROBOFS is set low, the ROBO clocks are nominally 19.44 MHz. DBENAB The DBENAB bit enable the drop side buffers. When the DBENAB bit is set high the drop side buffers are disabled. When the DBENAB bit is low the drop side buffers will be enable. Type Type R/W R/W R/W R/W R/W R/W R/W R/W Function Function unused unused unused unused DBENAB ROBOFS SCLKSEL REFINT Default Default 0 0 0 0 0 0 0 0
The MUX control logic block generates the necessary control signals to enable the appropriate MUX or MUXs during the correct time slot time slot or time slots
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SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
to provide the data throughput of the of the STS-1s. Time slots can be selected by programming the bits of registers 0-3 as described in table 1 below.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
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SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Register 0x00: STS-3 #1 MUX timing control register Bit 7 6 5 4 3 2 1 0 STS-3#1: The STS-3#1 bit selects the STS-3 #1 STS-1 # 1 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #1 STS-1 #1 will inserted on the add bus, and when this bit is low the STS-3 #1 STS-1 #1 will be throughput data. STS-3#2 The STS-3#2 bit selects the STS-3 #1 STS-1 # 2 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #1 STS-1 #2 will inserted on the add bus, and when this bit is low the STS-3 #1 STS-1 #2 will be throughput data. STS-3#3 The STS-3#3 bit selects the STS-3 #1 STS-1 # 3 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #1 STS-1 #3 will inserted on the add bus, and when this bit is low the STS-3 #1 STS-1 #3 will be throughput data. Type R/W R/W R/W R/W R/W R/W R/W R/W Function unused unused unused unused unused STS-3 #3 STS-3#2 STS-3#1 Default 0 0 0 0 0 0 0 0
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Register 0x01: STS-3 #2 MUX timing control register Bit 7 6 5 4 3 2 1 0 STS-3#1: The STS-3#1 bit selects the STS-3 #2 STS-1 # 1 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #2 STS-1 #1 will inserted on the add bus, and when this bit is low the STS-3 #2 STS-1 #1 will be throughput data. STS-3#2 The STS-3#2 bit selects the STS-3 #2 STS-1 # 2 to be inserted on the add bus. When the STS-3#2 bit is set high the STS-3 #2 STS-1 #2 will inserted on the add bus, and when this bit is low the STS-3 #2 STS-1 #2 will be throughput data. STS-3#3 The STS-3#3 bit selects the STS-3 #2 STS-1 # 3 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #2 STS-1 #3 will inserted on the add bus, and when this bit is low the STS-3 #2 STS-1 #3 will be throughput data. Type R/W R/W R/W R/W R/W R/W R/W R/W Function unused unused unused unused unused STS-3 #3 STS-3#2 STS-3#1 Default 0 0 0 0 0 0 0 0
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Register 0x02: STS-3 #3 MUX timing control register Bit 7 6 5 4 3 2 1 0 STS-3#1: The STS-3#1 bit selects the STS-3 #3 STS-1 # 1 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #3 STS-1 #1 will inserted on the add bus, and when this bit is low the STS-3 #3 STS-1 #1 will be throughput data. STS-3#2 The STS-3#2 bit selects the STS-3 #3 STS-1 # 2 to be inserted on the add bus. When the STS-3#2 bit is set high the STS-3 #3 STS-1 #2 will inserted on the add bus, and when this bit is low the STS-3 #3 STS-1 #2 will be throughput data. STS-3#3 The STS-3#3 bit selects the STS-3 #3 STS-1 # 3 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #3 STS-1 #3 will inserted on the add bus, and when this bit is low the STS-3 #3 STS-1 #3 will be throughput data. Type R/W R/W R/W R/W R/W R/W R/W R/W Function unused unused unused unused unused STS-3 #3 STS-3#2 STS-3#1 Default 0 0 0 0 0 0 0 0
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Register 0x03: STS-3 #4 MUX timing control register Bit 7 6 5 4 3 2 1 0 STS-3#1: The STS-3#1 bit selects the STS-3 #4 STS-1 # 1 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #4 STS-1 #1 will inserted on the add bus, and when this bit is low the STS-3 #4 STS-1 #1 will be throughput data. STS-3#2 The STS-3#2 bit selects the STS-3 #4 STS-1 # 2 to be inserted on the add bus. When the STS-3#2 bit is set high the STS-3 #4 STS-1 #2 will inserted on the add bus, and when this bit is low the STS-3 #4 STS-1 #2 will be throughput data. STS-3#3 The STS-3#3 bit selects the STS-3 #4 STS-1 # 3 to be inserted on the add bus. When the STS-3#1 bit is set high the STS-3 #4 STS-1 #3 will inserted on the add bus, and when this bit is low the STS-3 #3 STS-1 #3 will be throughput data. Type R/W R/W R/W R/W R/W R/W R/W R/W Function unused unused unused unused unused STS-3 #3 STS-3#2 STS-3#1 Default 0 0 0 0 0 0 0 0
REFINT: The REFINT bit selects the source for the 77.76 MHz reference clock. When REFINT is set high, the reference clock will be source from the on board oscillator. When REFINT is set low, the reference clock source will be external.
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SCLKSEL: The SCLKSEL bit selects the clock frequency of the SCLK output. When the SCLKSEL is set high, SCLK is nominally 19.44 MHz. When SCLK is set low, SCLK is nominally 77.76 MHz. ROBOFS: The ROBOFS bit selects the clock frequency of the ROBO clock devices. When the ROBOFS is set high, the ROBO clocks are nominally 77.76MHz. When ROBOFS is set low, the ROBO clocks are nominally 19.44 MHz.
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7.3.2 77.76 MHz Telecom Bus Interface FPGA Figure 5 77.76 MHz Telecom Bus FPGA
DC1J1V1[4:1] DPL[4:1] DD[31:0] DDP[4:1] AC1J1V1[1] APL[1] AD[7:0] ADP[1]
DC1J1V1[4:1] DPL[4:1] DD[31:0] DDP[4:1]
I / O R E G I S T E R S
I / O R E G I S T E R S
AC1J1V1[1] APL[1] AD[7:0] ADP[1]
AC1J1V1[2] APL[2] AD[15:8] ADP[2]
AC1J1V1[2] APL[2] AD[15:8] ADP[2]
AC1J1V1[3] APL[3] AD[23:16] ADP[3]
AC1J1V1[3] APL[3] AD[23:16] ADP[3]
AC1J1V1[4] APL[4] AD[31:24] ADP[4] C SCLK_ROBO PLX_CLK D[7:0] A[3:0] TOH TOHCLK RRCPFP RRCPDAT RRCPCLK TRCPFP TRCPCLK TRCPDAT ROBO_FS INTB_TUPP INTB_SPECTRA INTB INTB_LED SCLK REFCLK_OUT 77 MHz CLK Microprocessor interface
4[3] 4[2] 4[1] 4[0] 4[1:0]
AC1J1V1[4] APL[4] AD[31:24] ADP[4] C
DBUS_EN
CUSTOM LOGIC
L A T C H
INT_BLOCK
REFCLK_BLOCK
M U X
4
M U X
EXT_REF
The 77.76 MHz Telecom bus Interface FPGA provides a direct interface to all the standard telecom signals, for both the TUPP-Plus-622, and the SPECTRA-622. All signals are clocked in and out of the FPGA on the rising edge of the 77.76
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MHz system clock. Although the FPGA clocks through all of the telecom bus signals, it has been designed to ensure operation at 77.76 MHz. The 77.76 MHz Telecom Bus Interface FPGA also contains the REFCLK_BLOCK and the microprocessor interface block.
7.4
Buffers The Telecom Bus will have both output and input buffering. The Telecom Drop Bus will have tristate buffering to accommodate APS. Buffers will be 3.3V and the inputs will be 5V tolerant.
7.5
PLX Technology 9050 PCI Bridge The PCI 9050 provides a compact high performance PCI bus target (slave) interface for adapter boards. For more information on this device, please refer to the manufacturer's specification found on the PLX Technology web site. This device is programmed, via the external serial EEPROM, U13 at power up, for a 32 bit, local data bus. The PLX chip allows the board to map SPECTRA-622, TUPP-Plus-622, and the FPGA to the cPCI bus. The signals from the J1 connector to the PLX chip are tightly controlled and must adhere to the cPCI physical specification for proper operation. Ten ohm series terminating resistors are used to minimize reflection in all the signals. Any unused inputs such as the unused LAD (address/data) pins are pulled up with 4.7K resistors. Also, all tri-state outputs, such as RDB, are pulled up via a 4.7K resistor to prevent the bus from chattering during power up. The PLX does 32 bit, 4 byte accesses to/from the cPCI system Software selects the bottom byte only. Notice that the top three data bytes on the PLX are not connected to the bus and LA(2) is connected to A(0).
7.5.1 Serial EEPROM The PLX chip, PCI9050, requires a configuration EEPROM during power up to configure itself. A serial device, U13, NM93CS46 contains the following code to configure the PLX for our system
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Table 1
EEPROM Contents PLX Register Device ID Vendor ID Class Code ClassCode Subsystem ID Subsystem Vendor ID Max Latency and Min Grant (not loadable) Interrupt Pin MSW of Address Space 0 Range LSW of Address Space 0 Range MSW of Address Space 1 Range LSW of Address Space 1 Range MSW of Address Space 2 Range LSW of Address Space 2 Range MSW of Address Space 3 Range LSW of Address Space 3 Range MSW of Expansion Rom Range LSW of Expansion Rom Range MSW of Address Space 0 Remap LSW of Address Space 0 Remap MSW of Address Space 1 Remap LSW of Address Space 1 Remap MSW of Address Space 2 Remap LSW of Address Space 2 Remap MSW of Address Space 3 Remap LSW of Address Space 3 Remap MSW of Expansion Rom Remap
EEPROM Offset (Hex) Value (Hex) 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 9050 10B5 0680 0000 7324 11F8 FFFF 00FF 0FFF 0000 0FFF 0000 0FFF 0000 0000 0000 0FFF 0000 0000 0001 0001 0001 0002 0001 0000 0000 0000
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EEPROM Offset (Hex) Value (Hex) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 - 7F 0000 1681 A1A0 1681 A1A0 1681 A1A0 0000 0000 0000 0000 0000 8001 0001 8001 0002 8001 0000 0000 0000 0000 0002 44C0 FFFF
PLX Register LSW of Expansion Rom Remap MSW of Space 0 Bus Descriptor LSW of Space 0 Bus Descriptor MSW of Space 1 Bus Descriptor LSW of Space 1 Bus Descriptor MSW of Space 2 Bus Descriptor LSW of Space 2 Bus Descriptor MSW of Space 3 Bus Descriptor LSW of Space 3 Bus Descriptor MSW of Expansion Rom Bus Descriptor LSW of Expansion Rom Bus Descriptor MSW of CS0 Register LSW of CS0 Register MSW of CS1 Register LSW of CS1 Register MSW of CS2 Register LSW of CS2 Register MSW of CS3 Register LSW of CS3 Register MSW of Interrupt Control/Status LSW of Interrupt Control/Status MSW of EEPROM and Misc. Control LSW of EEPROM and Misc. Control Unused
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7.6
Reference clocks The SPECTRA-622 WITH TUPP-PLUS-622 reference design requires a jitter free 77.76 MHz line side clock reference with a tolerance of +/- 20ppm. This reference clock can be generated onboard, with a PECL oscillator, or a HCMOS/TTL oscillator. The reference clock can also be supplied externally, through a SMB connector on the front panel, or from the backplane. It should be note that when reference clock is supplied from the backplane or the front panel, the line side clock will be synchronous with the system clock. System clocks for the SPECTRA-622, TUPP-PLUS-622, backplane and the FPGA are generated using the Cypress CY7B991V, programmable skew clock buffer. These multiple-output clock buffers provide the system with a number of low skew clocks and if necessary, the delay between each clock, can be programmed to optimize timing.
7.7
Power Power requirements for the board are +5 Volts and +3.3 Volts and is supplied from the backplane through CPCI connector J1. linear regulators will be used produce the +2.5 Volts for the TUPP-PLUS-622 core and the +3.3 Volts for the SPECTRA-622 analog power. Front panel LEDs will be used to indicate power status.
7.8
Telecom Bus The telecom bus supports a single STS-12 (STM-4) 77.76 MHz byte bus or a quad STS-3 (STM-1) 19.44 MHz byte bus.
7.9
Mechanical Form Factor The board is a based on the CPCI 6U (233.35 mm by 160 mm) board size. Rear connectors are numbered J1, J3 and J5 starting at the bottom connector. J1 is used for the 32 bit CPCI signals. J3 and J5 will carry the telecom bus and DS3 signals.
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Table 2
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DC1J1V1[3] DTPL[3] AD[24] AD[28] AD[31] DD[24] DD[28] DD[31] DTV5[4] POHCK RAD[3] POHFP[10] DS3ROCLK[9] RSV DS3TIDAT[5] TXRNG[2] RXRNG[2] GND RCLK
J3 Pin Assignment
B GND DTV5[3] AD[25] GND AC1J1V1[4] DD[25] GND DC1J1V1[4] ROBO[4] GND RAD[4] DS3RICLK GND DS3TICLK[1] DAS3T1DAT[9] GND RXRNG[3] GND RSV C DPL[3] ROBO[3] GND AD[29] APL[4] GND DD[29] DPL[4] GND RAD[1] POHFP[1] GND DS3RDAT[1] DS3TICLK[5] GND TXRNG[3] SPARE7 GND RSV D GND RSV AD[26] GND ADP[4] DD[26] GND DDP[4] SPARE5 GND POHFP[4] DS3ROCLK[1] GND DS3RDAT[5] DS3TICLK[9] GND RSV GND RSV E DDP[3] RSV AD[27] AD[30] LAC1[4] DD[27] DD[30] DTPL[4] SPARE6 RAD[2] POHFP[7] DS3ROCLK[5] DS3RDAT[9] DS3TIDAT[1] TXRNG[1] RXRNG[1] RSV GND EXTREF F GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Table 3
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND AD[3] AC1J1V1[1] GND RSV DD[0] GND DD[6] DTPL[1] GND AD[11] AC1J1V1[2] GND DD[10] DD[15] GND ROBO[2] AD[20} GND ADP[3] DD[18] GND
J5 Pin Assignment
B AD[0] AD[4] GND LAC1[1] ROBO[1] GND DD[3] DD[7] GND AD[8] AD[12] GND LAC1[2] DD[11] GND DDP[2] AD[16] GND AD[23] LAC1_3 GND DD[21] C GND AD[5] APL[1] GND RSV DD[1] GND DC1J1V1[1] DTV5[1] GND AD[13] APL[2] GND DD[12] DC1J1V1[2] GND AD[17] AD[21] GND SPARE4 DD[19] GND D AD[1] AD[6] GND SPARE1 SPARE2 GND DD[4] DPL[1] GND AD[9] AD[14] GND DD[8] DD[13] GND DTPL[2] AD[18] GND AC1J1V1[3] DD[16] GND DD[22] E AD[2] AD[7] ADP[1] RSV RSV DD[2] DD[5] DDP[1] SPARE3 AD[10] AD[15] ADP[2] DD[9] DD[14] DPL[2] DTV5[2] AD[19] AD[22] APL[3] DD[17] DD[20] DD[23] F GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Table 4
Signal Name AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
J3 and J5 Signal Description
Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Connector/Pin J4/B1 J4/D1 J4/E1 J4/A2 J4/B2 J4/C2 J4/D2 J4/E2 J4/B10 J4/D10 J4/E10 J4/A11 J4/B11 J4/C11 J4/D11 J4/E11 J4/B17 J4/C17 J4/D17 J4/E17 J4/A18 J4/C18 J4/E18 J4/B19 J5/A3 J5/B3 J5/D3 J5/E3 J5/A4 J5/C4 J5/E4 J5/A5 In single ADD bus interface STS-12 (STM-4) mode, the ADD bus data (AD[31:24]) inputs are unused and should be tied low. In quad ADD bus interface STS-3 (STM-1) mode, the ADD th bus data (AD[31:24]) contains the 4 STS-3/3c (STM-1/AU3/AU4) SONET/SDH payload data to transmit. In single ADD bus interface STS-12 (STM-4) mode, the ADD bus data (AD[23:16]) inputs are unused and should be tied low. In quad ADD bus interface STS-3 (STM-1) mode, the ADD rd bus data (AD[23:16]) contains the 3 STS-3/3c (STM-1/AU3/AU4) SONET/SDH payload data to transmit. In single ADD bus interface STS-12 (STM-4) mode, the ADD bus data (AD[15:8]) inputs are unused and should be tied low. In quad ADD bus interface STS-3 (STM-1) mode, the ADD nd bus data (AD[15:8]) contains the 2 STS-3/3c (STM-1/AU3/AU4) SONET/SDH payload data to transmit. Function In single ADD bus interface STS-12 (STM-4) mode, the ADD bus data (AD[7:0]) contains the STS-12/12c (STM-4/AU3/AU4/AU4-Xc) SONET/SDH payload data to transmit. In quad ADD bus interface STS-3 (STM-1) mode, the st ADD bus data (AD[7:0]) contains the 1 STS3/3c (STM-1/AU3/AU4) SONET/SDH payload data to transmit.
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Signal Name APL[1] APL[2] APL[3] APL[4] AC1J1V1[1] AC1J1V1[2] AC1J1V1[3] AC1J1V1[4] ADP[1] ADP[2] ADP[3] ADP[4] LAC1[1] LAC1[2] LAC1[3] LAC1[4] ROBO[1] ROBO[2] ROBO[3] ROBO[4] DD[0] DD[1]
Type I I I I I I I I I I I I O O O O O O O O O O
Connector/Pin J4/C3 J4/C12 J4/E19 J5/C5 J4/A3 J4/A12 J4/D19 J5/B5 J4/E3 J4/E12 J4/A20 J5/D5 J4/B4 J4/B13 J4/B20 J5/E5 J4/B5 J4/A17 J5/C2 J5/B9 J4/A6 J4/C6
Function The ADD bus payload active signals APL[4:1] indicate when AD[7:0], AD[15:8], AD[16:23], and AD[24:31] respectively, are carrying payload bytes. The ADD bus composite timing signals (AC1J1V1[4:1]) indentify the frame and optionally the payload and tributary multi-frame boundaries on the ADD data bus signals AD[7:0] ], AD[15:8], AD[16:23], and AD[24:31] respectively. The ADD bus data parity signals (ADP[4:1]) indicate the parity of the ADD bus signals AD[7:0], AD[15:8], AD[16:23], and AD[24:31] respectively. The line add C1 frame pulse signals (LAC1[4:1]) identify the frame and multi-frame boundaries on the ADD data bus signals AD[7:0] ], AD[15:8], AD[16:23], and AD[24:31] respectively. ROBO[4:1] provide timing signals for the ADD and Drop bus and can be set to either 19.44 MHz or 77.76 MHz. The duty cycle is nominally 50%. In single DROP bus interface STS-12(STM-4) mode, the DROP bus data (DD[7:0]) contains the STS-12/12c (STM-4/AU3/AU4/AU4-Xc) received SONET/SDH payload data. In quad DROP bus interface STS-3(STM-1) mode, the st DROP bus data (DD[7:0]) contains the 1 STS3/3c (STM-1/AU3/AU4) received SONET/SDH payload data.
DD[2] DD[3] DD[4] DD[5] DD[6] DD[7]
O O O O O O
J4/E6 J4/B7 J4/D7 J4/E7 J4/A8 J4/B8
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Signal Name DD[8] DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15] DD[16] DD[17] DD[18] DD[19] DD[20] DD[21] DD[22] DD[23] DD[24] DD[25] DD[26] DD[27] DD[28] DD[29] DD[30] DD[31] DPL[1] DPL[2] DPL[3] DPL[4] DTPL[1] DTPL[2] DTPL[3] DTPL[4]
Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Connector/Pin J4/D13 J4/E13 J4/A14 J4/B14 J4/C14 J4/D14 J4/E14 J4/A15 J4/D20 J4/E20 J4/A21 J4/C21 J4/E20 J4/B21 J4/D22 J4/E22 J5/A6 J5/B6 J5/D6 J5/E6 J5/A7 J5/C7 J5/E7 J5/A8 J4/D8 J4/E15 J5/C1 J5/C8 J4/A9 J4/D16 J5/A2 J5/E8
Function In single DROP bus interface STS-12(STM-4) mode, the DROP bus data (DD[15:8]) is forced low. In quad DROP bus interface STS-3(STM1) mode, the DROP bus data (DD[15:8]) contains the 2nd STS-3/3c (STM-1/AU3/AU4) received SONET/SDH payload data.
In single DROP bus interface STS-12(STM-4) mode, the DROP bus data (DD[23:16]) is forced low. In quad bus interface STS-3(STM1) mode, the DROP bus data (DD[15:8]) rd contains the 3 STS-3/3c (STM-1/AU3/AU4) received SONET/SDH payload data.
In single DROP bus interface STS-12(STM-4) mode, the DROP bus data (DD[31:24]) is forced low. In quad bus interface STS-3(STM1) mode, the DROP bus data (DD[31:24]) th contains the 4 STS-3/3c (STM-1/AU3/AU4) received SONET/SDH payload data.
The active high DROP bus payload active signals (DPL[4:1]) indicate when DD[7:0], DD[15:8], DD[24:16], and DD[31:24] respectively are carrying payload bytes. It is set high during path overhead and payload bytes and low during transport overhead bytes. The active high DROP bus tributary payload active signals (DTPL[4:1]) indicate when DD[7:0], DD[15:8], DD[24:16], and DD[31:24] respectively are carrying tributary payload bytes overhead bytes.
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Signal Name DC1J1V1[1] DC1J1V1[2] DC1J1V1[3] DC1J1V1[4] DTV5[1] DTV5[2] DTV5[3] DTV5[4] DDP[1] DDP[2] DDP[3] DDP[4] RCLK
Type O O O O O O O O O O O O O
Connector/Pin J4/C8 J4/C15 J5/A1 J5/B8 J4/C9 J4/E16 J5/B2 J5/A9 J4/E8 J4/B16 J5/E1 J5/D8 J5/A19
Function The DROP bus composite timing signals (DC1J1V1[4:1]) indicate the frame, payload and tributary multi-frame boundaries on the DROP data bus signals DD[7:0], DD[15:8], DD[24:16], and DD[31:24] respectively. The DROP bus tributary V5 signals (DTV5[4:1]) mark the tributary V5 bytes on the DROP data bus signals DD[7:0], DD[15:8], DD[24:16], and DD[31:24] respectively. The DROP bus data parity signals (DDP[4:1]) indicate the parity of the DROP bus signals DD[7:0], DD[15:8], DD[16:23], and DD[24:31] respectively. The receive clock (RCLK) output provides timing for the SPECTRA-622 line side interface outputs and is nominally 77.76 MHz with a 50% duty cycle. The external reference (EXTREF) input can be fed with a 77.76 MHz CMOS/TTL clock. The tributary path overhead clock (POHCK) signal provides timing to sample the extracted tributary path overhead stream and the receive alarm port for the STM-1/STS-3 #1, #2, #3 and #4. POHCK is a nominally 9.72 MHz clock. The POHFP[1, 4, 7, 10] and RAD[4:1] outputs are updated on the falling edge of POHCK. The receive alarm ports (RAD[4:1]) contain the tributary path BIP error count, the RDI status and the PDI status of each tributary in the (STM-1/STS) #1,#2, #3, and #4. RAD[4:1] is updated on the falling edge of POHCK.
EXTREF POHCK
I O
J5/E19 J5/A10
RAD[1] RAD[2] RAD[3] RAD[4]
O O O O
J5/C10 J5/E10 J5/A11 J5/B11
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Signal Name POHFP[1] POHFP[4] POHFP[7] POHFP[10]
Type 0 0 0 0
Connector/Pin J5/C11 J5/D11 J5/E11 J5/A12
Function POHFP[1], POHFP[4], POHFP[7], and POHFP[10] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #4, #7and #10, respectively. In AU4 mode, POHFP[1], POHFP[2] and POHFP[3] identify frame boundaries of TUG3 #1, #4, #7, and #10, respectively. Each POHFP signal is updated on the falling edge of POHCK The DS3 receive input clock (DS3RICLK) provides timing for the receive DS3 interface. It is a nominally 44.928 MHz, 50% duty cycle clock. The DS3RICLK is gapped to generate the DS3 receive output clocks (D3ROCLK[3:1]). The DS3 receive output clocks (DS3ROCLK[1, 5, 9]) provide timing to the DS3 received streams that have been de-mapped from the SONET/SDH stream. The DS3 receive data (DS3RDAT[1, 5, 9]) output signals contain NRZ encoded data of the DS3 streams that have been de-mapped from the receive SONET/SDH stream STS3/STM-1 #1. The DS3 transmit input clocks (DS3TICLK[1, 5, 9]) provide timing for the transmit DS3 data streams.
DS3RICLK
I
J5/B12
DS3ROCLK[1] DS3ROCLK[5] DS3ROCLK[9] DS3RDAT[1] DS3RDAT[5] DS3RDAT[9]
O O O O O O
J5/D12 J5/E12 J5/A13 J5/C13 J5/D14 J5/E13
DS3TICLK[1] DS3TICLK[5] DS3TICLK[9]
I I I
J5/B14 J5/C14 J5/D15
DS3TIDAT[1] DS3TIDAT[5] DS3TIDAT[9]
I I I
J5/E14 J5/A15 J5/B15
The DS3 transmit data (DS3TDAT[1, 5, 9]) signals contain the DS3 or payload streams to be mapped into the SONET/SDH transmit streams STS-3/STM-1 #1
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Signal Name TXRNG[1] : TRCPDAT
Type I
Connector/Pin J5/E15
Function The transmit ring control port data (TRCPDAT) signal contains the transmit ring control port data stream. The data stream consists of the filtered K1, K2 bytes values, APS status bit, AIS, RDI, and the REI bit positions. The transmit ring control port clock (TRCPCLK) signal provides timing for the transmit ring control port. TRCPCLK is nominally a 3.24 MHz, 50% duty cycle clock. The transmit ring control port frame position (TRCPFP) signal identifies bit positions in the transmit ring control port data (TRCPDAT). The receive ring control port clock (RRCPCLK) signal provides timing for the transmit ring control port. RRCPCLK is nominally a 3.24 MHz, 50% duty cycle clock. The receive ring control port data (RRCPDAT) signal contains the transmit ring control port data stream. The data stream consists of the filtered K1, K2 bytes values, APS status bit, AIS, RDI, and the REI bit positions. The receive ring control port frame position (RRCPFP) signal identifies bit positions in the transmit ring control port data (RRCPDAT).
TXRNG[2] : TRCPCLK
I
J5/A16
TXRNG[3] : TRCPFP
I
J5/C16
RXRNG[1] : RRCPCLK
O
J5/E16
RXRNG[2] : RRCPDAT
O
J5/A17
RXRNG[3] : RRCPFP
O
J5/B17
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
8
IMPLEMENTATION DESCRIPTION This section describes the hardware implementation of the SPECTRA-622 WITH TUPP-PLUS-622 reference design, as contained in the schematics in Section 9.
8.1
Root Drawing, Sheet 1 This sheet shows the interconnection between the functional blocks of the design.
8.2
OPTICS _REFCLK_BLOCK, Sheet 2 Sheet 2 shows the system clock PLL drivers, Optics interface, and 77.76 MHz reference clock circuitry. The system clock (SCLK) comes from the FPGA and is used as a reference for PLL clock driver U6. The recovered clock from U6 is used to supply a reference to PLL clock driver U7. When ROBO_FS is high the PLL clock drivers will expect a 77.76 MHz reference, and when ROBO_FS is low, the clock drivers expect a 19.44 MHz reference. The delay between the clock outputs (SCLK_ROB<7..1>) can be varied by removing or adding 4.7K pull-up and pull-down resistors connected to pins 26, 27, 29, and 30 of U6 and U7 . The 51 Ohm resistors at the output of the clock divers provide some source termination to help prevent reflections. U5 (HP HFCT-5208) is the Optical Data Link (ODL) which provides the optical to electrical (O/E) function for the SPECTRA-622 device. The HFCT-5208 transceiver is 5V PECL device in a 1 x 9-pin package with a duplex SC receptacle. The PECL signals connect to the SPECTRA-622 on 50 Ohm controlled impedance signal lines and are properly terminated at the ODL and at the SPECTRA-622 device. The 330 Ohms resistors provide source terminations for the PECL outputs and should be located as close as possible to the HFCT5208. R77, R78, R79, and C25 provide biasing for the SPECTRA-622 PECL TX outputs and should be located as close as possible to the ODL Y1 is a 77.76 MHz PECL oscillator and provides the line side reference clock for the SPECTRA. When 3.3V optics are used the PECL reference oscillator should be a 3.3V PECL oscillator and when using 5V optics it should be a 5V oscillator. This oscillator should be located as close as possible to the SPECTRA 622 and signal traces should be 50 ohm differential pairs. The 77.76 MHz external TTL line side reference clock is fed to U1 where it is translated to either 3.3V PECL or 5V PECL depending on the optics installed. When 3.3V OPTICS is used the MC100LVELT22 will be installed and if 5V OPTICS is used the MC100ELT22 will
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
be installed. The 330 ohm resistors at the outputs of U1 provide DC biasing for the PECL driver. The second pair of outputs is used to terminate the RRCLK_P and RRCLK_N inputs of the SPECTRA-622 to the appropriate PECL levels. Solder bridges SB5-SB8 are used to select between the external line side reference clock and the internal line side clock. The 77.76 MHz HCMO/TTL oscillator used to generate the system clocks, can also be used to provide the line side clock reference. This can be done, by opening solder bridge SB3, and closing solder bridge SB4. 8.3 SPECTRA_622 _BLOCK, Sheet 3 & 4 The SPECTRA_622_BLOCK shows the SPECTRA-622 signals and the power circuitry. J8 provides access to the SPECTRA-622 RX and TX overhead and alarm signals. Resistor arrays RN1-RN4 ensure no inputs are left floating. Resistors R34, R35, and R39 provide terminations for PECL line side inputs signals, REFCLK+/-, RXD+/- and RRCLK+/-. PECREF and PREFEN are tied low through 4.7K ohm resistors to ensure that the PECL bias voltage is set by the internal bandgap reference. A 47 nF capacitor is placed across the loop filter pins C1 and C0, which sets the loop bandwidth of the clock recovery circuit to approximately 500 KHz. A 2k Ohm resistor is placed across the TDREF0 and TDREF1 pins to set calibrated currents for the PECL output transceivers TXD+/to approximately 15 ma. Test points T16-T21 provide access to the TPAIS, TPAISFP, TPAISCK, DPAIS, DPAIS, and DPAISCK signals. The 48 digital power pins are decoupled using 39, .10UF capacitors. A 3.3V low dropout linear regulator (U3 LT1129-3.3) and additional filtering capacitors and resistors are provided to ensure a clean 3.3V power source to analog power pins. U19 and its' associated components can be installed if it is required to generate a clean 3.3V linear regulated supply from a 3.3V supply. The TPS60100 consists of a charge pump followed by a linear regulator. VBIAS pins (VBIAS<1..0>) are tied to +5V through a 1K resistor, to bias the wells of the digital inputs so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. PBIAS pins perform the same function for the PECL signals and must be tied to either 3.3V or 5V. 8.4 TUPP_622_BLOCK, Sheets 5, & 6 The TUPP_622_BLOCK shows the TUPP-PLUS-622 signals and the power circuitry.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
J6 configures the incoming and outgoing interface mode of the TUPP-PLUS-622 to either 77.76 MHz (STS-12) STM-4 or 19.44 MHz (STS-3) STM-1. J2 and J4 connect the system clock to HSCLK and the GSCLK<0> to the TUPP SCLK when in the 77.76 MHz interface mode, and connect the system clock to the TUPP SCLK when in the 19.44 MHz interface mode. TUPP-PLUS-622 digital power digital pins are decoupled using 24 0.1 uF capacitors. The 2.5V TUPP core power is generated from the 3.3V supply (VCC) using a low dropout linear regulator (MC3950-2.5T). This ensures that the 3.3V supply should never be at a lower voltage than the 2.5V supply (there is an internal diode between the supplies that shouldn't be forward biased). The regulator and its associated components should be located as close as possible to the TUPP-PLUS-622 device. 8.5 FPGA BLOCK Sheet, 7 The FPGA block shows the FPGA (XC4028XL) signals, decoupling caps, serial EPROM, 77.76 MHz HCMOS/TTL reference oscillator, interrupt LED, and reset circuitry. U2, U4 and their associated components provide power up and manual reset signals for the FPGA, TUPP-PLUS-622, and SPECTRA-622. Y2 is a 77.76 MHz, HCMOS/TTL oscillator and is used to generate the reference clock as well as the system clock. It should be located as close as possible to the FPGA. J9 provides an interface to the FPGA programming port (Xilinx XCHKR port). Headers, J10, J11 and J12 are used to select how the FPGA is to be configured. The FPGA can be configured on power up by a serial EPROM (U15), through the XCHK port, or through the cPCI interface. When using the XCHK port the serial EPROM should be removed. Table 5 below describes the settings for these headers. Table 5 MODE Serial EPROM XCHK Port (J9) cPCI FPGA Configuration jumper settings J10 All jumpers on All jumpers off Only center jumper on J11 Pins 2-3 Pins 3-3 Pins 1-2 J12 N/C Pins 2-3 Pins 1-2
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
A number of I/O pins are connected to the SPECTRA-622's overhead and alarm signals. These signals were provided for future custom applications. Several of these pins were brought out into headers (TP's) just in case we wanted to use this device for a different function other than originally envisioned. The XC1701L EEPROM devices contain 832,528 bits. 20 pin PLCC sockets are used to facilitate ease of changing these programmable devices 8.6 SYS_INTERFACE , Sheet 8, 9, & 10 Sheet 8 shows the CPCI connector, PCI bridge chip and power connections. Fuses F1 and F2 are necessary to prevent any serious damage in the event of a short on the +5V or +3.3V power buses. D2 and D3 indicate +3.3 and +5.0V power and are front panel mounted. Sheet 9 shows the telecom bus interface connector J5 and the telecom bus signals from the FPGA. All signals are buffered through 3.3V CMOS buffers and outputs have 22 ohm series terminations to reduce reflections. When operating at 77.76 MHz it may be necessary to provide Thevenin terminations for add bus (bits [7:0]). If Thevenin terminations are required, install 150 ohm resistors connected to U24 pins 33-36, 37, 38, 40, 41, 43, 44, 46 and 47. Sheet 10 shows the telecom bus/DS3 bus interface connector J3 and the remainder of the telecom bus signals from the FPGA and the DS3 signals from the SPECTRA-622 signals are buffered through 3.3V CMOS buffers and outputs have 22 ohm series terminations to reduce reflections.
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PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
9
SCHEMATICS AND LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
38
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
CSB_SPECTRA INTB_SPECTRA CSB_TUPP TDO_TDI_SPECTRA RESETB TMS TRSTB TCK D<7..0> A<13..0> TDO_TDI_PCI
H
G PAGE 3, 4 SPECTRA_622_BLOCK RDB WRB A<13..0> D<7..0> CSB_SPECTRA INTB_SPECTRA F TDO_TDI_SPECTRA PAGE 2 OPTICS_REFCLK_BLOCK TDO_TDI_TUPP RESETB TMS TRSTB TCK TDO_TDI_TUPP RESETB TMS TRSTB TCK RDB
WRB RDB PAGE 5, 6 TUPP_622_BLOCK PAGE 7 FPGA INTB RDB WRB WRB A<13..0> A<13..0> D<7..0> D<7..0> CSB_TUPP INTB_TUPP INTB_TUPP INTB_SPECTRA CSB_FPGA INTB_TUPP CSB_SPECTRA CSB_TUPP TRSTB TDO_TDI_TUPP RESETB TMS TRSTB TCK RAD_T<4..1> RAD_T<4..1> POHCK_T TDO_TDI_PCI TMS TDO_TDI_PCI TDO_TDI_SPECTRA TRSTB_PCI TRSTB_PCI PLX_CLK POHCK_T GSCLK_FP TXD_P TXD_N TXD_P TXD_N TXD_P SCLK_ROBO<8..1> TXD_N DTPL_T<4..1> DC1J1V1<4..1> DPL<4..1> DD<31..0> PBIAS PECLV PBIAS PECL RRCLK_P RRCLK_N REFCLK_P REFCLK_N DDP<4..1> PBIAS PECLV RRCLK_P DS3RODAT<3..1> RRCLK_N REFCLK_P REFCLK_N ROWCLK RSOW ROHCLK SCLK_ROBO<8..1> ROH RX_RNG_CTRL<3..1> SCLK AC1J1V1<4..1> AC1J1V1<4..1> APL<4..1> AD<31..0> ADP<4..1> AC1J1V1<4..1> APL<4..1> ADD_F<47..0> AD<31..0> ADP<4..1> DS3TICLK<3..1> DS3TICLK<3..1> DS3TIDAT<3..1> TOWCLK TSOW TOHCLK TOH TX_RNG_CTRL<3..1> DS3TICLK<3..1> DS3TIDAT<3..1> TOWCLK TSOW TOHCLK TOH TX_RNG_CTRL<3..1> TOWCLK TSOW TOHCLK TOH SCLK_EXT TX_RNG_CTRL<3..1> EXT_REF RCLK RFP RCLK RFP RCLK RFP EXT_REF SCLK_EXT EXT_REF DRAWING: TITLE=SPECTRA_622_ROOT ABBREV=SPECTRA_622_ROOT LAST_MODIFIED=Thu Jan 20 08:39:38 2000 RCLK SCLK_ROBO<8..1> RCLK SCLK_ROBO<8..1> DS3TIDAT<3..1> TX_RNG_CTRL<3..1> DS3TICLK<3..1> DS3TIDAT<3..1> TX_RNG_CTRL<3..1> PIO<5..0> PIO<5..0> ADD_F<47..0> PIO<5..0> DS3RICLK DS3ROCLK<3..1> DS3RICLK DS3RICLK DS3ROCLK<3..1> DS3ROCLK<3..1> DS3RODAT<3..1> SCLK_ROBO<8..1> ROWCLK RSOW ROHCLK ROH RX_RNG_CTRL<3..1> SCLK_ROBO<8..1> ROWCLK RSOW ROHCLK ROH RX_RNG_CTRL<3..1> DS3RODAT<3..1> RX_RNG_CTRL<3..1> DS3RICLK DS3ROCLK<3..1> DS3RODAT<3..1> RX_RNG_CTRL<3..1> DC1J1V1<4..1> DPL<4..1> DD<31..0> DDP<4..1> DC1J1V1<4..1> DPL<4..1> DD<31..0> DDP<4..1> SCLK_ROBO<8..1> GSCLK_FP GSCLK_FP RAD_T<4..1> POHFP_T<4..1> SCLK_ROBO<8..1> DTV5_T<4..1> DTV5_T<4..1> DTPL_T<4..1> DTV5_T<4..1> DROP_F<52..0> DBUS_EN TRSTB_PCI TCK SD PLX_CLK RXD_P RXD_N PLX_CLK POHCK_T RAD_T<4..1> POHFP_T<4..1> RESETB PROG DONE RESET_PCI PROG DONE RESET_PCI PROG DONE RESET_PCI CSB_FPGA D<7..0> CSB_FPGA A<13..0> WRB PAGE 8, 9, 10 SYS_INTERFACE INTB RDB 17P
G
F
POHCK_T POHFP_T<4..1> POHFP_T<4..1>
SD E RXD_P RXD_N
SD RDX_P RXD_N
E
DTPL_T<4..1> DC1J1V1_T<4..1> DC1J1V1_T<4..1> DC1J1V1_T<4..1> DPL_T<4..1> DPL_T<4..1> DPL_T<4..1> DD_T<31..0> DD_T<31..0> DD_T<31..0> DDP_T<4..1> DDP_T<4..1> DDP_T<4..1>
DROP_F<52..0> DBUS_EN
DROP_F<52..0> DBUS_EN
D RRCLK_P RRCLK_N REFCLK_P REFCLK_N
D
C
REFCLK_OUT ROBO_FS
APL<4..1> AD<31..0> ADP<4..1>
C ADD_F<47..0>
B
B
SCLK
SCLK
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER:2 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN ROOT DRAWING ENGINEER: MK ISSUE DATE: 00/01/19 REVISION NUMBER: 2 PAGE:1 2 1 OF 10 A
REFCLK_OUT A ROBO_FS
REFCLK_OUT ROBO_FS
10
9
8
7
6
5
4
3
10
9 VCC
8
7
5V
6 VCC
2 2
5
4
3
2
1
REVISIONS
NOTE: 1
ZONE
REV
DESCRIPTION
DATE
APPR
SB2 P<1> P<2>
3.3V OPTICS
SB1 P<1> P<2>
R49
1.0
1.0
R48
H
7B3>
5V OPTICS
PECL_VCC
1.0K 1.0UH L2 4.7UF C27 R38 0.01UF
H PBIAS\I
4F10<
0.1UF
0.1UF
0.1UF
0.1UF
C94 0.1UF
C59 0.1UF
SCLK\I
C92
C95
C60
C93
1
10UF
0.01UF
+
1
+
VCC
17 1 3 6 7 4.7K 4.7K 4.7K 4.7K R18 R20 R13 R17
7B10>
ROBO_FS\I
FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST
VCCN VCCN VCCN VCCN VCCQ VCCQ
9 16 18 25 2 8
U6
4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 GND GND GND GND GND GND
11 10 15 14 20 19 24 23 51 R46 51 R47 51 R45 4 3 5
1.0UH L1 0.01UF
G
4 5 29 30
C26
C5
C7
G
C24
CY7B991V
NOTE: 5
4.7K 4.7K 4.7K 4.7K R19 R21 R12 R16
26 27 31
12 13 21 22 28 32
5
U5
VCCR
VEER SD
4 2 3 R80 R82 330 330 330 R81
1
50 OHM 50 OHM 50 OHM
SD\I RXD_P\I RXD_N\I
3C10< 3C10< 3C10<
VCC F
R56 1.0 1.0 R55
1
TP1
RXDP RXDN
RX
OPTICAL SIGNAL
0.1UF C57 0.1UF C84 0.1UF C58 0.1UF C87 0.1UF C86 0.1UF
F 50 OHM PECL_VCC
0.01UF 49.9 R78 63.4 R77
TXD_P\I
3C10>
HFCT-5208 TX
VCCT
6
NOTE:4
C25 8 7
E
FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST
49.9
17 1 3 6 7 4.7K 4.7K 4.7K 4.7K R31 R33 R27 R28 4 5 29 30
VCCN VCCN VCCN VCCN VCCQ VCCQ
9
VCC
9 16 18 25 2 8
U7
C89
TXDP TXDN
VEET
R79
E 50 OHM TXD_N\I
4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 GND GND GND GND GND GND
11 10 15 14 20 19 24 23
51 R50 R51 51 51 R52 51 R53 51 R54
6 7 8 2 1
3C10>
CY7B991V
NOTE: 5
4.7K 4.7K 4.7K 4.7K R30 R32 R26 R29
26 27 31
SCLK_ROBO<8..1>\I VCC
3E1> 5G9< 10C1< 7G10< 9F10<
12 13 21 22 28 32
4.7K
R41
PECL_VCC D
14 C166 0.01UF 7
Y1 OSC_PECL PWR OUTP GND OUTN NOTE:4
8 1 270 R25 270 R23 1
DO NOT POPULATE FOR 5V OPTICS
D
TP22
PECLV\I
3C10<
OHMS
OHMS
4.7K
77.76MHZ 20 PPM NOTE: 3
R42
2
5
3
C SMB
4 1
PECL_VCC SOIC8 U4 50 OHMS
2
R4
NOTE:4
2
PECL
SB3 21 SB
1 1
7 6 8 0.01UF
TTL
D0
IN
Q0P Q0N
OUT
1 2 3 4 5 330 R2 330
2
SB4 221 SB
SB6 21 1 SB SB5 1 21 SB
SB7 21 SB SB8 2 21 SB
330
R5 330
1 50
1 50
J7 322P RIGHT_ANGLE
DO NOT POPULATE FOR 3.3V OPTICS
2
50 OHMS 50 OHMS 50 OHMS 50 OHMS
REFCLK_P\I REFCLK_N\I RRCLK_P\I RRCLK_N\I
3C10< 3C10< 3C10< 3C10<
C
D1 VCC
51
R9
Q1P Q1N GND
MC100ELT22
NOTE:2
C4
R3
B
REFCLK_OUT\I
7B3>
B
PMC-Sierra, Inc.
DRAWING A FOR 3.3V OPTICS CONNECT SOLDER BRIDGE SB2 AND FOR 5V OPTICS OPERATION CONNECT SOLDER BRIDGE SB1. FOR 3.3V OPTICS POPULATE U4 WITH A MC100LVELT22 AND FOR 5V OPTICS POPULATE U4 WITH A MC100ELT22. FOR 3.3V OPTICS INSTALL A 3V PECL MHZ OSCILLATOR AND FOR 5V OPTICS INSTALL A 5V PECL OSCILLATOR. FOR 3.3V OPTICS POPULATE RESISTORS R4, R5, R25, R46, R80, R81, AND R82 WITH 150 OHM RESISTORS. FOR 5.0V OPTICS POPULATE RESISTORS R4, R5, R80, R81, AND R82 WITH 330 OHM RESISTORS AND R25 AND R46 WITH 270 OHM RESISTORS. NOTE 5: DO NOT INSTALL 4.7K RESISTORS CONNECTED TO PINS 26, 27, 29, AND 30 OF U6 AND U7, UNLESS SCLK_ROBO<4..1> SIGNALS REQUIRE TIMING SKEWS. 10 9 8 7 6 5 NOTE NOTE NOTE NOTE 1: 2: 3: 4: TITLE=OPTICS_REFCLK_BLOCK ABBREV=OPTICS_REFCLK_BLOCK LAST_MODIFIED=Thu Jan 20 14:17:39 2000 DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN OPTICS_REFCLK_BLOCK ENGINEER: MK 4 3 2 ISSUE DATE: 00/01/19 REVISION NUMBER: 2 PAGE:2 TRUE 1 OF 10 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
U8
TP10 TP11
REV
DESCRIPTION
DATE
APPR
SBGA
7H7> H 10D10>
TX_RNG_CTRL<3..1>\I
TP4 TP5
3 C17 2 E17 1 D17 1 B23 A24 E22 E23 B24 D23 A25 C23 C24 D24 E24 B25 D25 C25 A23 AL7 B17 C14 E14 B13 D14 E25 C26 B27 B14
RX_RNG_CTRL<3..1>\I
TLRDI/TRCPFP RLAIS/TRCPCLK TLAIS/TRCPDAT LOS/RRCPFP LAIS/RRCPDAT LRDI/RRCPCLK LOF TSLDCLK SALM TOWCLK RSLDCLK ROWCLK TSLD TSOW RSLD TSUC RSOW TLDCLK RSUC TOHCLK RLDCLK TLD ROHCLK TLOW RLD RLOW TOH SPECTRA622 TTOH ROH TTOHFP PM5313 RTOH TTOHCLK RTOHFP RX/TX TTOHEN RTOHCLK OVERHEAD TTOHREI PGMRCLK TCLK 3 OF 6 RCLK PGMTCLK RFPO TPOH RPOH TPOHFP RPOHFP TPOHCLK RPOHCLK RPOHEN TPOHEN RALM TAD TAFP RTCEN TACK RTCOH TPOHRDY B3E RAD
B18 C18 A18 D18 E18 C19 A20 B19 B20 C20 E19 B21 D19 D20 E20 C21 D21 A22 D26 B22 C22 B15 D15 E15 C15 A19 A15 A17 A14 B26 3 2 1 1 2 3
7H7<
10C10<
H
7D10< 7D10> 7D10< 7D10>
TOWCLK\I
2
DS3RICLK\I ROWCLK\I
7D10< 7D10< 7D10< 7D10<
10G10> 10F10< 10F10< 10E10> 10E10>
TSOW\I
3 4
4
DS3ROCLK<3..1>\I DS3RODAT<3..1>\I DS3TIDAT<3..1>\I DS3TICLK<3..1>\I
U8 SBGA
RSOW\I
5 6
TOHCLK\I
5 6
ROHCLK\I
7 8
TOH\I
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 4.7K 4.7K R76 R87
ROH\I
9 10 11 12
G
RCLK\I RFP\I
13 14 15 16 17 18 19 20 21
7B3< 7B3<
10C1<
3
2
TX_OH_ALM<22..1>
1
RCV_OH_ALM<22..1> TRANSMIT OVERHEAD AND ALARM SIGNALS
1 2 3 4
100MIL J8
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
F
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
E
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31 P_33 P_35 P_37 P_39 P_41 P_43 P_45 P_47 P_49
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32 P_34 P_36 P_38 P_40 P_42 P_44 P_46 P_48 P_50
2
1
AK25 AL25 AJ24 AK24 AL20 AH19 AK19 AL19 AJ14 AG14 AJ13 AK13 AJ27 AK27 AH26 AJ26 AH21 AJ21 AK21 AH20 AG15 AH15 AK15 AL15
DS3RICLK DS3TICLK<12> DS3ROCLK<12> DS3TICLK<11> DS3ROCLK<11> DS3TICLK<10> DS3ROCLK<10> DS3TICLK<9> DS3ROCLK<9> DS3TICLK<8> DS3ROCLK<8> DS3TICLK<7> DS3ROCLK<7> DS3TICLK<6> DS3ROCLK<6> DS3TICLK<5> DS3ROCLK<5> DS3TICLK<4> DS3ROCLK<4> DS3TICLK<3> DS3ROCLK<3> DS3TICLK<2> DS3ROCLK<2> DS3TICLK<1> DS3ROCLK<1> DS3TDAT<12> DS3RDAT<12> DS3TDAT<11> DS3RDAT<11> DS3TDAT<10> DS3RDAT<10> DS3TDAT<9> DS3RDAT<9> DS3TDAT<8> DS3RDAT<8> DS3TDAT<7> DS3RDAT<7> DS3TDAT<6> DS3RDAT<6> DS3TDAT<5> DS3RDAT<5> DS3TDAT<4> DS3RDAT<4> DS3TDAT<3> DS3RDAT<3> DS3TDAT<2> DS3RDAT<2> DS3TDAT<1> DS3 DS3RDAT<1>
PM5313
AL27 AL23 AJ22 AK22 AL22 AG17 AH17 AJ17 AK17 AH12 AH11 AJ11 AK11 AG22 AH23 AJ23 AK23 AK18 AJ18 AH18 AG18 AG12 AJ12 AK12 AL12
TP8
TP9
TP6
TP7
G
3
2
1
3
2
F
1
SPECTRA622
4 OF 6
RECEIVE OVERHEAD AND ALARM SIGNALS SCLK_ROBO<8..1>\I
8
2D1> 5G9< 10C1<
7G10< 9F10<
ACK
7
APL<4..1>\I AC1J1V1<4..1>\I ADP<4..1>\I
7H2> 7H2> 7H2>
HEADER 25X2
E
4 3 2 1 4 3 2 1 4 3 2 1
U8
RN4 4.7K
RN3 4.7K
RN2 4.7K
RN1 4.7K
8 7 6 5
8 7 6 5
8 7 6 5
5 7 8 6
7H2>
RES_ARRAY_4
AD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD31 AC28 AC29 AC30 AC31 AB27 AB28 AB29 V27 V28 V29 V30 V31 U27 U28 U29 M29 M30 M31 L28 L29 L30 K27 K28 G29 G30 G31 F27 F28 F29 F30 E28
ACK APL<4> APL<3> APL<2> APL<1> AC1J1V1/AFP<4> AC1J1V1/AFP<3> AC1J1V1/AFP<2> AC1J1V1/AFP<1> ADP<4> ADP<3> ADP<2> ADP<1> TPAISCK TPAISFP TPAIS
E31 AB31 U31 K30 E30 AB30 U30 K29 E29 AD30 W31 M28 G28 E13 D13 C13
DD<31..0>\I
DD<31> DD<30> DD<29> DD<28> DD<27> DD<26> DD<25> DD<24> DD<23> DD<22> DD<21> DD<20> DD<19> DD<18> DD<17> DD<16> DD<15> DD<14> DD<13> DD<12> DD<11> DD<10> DD<9> DD<8> DD<7> DD<6> DD<5> DD<4> DD<3> DD<2> DD<1> DD<0>
AG31 AF29 AF30 AE27 AE28 AE29 AE30 AE31 AA29 AA30 Y27 Y28 Y29 Y30 Y31 W27 P27 P28 P29 P30 P31 N27 N28 N29 J27 J28 J29 J30 J31 H27 H28 H29 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5E9<
D
1 2 3 4 1 2 3 4 1 2 3 4 4 2 1 3
U8
SBGA
LINE SIDE 2 OF 6 SCPI<3> SCPI<2> SCPI<1> SCPI<0> SCPO<1> SCPO<0> C0 TDREF2 TDREF1
C1
4.7K
R36 4.7K
R40
0.047UF V1
V2 N1 P5
R37
E1 E2 F5 E3 E4 D2
4 3 2 1 4 3 2 1
C6
4.7K
VCC
4 3 2 1
AH30 AD28 W29 N31 H31 AD27 W28 N30 H30 AH27 AG26 AF28 AA28 R28 K31 B12 A12 A13 AG29
DCK DPL<4> DPL<3> DPL<2> DPL<1> DC1J1V1<4> DC1J1V1<3> DC1J1V1<2> DC1J1V1<1> DMODE<1> DMODE<0> DDP<4> DDP<3> DDP<2> DDP<1> DPAISCK DPAISFP DPAIS DFP
C
2C6> 2C6> 2F1> 2F1> 2F1> 2C6> 2C6> 2F1< 2E1< 2D2>
REFCLK_P\I REFCLK_N\I SD\I RXD_P\I RXD_N\I RRCLK_P\I RRCLK_N\I TXD_P\I TXD_N\I PECLV\I
M2 M1 U2 Y2 Y1 W1 W2 P2 P1 G2 R2 G3
REFCLK+ REFCLKSD RXD+ RXDRRCLK+ RRCLKTXD+ TXDPECLV PECLREF PREFEN
SPECTRA622 PM5313
ATP1 ATP0 PICLK PIN<7> PIN<6> PIN<5> PIN<4> PIN<3> PIN<2> PIN<1> PIN<0> FPIN OOF
L2 L3 AK4 AJ7 AH6 AJ6 AK6 AH5 AJ5 AK5 AL5 AH7 AH8
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
RES_ARRAY_4
RES_ARRAY_4
RES_ARRAY_4
D
AL10 AJ8 AK7 AJ10 AH10 AL9 AK9 AJ9 AH9 AL8 AK8 AK10 AG10 E26
SPECTRA622 PM5313
SYSTEM 1 OF 6
TDCK TC1J1V1/TFPO TPL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> TDP TFPI TFP
R35
R34
100
100
100
R39
TP16 TP21 TP20 TP19 TP17 TP18
4.7K R65 4.7K R66 4.7K R67 4.7K R68 4.7K R69 4.7K
R70
C
2K00
R59
4.7K
4.7K
B
U8
8E1>
B
R44
SBGA
R43
A<13..0>\I
13 12 11 10 9 8 7 6 5 4 3 2 1 0 D10 E10 A9 B9 C9 D9 E9 A8 B8 C8 D8 E8 A7 B7 B4 D5 B5 C5 A5
A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> TCK TMS TDI TDO TRSTB
PM5313
D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> ALE CSB WRB/RWB RDB/E RSTB INTB MBEB
C12 D12 E12 B11 C11 D11 A10 B10 D7 C7 C6 B6 D6 C10 E7 7 6 5 4 3 2 1 0
DDP<4..1>\I DC1J1V1<4..1>\I DPL<4..1>\I D<7..0>\I
5B6<> 7G2<> 8G1<>
4.7K R58 4.7K R57
5F9< 5G9< 5F9<
A
8G7> 8G7> 5A6> 8G7< 7A8>
TCK\I TMS\I TDO_TDI_TUPP\I TDO_TDI_SPECTRA\I TRSTB\I
CSB_SPECTRA\I WRB\I RDB\I RESETB\I INTB_SPECTRA\I
8C3> 8C3> 8C3> 7B8> 7D10<
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 DRAWING TITLE=SPECTRA_622_BLOCPCK ABBREV=SPECTRA_622_BLOCK LAST_MODIFIED=Thu Jan 20 14:18:10 2000 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN SPECTRA_622_BLOCK ENGINEER: MK 3 2 ISSUE DATE: 00/01/19 REVISION NUMBER:2 A
SPECTRA622
JTAG/MICRO 5 OF 6
PAGE:3 TRUE 1
OF 10
10
9
8
7
6
5
4
C
D
A E F G H
B
10
2H1>
0.1UF 0.1UF C43 0.1UF C53 0.1UF C103 0.1UF C62 0.1UF C55 0.1UF C52 C31 0.1UF 0.1UF C67 0.1UF 0.1UF 0.1UF C75 0.1UF C68 0.1UF C111 C77 C49 0.1UF C74 C44 0.1UF R60 0.1UF 0.1UF
5V
10
0.1UF 0.1UF C42 0.1UF C34 0.1UF C79 0.1UF C110 0.1UF C70 C66 0.1UF C80 0.1UF C56 0.1UF C63 0.1UF C51 0.1UF C64 0.1UF C29 0.1UF C50 C73 0.1UF C33 0.1UF
C71 0.1UF C30 0.1UF C61 0.1UF C28 0.1UF
PBIAS\I
VCC
VCC
VCC
VCC
C78 0.1UF
9
C32 C81 0.1UF 0.1UF C76 C98 0.1UF C65 C54 1.0K
9
8 7 6 5 DRAWING TITLE=SPECTRA_622_BLOCK ABBREV=SPECTRA_622_BLOCK LAST_MODIFIED=Thu Jan 20 14:18:14 2000 ENGINEER: MK 2 TRUE 1 PAGE:4 OF 10 DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN SPECTRA_622_BLOCK 4 3
0.01UF C69 9 8 18 C40 0.01UF C41 17 14 C36 0.01UF 0.01UF C35 C38 0.01UF 0.01UF 0.01UF 13 10 C37 C46 4.7UF R83 1.0 12 A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31 AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30
8
W4 M5 Y4 R4
E6 AK28
AB3 AA4 Y5 U1 R1 R3 N3 K2
V4 K1
V3 L4
SBGA
SAVS<7> SAVS<6> SAVS<5> SAVS<4> SAVS<3> SAVS<2> SAVS<1> SAVS<0> POWER 6 OF 6
QAVS<1> QAVS<0>
QAVD<1> QAVD<0>
PBIAS<3> PBIAS<2> PBIAS<1> PBIAS<0>
VBIAS<1> VBIAS<0>
7 6
VCC
SPECTRA622 PM5313
5
VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10> VSS<11> VSS<12> VSS<13> VSS<14> VSS<15> VSS<16> VSS<17> VSS<18> VSS<19> VSS<20> VSS<21> VSS<22> VSS<23> VSS<24> VSS<25> VSS<26> VSS<27> VSS<28> VSS<29> VSS<30> VSS<31> VSS<32> VSS<33> VSS<34> VSS<35> VSS<36> VSS<37> VSS<38> VSS<39> VSS<40> VSS<41> VSS<42> VSS<43> VSS<44> VSS<45> VSS<46> VSS<47> VSS<48> VSS<49> VSS<50> VSS<51> VSS<52> VSS<53> VSS<54> VSS<55>
VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10> VDD<11> VDD<12> VDD<13> VDD<14> VDD<15> VDD<16> VDD<17> VDD<18> VDD<19> VDD<20> VDD<21> VDD<22> VDD<23> VDD<24> VDD<25> VDD<26> VDD<27> VDD<28> VDD<29> VDD<30> VDD<31> VDD<32> VDD<33> VDD<34> VDD<35> VDD<36> VDD<37> VDD<38> VDD<39> VDD<40> VDD<41> VDD<42> VDD<43> VDD<44> VDD<45> VDD<46> VDD<47> AVS<18> AVS<17> AVS<16> AVS<15> AVS<14> AVS<13> AVS<12> AVS<11> AVS<10> AVS<9> AVS<8> AVS<7> AVS<6> AVS<5> AVS<4> AVS<3> AVS<2> AVS<1> AVS<0>
R5 P4 V5 Y3 N4 N5 J1 K4 J5 H1 J3 AD2 AD1 AC3 U4 AC2 AC1 AB2 AA3 0 7 3
A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31
AVD<18> AVD<17> AVD<16> AVD<15> AVD<14> AVD<13> AVD<12> AVD<11> AVD<10> AVD<9> AVD<8> AVD<7> AVD<6> AVD<5> AVD<4> AVD<3> AVD<2> AVD<1> AVD<0>
P3 N2 W3 W5 M4 M3 K5 K3 H2 J4 J2 AD3 AC5 AC4 U5 AB5 AB4 AB1 AA2 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 6 1 5
U8
4
AVD<18..0>
4
11
16
15
C45
C47 0.01UF
C48 0.01UF
0.01UF C39 0.01UF C72 4.7UF
3
ZONE
REV
R84
1 C200 22UF C201 2.2UF 1
1.0
SB9 122 SB SB10 122 SB
C1 10UF 2 1
SENSE
13 2
2
15
5 16 4
SOIC U19
C2-
C2+
DESCRIPTION
REVISIONS
SYNC
20 1 12 11 10 9
OUT1 OUT2 FB
6 3
GND TAB/ GND SHDN
3.3V U3 LT1129CQ VOUT VIN
TO263
GND2 GND1
19
3V8
18
COM
17 C3
4
5
TPS60100 PGND4 PGND3 PGND2 PGND1 C1C1+
SKIP
47UF C2
IN1 IN2
ENABLE
10UF C202 3
47UF 7 14 8 6 2.7 R1
1
PMC-Sierra, Inc.
ISSUE DATE: 00/01/19 A
DATE
10
VCC
2.2UF C203
R88 10 R89
APPR
5V
REVISION NUMBER:2
B
C
D
E
F
G
H
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
RN57 4.7K
8 7 6 5
REV
DESCRIPTION
DATE
APPR
RES_ARRAY_4
H VCC J6 STM-1 (STS-3) STM-4 (STS-12)
H
J2 D23 L21 AA11
H3
U11
AB16 T22 K22 H3 AA16 U23 L20 J3 AC17 T21 K23 H2 AC10 Y10 AB8 W21 V21 V22 D22 D21 A21 P2 M3 L4
1 2 3
1 2 3 4
SBGA
OTMF<1> OTMF<2> OTMF<3> OTMF<4>
P1 K4 W3 Y2 N4 J1 N3 AC5 AA20 D17 U4 AA1 AA17 A15 R1 W4 AB18 D14 P4 AA7 W20 B19 W2 AB6 Y21 C18 V3 Y8 AA23 A20 Y1 AA6 Y19 A19 W1 AB5 AC4 AA5 AB4 AC3 Y5 AA4 Y3 AC21 AB20 AA19 AC20 AB19 AA18 Y17 AC19 B18 C17 D16 A17 C16 B16 C15 B15 V2 U3 T4 T3 U1 T2 R3 R2
J2 STM-1 (STS-3) G STM-4 (STS-12)
6 1 2 3
H3
J4
1 2 3
H3
3E1> 2D1> 7H2> 3B1>
SCLK_ROBO<8..1>\I GSCLK_FP\I DC1J1V1<4..1>\I DPL<4..1>\I
4 3 2 1 4 3 2 1
3B1>
F
3B1>
DDP<4..1>\I DD<31..0>\I
3D1>
E
D
4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLK HSCLK IHSMODEB OHSMODEB GSCLK<1> GSCLK_FP GSCLK<0> ITMF<4> ITMF<3> ITMF<2> ITMF<1> IC1J1<4> IC1J1<3> IC1J1<2> IC1J1<1> IPL<4> IPL<3> IPL<2> IPL<1> ITPL<4> ITPL<3> ITPL<2> ITPL<1> ITV5<4> ITV5<3> ITV5<2> ITV5<1> IAIS<4> IAIS<3> IAIS<2> IAIS<1> IDP<4> IDP<3> IDP<2> IDP<1> ID<31> ID<30> ID<29> ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ID<0>
IDLE<4> IDLE<3> IDLE<2> IDLE<1> COUT<4> COUT<3> COUT<2> COUT<1> TPOH<4> TPOH<3> TPOH<2> TPOH<1> POH<12> POH<11> POH<10> POH<9> POH<8> POH<7> POH<6> POH<5> POH<4> POH<3> POH<2> POH<1>
G
TUPP+622 PM5363
SYSTEM 1 OF 3
OC1J1V1<4> OC1J1V1<3> OC1J1V1<2> OC1J1V1<1> OPL<4> OPL<3> OPL<2> OPL<1> OTPL<4> OTPL<3> OTPL<2> OTPL<1> OTV5<4> OTV5<3> OTV5<2> OTV5<1> AIS<4> AIS<3> AIS<2> AIS<1> ODP<4> ODP<3> ODP<2> ODP<1> OD<31> OD<30> OD<29> OD<28> OD<27> OD<26> OD<25> OD<24> OD<23> OD<22> OD<21> OD<20> OD<19> OD<18> OD<17> OD<16> OD<15> OD<14> OD<13> OD<12> OD<11> OD<10> OD<9> OD<8> OD<7> OD<6> OD<5> OD<4> OD<3> OD<2> OD<1> OD<0>
AB11 L22 F21 D3 AC11 L23 G20 E4 AB15 R22 J23 H4 Y14 P20 K20 G3 AA15 R21 K21 G1 AC15 R23 J21 F2 AA14 AB14 AC14 Y13 AA13 AC13 AB12 AA12 P21 P22 P23 N20 N21 N23 M21 M22 H22 G23 H21 G22 H20 G21 F22 E23 E1 G4 F3 E2 D1 E3 D2 C1
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
DC1J1V1_T<4..1>\I DPL_T<4..1>\I
7H10<
7H10<
DTPL_T<4..1>\I
7H10<
F DTV5_T<4..1>\I
7H10<
4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDP_T<4..1>\I DD_T<31..0>\I
7H10<
7H10<
E
D
AA10 AB9 AA8 Y23 U20 U21 C23 C20 B20 N1 L1 K1 Y11 AC9 AA9 Y22 W22 W23 E21 E20 D19 P3 M2 L3 L2 AC7 T20 C19 K3
POHFP<12> POHFP<11> POHFP<10> POHFP<9> POHFP<8> POHFP<7> POHFP<6> POHFP<5> POHFP<4> POHFP<3> POHFP<2> POHFP<1> POHEN<12> POHEN<11> POHEN<10> POHEN<9> POHEN<8> POHEN<7> POHEN<6> POHEN<5> POHEN<4> POHEN<3> POHEN<2> POHEN<1> POHCK RAD<4> RAD<3> RAD<2> RAD<1>
POHCK_T\I RAD_T<4..1>\I POHFP_T<4..1>\I
10C1< 10C1< 10G10< 10G10<
C
4 3 2 1
C
4
3
2
VCC
4.7K
4.7K
R72
R71
U11
C6 D7 A4 B6 C7 A5 C11 D11 A10 B10 C10 A9 D10 B9 C9 B8 A7 C8 B7 D8
SBGA
B
7B8> 8C3> 8C3> 8C3> 8E1>
RESETB\I CSB_TUPP\I RDB\I WRB\I A<13..0>\I
13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBEB PM5363 RSTB CSB D<7> RDB/E D<6> WRB/RWB D<5> ALE D<4> A<13> D<3> A<12> D<2> A<11> D<1> A<10> D<0> A<9> INTB A<8> A<7> TCK A<6> TMS A<5> TDI A<4> TDO A<3> TRSTB A<2> A<1>JTAG/MICRO A<0>
A14 D13 C13 B13 A13 C12 B12 A11 C14 C5 C4 B4 A3 D5
7 6 5 4 3 2 1 0
D<7..0>\I
3B6<> 7G2<> 8G1<>
1
B
INTB_TUPP\I TCK\I TMS\I TDO_TDI_PCI\I TDO_TDI_TUPP\I TRSTB\I
7D10< 8G7> 8G7> 8G7> 3A10< 7A8>
TUPP+622
2 OF 3
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 DRAWING TITLE=TUPP_622_BLOCK ABBREV=TUPP_622_BLOCK LAST_MODIFIED=Thu Jan 20 14:17:34 2000 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN TUPP_622_BLOCK ENGINEER: MK 3 2 ISSUE DATE: 00/01/19 REVISION NUMBER:2 A
A
PAGE:5 TRUE 1
OF 10
10
9
8
7
6
5
4
C
D
0.1UF C163 0.1UF C88 0.1UF 0.1UF C127 0.1UF C131 0.1UF C118 0.1UF C132 0.1UF C165 0.1UF C129 0.1UF C115 0.1UF C117 0.1UF 0.1UF 0.1UF C136 0.1UF C128 0.1UF C130 0.1UF C91 0.1UF C126 0.1UF C119 0.1UF C116 0.1UF C83 0.1UF C122 C120 0.1UF 0.1UF C82 C124
A E F G H
0.1UF 0.1UF
B
10
C134 0.1UF C112 0.1UF C90 0.1UF C133 0.1UF C114 0.1UF C113 0.1UF C164 0.1UF C135 0.1UF
10
9 VCC
C162 0.1UF 1 0.1UF 0.1UF C123 C121 C10
9
VCC
VCC
2.5 V
C85
C161
C125
IN
U10
MIC39150
2
2.5V
10UF C9 270 R122
GND TAB
TO220
OUT
8
4 AB17 AB13 AB10 AB7 U2 N2 K2 G2 3
8
2.5 V
U11
7
VDDI<8> VDDI<7> VDDI<6> VDDI<5> VDDI<4> VDDI<3> VDDI<2> VDDI<1> POWER
7
VCC
TUPP+622 PM5363
3 OF 3
6 5 DRAWING TITLE=TUPP_622_BLOCK ABBREV=TUPP_622_BLOCK LAST_MODIFIED=Thu Jan 20 14:17:36 2000 MK ENGINEER: 2 TRUE 1 PAGE:6 OF 10 DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN TUPP_622_BLOCK 4 3
6
AC22 AC18 AC16 AC12 AC8 AC6 AC2 AB23 AB21 AB3 AB1 AA22 AA2 V23 V1 T23 T1 M23 M1 H23 H1 F23 F1 C22 C2 B23 B21 B3 B1 A22 A18 A16 A12 A8 A6 A2
VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>
VDD<35> VDD<34> VDD<33> VDD<32> VDD<31> VDD<30> VDD<29> VDD<28> VDD<27> VDD<26> VDD<25> VDD<24> VDD<23> VDD<22> VDD<21> VDD<20> VDD<19> VDD<18> VDD<17> VDD<16> VDD<15> VDD<14> VDD<13> VDD<12> VDD<11> VDD<10> VDD<9> VDD<8> VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0> VDDI<16> VDDI<15> VDDI<14> VDDI<13> VDDI<12> VDDI<11> VDDI<10> VDDI<9>
B5 B11 B14 B17 E22 J22 N22 U22
AC23 AC1 AB22 AB2 AA21 AA3 Y20 Y18 Y15 Y12 Y9 Y6 Y4 V20 V4 R20 R4 M20 M4 J20 J4 F20 F4 D20 D18 D15 D12 D9 D6 D4 C21 C3 B22 B2 A23 A1
5
SBGA
2.5 V 4 3
ZONE REV DESCRIPTION
2 1
REVISIONS
PMC-Sierra, Inc.
ISSUE DATE: 00/01/19 A
DATE APPR
REVISION NUMBER:2
B
C
D
E
F
G
H
10
9 D1 VCC
330 R6
8
7
6 RX_RNG_CTRL<3..1>\I TX_RNG_CTRL<3..1>\I
5
4 VCC
3
2
1
REVISIONS
ZONE REV DESCRIPTION
GSCLK_FP\I
5G9<
3H6> 3H10< 10D10>
GREEN PCB RIGHT ANGLE
2 1
DATE
APPR
INT_OUT
3 2
H
5F2> 5F2> 5G2> 5F2> 5F2> 5E2>
DDP_T<4..1>\I DPL_T<4..1>\I DC1J1V1_T<4..1>\I DTPL_T<4..1>\I DTV5_T<4..1>\I DD_T<31..0>\I RESETB\I
INT
H ADP<4..1>\I APL<4..1>\I AC1J1V1<4..1>\I AD<31..0>\I
3E1< 3E1< 3E1< 3D6<
7 6 5 4 3 2 1 0 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 7 6 5 4 3 2 1 0
3 2 1 3 2 1
1
TP3
CCLK
3E1> 2D1>
SCLK_ROBO<8..1>\I
C24 D22 C23 B24 C22 D21 A23 D20 C21 B22 B21 C20 B20 A21 D18 C19 B19 A20 D17 C18 B18 C17 B17 C16 B16 A16 D15 C15 B15 A15 C14 D14 B14 A13 B13 C13 A12 B12 C12 D12 A11 B11 D11 A9 B9 C10 D10 B8 C9 D9 A7 B7 D8 A6 B6 C7 A4 B5 C6 D6 A3 D5 C4 B3 D4 5
0R1 R14
0
WRB\I D<7..0>\I A<13..0>\I RDB\I
8C3> 3B6<> 5B6<> 8G1<> 8E1> 8C3>
U12
J11 CPCI PROM
H3
IO/GCK8/A15 IO/A14 IO IO IO IO IO IO IO/A13 IO/A12 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO/A11 IO/A10 IO IO IO/A18 IO/A19 IO/A9 IO/A8 IO/A7 IO/A6 IO/A20 IO/A21 IO IO IO/A5 IO/A4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO/A3 IO/CS1/A2 IO IO IO/GCK7/A1 IO/WS/A0 O/TDO
1 2 3
DATA_EPROM
VCC G
G
5 1 D23 C25 D24 E23 C26 E24 F24 E25 D26 G24 F25 F26 H23 H24 G25 G26 J23 J24 H25 K23 K24 J25 L24 K25 L25 L26 M23 M24 M25 M26 N24 N25 N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 T23 V26 U24 V25 V24 U23 Y26 W25 W24 V23 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 AB23 AD24
DIN
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C108 C102 C105 C154 C149 C107 C104 C160 C152 C153 0.1UF 0.1UF C156 C99
8C3< 9F10<> 9D10<> 9B1<> 10C10<>
INTB\I PIO<5..0>\I
4 3 10 11 12 13 14 15 16 17 18 19 20 21 2 22 23 24 25 26 27 28 29 30 31 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 52 8 9
TP2
F
VCC E Y2
0.01UF C18
3V3
4
8 5
GND 77.76MHZ 20PPM
OUT
REFCLKTTL
3A6> 5B6>
INTB_SPECTRA\I INTB_TUPP\I
D
3H6> 3H6> 3G6> 3G6> 3H10> 3H10< 3G10> 3G10<
ROWCLK\I RSOW\I ROHCLK\I ROH\I TOWCLK\I TSOW\I TOHCLK\I TOH\I
1
TP12
1
IO/GCK1/A16 IO/A17 IO IO IO/TDI IO/TCK IO IO IO IO IO IO IO IO IO IO IO IO IO/TMS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO/GCK2 O/M1 I/M0
XC4028XL-BG352 BGA
CCLK IO/GCK6/DOUT IO/DIN/D0 IO IO IO IO IO/RCLK/RDY/BUSY IO/D1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO/D2 IO IO IO IO IO IO IO IO IO/RS IO/D3 IO IO/D4 IO IO IO IO IO IO IO IO IO/CSO IO/D5 IO IO IO IO IO IO IO IO IO IO IO IO/D6 IO IO IO IO IO IO IO/GCK5 IO/D7 PROGRAM
C3 E4 D3 C2 E3 F4 D2 G4 F3 E2 F2 G3 G2 F1 J4 H3 H2 G1 K4 J3 J2 K3 J1 L3 L2 L1 M4 M3 M2 M1 N3 N4 N2 P1 P2 P3 R1 R2 R3 R4 T1 T2 U2 V1 V2 U3 U4 W2 V3 V4 Y1 Y2 W3 W4 AA1 AA2 Y3 AC1 AB2 AA3 AA4 AD1 AB4 AC3 AD2 AC4
26 8 9 10 11 12 1 13 14 15 16 17 18 19 20 21 22 23 24 25 2 27 28 29 30 31 0 1 47 3 46 4 45 44 43 42 41 40 39
VCC
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C100
C155
C101
C106
C150
C151
C158
C109
C157
0.1UF
C159
C97
C96
F
VCC
E
CSB_FPGA\I
5 38 37 36 35 34 33 32 31 30 29 28 6 27 26 25 24 23 22 1
8C3>
D
TP13
7
J12 1 CPCI
2
PROG\I PROG_XCHK
8C3>
J10
P_1 P_3 P_5 P_2 P_4 P_6
I/M2 IO/GCK3 I/HDC IO IO IO IO/LDC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO/INIT IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO/GCK4 DONE
1 3 5 4.7K 4.7K R10 4.7K
2 4 6
VCC
XCHK 3 H3 PROG
HEADER 3X2
R11
R24
4.7K
C
R61
C DONE\I
8C3<
0
2G10< 10D1< 9F1< 9D1< 9G10>
ROBO_FS\I DBUS_EN\I SCLK_EXT\I
TP15
1
10D1< 9G1<
9E10< 9D1>
DROP_F<52..0>\I
TP14
8C1>
PLX_CLK\I
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2
1
AC23 AE24 AD23 AC22 AF24 AD22 AE23 AE22 AF23 AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 AD18 AE19 AC17 AD17 AE18 AF18 AE17 AE16 AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AD11 AF9 AD10 AE9 AD9 AC10 AF7 AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 AD6 AC7 AF4 AF3 AD5 AE3 AD4 AC5 AD3
ADD_F<47..0>\I
9C1<> 9C10<> 9E1<> 9H10<> 10F1<>
51 51 R73 R15
SCLK\I REFCLK_OUT\I EXT_REF\I RCLK\I RFP\I
2H10< 2B6< 10C10> 3G6> 3G6>
B
TC74LVX08FN
B
U2 VCC
0.1UF C204
8C3>
RESET_PCI\I VCC U1
9 8 10
RESETB\I
3A6<
5B10<
VCC
0.1UF
4 0.1UF 4.7K
C17
5V
VCC
20
R22
MAX811T
3 1
U2
1 3 2
MR
17 14
VCC
RESET GND
1
2
C19
TC74LVX08FN
U15 VPP CEO
TC74LVX08FN
PBNO
A
4
TC74LVX08FN
2
11 TRSTB\I
U2
6 5
8G7>
TRSTB_PCI\I
13
3A10< 5A6<
GND
RESET SW1
U2
12
XC1701L-PD20C DATA 2 CLK 4 OE 6 CE 8
100MIL J9
1 2 3 4 5 6 7 8
CCLK PROG_XCHK
VCC VCC+5 GND CCLK DONE DIN PROG INIT XCHK
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 DRAWING TITLE=FPGA ABBREV=FPGA LAST_MODIFIED=Thu Jan 20 14:17:45 2000 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN FPGA ENGINEER: MK 3 2 ISSUE DATE: 00/01/19 REVISION NUMBER:2 A
10
DATA_EPROM
PAGE:7 TRUE 1
OF 10
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
RN11 4.7K
5 7 6 8
RES_ARRAY_4
PCI_VCC_5V
4 2 3 1
U14
3A10< 5B6< 3A10< 5B6< 3A10> 5B6< 7A9<
5V 5V
PCI_VCC_5V G PCI_VCC_3.3V TMS\I TCK\I TDO_TDI_SPECTRA\I TDO_TDI_PCI\I TRSTB_PCI\I PCI_AD<31..0> PCI_CBE<3..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 28 23 16
VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10>
3 2 1 4 3 2 1 4 2 1 4 3 2 1 4 1 3 2 1 4 3 2 1 4 1 4 3 2 1 4 3 2 3 3 4 2 2 1 2 3 4 3 4 3 2 1 4 1
1 10 27 41 50 66 81 103 121 146 91 90 89 88 87 86 85 84 83 5 82 6 79 7 78 8 77 5 76 6 75 7 74 8 73 5 72 6 71 7 70 8 69 5 62 6 61 7 60 8 59 5 58 6 57 7 56 8 55 5 54 6 53 7 52 8 92 93 94 95 96 97 98 100 101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 122 49 48 47 46 137 136 135 134 133 132 63 130 131 138 139 140 141 123 124 127 126 125 128 129 64 68 0 1 2 3 4 5 6 7 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
RN42
5 6 7 8
5 6 7 8
4.7K RN46
4 3 2 1
7 6 5 4
3 2 1 0
4 3 2 1
4.7K
G
DATA BUS
D<7..0>\I
3B6<> 5B6<> 7G2<>
J1
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
F
29
17
4.7K
R121
15 9 4
1RN488 2 7 3 6 4 5
4.7K RN47 8
4.7K
RN50
4.7K
1
RN51
E
25 20
11 6 0
D
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25
RN55 4.7K
0 1 2 3 4 5 6 7 8 9 10 11 12 13
31 22 13 04
111 102 93 84
1 2 133 124
4.7K
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
30 26 3 21 18
12 7
RN22 RN22 RN22 RN21 RN21 RN21 RN21 RN20 RN20 RN20 RN19 RN19 RN19 RN19 RN18 RN56 RN16 RN16 RN16 RN15 RN15 RN15 RN15 RN14 RN14 RN13 RN13 RN13 RN13 RN12 RN12 RN12 RN20 RN18 RN16 RN14 RN56 RN17 RN17 RN17 RN56 RN14 RN17 RN56 RN18 RN12 RN22 RN18
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
6 7 8 5 6 7 8 5 7 8 5 6 7 8 5 8 6 7 8 5 6 7 8 5 8 5 6 7 8 5 6 7 6 6 5 7 7 8 7 6 5 6 5 6 7 8 5 8
43 42 39 38 37 36 35 34 32 31 30 29 28 25 24 23 11 8 7 6 5 4 3 2 157 156 155 154 153 152 151 150 33 22 12 158 21 13 14 15 17 159 16 19 20 149 148 44 18 144 143 145 142
AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31> C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3> PAR FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB PERRB SERRB CLK RSTB INTAB LOCKB EESK EEDO EEDI EECS TEST VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10>
14 8 3
4.7K
4.7K R74
R93
C
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A CPCI
99 9 26 40 51 65 80 104 120 147 160
NM93CS46
4.7K
R91
31 27 24 22 19 2
CS SK DI DO
4 3 2 1
U13
VCC PRE PE GND
5V
8 7 6 5
1 13 10 0 5 2 4.7K R92
RN49
PCI_VCC_5V F1 B
C12 0.1UF C14 0.1UF 47UF C21 0.1UF
5V
1 2 3 4
RN52
7 8 6 5
D3
330 R8 47UF C23 2 1
5V
4.7K
5V
C8
5V
PCI-9050-1
4.7K
0.1UF
LAD<0> LAD<1> LAD<2> LAD<3> LAD<4> LAD<5> LAD<6> LAD<7> LAD<8> LAD<9> LAD<10> LAD<11> LAD<12> LAD<13> LAD<14> LAD<15> LAD<16> LAD<17> LAD<18> LAD<19> LAD<20> LAD<21> LAD<22> LAD<23> LAD<24> LAD<25> LAD<26> LAD<27> LAD<28> LAD<29> LAD<30> LAD<31> LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LBEB<0> LBEB<1> LBEB<2> LBEB<3> LINTI1 LINTI2 LCLK LHOLD LHOLDA LRESETB BCLKO CSB<0> CSB<1> USER0/WAITOB USER1/LLOCKOB USER2/CS2B USER3/CS3B ADSB BLASTB LWR RDB WRB LRDYIB BTERMB ALE MODE
5V
RN41 4.7K F RN43 4.7K RN44 4.7K
5V
RN45 4.7K RN54 4.7K
8 7 6 5 8 7 6 5 7 6 5
ADDRESS BUS A<13..0>\I
7 6 5 4
3B10< 5B10< 7G2<
E
5V
D 4.7K
RN53
1 2 3 4
5 6 7 8
INTB\I
7G10>
47
R90
RESET_PCI\I CSB_SPECTRA\I CSB_TUPP\I DONE\I PROG\I CSB_FPGA\I
7B10< 3A6< 5B10< 7C2> 7D2< 7E2<
U9
74FCT807
RN5 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10
3 5 7 9 11 12 14 16 18 19 3 2 1 4
47
6 7 8 5
C PLX_CLK\I
7C10<
RDB\I WRB\I
1 IN 3A6< 7G2< 5B10< 3A6< 7G2< 5B10<
5V
8 7 6 5
2.000A
C13
+5.0 VOLTS
0.1UF C198 0.1UF C167 0.1UF C199 0.1UF C197 0.1UF C196
LOCATE CAPS AT FUSE VCC PCI_VCC_3.3V F2
0.1UF 0.1UF 0.1UF 47UF 220 R7
D2
2 1 3 4
B
PMC-Sierra, Inc.
2 1
3.000A
C15
47UF
C20
C11
C16
C22
A
+3.3VOLTS DRAWING
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Thu Jan 20 14:17:53 2000 8 7 6 5 4 3 TITLE: SPECTR-622/TUPP+622 REF. DESIGN SYS_INTERFACE ENGINEER: MK 2
ISSUE DATE: 00/01/19 REVISION NUMBER:2
A
LOCATE CAPS AT FUSE
PAGE:8 TRUE 1
OF 10
10
9
10
9
8
7
6
5
4
3
2
1
REVISIONS
VCC NOTE:1
R101 R103 R105 R107 R109 R111 R113 R116 R95 R97 R99 R63
ZONE
REV
DESCRIPTION
DATE
APPR
150
150
150
150
150
150
150
150
150
150
150
150
H
PI74FCT163244
10F1<> 9E1<> 9C1<> 7C2<> 9C10<> 7C2<>
H
THEV_TERM<11..0>
0
1
2
3
4
5
6
7
8
9
10
11
R100
R102
R104
R106
R108
R110
R112
R114
R96
R98
R115
U24 ADD_F<47..0>\I
0 1 2 3 4 5 6 7 51 R62 8 9 10 11 2 3 5 6 8 9 11 12 13 14 16 17 8 7 6 5 19 20 22 23 7 18 31 42 45 39
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND 1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
G
7B10<
SCLK_EXT\I LACI_1 VCC
1 2 3 4
RN33 RN33 RN33 RN33
C178 0.1UF
22 22 22 22
C179 0.1UF
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
0 1 2 3 4 5 6 7 8 9 10 11
AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AC1J1V1_1 APL_1 ADP_1 LAC1_1
J5
A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 A5 B5 C5 D5 E5 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 A8 B8 C8 D8 E8 A9 B9 C9 D9 E9 A10 B10 C10 D10 E10 A11 B11 C11 D11 E11 A12 B12 C12 D12 E12 A13 B13 C13 D13 E13
150
150
150
150
150
150
150
150
150
150
150
R64
150
PI74FCT163244
G
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
U17 DD_8 DD_9 DD_10 DD_11 DD_12 DD_13 DD_14 DD_15 DC1J1V1_2 DPL_2 DDP_2 DTPL_2 DTV5_2 ROBO_2 AD_16 AD_17 AD_18 AD_19 AD_20 AD_21 AD_22 AD_23 AC1J1V1_3 APL_3 ADP_3 SPARE_4 DD_16 DD_17 DD_18 DD_19 DD_20 DD_21 DD_22 DD_23 LAC1_3
26 27 28 1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34 2 3 4 1 2 2 3 4 1 2 3 4 1
DBUS_EN\I
F
9B1<> 7G10<> 10C10<> 9D10<>
SPARE_2 SPARE_1 PIO<5..0>\I
0 1
PI74FCT163244
U25 DBUS_EN\I
2D1> 3E1>
SCLK_EXT_1 ROBO_1
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
SCLK_ROBO<8..1>\I
1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12
7C10> 9D1>
DROP_F<52..0>\I
E
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
RN37 RN37 RN37 RN37 RN36 RN36 RN36 RN36 RN35 RN35 RN35 RN35 RN34 RN34 RN34 RN34
C172 0.1UF C174 0.1UF
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
C173 0.1UF
5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8
ROBO_2
DD_0 DD_1 DD_2 DD_3 DD_4 DD_5 DD_6 DD_7 DC1J1V1_1 DPL_1 DDP_1 DTPL_1 VCC DTV5_1
10F3<
ROBO_3
D
9B1<> 7G10<> 10C10<> 9F10<>
PIO<5..0>\I
2
PI74FCT163244
10F1<> 9E1<> 7C2<> 9C1<> 9H10<>
A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 A5 B5 C5 D5 E5 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 A8 B8 C8 D8 E8 A9 B9 C9 D9 E9 A10 B10 C10 D10 E10 A11 B11 C11 D11 E11 A12 B12 C12 D12 E12 A13 B13 C13 D13 E13
0.1UF
C175
A14 B14 C14 D14 E14 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 D19 E19 A20 B20 C20 D20 E20 A21 B21 C21 D21 E21 A22 B22 C22 D22 E22
A14 B14 C14 D14 E14 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 D19 E19 A20 B20 C20 D20 E20 A21 B21 C21 D21 E21 A22 B22 C22 D22 E22
RN9 RN9 RN9 RN8 RN8 RN8 RN8 RN7 RN7 RN7 RN7 RN6 RN6
22 22 22 22 22 22 22 22 22 22 22 22 22
7 6 5 8 7 6 5 8 7 6 5 8 7
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
DROP_F<52..0>\I
13 14 15 16 17 18 19 20 21 22 23 24
7C10> 9D1>
0.1UF
C177 0.1UF
C176
4.7K
R117
DBUS_EN\I
25
7B10>
F
0.1UF
C141 0.1UF
C144 0.1UF
C143 0.1UF
C142
VCC
PI74FCT163244
U18
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
ADD_F<47..0>\I
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
24 25 26 27 28 29 30 31 32 33 34 35 22 R85 4 3 2
7C2<> 9C1<> 9C10<> 9H10<> 10F1<>
E
LAC1_3 RN10 RN10 RN10 VCC
0.1UF
22 22 22
5 6 7
DD_16 DD_17 D_18
0.1UF C137
0.1UF C138
0.1UF C139
C140
F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22
F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 2 3 4 1
D DBUS_EN\I
7B10>
PI74FCT163244
DROP_F<52..0>\I
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34 29 30 31 32 33 34 35 36 37 38 39 36
U26 RN40 RN40 RN40 RN39 RN39 RN39 RN39 RN38 RN38 RN38 RN38
22 R94
7C10> 9E10< 9G1< 10D1<
U16 ADD_F<47..0>\I
12 13 14 15 16 17 18 19 20 21 22 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND 1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
C
LAC1_2 VCC
23 22 R86
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
SPARE_3 AD_8 AD_9 AD_10 AD_11 AD_12 AD_13 AD_14 AD_15 AC1J1V1_2 APL_2 ADP_2 LAC1_2
ZPACK5X22B CPCI
22 22 22 22 22 22 22 22 22 22 22
7 6 5 8 7 6 5 8 7 6 5
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
CPCI CONNECTOR J5
10F3< 10F3< 10F3< 10F3< 10F3< 10E3<
DC1J1V1_3 DPL_3 DDP_3 DTPL_3 DTV5_3 LAC1_4
2 3 4 1 2 3 4
VCC
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
C
10F1<> 9E1<> 7C2<> 9C10<> 9H10<>
ADD_F<47..0>\I SPARE_4
0.1UF
0.1UF
C148 0.1UF
C146 0.1UF
0.1UF
C170 0.1UF
C169 0.1UF
C168 0.1UF
C145
C147
C171
B
B
3
PIO<5..0>\I
9F10<> 7G10<> 9D10<> 10C10<>
PMC-Sierra, Inc.
A SPARE RN31 RN10 RN40 RN29 NOTE 1: WHEN OPERATING AT 77.76 MHZ INSTALL 150 OHM PULL-UP AND PULL-DOWN RESISTORS. ENGINEER: MK 10 9 8 7 6 5 4 3 2 PAGE:9 1 OF 10
4 1 1 3 5 8 8 6
22 22 22 22
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA-622/TUPP+622 REF. DESIGN SYS_INTERFACE
ISSUE DATE: 00/01/19 REVISION NUMBER:2
A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
CPCI CONNECTOR J3
3H1<
DS3RICLK\I G
PI74FCT163244
G U22
5C2> 5C2>
RAD_T<4..1>\I POHFP_T<4..1>\I
4 1 2 3 4 1 2
3H1> 3H1>
DS3ROCLK<3..1>\I DS3RODAT<3..1>\I DS3TICLK_1 DS3TICLK_5 DS3TICLK_9
3 1 2 3
F
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
4 3 2 1 4 2 1 4 3 2 1
RN30 RN30 RN30 RN30 RN29 RN29 RN29 RN28 RN28 RN28 RN28
1 2 3
22 22 22 22 22 22 22 22 22 22 22
5 6 7 8 5 7 8 5 6 7 8
RAD_4 POHFP_1 POHFP_4 POHFP_7 POHFP_10 DS3ROCLK_1 DS3ROCLK_5 DS3ROCLK_9 DS3RDAT_1 DS3RDAT_5 DS3RDAT_9 DS3TICLK_1 DS3TICLK_5 DS3TIDAT_1 DS3TIDAT_5 DS3TIDAT_9
A12 B12 C12 D12 E12 A13 B13 C13 D13 E13 A14 B14 C14 D14 E14 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 D19 E19
J3 A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 A5 B5 C5 D5 E5 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 A8 B8 C8 D8 E8 A9 B9 C9 D9 E9 A10 F1 B10 F3 C10 F5 D10 F7 E10 F9 A11 F11 B11 F13 C11 F15 D11 F17 E11 F19 ZPACK5X19 CPCI A12 B12 C12 D12 E12 A13 B13 C13 D13 E13 A14 B14 C14 D14 E14 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 D19 E19
A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 A5 B5 C5 D5 E5 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 A8 B8 C8 D8 E8 A9 B9 C9 D9 E9 A10 B10 C10 D10 E10 A11 B11 C11 D11 E11
DC1J1V1_3 DPL_3 DDP_3 DTPL_3 DTV5_3 ROBO_3
9C4> 9C4> 9C4> 9C4> 9C4> 9D10>
PI74FCT163244
VCC
AD_24 AD_25 AD_26 AD_27 AD_28 AD_29 AD_30 AD_31 AC1J1V1_4 APL_4 ADP_4 DD_24 DD_25 DD_26 DD_27 DD_28 DD_29 DD_30 DD_31 DC1J1V1_4 DPL_4 DDP_4 DTPL_4 DTV5_4 ROBO_4 SAPRE_5 SPARE_6 POHCK_1 RAD_1 RAD_2 RAD_3 RAD_4 POHFP_1 POHFP_4 POHFP_7
1 2 3 4 1 2 3 4 1 2 3 1 2 3 4 4 10 15 21 28 34 1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26
F U20
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
ADD_F<47..0>\I
2 3 5 6 8 9 11 12 13 14 16 17 19 4 20 3 22 2 23 1 7 18 31 42 45 39 37 38 39 40 41 42 43 44 45 46 47
7C2<> 9C1<> 9C10<> 9E1<> 9H10<>
0.1UF
C184 0.1UF
C186 0.1UF
C187 0.1UF
3G1<
DS3TICLK<3..1>\I
C185
LAC1_4
9C4>
40 41 42 43
E
PI74FCT163244
DS3TICLK_9
RN23 RN23 RN23 RN23
225 226 227 228
DD_24 DD_25 DD_26 DD_27
E VCC
U23
3G1<
0.1UF
C192 0.1UF
C194 0.1UF
3 2 1
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
3H10< 7H7>
TX_RNG_CTRL<3..1>\I
3 2 1
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND
RX_RNG_CTRL_1 RX_RNG_CTRL_2 RX_RNG_CTRL_3 D SPARE_5 SPARE_6
1 2 3 4
RN32 RN32 RN32 RN32
1 2 3
22 22 22 22
8 7 6 5 8 7 6
RN31 RN31 RN31 VCC
0.1UF C180 0.1UF C181 0.1UF
22 22 22
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
C193 0.1UF
DS3TIDAT<3..1>\I
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34 R119 4.7K R120 4.7K 4.7K R75 4.7K
SPARE_7
1 2 3
TX_RNG_CTRL_1 TX_RNG_CTRL_2 TX_RNG_CTRL_3 RX_RNG_CTRL_1 RX_RNG_CTRL_2 RX_RNG_CTRL_3
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19
DROP_F<52..0>\I DBUS_EN\I
PI74FCT163244
C195
7C10> 9D1> 7B10>
D U21 RN24 RN24 RN24 RN24 RN25 RN25 RN25 RN25 RN26 RN26 RN26 RN27 RN27 RN27 RN27 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
8 7 6 5 8 7 6 5 8 7 6 8 7 6 5 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 7 18 31 42 45 39
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VCC VCC VCC VCC GND GND 1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 GND GND GND GND GND GND
4 5
C
9B1<> 7G10<> 9F10<> 9D10<> 3H6> 7B3<
PIO<5..0>\I RX_RNG_CTRL<3..1>\I EXT_REF\I
1 47 46 44 43 48 41 40 38 37 25 36 35 33 32 24 30 29 27 26 4 10 15 21 28 34
C183 0.1UF
C182
44 45 46 47 48 49 50 51 52 4
R118
SCLK_ROBO<8..1>\I RCLK\I POHCK_T\I
2D1> 3E1> 3G6> 5C2>
C
1 2 3
RAD_T<4..1>\I
5C2>
0.1UF
C189 0.1UF
C190 0.1UF
C188 0.1UF
C191
VCC
B
B
PMC-Sierra, Inc.
A RN6 RN6 RN9 RN26
3 4 1 4
SPARE
DOCUMENT NUMBER: PMC-990229 DOCUMENT ISSUE NUMBER: 2
6 5 8 5
ISSUE DATE: 00/01/19 REVISION NUMBER:2
A
22 22 22 22
DRAWING TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Thu Jan 20 14:18:05 2000 9 8 7 6 5 4 3
TITLE: SPECTRA-622/TUPP+622 REF. DESIGN SYS_INTERFACE ENGINEER: MK 2
PAGE:10 TRUE 1
OF 10
10
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
10
BILL OF MATERIAL Table 6 Bill of Materials
Description CAPACITOR, 0.01UF, 50V, X7R_805 10% Manufactures Part # DIGI-KEY - PCC103BNCTND
Item 1
Ref. No C4, C7, C18, C24-C26, C35-C41, C45-C48, C166 C6
2
CAPACITOR, .047UF, 50V, X7R 5% CAPACITOR, 0.1UF, 50V, X7R_805 10%
AVX - 08055C473JATN
3
C8, C10, C13-C17, C19, C22, C23, C28-C34, C42-C44, C49-C68, C70, C71, C73-C165, C167-C199, C204. C27, C69, C72
AVX - 08055C104KAT
4
CAPACITOR, 4.7UF, 6.3V, TANT TEH CAPACITOR, 10UF, 6.3V, TANT TEH CAPACITOR, 47UF, 16V, ELECTRO CAPACITOR, 47UF, 6.3V, TANT TEH LED-Green, PCB Right angle 2.0 Amp FUSE & SOCKET
DIGI-KEY - PCS1475CT-ND
5
C1, C5, C9
DIGI-KEY - PCS1106CT-ND
6
C11, C12, C20, C21
DIGI-KEY - P1210-ND
7
C2, C3
DIGI-KEY - PCT1476CT-ND
8 9
D1-D3 F1
DIGI-KEY - LU20095-ND DIGI-KEY - F1224CT-ND
10
F2
3.0 Amp FUSE & SOCKET
DIGI-KEY - F1226CT-ND
11 12 13 14 15
J3 J5 J1 J9 J2, J4, J6, J11, J12
ZPACK5X19FH_SCPCI_2M M ZPACK5X22FH_BSCPI_2M M ZPACK5X22FH_ASCPCI_2 MM HEADER .1 " 1 x 8 HEADER .1 " 1 x 3
352171-1 352152-1 352068-1 DIGI-KEY - S1011-36-ND DIGI-KEY - S1011-36-ND
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
39
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Item 16
Ref. No J8
Description HEADER .1 " 25X2
Manufactures Part # DIGI-KEY - S2011-36-ND
17
J10
HEADER .1 " 3X2
DIGI-KEY - S2011-36-ND
18 19 20 21 22 23 24 25 26 27 28 29 30
L1, L2 R1 R54 R48, R49, R55, R56, R83, R84 R38, R60 R34, R35, R39 R63, R64, R95-R116 R85, R86, R94 R7 R25, R46 R37 R2-R6, R8, R80-R82 R12, R13, R16-R21, R26-R33, R36, R40R44, R47, R50-R52, R57-R59, R61, R65R72, R74-R76, R87 R91-R93, R117-R121 R122 R90
Inductor, 1.0UH RESISTOR-2.7, 5%, 1206 RESISTOR-0, 5%, 805 RESISTOR-1.0, 5%, 805 RESISTOR-1.0K, 5%, 805 RESISTOR-100, 1%, 805 RESISTOR-150, 5%, 603 RESISTOR-22, 5%, 805 RESISTOR-220, 5%, 805 RESISTOR-270, 5%, 805 RESISTOR-2.0K, 1%, 805 RESISTOR-330, 5%, 805 RESISTOR-4.7K, 5%, 805
DIGI-KEY - PCT1187CT-ND DIGI-KEY - PPCTND DIGI-KEY - P.10BCT-ND DIGI-KEY - PBCTND DIGI-KEY - PACTND DIGI-KEY - PCCTND DIGI-KEY - PACTND DIGI-KEY - PACTND DIGI-KEY - PACTND DIGI-KEY - PACTND DIGI-KEY - P2.00KCCT-ND DIGI-KEY - PACTND DIGI-KEY - PACTND
19 31
RESISTOR-270, 5%, 1206 RESISTOR-47, 5%, 805
DIGI-KEY - PPCTND DIGI-KEY - P47ACT-ND
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
40
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Item 32 33 34 35 36 37 38 39 40 41 42
Ref. No R78, R79 R9-R11, R14, R15, R22R24, R45, R53, R62 R77 RN12-RN22, RN56 RN6-RN10, RN23-RN40 RN1-RN4, R11, RN41RN55, RN57 RN5 SW1 Y1 Y2 U1
Description RESISTOR-49.9, 1%, 805 RESISTOR-47, 5%, 805 RESISTOR-63.4, 1%, 805 RES_ARRAY_4_SMD-10 RES_ARRAY_4_SMD-22 RES_ARRAY_4_SMD-4.7K RES_ARRAY_4_SMD-47 Right Angle SPST Push button PECL Oscillator 77.76 MHz 20 ppm HCMOS/TTL Oscillator 77.76 MHz 20 ppm 5V Dual TTL/PECL Translator 3.3V Dual TTL/PECL Translator
Manufactures Part # DIGI-KEY - PCCTND DIGI-KEY - P47ACT-ND DIGI-KEY - PCCTND DIGI-KEY - Y4-ND DIGI-KEY - Y4-ND DIGI-KEY - Y4-ND DIGI-KEY - Y4-ND DIGI-KEY - CKN4002-ND CONNOR WINFIELD EE14541-77.76 MHz MMD-MB3020H48-77.76MHz MOT - MC100ELT22 MOT - MC100LVELT22 TOSHIBA - TC74LVX08FN Linear Technology LT1129CQ-3.3 MAXIM - MAX811_EUS-T
43 44 45
U2 U3 U4
74HC08, Quad and gate LT1129-3.3, 3.3V Low Dropout Linear regulator MAX811_EUS-T, Voltage Monitor with Reset HP SC Duplex Single Mode Optical Transceiver CY7B991V, Programmable skew clock buffer PMC-5313 SPECTRA-622 520 Pin SBGA 74FCT807, 10 bit clock Buffer
46 47
U5 U6, U7
HP - HFCT-5208B CYPRESS - CY7B991V-5JC
48 49
U8 U9
PMC - PM5313 IDT - IDT74FCT807BTSO
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
41
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
Item 50
Ref. No U10
Description MIC39150-2.5, 2.5V Low dropout Regulator PMC-5363 TUPP-PLUS-622 304 Pin SBGA XC4028XLA FPGA 352 Pin BG352 NM93CS46 Serial EEPROM PCI9050 PCI BUS Target Interface chip 160 Pin PQFPXC1701 Serial OTP EPROM 74FCT163244, 16 bit buffer
Manufactures Part # MICREL - MIC39150-2.5BT
51
U11
PMC - PM5363
52 53 54 55 56
U12 U13 U14 U15 U16-U21, U23-U26
XILINX-XC4028XLA 09BG352C NATIONAL-NM93CS46EN PLX - PCI9050-1 XILINX - XC1701 PI - PI74FCT163244V
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
42
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
43
PRELIMINARY REFERENCE DESIGN PMC-1990229 ISSUE 2
PM5313/PM5363
SPECTRA-622 WITH TUPP-PLUS-622 REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990229 (P2) ref 981162 Issue date: Dec 1999
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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