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| PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE PM5347 S/UNI-155 PLUS SATURN USER NETWORK INTERFACE DATASHEET ERRATA ISSUE 1: JANUARY 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE REVISION HISTORY Issue No. 1 Issue Date April 1999 Details of Change This document contains changes to the datasheet revision 6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE CONTENTS 1 2 ISSUE 1 ERRATA ..................................................................................... 2 DATASHEET ISSUE 6 ERRATA ................................................................ 3 NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 1 ISSUE 1 ERRATA This document is the errata notice for Issue 6 of the S/UNI-PLUS datasheet (PMC-941033). Issue 1 of the S/UNI-PLUS errata notice and issue 6 of the datasheet supersedes all prior editions & versions. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 2 DATASHEET ISSUE 6 ERRATA The following details documentation errors in datasheet issue 6. PAGE 3 ERROR Correction to synthesizer feature. DESCRIPTION/CORRECTION The text states: "* Synthesizes the 155.52 MHz or 51.84 MHz transmit clock from a 19.44 MHz or 6.48 MHz reference." The text should have read: "* Synthesizes a 155.52 MHz transmit clock from a 19.44 MHz reference". The rev D S/UNI-PLUS will not synthesize a 51.84 MHz clock. For STS-1 operation the rev D S/UNIPLUS needs to be in clock bypass mode in both the receive and transmit directions. In STS-3 mode, the 19.44 MHz reference is required when not in bypass, the 6.48 MHz reference is not applicable. 7 Correction to block diagram. The TOWCLK, TSDCLK and TLDCLK signals were incorrectly shown as inputs. The block diagram has been updated to show them as outputs. TLAIS TSDCLK,TOWCLK TSD,TSOW,TSUC TLRDI TLDCLK TLD,TLOW TTOH TTOHFP TTOHCLK TTOHEN TOHFP TFP GTOCLK TPOH TPOHFP TPOHCLK TPOHEN POP[3:0] PIP[3:0] TDO TDI TCK TMS TRSTB JTAG Test Access Port TSOC TDAT[15:0] TXPRTY[1:0] TCA TWRENB TFCLK RSOC RDAT[15:0] RXPRTY[1:0] RCA RRDENB RFCLK Drop Side I/F BUS8 TSEN TPAIS TPRDI Transport O/H Insert Path O/H Insert Parallel Input/Output Port TRCLK+/TXD+/TXC+/RXDO+/RXD+/ALOS+/RRCLK+/- Clock Synthesizer PISO Clock Recovery SIPO Tx Section O/H Processor Section Trace Buffer Rx Section O/H Processor Tx Line O/H Processor Tx Path O/H Processor Path Trace Buffer Rx Path O/H Processor Tx ATM Cell Processor Rx Line O/H Processor Rx ATM Cell Processor Transport O/H Extract LF+/LFO RATP RBYP Path O/H Extract Microprocessor I/F LOS LOF RSDCLK,ROWCLK RSD,RSOW,RSUC LAIS LRDI RLDCLK RLD,RLOW RTOH RTOHFP RTOHCLK RPOH RPOHFP RPOHCLK D[7:0] A[7:0] ALE CSB WRB RDB RSTB INTB LOP PRDI PAIS LCD 26 63 Correction to PIP[3:0] pin description. Clarification of SDH J0/Z0 and TSTBEN description. Applications information for the RXDINV bit. 67 68 Correction to RRCLKA description. The PIP[3:0] pin description incorrectly states that each input contains an integral pull-down resistor. No input pull-ups or pull-downs are used on these pins. The description of the SDH J0/Z0 states that if the TSTBEN bit is high, the section trace message, stored in the SSTB block, will overwrite the J0 byte regardless of the SDH J0/Z0 state. In fact both the SDH J0/Z0 and TSTBEN bits must be high to enable overwriting the J0 byte. In Line Loopback mode (LLE=1) the RXD+ and RXD- inputs are connected to the TXD+ and TXD- outputs respectively. In Line Loopback mode the RXD inputs are not inverted before they are connected to the TXD outputs. Designs requiring RXD to be inverted will not operate correctly in Line Loopback mode. The LOS detection logic is connected to the non-inverted RXD inputs and therefore will not work correctly when the RXD inputs are inverted. The RRCLKA bit is incorrectly titled "TTCLKA". It should be titled "RRCLKA". PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ROHFP GROCLK 3 RCP RGFC TCP TGFC XOFF TATP TBYP Tx ATM 4 Cell FIFO Rx ATM 4 Cell FIFO PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 68 Correction to TRCLKA description. 70 71 71 Correction to TREFSEL description. Correction to RREFSEL description. Applications information for the RDOOLV bit The TRCLKA bit description incorrectly states that this bit monitors "for low to high transitions on the TRCLK+ and TRCLK- inputs. This should be changed to the following: TTIME[0] bit of Reg. 0x03 selects which clock TRCLKA monitors. If TTIME[0] = 0, then TRCLKA monitors the activity of the TRCLK+/- pins. If TTIME[0] = 1, then TRCLKA monitors the activity of the RRCLK+/pins The S/UNI-PLUS rev D will not work with a 6.48 MHz reference clock; therefore, TREFSEL should always be a logic zero for correct operation. The S/UNI-PLUS rev D will not work with a 6.48 MHz reference clock; therefore, RREFSEL should always be a logic zero for correct operation. While the PLL is locking onto the incoming data, the RDOOLV status will make numerous transitions. Correct interpretation of RDOOLV can be accomplished by polling the RDOOLV and RDOOLI bits at 100 msec intervals. When RROOLV and RROOLI are both polled at logic 0, then the recovered clock and reference are within 488 ppm. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W Function Unused RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default X 0 0 0 0 1 0 0 101 RTIMIE and RTIUIE functions have been added to Register 28H, SSTB Control, description. RTIMIE: The RTIMIE bit controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state. When RTIMIE is a logic one, changes in match state activates the interrupt (INTB) output. RTIUIE: The RTIUIE bit controls the activation of the interrupt output when the receive identifier message changes state. When RTIUIE is a logic one, changes in the received section trace identifier message stable/unstable state will activate the interrupt (INTB) output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 103 RTIMV, RTIMI, RTIUV and RTIUI functions have been added to Register 29H, SSTB Section Trace Identifier Status, description. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R Function Busy Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default 0 X X X X X X X RTIMV: The RTIMV bit reports the match/mismatch status of the identifier message framer. RTIMV is a logic one when the accepted identifier message differs from the expected message written by the microprocessor. RTIMV is a logic zero when the accepted message matches the expected message. RTIMI: The RTIMI bit is a logic one when match/mismatch status of the trace identifier framer changes state. This bit is cleared when this register is read. RTIUV: The RTIUV bit reports the stable/unstable status of the identifier message framer. RTIUV is a logic one when the current received section trace identifier message has not matched the previous message for eight consecutive messages. RTIUV is a logic zero when the current message becomes the accepted message as determined by the PER5 bit in the SSTB Control register. RTIUI: The RTIUI bit is a logic one when stable/unstable status of the trace identifier framer changes state. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 106 SSTB Synchronization Message Status Register (Reg. 2D) have been added. Note: The current GR253-CORE (5.4.7.1) requires the byte validation to be done over 8 frames, instead of 5 frames as is done in the S/UNI-PLUS. This, however, is still useful to be included, since it relieves the microprocessor from polling Reg. 0x0E, the Receive S1 register, every frame to validate the synchronization message. Register 0x2D: SSTB Synchronization Message Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Function SMUE Unused Unused Unused SMUI SMUV Unused Unused Default 0 X X X X X X X R R This register reports the synchronization message status of the SSTB. SMUV: The SMUV bit reports the unstable status of the received synchronization message. SMUV is a logic one when the received S1 byte differs from the previously received S1 byte for five consecutive frames. SMUV is a logic zero when S1 byte values are identical for five consecutive frames. SMUI: The SMUI bit is a logic one when the synchronization message unstable status changes state. This bit is cleared when this register is read. SMUE: The SMUE bit controls the activation of the interrupt output when the synchronization message unstable status changes state. When SMUE is a logic one, an unstable status state change activates the interrupt (INTB) output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 130-131 Correction to TPOP Path Status Register Description All references to the TPOP Source Control Register should be ignored: G1[1], G1[0]: The G1[1:0] bits are inserted in the unused bit positions in the path status byte when the primary input TPOHEN is low during the unused bit positions in the path overhead input stream, TPOH. APRDI: The APRDI bit controls the insertion of the auxiliary path remote defect indication. When APRDI is a logic one, the APRDI bit position in the path status byte is set high. When APRDI is a logic zero, the APRDI bit position in the path status byte is set low. This bit has no effect if the primary input TPOHEN is high during the path status remote defect indication bit position in the path overhead input stream in which case the value is inserted from TPOH. PRDI: The PRDI bit controls the insertion of the path remote defect indication. This register bit value is logically ORed with the input TPRDI. When PRDI is a logic one, the PRDI bit position in the path status byte is set high. When PRDI is a logic zero, the PRDI bit position in the path status byte is set low. This bit has no effect if the primary input TPOHEN is high during the path status remote defect indication bit position in the path overhead input stream in which case the value is inserted from TPOH. FEBE[3:0]: The FEBE[3:0] bits are inserted in the FEBE bit positions in the path status byte when the primary input TPOHEN is low during the path status FEBE bit positions in the path overhead input stream, TPOH. The value contained in FEBE[3:0] is cleared after being inserted in the path status byte. Any non-zero FEBE value overwrites the value that would normally have been inserted based on the number of receive B3 errors during the last frame. When reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending. 140 149 149 Clarification of HCSFTR[1:0]. Correction to the description of the DHCS bit. Application information for the FIFORST bit. For correct operation the HCSFTR[1:0] bits must be set to 00. This condition requires one ATM cell with correct HCS to switch from detection mode to correction mode. The DHCS bit description states that DHCS controls the insertion of single bit errors. The assertion of DHCS causes the next HCS octet to be inverted forcing 8 bit errors not just one. The FIFORST bit in register 0x60: "TACP Control/Status" initializes the transmit FIFO. For correct operation, a FIFORST should be issued at the end of each initialization cycle (ie. at the end of the reset routine). A transmit FIFORST should also be issued each time TSOC changes boundaries. Boundary changes are identified by TSOCI (bit 6). The FIFORST should be asserted for a minumum of 3.5us. (one cell period at 155Mbps). 179 Sources for filter caps. Surface mount capacitors for these values are available from ATC, AVX, muRata, and NEC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE 186 Changes to Bit Error Rate The recommended register settings for STS-1 mode should be as follows: Monitor Settings BER 10-4 10-5 10-6 Reg.0x72 A0 B0 E0 Reg.0x73 00 04 2E Reg.0x74 4F 3E 3E Reg.0x75 00 00 00 The recommended register settings for STS-3c mode should be as follows: BER 10-4 10-5 10-6 Reg.0x72 34 90 A0 Reg.0x73 00 01 0F Reg.0x74 4D 3E 3E Reg.0x75 00 00 00 203-204 Clarification of RRDENB RRDENB must not be de-asserted during the second to last word (or byte) of a cell. It has been found that de-asserting RRDENB during the second to last word (or byte) of a cell may result in the loss of the last word ( or byte). VTPIH is the guaranteed input HIGH voltage of inputs while in TTL mode. See Figure 11 on Page 178 of the datasheet. VTPIL is the guaranteed input LOW voltage when in TTL mode. These specifications apply to the inputs ALOS- and REFCLK- only. VTPIH minimum voltage is 2.2V. The maximum voltage is VDD+0.5V. VTPIL minimum voltage is -0.5V. The maximum voltage is 0.8V. 207 Addition of VTPIH and VTPIL DC characteristic 208 224 Clarification of the IIL parameter. Addition of TFP timing. The IIL parameter is not relevant for PECL inputs. The following timing parameters for the TFP input should be added to figure 38. Symbol tS TFP tHTFP Description TFP Set-up time to GTOCLK TFP Hold time to GTOCLK Min 15 0 Max Units ns ns GTOCLK tS TFP TFP tH TFP 230 Change to tPRCA, tPRDAT, tPRSOC and tPRXPRTY min delay. The tPRCA, tPRDAT, tPRSOC and tPRXPRTY min delays have been changed to 2 ns from 1 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PM5347 S/UNI-PLUS DATASHEET ERRATA PMC-990127 ISSUE 1 SATURN USER NETWORK INTERFACE CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990127 (R1) ref PMC-941033 (R6) Issue date: April 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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