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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
PM5349 S/UNI155-QUAD
TM
S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
REFERENCE DESIGN
ISSUE 3
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 3 2 1 August 1999 August 1998 Issue Date Details of Change Updated Filtering Recommendation (Section 7.2) to meet reference design schematics. Added Design Consideration Section and Updated the Schematics Document created.
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CONTENTS 1 2 3 4 5 6 INTRODUCTION ......................................................................................1 FEATURES...............................................................................................2 APPLICATIONS........................................................................................3 DESIGN OVERVIEW................................................................................4 BLOCK DIAGRAM....................................................................................5 FUNCTIONAL DESCRIPTION .................................................................6 6.1 6.2 6.3 6.4 6.5 7 S/UNI-QUAD..................................................................................6 OPTICAL LINE INTERFACE..........................................................7 MICROCONTROLLER BLOCK .....................................................8 SYSTEM SIDE LOOPBACK ..........................................................8 EXTERNAL CONNECTOR ............................................................9
DESIGN CONSIDERATIONS .................................................................14 7.1 PECL INTERFACE.......................................................................14 7.1.1 RECEIVE INPUTS ............................................................14 7.1.2 TRANSMIT OUTPUTS ......................................................15 7.2 7.3 7.4 7.5 FILTERING AND DECOUPLING .................................................16 UNUSED INPUT PINS AND CHANNEL ......................................18 JTAG PORT .................................................................................18 ROUTING ....................................................................................18
8
IMPLEMENTATION DESCRIPTION.......................................................20 8.1 8.2 ROOT DRAWING, SHEET 1........................................................20 QUAD_BLOCK, SHEET 2 & 3 .....................................................20
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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8.3 8.4 8.5 8.6 9
LOOPBACK_BLOCK, SHEET 4 & 5............................................20 SYS_INTERFACE, SHEET 6 & 7 ................................................21 MICRO_BLOCK, SHEET 8 ..........................................................21 OPTICS_BLOCK, SHEET 9.........................................................21
SCHEMATICS ........................................................................................22 9.1 BILL OF MATERIALS...................................................................23
10
REFERENCES .......................................................................................25
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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LIST OF FIGURES FIGURE 1 : S/UNI-QUAD REF DESIGN WITH PMC-SIERRA ATM CHIPSETS.3 FIGURE 2 : STS-3C FRAME..............................................................................6 FIGURE 3 : LOOPBACK DIAGRAM ..............................................................998 FIGURE 4 : RECEIVE RXD+/- INTERFACE .....................................................14 FIGURE 5 : RECEIVE SD INTERFACE ............................................................15 FIGURE 6 : TRANSMIT TXD+/- INTERFACE ...................................................16 FIGURE 7 : S/UNI QUAD ANALOG FILTERING...............................................17
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LIST OF TABLES TABLE 1 : INTERFACE CONNECTOR ONE ..............................................10109 TABLE 2 : INTERFACE CONNECTOR TWO ....................................................12 TABLE 3 : MAJOR COMPONENTS LIST..........................................................23
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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1
INTRODUCTION The PM5349 S/UNI-QUAD standard product is a Quad SATURN User Network Interface with SONET/SDH processing, and ATM mapping functions at the STS3c (STM-1) 155.52 Mbit/s rate. The S/UNI-QUAD is intended for use in equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interface (UNI), and ATM Network-Network Interfaces (NNI) interfaces. The S/UNI-QUAD may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. The S/UNI-QUAD reference design provides a physical interface implementation of a SONET/SDH line card for the ATM application. It provides four optical interfaces at OC-3 rates and a system side interface of 25MHz to 50MHz for a 16-bit wide bus.
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2
FEATURES * * * * Provides four OC-3 rate 155.52 Mbits/s SONET/SDH Physical Layer Ports Provides a Utopia Level 2, 50 MHz, 16-bit ATM Multi-PHY System Interface Provides Dropside Loopback for Diagnostic Purposes Provides a software package for demonstration and evaluation of the S/UNIQUAD reference board
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3
APPLICATIONS The S/UNI-QUAD reference design demonstrates a physical interface implementation for ATM applications. The list below shows the networking equipment that can incorporate the S/UNI-QUAD device: * * WAN and Edge ATM switches physical Interface LAN switches and hubs physical Interface
The S/UNI-QUAD reference design interfaces to four OC-3 rate SONET/SDH signals on the line side. On the drop side, the S/UNI-QUAD interfaces directly to ATM layer processors and switching or adaptation functions using a Utopia Level 2 compliant synchronous FIFO style interface. Figure 1 shows an example of the S/UNI-QUAD reference design in a complete ATM switching design using PMC-Sierra's ATM chipsets.
Figure 1 : S/UNI-QUAD Ref Design with PMC-Sierra ATM Chipsets
Utopia Level 2
Utopia Level 2
Optics #1 OC-3
QSE QSE
QRT
Traffic Manager
ATLAS
ATM Layer
Multi-PHY Cell I/F
QUAD
Ref Design
OC-3 Optics #4
OC-3
ATM Switch Fabric
Optics #1
QRT
Traffic Manager
ATLAS
ATM Layer
Multi-PHY Cell I/F
QUAD
Ref Design
OC-3 Optics #4
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DESIGN OVERVIEW The S/UNI-QUAD reference design consists of a S/UNI-QUAD device and four optical transceivers in a four port optical physical interface for Asynchronous Transfer Mode (ATM) applications. The S/UNI-QUAD reference design contains an on-board microcontroller for accessing and controlling the S/UNI-QUAD device. The dropside Loopback function is provided by an on-board FPGA. The S/UNI-QUAD reference design is capable of a maximum bandwidth of approximately 622 Mbps and can be used as an ATM line card. The S/UNI-QUAD reference design supports the Utopia level 2 ATM PHY to ATM Layer specification. Since the S/UNI-QUAD is a quad PHY chip, the PHY interface is configured as multi-PHY address polling at 50 MHz over a 16 bit bus. The loopback feature allows the receive data to be looped back to the transmit stream at the drop side. This allows the evaluation of both the line side and drop side interface. An external Field Programmable Gate Array (FPGA) implements the loopback feature and provides a microprocessor interface to the 68322 microcontroller. This FPGA also provides transmit data reclocking. The FPGA reclocks the transmit data and control signals to meet the setup and hold times of the S/UNI-QUAD device. The S/UNI-QUAD reference design can be run either as a stand-alone evaluation platform or interfaced to other S/UNI reference designs. As a standalone board, the S/UNI-QUAD reference design allows access to on-chip registers, and performs the system side loopback feature for the Utopia interface. When interfaced to other reference boards, cell generation functions are provided by these external boards for further demonstration and evaluation of the S/UNI-QUAD device.
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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5
BLOCK DIAGRAM
3.3/5V Pwr Supply
Loopback Block
50 MHz Crystal Oscillator
ATM Signals (Loopbacked)
HP Optics HFCT-5905
TFCLK, RFCLK
FPGA
ATM Signals
HP Optics HFCT-5905
RxD +/-, TxD +/-, SD x 4
PM5349 S/UNI-QUAD
Micro-Interface Signals
C Block
Micro Interface
C
Flash ROM & RAM
HP Optics HFCT-5905
REFCLK
19.44 MHz Crystal Oscillator
HP Optics HFCT-5905
Alarm Status Indicator
RS-232
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UTOPIA LEVEL 2 INTERFACE
Tx/Rx Utopia Level 2 I/F
Bus Switch
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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6 6.1
FUNCTIONAL DESCRIPTION S/UNI-QUAD The PM5349 S/UNI-QUAD SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET/SDH processing and ATM mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate. Figure 2 shows the overhead of a STS-3c frame. Figure 2 : STS-3c Frame
270 bytes 9 bytes
Section Overhead (Regen. Section) Pointer Line Overhead (Multiplex Section) J1 B3 C2 G1 F2 H4 Z3 Z4 Z5
261 bytes
ATM Cell
ATM Cell
9 bytes
ATM Cell ATM Cell
STS-3c Transport Overhead STM-1 Section Overhead
A1 B1 D1 H1 B2 D4 D7 D10 S1 Z1 Z1 H1 B2 H1 B2 A1 A1 A2 E1 D2 H2 K1 D5 D8 D11 Z2 Z2 M1 H2 H2 A2 A2 J0 F1 D3 H3 K2 D6 D9 D12 E2 H3 H3 Z0 Z0
C2 byte must be set to indicate ATM
The S/UNI-QUAD receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M1, G1) are also accumulated. The S/UNI-QUAD interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. The S/UNI-QUAD frames to the ATM payload using cell delineation. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a 16 bit wide Utopia level 2 compliant datapath interface. Counts of
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes. The S/UNI-QUAD transmits SONET/SDH streams using a bit serial interface and formats section, line, and path overhead appropriately. It synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (M1, G1) are also inserted. The S/UNI-QUAD generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. The S/UNI-QUAD also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications. ATM cells are written to an internal four cell FIFO using a generic 16-bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-QUAD provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. No line rate clocks are required directly by the S/UNI-QUAD as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz reference clock. Normally, the S/UNI-QUAD outputs only differential PECL line data (TXD+/-). 6.2 Optical Line Interface The S/UNI-QUAD reference design provides four optical line interfaces at the 155.52 Mbit/s OC-3 rate. The line interface consists of four optical data links (ODL) and a termination scheme for the PECL signals into and out from the four S/UNI-QUAD transmit and receive signal pairs. The suggested termination scheme is discussed in the design consideration section. In normal operation, the S/UNI-QUAD performs clock recovery and serial to parallel conversion on the incoming data stream. In a loss of signal condition, indicated on each of the four SD pins, the S/UNI-QUAD will squelch the receive data and the clock recovery unit and will switch to the reference clock (19.44MHz) to keep the recovered clock in range. This technique guarantees that the S/UNI-QUAD will generate an LOS indication when the ODL loses the incoming optical signal.
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
For this reference design, 3.3V ODL transceivers are used to reduce power consumption and match PECL level signals. 6.3 Microcontroller Block The S/UNI-QUAD reference design uses a 32-bit Motorola 68332 microcontroller running at 16.7MHz as its on-board processor. The microcontroller block contains separate flash ROM and RAM for program data storage and run-time program execution, respectively. The S/UNI-QUAD registers are accessed through a 10-bit address and a 8-bit data bus microprocessor interface by the 68322. The microcontroller can be accessed through either the RS-232 port or the Background Debug Monitor (BDM) connector sitting on the reference board. The RS-232 port allows access to the serial port on the 68332. The microcontroller also provides additional control to external adapter cards through the Utopia interface connector. This allows the microcontroller to access external devices. 6.4 System Side Loopback The Loopback block consists of an FPGA and a bus exchange switch. The Bus exchange switch allows the S/UNI-QUAD's system side to be either connected to an external FPGA for loopback functionality or to a link layer interface board. The bus exchange switch adds minimum delay and presents low capacitance and impedance to the line. The loopback setup is shown in Figure 4 below.
Figure 3 : Loopback Diagram
Normal Mode Loopback Mode
Loopback FPGA S/UNIQUAD
POS/ATM Signals POS/ATM Signals
Loopback FPGA S/UNIQUAD
To Link Layer
To Link Layer
Bus Exchange Switch
Bus Exchange Switch
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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In normal mode, the S/UNI-QUAD's Dropside data and control signals are connected to the system interface connector. In loopback mode, the receive data and control signals are input into and loopbacked out of the FPGA as transmit signals. The FPGA loopback supports multi-PHY direct status addressing mode with each PHY. In loopback mode, the FPGA polls for receive cells available signals. The FPGA starts to receive and transmit cells only when PHY received data is available. This prevents the need for implementing a FIFO inside the FPGA. 6.5 External Connector The S/UNI-QUAD reference design contains two Molex connectors for interfacing to a link layer or the HP ATM tester adapter card. The Molex connectors have been measured with a network analyzer and showed adequate results for running at 50MHz. The first connector is used for microprocessor communication between the two microcontrollers on the S/UNI-QUAD reference and MB1503 boards. It supplies both 3.3V and 5V power supply to the S/UNI-QUAD board. It is also used for the FIFO clock signals for the Utopia interface. The second connector is used for interfacing Utopia data and control signals. Table 1 : Interface Connector One Pin Name SCK MISO MOSI CS_MICRO Type Input / Output Input / Output Input / Output Input / Output Pin No. D17 D19 D18 D20 Function Serial Clock. Clock for the microcontroller's QSPI module Master In Slave Out. Serial Data for the microcontroller's QSPI module. Master Out Slave In. Serial Data for the microcontroller's QSPI module. Chip select for communication between the microcontrollers on the S/UNI-QUAD and link layer boards.
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Pin Name M/S_MICRO
Type Input
Pin No. D21
Function Signal to indicate if the link layer board is the master or slave for the QSM bus. For M_MICRO = 0, the micro on the QUAD board is the master. For M_MICRO = 1, MB1503 acts as the master. Interrupt signal from the S/UNI-QUAD device Negative differential receive clock signal. This signal, along with RFCLK+ comprise the differential RFCLK clock signal sent across the connector. RFCLK is to be used as a reference to sample RDAT. Positive differential receive clock signal. This signal, along with RFCLK- comprise the differential RFCLK clock signal sent across the connector. RFCLK is to be used as a reference to sample RDAT. Positive differential receive clock signal. This signal, along with TFCLK- comprise the differential TFCLK clock signal sent across the connector. TFCLK is used as a reference to sample TDAT. Negative differential receive clock signal. This signal, along with TFCLK+ comprise the differential TFCLK clock signal sent across the connector. TFCLK is used as a reference to sample TDAT.
INTB RFCLK-
Output Output
D27 D35
RFCLK+
Output
D36
TFCLK+
Input
D39
TFCLK-
Input
D40
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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Pin Name NC
Type NC
Pin No. A20 A38, B17 B30, C1 C30, D1 D16, D20 D22, D28 D34, D37, D38 A1, A2, B1, B2 A3-A9, B3-B9, A10 A19, B10 B16, B31 B40, C31 C40
Function Not Connected.
VCC1 (+5V)
Input
+ 5 Volt supply
+ 3.3V GND
Input Input
+ 3.3 Volt supply Ground
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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Table 2 : Interface Connector Two Pin Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RPRTY Type Output Pin No. A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 A8 D8 A9 Function Receive Cell Data Bus This bus carries the ATM cell octets that are read from the selected receive FIFO.
Output
DRCA[1] DRCA[2] DRCA[3] DRCA[4] RADDR[0] RADDR[1] RADDR[2] RADDR[3] RADDR[4] RENB
Output
Input
Input
A10 A11 A12 A13 D9 D10 D11 D12 D13 A14
Receive bus parity The receive parity signal indicates the parity of the RDAT bus. Direct Receive Cell Available These signals indicate available cells to be transferred across the UTOPIA bus. Receive PHY port address These signals are used to select the PHY port to be read from or polled.
RCA
Output
A15
RSOC
Output
D14
Receive Multi-Phy Write Enable The RENB signal is an active low input which is used to initiate reads from the receive FIFOs. Receive Multi-PHY Cell Available This signal indicates an available cell during receive PHY port polling Receive Start of Cell This signal marks the start of cell on the RDAT bus.
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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Pin Name TENB
Type Input
Pin No. A27
Function Transmit Multi-Phy Write Enable The TENB signal is an active low input which is used to initiate writes to the transmit FIFOs Transmit cell available signal This signal is used to indicate available cell FIFO space by polled PHY ports. Transmit Start of Cell The transmit start of cell signal marks the start of cell on the TDAT bus. Transmit Address The TADR[4:0] bus is used to select the port that is to be written to or being polled.
TCA
Output
D26
TSOC
Input
A28
TADDR[0] TADDR[1] TADDR[2] TADDR[3] TADDR[4] DTCA[1] DTCA[2] DTCA[3] DTCA[4] TPRTY
INPUT
Output
INPUT
D27 D28 D29 D30 D31 A29 A30 A31 A32 D32
Direct Receive Cell Available These signals indicate available cells to be transferred across the UTOPIA. Transmit bus parity The transmit parity signal indicates the parity of the TDAT bus. Transmit Cell Data Bus This bus carries the ATM cell octets that are written to the selected transmit FIFO.
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
INPUT
A40 D40 A39 D39 A38 D38 A37 D37 A36 D36 A35 D35 A34 D34 A33 D33
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7 7.1
DESIGN CONSIDERATIONS PECL INTERFACE
7.1.1 RECEIVE INPUTS The S/UNI-QUAD's receive RxD+/- inputs are true differential PECL receivers. The receive signals are high-speed signals and must be properly terminated to reduce reflection. Unlike previous generation S/UNI products, the S/UNI-QUAD RxD+/- pair are not self-biased to the PECL Vbb level. Given that the RxD+/inputs have wide common mode operating voltage, the receive inputs can be directly DC-coupled from the optics. Most of the commercially avaliable optics on the market today provide PECL level RxD+/- outputs. The emitter on these PECL outputs need to be biased through a series resistor ground to provide adequate signal levels on the outputs. For 3.3V PECL drivers, a 150 Ohm series resistor is recommended. For 5V PECL drivers, a 330 Ohm series resistor is recommeded. The bias resistor location and value is shown in Figure 4. The RxD+/- differential signals require termination at the S/UNI-QUAD's input . With 50 ohm controlled impedence lines, a 100 ohm resistor connected across the RxD+/- pair can properly terminate the signal with minimum current draw. Figure 4 : Receive RxD+/- Interface
ptics MD RD+
Rd
S/UNI-QUAD RxD+ Zo 2*Zo Zo
Gnd
RDRd
Gnd
RxDZo = 50
For 3.3V, Rd = 150 For 5.0V, Rd = 330
The SD detect input can also be DC-coupled from the SD output from an Optics. Similar to the optics RxD+/-`s outputs, the optic's SD output needs a emitter biasing resistor. Since SD is a relative slow signal, termination is not required at the S/UNI-QUAD. The SD input on the S/UNI-QUAD can also be supplied from
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PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
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a TTL or CMOS source as long as the input signal level doesn't exceed the receiver voltage reference(3.3V or 5V). Figure 5 : Receive SD Interface
Optics PMD S/UNI-QUAD
SD
Rd
Gnd
Zo
For 3.3V : Rd = 150 For 5.0V : Rd = 330
SD
7.1.2 TRANSMIT OUTPUTS The S/UNI-QUAD's transmit TxD+/- outputs are 3.3V CMOS rail to rail outputs. Since most of the optics have PECL level TxD+/- inputs, the TxD+/- signal from the S/UNI-QUAD needs to be converted to PECL level. The PECL level conversion is done by first AC-coupling the TxD+/- outputs and attenuating the output voltage swing to PECL level. The PECL voltage swing is typically 800mV where as the S/UNI-QUAD outputs provide 3.3V swing. The 800mV swing can be attained by inserting a series resistor between the 50 Ohm impedance line and the AC-coupled resistor. The exact calculation of this attenuation resistor value is shown in figure 6. At the optics TxD+/- inputs, the 800mV voltage level needs to swing around the PECL bias point. For 5V PECL, the bias point is 3.7V and for 3.3V LVPECL, the bias point is 2.0V. A simple voltage divider network is shown in figure 6 for biasing the TxD+/- inputs to the PECL center point. The Vdd reference for the resistor and capacitor should be the same as the optics Vdd. Two 50 ohm resistors between the TxD+/- line and the PECL bias point provide the proper termination The S/UNI-QUAD's transmitter and external termination circuity have been designed and throughly tested to meet Bellcore and ANSI jitter generation requirements. Using single-ended transmit output is not recommended due to duty-cycle distortion and poor jitter performance.
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Figure 6 : Transmit TxD+/- Interface
Optics PMD
RS1 0.1 uF
S/UNI-QUAD
TD+
Zo Zo
Vcc
0.01uF or 0.1 uF
Zo
TxD+
RS1
Vcc R1
0.1uF
TD-
Zo
TxD-
Vdd * R2/(R1+R2) = Vbb
R2 Gnd
Notes: Vpp is minimum input swing required by the optical PMD device. Vbb is the switching threshold of the PMD device (typically Vdd - 1.3 volts) Vpp is Voh - Vol (typically 800 mVolts) Vpp = (Zo/((RS1+Rs)+Z0) * Vdd - Vdd (S/UNI-QUAD's analog transmit power) 3.3V - Zo (trace impedance) typically 50 - Rs (TxD source impedance) typically 15-20 - RS1 : ~ 158 Vcc = Optics Power (5.0V or 3.3V) For interfacing to 5.0V ODL, R1 : 237 , R2 : 698 For interfacing to 3.3V ODL, R1 : 220, R2: 330
7.2
FILTERING AND DECOUPLING High speed analog circuitry is generally sensitive to any broadband noise on its power supply. The S/UNI-QUAD transmit CSU circuitry is sensitive to both low and high frequency noise. Care should be taken to reduce the noise at the CSU power pins, TAVD1_A and TAVD2_B. Since each board design can have different noise levels on the power rail, the transmit filtering circuit shown in figure 7 is recommended to ensure that the S/UNI-QUAD will be within 10% of its optimal jitter performance even when powered in a noisy environment. The RC filtering circuitry provides a pole of around 1.25KHz for the purpose of filtering out low frequency noise. Additional 0.1F decoupling capacitors should be placed near the following analog pins: C4, J1, N4, U2, and AA4. A single The RC filtering circuitry provides a pole of around 1.25KHz for the purpose of filtering out low frequency noise. Additional 0.1F decoupling capacitors should
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
16
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
be placed near the following analog pins: C4, J1, N4, U2, and AA4. A single uncut ground plane can be used for all S/UNI-QUAD board designs for both digital and analog circuitry. Ferrite beads are not recommended as a very small ferrite value will be needed to have a pole at the same location as an RC circuit and because LC circuity self-resonates at certain frequencies. For the digital power pins, place 0.1F caps near the following VDD pins: B2 For the digital power pins, place 0.1F caps near the following VDD pins: B2, B22, D9, D15, F20, J4, M20, R4, V20, Y9, Y15, AB2, and AB22. Figure 7 : S/UNI Quad Analog FilteringS/UNI-Quad Analog Filtering
27 3.3V + 4.7uF 0.1uF TAVD1_A Pin # L3
2.7 TAVD1_B Pin # L1
+ 47uF 0.1uF
QAVD1 Pin # AA6 100 3.3V QAVD2 Pin # C6
NOTES 1) Additional 0.1uF caps placed near analog pins: C4, J1, N4, U2, AA4. 2) place 0.1uF as close to power pin as possible. 3) 47uF and resistors do not have to be very close to power pins 4) Resistors may be 1/10 Watt
0.1uF
A 100 Ohm resistor should be added in series with a 0.1uF capacitor to ground on the quiet analog pins QAVD1 and QAVD2. This will protect the device from latching-up during power up.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
7.3
UNUSED INPUT PINS AND CHANNEL All unused input pins on the S/UNI-QUAD must be tied to their inactive state. If the inputs are left floating, noise can coupled into the CMOS gates and cause the S/UNI-QUAD device to malfunction. For tying an used input to 3.3V/5V, a 4.7K Ohm pull-up resistor can be used to prevent latchup during power up. If one of the four channels is not being used, the analog differential inputs, RxD+/-, should be also be tied to ground to avoid chattering the receiver. For any unused channel, power still needs to be supplied to the analog power pins due to S/UNI-QUAD internal power structure.
7.4
JTAG PORT When the JTAG is unused for boundary scan, the TRSTB on the S/UNI-QUAD should be tied to RSTB. This will reset the JTAG port as the same time as system reset. TMS, TCK, and TDI should all be tied high. In addition, TCK can be optionally tied to a free-running clock to ensure that the JTAG port logic is continuously put back to the correct initial state.
7.5
ROUTING Routing is based on the design considerations as well as manufacturability. Several suggestions are listed below: * Allow at least 10 mil clearance between vias, traces, and pads to prevent shorts and reduce crosstalk. If possible, allow 20 mil or more clearance around vias as manufacturers may have minimum clearance requirements. The differential signal pairs should be of equal length so that both signals arrive at the inputs at the same time. They should also run parallel and close to one another for as long as possible so that noise will couple onto both lines and become common mode noise which is ignored by the differential inputs. All power and ground traces should be made as wide as possible to provide low impedance paths for the supply current as well as to allow quick noise dissipation. Since vias have an impedance, avoid them where possible, especially on critical traces such as TXD and RXD. Also where decoupling is critical, try to place capacitors at the pins (component side) and not have vias in series with the capacitors.
*
*
*
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
18
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
19
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
8
IMPLEMENTATION DESCRIPTION The S/UNI-QUAD reference design schematics were captured using Cadence software, Concept Schematics Capture Tool.
8.1
ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the S/UNIQUAD schematics. It shows interconnections between the QUAD_BLOCK, LOOPBACK_BLOCK, MICRO_BLOCK, SYS_INTEFACE, and OPTICS_BLOCK.
8.2
QUAD_BLOCK, Sheet 2 & 3 The QUAD_BLOCK shows the S/UNI-QUAD's signals and the power circuitry. Series resistors are used to source terminate the Utopia bus lines. The 51 Ohm termination resistors combined with the output impedance of the Utopia pads matches the impedance of the trace at 75 Ohms. Four LEDs are provided to display alarm status from each of the four channels in the S/UNI-QUAD. A 1K Ohm resistor is also placed in series to limit the Vbias current to prevent Vbias latchup. For analog power, RC filtering is provided for the transmit analog power pins as recommended in the design consideration. Refer to Section 7.2 for additional details on decoupling recommendations. Refer to Section 7.2 for additional details on decoupling recommendations.
8.3
LOOPBACK_BLOCK, Sheet 4 & 5 These sheets show the loopback function implemented for the QUAD's Utopia/ Level 2 interface signals. P15C16212 bus exchange switches are connected to Utopia signals from and to both the S/UNI-QUAD and the loopback FPGA. These bus switches are controlled by the loopback enable, LB_EN, signal. When in loopback, the signals driving the board connector are tied low by the resistor arrays connected through the bus switches. The 74FCT807 3.3V clock driver supplies receive clocks to both the S/UNIQUAD and the board connector for the ATM/POS layer devices. The transmit clock is supplied from the board connector during regular mode. When in loopback mode, both the transmit and receive clocks are supplied by the 74FCT807 clock driver. The Xilinx XC4020XL FPGA has 3.3V outputs to meet with the Utopia interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
8.4
SYS_INTERFACE, Sheet 6 & 7 The SYS_INTERFACE block contains the board connectors and the power supply circuitry. On Sheet 6, two MOLEX 160 pin connectors are shown. Balun transformers are used to transform differential transmit and receive clock signals to a single-ended signal for the S/UNI-QUAD. Sheet 6 shows power to the reference board may be supplied either from an external power supply or through the board connectors. Solder bridges are used to select the desired power source. Fuses and transils are provided to protect the board from over-voltage and over-current.
8.5
MICRO_BLOCK, Sheet 8 The MICRO_BLOCK sheet shows the 68322 microcontroller and its external circuitry. The 68322 operates at 16.337 MHz using a 32.768MHz crystal. 1 MB (128K x 8) Flash and SRAM are provided for program storage and run-time execution. The BDM header allows the microcontroller to run in background debug mode for downloading the program to the FLASH and debugging purposes. The MC33064 low voltage sensing circuit puts the 68322 in reset mode when the voltage supply drops below 4.5V.
8.6
OPTICS_BLOCK, Sheet 9 This sheet shows the four Optical Data Links (ODLs) that provide the optical to electrical (O/E) function for the S/UNI-QUAD device. The PECL signals run on 50 Ohm controlled impedance signal lines and are properly terminated at the ODL and at the S/UNI-QUAD device. The S/UNI-QUAD device interfaces to four HP HFCT-5905 Singlemode Fiber Transceivers. The HFCT-5905 can also be replaced with HFBR-5905 Multimode from HP. The HFBR-5905 transceivers are in a 2x5 DIP package with a MT-RJ connector interface. The smaller footprint MT-RJ interface allows higher optical port density on a typical ATM line card.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
21
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
9
SCHEMATICS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
22
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G PAGE 9 OPTICS_BLOCK PAGE 2,3 QUAD_BLOCK 15P PAGE 4,5 LOOPBACK_BLOCK PAGE 6,7 SYS_INTERFACE
G
TXD1P TXD1N RXD1P RXD1N SD1
TXD1P TXD1N RXD1P RXD1N SD1
TXD1P TXD1N RXD1P RXD1N SD1
DTCA<4..1> TADDR<4..0> TDAT<15..0> TSOC TCA TPRTY TENB
DTCA<4..1> TADDR<4..0> TDAT<15..0> TSOC TCA TPRTY TENB
DTCA<4..1> TADDR<4..0> TDAT<15..0> TSOC TCA TPRTY TENB
DTXCA<4..1> TXADDR<4..0> TXDAT<15..0> TXSOC TXCA TXPRTY TXENB
DTXCA<4..1> TXADDR<4..0> TXDAT<15..0> TXSOC TXCA TXPRTY TXENB
DTXCA<4..1> TXADDR<4..0> TXDAT<15..0> TXSOC TXCA TXPRTY TXENB F
F
TFCLK TXD2P TXD2N RXD2P RXD2N SD2 TXD2P TXD2N RXD2P RXD2N SD2 TXD2P TXD2N RXD2P RXD2N SD2 DRCA<4..1> RADDR<4..0> RDAT<15..0> RSOC RCA RPRTY RENB
TFCLK
TFCLK
TXCLK
TXCLK
TXCLK
E
DRCA<4..1> RADDR<4..0> RDAT<15..0> RSOC RCA RPRTY RENB
DRCA<4..1> RADDR<4..0> RDAT<15..0> RSOC RCA RPRTY RENB
DRXCA<4..1> RXADDR<4..0> RXDAT<15..0> RXSOC RXCA RXPRTY RXENB
DRXCA<4..1> RXADDR<4..0> RXDAT<15..0> RXSOC RXCA RXPRTY RXENB
DRXCA<4..1> RXADDR<4..0> RXDAT<15..0> RXSOC RXCA RXPRTY RXENB
E
TXD3P TXD3N RXD3P RXD3N SD3
TXD3P TXD3N RXD3P RXD3N SD3
TXD3P TXD3N RXD3P RXD3N SD3
RFCLK
RFCLK
RFCLK RESET_B LB_EN CSB_FPGA R/W_B DATA<7..0> ADDR<5..0> PAGE 8
RXCLK
RXCLK
RXCLK
PROGRAM DONE
D
<5..0>
MICRO_BLOCK CSB_FPGA LB_EN ADDR<9..0> DATA<7..0> CSB R/W_B RESET_B INTB
D
TXD4P TXD4N RXD4P RXD4N SD4
TXD4P TXD4N RXD4P RXD4N SD4
TXD4P TXD4N RXD4P RXD4N SD4
ADDR<9..0> DATA<7..0> CSB R/W_B RESET_B INTB
ADDR<9..0> DATA<7..0> CSB R/W_B RESET_B INTB
PROGRAM DONE SCK MOSI MISO CS_MICRO M/S_MICRO INTB SCK MOSI MISO CS_MICRO M/S_MICRO INTB SCK MOSI MISO CS_MICRO M/S_MICRO INTB C
C
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=QUAD_ROOT ABBREV=QUAD_ROOT LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN ROOT DRAWING 1 15:47:42 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:1 TRUE 1 OF 9 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3VD QAVD<2..1> TAVD1<2..1> RAVD4<3..1> RAVD3<3..1> RAVD2<3..1> RAVD1<3..1>
K21 C17
REV
DESCRIPTION
DATE
APPR
H
3D2> 3F2> 3H2> 3D7> 3F6> 3H6>
H
VCC
1.0K R57 0.1UF
VCC
0.01UF
Y2
9 C6 4
5V
OSC_TTL OUT
C74
7
SBGA U6 QAVD<2..1> RAVD1<3..1> RAVD2<3..1> RAVD3<3..1> RAVD4<3..1> TAVD1<2..1> VDD<36..1> D ATB<4..1> REFCLK
AC5
D BIAS1 BIAS2
GND 19.44MHZ 20 PPM
G D
G
REFCLK
TCK TMS TDI TDO TRSTB
B8 B9 D10 A9 C9
100
9F6> 9F6> 9F6>
RXD1P\I RXD1N\I SD1\I
50 OHM 50 OHM
R3
E2 D1 E3
RXD1+ RXD1SD1
RESET_B\I
8C10>
F
9G6< 9F6<
TXD1P\I TXD1N\I
50 OHM 50 OHM 50 OHM 50 OHM
R1 R2
158 158 100
C2 C3
0.1UF 0.1UF
C1 D2
F TXD1+ TXD1DTCA<4..1> IDTCA<4..1> TDAT<15..0>\I
H22 J21 J23 2 RN4
47 7
DTCA<4..1>\I
4 3 2 1 4 3 1 1
RN4 RN4 RN4 RN6 47 47 47 47
4E2<
9C6> 9C6> 9C6>
RXD2P\I RXD2N\I SD2\I
R6
G1 G2 J3
RXD2+ RXD2SD2
TDAT<15..0> TPRTY TSOC TCA TADR<4..0>
4H2> 4E10> 4E10> 4C10< 4D1> 4C10> 4B10>
TPRTY\I TSOC\I TCA\I TADDR<4..0>\I TENB\I TFCLK\I 3.3VD
4.7K R37
5 6 8 8
4 3 2 1
9D6<
TXD2P\I TXD2N\I
50 OHM 50 OHM
R4 R5
158 158 100
C4 C5
0.1UF 0.1UF
E1 F2
TXD2+ TXD2-
TENB TFCLK
J22 K20
E
9C6<
E
9F1> 9F1> 9F1>
RXD3P\I RXD3N\I SD3\I
50 OHM 50 OHM
R9
W1 V2 U3
RXD3+ RXD3SD3
S/UNI QUAD
PM5349
PHY_OEN RFCLK RENB RADR<4..0> RCA RSOC RPRTY
A19
P21 P22
RFCLK\I RENB\I RADDR<4..0>\I
47 7 47 5 47 6
4B7> 4C10> 4C1> 4C10< 4E10< 4E10<
9G1< 9F1<
TXD3P\I TXD3N\I
50 OHM 50 OHM
R7 R8
158 158
C8 C9 100
0.1UF 0.1UF
T2 U1
TXD3+ TXD3
N20 2 RN7 P23 4 RN6 T21 3 RN7
RCA\I RSOC\I RPRTY\I
9C1>
RXD4P\I RXD4N\I SD4\I
50 OHM 50 OHM
R12
AA1 Y2 W3
RXD4+ RXD4SD4
RDAT<15..0> DRCA<4..1>
IRDAT<15..0> IDRCA<4..1>
4 4 RN7 3 2 RN6 2 3 RN6 1 1 RN7
47 5 47 7 47 6 47 8
RDAT<15..0>\I DRCA<4..1>\I
4 3 2 1 15 4 14 1 13 4 12 2 11 2 10 4 93 83 72 61 53 43 34 21 12 01
RN24 RN23 RN23 RN23 RN24 RN26 RN23 RN24 RN26 RN26 RN26 RN27 RN27 RN24 RN27 RN27 47 5 47 8 47 5 47 7 47 7 47 5 47 6 47 6 47 7 47 8 47 6 47 6 47 5 47 8 47 7 47 8
4H10<
D
9C1> 9C1>
9D1< 9C1<
TXD4P\I TXD4N\I
50 OHM 50 OHM
R10 R11
158 158
C10 C11
0.1UF 0.1UF
W2 Y1
TXD4+ TXD4INTB RSTB RDB WRB
C10 B10 D11 A10 8
INTB\I U1
9
RESET_B\I R/W_B\I
6D8> 8E10<> 8C10> 5G3> 8E1>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
4E10<
C CSB
AC11 AB11 B11 C11 A11 B12 C12 4.7K R62 9 8 7..0
74HC04 TCLK TFPO TFPI ALE A<10> A<9> A<8>
R23
C CSB\I
8F1> 8E1>
3.3VD
D7
1 1 1 1 2 1.2K R22 1.2K R21 1.2K R20 1.2K R19 4 4.7K 3 2
Y7
ADDR<9..0>\I
D6
2
A<7..0> D<7..0> RAVS1<3..1> RAVS2<3..1> RAVS3<3..1> RAVS4<3..1> TAVS1<2..1> QAVS<2..1> NC<67..1>
4.7K R60
D5
2
DATA<7..0>\I
5D3> 8D1>
D4
2
D
1
RCLK<4..1> RFPO<4..1> RALRM<4..1> RALRM<4..1>
B D
VSS<36..1>
B
D
U1
2 1 4
U1
3
VCC
0.01UF
D
D
D
D
D
D
D
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* DRAWING TITLE=QUAD_BLOCK ABBREV=QUAD_BLOCK LAST_MODIFIED=Mon Nov TITLE: S/UNI-QUAD REFERENCE DESIGN QUAD BLOCK 1 15:49:16 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:2 TRUE 1 OF 9 A
74HC04 A D
6
74HC04 U1
5
74HC04 D D 10 9 8 7 6 5
C56
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H ANALOG RECEIVE 4 ANALOG RECEIVE 1 3.3VD RAVD1_C
0.1UF
H 3.3VD PIN:C4
3
RAVD1<3..1>
RAVD4_C
2G9<
0.1UF C62
PIN:AA4 3
RAVD4<3..1>
2H9<
C54
D RAVD1_B G PIN:A4
2
D RAVD4_B PIN:AC4 2 G
RAVD1_A
PIN:G4
RAVD4_A
1
PIN:Y3
1
F ANALOG RECEIVE 2 3.3VD RAVD2_C
0.1UF
F ANALOG TRANSMIT PIN:J1
3
3.3VD
RAVD2<3..1>
2H9<
27
C57
TAVD1_A
4.7UF C60 0.1UF C64
PIN:L3
2
TAVD1<2..1>
2H9<
R13
D RAVD2_B E PIN:L4
2 2.7 R14 47UF C61
D TAVD1_A
0.1UF C71
PIN:L3
1
E
RAVD2_A
PIN:H2
1
D
3.3VD D ANALOG RECEIVE 3 ANALOG QUAD 3.3VD RAVD3_C
0.1UF 100
D QAVD1 PIN:AA6 1 QAVD<2..1>
2H9<
R15 0.1UF
PIN:N4
3
RAVD3<3..1>
2H9<
C12
D D RAVD3_B PIN:M2
2
C72
QAVD2
PIN:C6
2
C
C
RAVD3_A
0.1UF
PIN:U2
1
C13
NOTES D B 3.3VD PLACE 0.1UF CAPS AS CLOSE TO POWER PINS AS POSSIBLE. 47UF AND 4.7UF CAPACITORS ARE 6.3V TANTALUMS TANTALUM CAPS AND RESISTORS (ON TAVD PINS) DO NOT NEED TO BE PLACED CLOSE TO POWER PINS RESISTORS CAN BE 1/10 WATT SINGLE GROUND PLANE RECOMMENDED
0.1UF C101 0.1UF C83 0.1UF C70 0.1UF 0.1UF C31 0.1UF C100 0.1UF C93 0.1UF C105 0.1UF 0.1UF C7 0.1UF 0.1UF C107 0.1UF
B
C66
C48
C58
C59
PMC-Sierra, Inc.
PLACE DECOUPLING CAPS NEAR DIGITAL PWR PINS A D B2, B22, D9, D15, F20, J4, M20, R4, V20, Y9, Y15, AB2, AB22 DRAWING TITLE=QUAD_BLOCK ABBREV=QUAD_BLOCK LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN QUAD BLOCK 1 15:49:18 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:3 TRUE 1 OF 9 A
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5
4
3
2
1
REVISIONS
VCC LB_EN\I
R40 R41
ZONE
8D10>
REV
DESCRIPTION
DATE
APPR
VCC H
0.1UF 17 C29 1 4.7K 56 4.7K R35 55 R33
4.7K 1 56 55
C33 17
D
4.7K
H
0.1UF
QUAD
2D1>
U22
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 15 14 13 12 11 10 9 8 7 6 5 4 15 14 13 12 11 10 9 8 7 6 5 4
S0 S1 S2
VCC
RDAT<15..0>\I
15 14 13 12 11 10 9 8 7 6 5 4
2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
G
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
RXDAT<15..0>\I
S0 S1 S2
6H6< 6C6>
D TXDAT<15..0>\I
U14 108P TSSOP
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 15 14 13 12 11 10 9 8 7 6 5 4
VCC
CONNECTOR
CONNECTOR
PI5C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
15 14 13 12 11 10 9 8 7 6 5 4 15 14 13 12 11 10 9 8 7 6 5 4
2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
RDAT_F<15..0>
5F3< 5G3>
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
TDAT<15..0>\I
2F4<
QUAD
G
FPGA
TDAT_F<15..0>
FPGA
D SMD RN25 4.7K
16 15 14 13 12 11 10 9
RES_ARRAY_15
PI5C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
1 8 7 6 5 4 3 2
8 19 38 49
VCC F
1 4.7K 56 4.7K R32 55 R31
F VCC
1 4.7K R42 56 R43 55
D D
17
8 19 38 49
0.1UF C37
0.1UF 4.7K C26
U13 93P TSSOP
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 3 2 1 0
D
3 2 1 0 2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
17
D
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 3 2 1 0
U23
3 2 1 0
QUAD
E
2D4> 2D4> 2F4< 2E4< 2D3>
RPRTY\I RSOC\I TPRTY\I TSOC\I DRCA<4..1>\I
4 3 2 1
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
S0 S1 S2
VCC
1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
CONNECTOR
RXPRTY\I RXSOC\I TXPRTY\I TXSOC\I DRXCA<4..1>\I
6F6< 6F3> 6C3> 6D6> 6F6<
3 2 1 0
6C6<
DTXCA<4..1>\I
4 3 2 1 3 2 1 0
4 3 2 1
2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
S0 S1 S2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
VCC
4 3 2 1
DTCA<4..1>\I
2F2>
E
PI5C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
PI5C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
FPGA
RPRTY_F 5C10< RSOC_F 5C10< TPRTY_F 5F3> TSOC_F 5E10> DRCA_F<4..1> 5F10<
5E10<
DTCA_F<4..1>
4 3 2 1
4 3 2 1
VCC D
C32 1 4.7K 56 4.7K R39 55 R38
8 19 38 49
CHIP_RES_NETWORK_8
255P RN28 4.7K SMD VCC
8 19 38 49
D
0.1UF
D
9 8 7 6 1 2 3 4
U21 81P TSSOP
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 4 3 2 1 0 4 3 2 1 0
10
CONNECTOR
R34 R36
6D3>
TXADDR<4..0>\I
D
4 3 2 1 0 4 3 2 1 0 2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
S0 S1 S2
D
5
17
VCC
D
0.1UF
6F3>
RXADDR<4..0>\I
D C
1 4.7K 56 4.7K 55
C30 17
2E4< 2D4>
RENB\I RCA\I
S0 S1 S2
QUAD
2 4 6 9 11 13 15 18 21 23 25 27 3 5 7 10 12 14 16 20 22 24 26 28
U20 3P TSSOP
54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29
VCC
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
TADDR<4..0>\I
2E4<
QUAD
RADDR<4..0>\I
2D4<
C
2E4< 2E4>
TENB\I TCA\I
2E4<
TFCLK\I
1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1
1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
RXENB\I RXCA\I
6F6>
CONNECTOR
6E6<
PI5C16212
5E10>
FPGA
5C10>
TADDR_F<4..0>
TXENB\I TXCA\I
6D6> 6D3>
RADDR_F<4..0>
4 3 2 1 0 4 3 2 1 0
TXCLK\I RENB_F RCA_F
6B7> 5C10> FPGA 5F10<
B
CHIP_RES_NETWORK_8
8 19 38 49
10
5
3.3VD
0.01UF
R93
GND 50.0000MHZ 100 PPM
7
C128
IN
1
8
14
C129
75
1000PF
0.1UF
1P RN16 4.7K SMD
PI5C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10A2 10B2 11A2 11B2 12A2 12B2 VSS VSS VSS VSS
8 19 38 49
B
TENB_F TCA_F
5E10> 5F10<
U15
74FCT807
VCC Y1 OSC_TTL 5V OUT
D
9 8 7 6 4 3 2 1
5G10< 5D10< 2E4< 6B7<
FPGA_CLK RFCLK\I RXCLK\I
75 75 75 75
R54 R55 R56 R58
3 5 7 9 11 12 14 16 18 19
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10
D A
C55
D
PMC-Sierra, Inc.
D DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* ISSUE: 2.0 DATE: 99/08/04 PAGE:4 TRUE 1 OF 9 A
D
DRAWING TITLE=LOOPBACK_BLOCK ABBREV=LOOPBACK LAST_MODIFIED=Mon Nov
TITLE: S/UNI-QUAD REFERENCE DESIGN LOOPBACK BLOCK 1 15:49:21 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
VCC EXT_CLK 19.44 MHZ J5
2 10K R29 5 3 5 2 3 R28 4 6
REV
DESCRIPTION
DATE
APPR
H
H
0.1UF 1 7 8
LE IN -VS
+VS Q
4
1
SMA D
0.1UF C63 51
C69
U19 126P SOIC_NB
TP5 T
R66
0.1UF
AD9696
C67 10K R30
22
GND
TP16 T R/W_B\I TDAT_F<15..0>
9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 0
G
G
8E1> 2C3< 4G6<
D J6
H3
U28
IO/GCK8/A15 IO/A14 IO5 IO4 IO/A13 IO/A12 IO3 IO2 IO1 IO0 IO/A11 IO/A10 IO/A18 IO/A19 IO/A9 IO/A8 IO/A7 IO/A6 IO/A20 IO/A21 IO84 IO/A5 IO/A4 IO83 IO82 IO81 IO80 IO/A3 IO/CS1/A2 IO79 IO78 IO/GCK7/A1 IO/A0/WS O/TDO
4B7>
FPGA_CLK
1 2 3
159 158 157 156 155 154 153 152 150 149 148 147 146 145 144 143 140 139 138 137 136 135 134 133 132 130 129 128 127 126 125 124 123 121
F
4B8> 4B8>
TCA_F RCA_F
4D6>
DRCA_F<4..1>
4 3 2 1 4 3 2 1 4 3 2 1 0
4D5>
DTCA_F<4..1>
4C4<
TADDR_F<4..0>
E
4B8< 4D6< 4B7>
TENB_F TSOC_F FPGA_CLK
2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 38 40
IO/GCK1/A16 IO/A17 IO6 IO7 IO/TDI IO/TCK IO8 IO9 IO10 IO11 IO/TMS IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO/GCK2 O/M1 I/M0
XC4020XL 1PQ160
IO/GCK6/DOUT IO/D0/DIN IO77 IO76 IO/RCLK/RDY/BUSY IO/D1 IO75 IO74 IO73 IO72 IO71 IO/D2 IO70 IO69 IO/RS IO/D3 IO68 IO/D4 IO67 IO66 IO/CS0 IO/D5 IO65 IO64 IO63 IO62 IO61 IO/D6 IO60 IO59 IO/GCK5 IO/D7 DONE PROGRAM CCLK
118 117 116 115 114 113 112 111 109 108 107 106 105 104 103 102 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 80 82 119
0
F TPRTY_F
4D6<
1 0 1 2 3 2 4 3 5 4 6 7
RDAT_F<15..0>
4G7>
CSB_FPGA\I
5 8 9 10 11 12 6 13 14 15 7
8F1>
E
DATA<7..0>\I DONE\I PROGRAM\I
2B3<> 8D1> 8E10< 8D10>
D
JP1
R63 R64 R65 4.7K 1 4.7K 3 4.7K 5
I/M2 IO/GCK3 IO/HDC IO32 IO33 IO34 IO/LDC IO35 IO36 IO37 IO38 IO39 IO40 IO41 IO42 IO43 IO/INIT IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO58 IO/GCK4
D
HEADER 3X2
D
5 4 3 2 1 0
42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 71 72 73 74 75 76 77 78
P_1 P_3 P_5
P_2 P_4 P_6
2 4 6
ADDR<5..0>\I
8E1>
4
3
2
1
4C4< 4B8<
RADDR_F<4..0> RENB_F RPRTY_F RSOC_F 3.3VD
330 330 R67 2 R68 2
C
4D6> 4D6>
0
C D8
1 1
D12
3.3VD
R69 4.7K
B
B
3.3VD
0.1UF
C18 0.1UF
C23 0.1UF
C24 0.1UF
C25 0.1UF
C27 0.1UF
C28 0.1UF
C65
0.1UF
C68
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* DRAWING TITLE=LOOPBACK_BLOCK ABBREV=LOOPBACK LAST_MODIFIED=Mon Nov TITLE: S/UNI-QUAD REFERENCE DESIGN LOOPBACK BLOCK 1 15:49:23 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:5 TRUE 1 OF 9 A
A D
PLACE DECOUPLING CAPS CLOSE TO FPGA
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3 V VCC1 H
REV
DESCRIPTION
DATE
APPR
H
3.3 V P2 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37 A38 C38 A39 C39 A40 C40 RXDAT<15..0>\I
0 1 2 C20 3 4 5 6 7 8 9 10 11 12 13 14 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 1 2 C22 3 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17
4H7>
0.01UF 10UF
A1 C1 A2 C2 A3 C3
B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40
B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 C19
P1 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37 A38 C38 A39 C39 A40 C40
B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40
B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 0 1 2 3 4
G
A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10
+
G
DECOUPLING CAPS NEAR CONNECTOR POWER PINS
VCC1
4E6> 4E6>
0.01UF
15
RXPRTY\I DRXCA<4..1>\I
RXADDR<4..0>\I
4C4<
B10 D10 10UF B11 D11 B12 D12 C21
F
A11 C11
+
F
4 B13 D13
4C8<
B14 D14
RXENB\I RXCA\I
RXSOC\I
4E6>
4C8>
B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26
E
A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23
SCK\I MOSI\I MISO\I CS_MICRO\I M/S_MICRO\I
8D10<>
A18 C18
E
8D10<>
A19 C19
8D10<>
A20 C20
8D10<>
A21 C21
8D10<
A22 C22 A23 C23 A24 C24 A25 C25 A26 C26
D
A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30
D
B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40 0 1 2 3 4
TXCA\I TXADDR<4..0>\I
4C8> 4D4<
4C8<
B27 D27 B28 D28
TXENB\I TXSOC\I DTXCA<4..1>\I
1 2
A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37 A38 C38 A39 C39 A40 C40
INTB\I
2C3>
8E10<> 4E6< 4E5>
B29 D29 B30 D30 3 B31 D31 4 B32 D32
C
A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37
C TXPRTY\I
4E6<
4H6<
B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40 1 3 1 3
TXDAT<15..0>\I
14 15 12 13 10
T2 6P
BALUN
6 4 75 R27
11 8
RXCLK\I
4B7>
9 6 7 4 5 2
B
A38 C38 A39 C39 A40 C40
B
T1 5P
BALUN
6 4
22 R26
TXCLK\I
4B8<
3 0 1
71624-2000
71624-2000
PMC-Sierra, Inc.
A DRAWING TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN SYSTEM INTERFACE 1 15:49:30 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:6 TRUE 1 OF 9 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
1 3
SB2 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
ONLY ONE SET OF SOLDER BRIDGES CONNECTED AT ANY TIME
1 3
SB1 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
G PWR FROM EXTERNAL SUPPLY J3 +3.3V GND +5V
1 2 3 4
G
F1
3.000A
F2
2.000A SB3
1 3
P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
3.3VD TP2
VCC TP15 T 5V
F
1 3
SB4 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
T 3.3V
F
VCC E
3.3VD
E
270 R25
6.2V
SMLVT3V3
D11
D10 34P
68UF
1
80P
1 68UF
D9 33P +
C1 1
+
C14
1
2
D1
2
2
270 2
R24
SMD 1W
D D VCC1
TP13 T GND
TP3 T GND D
TP10 T GND TP11 T GND
2 4
TP4 T GND TP7 T GND
F3
1 3
2.000A
SB5 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
TP14 T GND
TP9 T GND
PWR FROM MOTHERBD CONNECTOR C
1 3
SB6 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
TP6 T GND
TP8 T GND
C
3.3 V
TP12 T GND
TP1 T GND
F4 3.000A
1 3
SB8 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
D
D
B SB7
1 3
B
P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
PMC-Sierra, Inc.
A DRAWING TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN SYSTEM INTERFACE 1 15:49:31 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:7 TRUE 1 OF 9 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
VCC VCC
1.0
H
0.01UF
C51 22UF
C17
+
U26
16
V1
0.1UF C111 0.1UF C35 0.1UF 0.1UF C36 0.1UF C34 0.1UF C46 0.1UF C118 0.1UF C112 0.1UF C120 0.1UF C122 0.1UF C123 0.1UF C45 0.1UF C42 0.1UF 22UF C47 C39 C38
R44 1.0 R45
D J4 DCD RXD TXD DTR GND DSR RTS CTS RI
1 2 3 4 5 6 7 8 9 0.1UF 4 C15 5 14 1000PF 13 7 C53 1000PF 8 C52 2 R52 10K
C2+ C2RS_O1 RS_I1 RS_O2 RS_I2
VCC
C1+ C1LOG_I1 LOG_O1 LOG_I2 LOG_O2
1 3
0.1UF C16
11 12 10 9 6 R53 10K 7 18 28 39 50 65 84 96 107 116 126 19 1 63
+
LT1181A
G
D
G D
V+
0.1UF C49
DB9_FEMALE
D
GND
15
V-
0.1UF C50
U17 V1
R89 10K R51
VSTBY
VDDI1 VDDI2
VDDE1 VDDE2 VDDE3 VDDE4 VDDE5 VDDE6 VDDE7 VDDE8 VDDE9 VDDEA VDDEB
D F
RN1 4.7K
1 2 3 4 8 7 6 5
RES_4_ARRAY
V1
16 15 14 13 12 11 10 9 6 5 4 3 132 131 130 129 128 71 72 73 74 75 76 77 78 89 88 87 86 82 85 81 80 53 52 49 48 47 46 45 44 43 10K 10K 10K R81 R87 R80 R84 69 57 68 70 56 58 55 54
TPUCH<0> TPUCH<1> TPUCH<2> TPUCH<3> TPUCH<4> TPUCH<5> TPUCH<6> TPUCH<7> TPUCH<8> TPUCH<9> TPUCH<10> TPUCH<11> TPUCH<12> TPUCH<13> TPUCH<14> TPUCH<15> T2CLK IRQ7_B/PF7 IRQ6_B/PF6 IRQ5_B/PF5 IRQ4_B/PF4 IRQ3_B/PF3 IRQ2_B/PF2 IRQ1_B/PF1 MODCLK/PF0 DSACK0_B/PE0 DSACK1_B/PE1 AVEC_B/PE2 RMC_B/PE3 AS_B/PE4 DS_B/PE5 SIZ0/PE6 SIZ1/PE7 RXD PQS7/TXD PQS6/PCS3 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS_B PQS2/SCK PQS1/MOSI PQS0/MISO HALT_B TSC RESET_B BERR_B BKPT_B/DSCLK FREEZE/QUOT IFETCH_B/DSI IPIPE_B/DSO VSSI1 VSSI2 VSSI3 VSSI4
CSBOOT_B ADDR23/CS10_B PC6/ADDR22/CS9_B PC5/ADDR21/CS8_B PC4/ADDR20/CS7_B PC3/ADDR19/CS6_B PC2/FC2/CS5_B PC1/FC1/CS4_B PC0/FC0/CS3_B BGACK_B/CS2_B BG_B/CS1_B BR_B/CS0_B R/W_B ADDR<0> ADDR<1> ADDR<2> ADDR<3> ADDR<4> ADDR<5> ADDR<6> ADDR<7> ADDR<8> ADDR<9> ADDR<10> ADDR<11> ADDR<12> ADDR<13> ADDR<14> ADDR<15> ADDR<16> ADDR<17> ADDR<18> DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15> CLKOUT XTAL EXTAL VDDSYN XFC
112 125 124 123 122 121 120 119 118 115 114 113 79 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
10K
F
CSB_FPGA\I CSB\I R/W_B\I IADDR<16..0>
9..0
5E3> 2C3<
5G3>2C3< 2C3<5C3<
ADDR<9..0>\I
U24
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 30 32 7
E
6D8> 2C3>
INTB\I
MC68332
10K
5D3>
DONE\I D LB_EN\I PROGRAM\I M/S_MICRO\I CS_MICRO\I SCK\I MOSI\I MISO\I
R61
4H7< 5D3> 6D8> 6E8<>
D
6E8<> 6E8<> 6E8<>
10K 111 110 10K 109 10K R49 108 105R50 104 103 102 100 0 99 1 98 2 97 3 94 4 93 5 92 6 91 7 66 60 62 61 64 0.1UF 75 R86
24
D
CE_B OE_B WE_B D
C41
C44
6 9
0.1UF
R48
AT29C010 D0 A0 D1 A1 D2 A2 D3 A3 D4 A4 D5 A5 D6 A6 D7 A7 A8 A9 A10 VCC A11 A12 NC1 A13 NC2 A14 A15 VSS A16
21 22 23 25 26 27 28 29
0 1 2 3 4 5 6 7
E
VCC
8 0.01UF 1.0 R47
D
DATA<7..0>\I U25
10M R82 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 16 15 14 13 3 2 31 1 12 4 11 7 10 5 32
2B3<>5D3>
V1
R17 R16
10K
820
10
SW1
2
PBNO
U12
1 2
C114
330K
INP
RST
1
2 34 59 101
0.01UF
0.1UF
1
2
GND
MC33064
Y3
4
8 17 29 40 51 67 83 95 106 117 127
C
VREF
V1
C113 C117
D
2F3<2C3<
D D
0.01UF
RESET_B\I
0.1UF
32.768MHZ
22PF C115 22PF
D J2
1 3 5 7 9 2 4 6 8 10
C116
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 WE OE CS1 CS2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC VCC
100
R18
21 22 23 25 26 27 28 29 9 8
0 1 2 3 4 5 6 7
VSSE1 VSSE2 VSSE3 VSSE4 VSSE5 VSSE6 VSSE7 VSSE8 VSSE9 VSSEA VSSEB
R83
C VCC
1.0 R46
C40
GND
24
V1 B
1.0 R88
P_1 P_2 P_3 P_4 P_5 P_6 P_8 P_7 P_9 P_10
HEADER 5X2
VCC D
30 6
C43
D
128KX8 SRAM B
D
PMC-Sierra, Inc.
A DRAWING TITLE=MICRO_BLOCK ABBREV=MICRO LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN MICRO BLOCK 1 15:49:27 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:8 TRUE 1 OF 9 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
OPTICS 1
3.3VD
FB 0.1UF C142 0.1UF L2 10UF C134 0.1UF C144
3.3VD
OPTICS 3
FB L6 0.1UF C143
10UF
C132
+
C133
+
50 OHM D D
0.01UF 49.9
TXD1P\I
2F10>
50 OHM D D
FB 0.1UF C141 L5 0.01UF 49.9 R109
TXD3P\I
2D10>
3.3VD
R95
3.3VD G
220 R111 R108
G
FB 0.1UF C131 220 R97 L1
C130
330
R94
49.9
R96
6
2
U2
13 14 15 16
U4 D 50 OHM 50 OHM 50 OHM TXD1N\I RXD1P\I RXD1N\I SD1\I
2F10> 2F10< 2F10< 2F10<
13 14 15 16 11 12
VCCT VCCR GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1 9 10 5 4 3 8
VCCT VCCR GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1 R114 150 R113 150 150 R112 9 10 5 4 3 8
49.9
R110
6
2
D 50 OHM 50 OHM 50 OHM
330
D
D
C140
TXD3N\I RXD3P\I RXD3N\I SD3\I
2D10> 2E10< 2E10<
F
11 12
CHASS1 CHASS2 VEET
CHASS1 CHASS2 VEET
F
2E10<
7
R100 150
R99 150
150
R98
7
D
D
D D E
D D
E
3.3VD
OPTICS 2
FB 0.1UF L4 C139 0.1UF C138 0.1UF
OPTICS 4
3.3VD
FB L8 C149 0.1UF C148
10UF
C137
+
10UF
50 OHM D D D
C136 L3 0.01UF FB 49.9 R102 0.1UF
TXD2P\I
2E10>
C147
+
3.3VD D D
R104 FB 0.1UF C146 220 R118 L7 0.01UF 49.9 R116 220
50 OHM 3.3VD
TXD4P\I
2D10>
D
C135
R103
330
D
49.9 6 2
R101
C145
U3
13 14 15 16 11 12
VCCT VCCR C GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1 R107 150 R106 150 150 R105 9 10 5 4 3 8
D 50 OHM 50 OHM 50 OHM TXD2N\I RXD2P\I RXD2N\I SD2\I
2E10> 2F10< 2F10< 2E10<
11 12 13 14 15 16
U5 GND GND GND GND
VCCT VCCR TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1 R121 150 R120 150 150 R119 9 10 5 4 3 8
49.9
R117
6
2
D 50 OHM 50 OHM 50 OHM TXD4N\I RXD4P\I RXD4N\I SD4\I
2C10> 2D10< 2D10< 2D10<
330
D
R115
C
CHASS1 CHASS2 VEET
CHASS1 CHASS2 VEET
7
D
7
D
D D D B D B
PMC-Sierra, Inc.
A DRAWING TITLE=OPTICS_BLOCK ABBREV=OPTICS_BLOCK LAST_MODIFIED=Mon Nov 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-980932 *PRELIMINARY* TITLE: S/UNI-QUAD REFERENCE DESIGN OPTICS_BLOCK 1 15:49:13 1999 3 ENGINEER: PMC-SIERRA EC 2 BDV ISSUE: 2.0 DATE: 99/08/04 PAGE:9 TRUE 1 OF 9 A
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
9.1
Bill of Materials Table 3 : Major Components List Ref. No U6 U2-U5 Component Description PMC-Sierra, Inc. PM5349 S/UNI-QUAD Hewlett Packard Co. Tel: 1-800-235-0312 Fiber transceivers Singlemode: HFCT-5905 Multimode: HFBR-5905 U12 U13, U14, U20-U23 U15 U17 U24 U25 U26 U28 Y1 Motorola undervoltage sensor MC33064 Pericom 24 bit bus switch PI5C16212 Pericom clock driver 74FCT807 Motorola 32 bit microcontroller MC68332 Atmel FLASH memory AT29C010A Cypress SRAM CY62128 Linear Technology RS232 driver LT1181A Xilinx FPGA XC4020XL MMD Clock Oscillator 50.00 MHz, 100 PPM 4 Pins 1 PQFP160 1 SOIC16 1 TSOP 32 1 TSOP 32 1 PQFP 100 1 SOIC20 1 TSSOP 54 6 SOIC8 1 2x5 DIP Style 4 Package Type SBGA304 Quantity 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
Ref. No Y2
Component Description Connor-Winfield Clock Oscillator ASM54 19.44 MHz, 20 PPM
Package Type SMT
Quantity 1
D1
SGS-Thomson Transil SMLVT3V3
SMB
1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
24
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
1110 * * * *
REFERENCES PMC-Sierra, Inc., PM5349 S/UNI-QUAD Data Sheet, Issue 2, March 1998 Bell Communication Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, December 1995 Hewlett Packard, HFBR-5905 ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1 in low cost 2x5 package style, Technical Data, July 1998 Hewlett Packard, HFCT-5905 MT Duplex Single Mode Transceiver, Preliminary Technical Data, April 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
25
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
26
PRELIMINARY REFERNCE DESIGN PMC-980932 ISSUE 3
PM5349 S/UNI-QUAD
S/UNI-QUAD REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-980932 (R3) Issue date: September 1999
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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