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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
PM4344/PM6344
TQUAD/EQUAD WITH QDSX REFERENCE DESIGN
ISSUE 1: DECEMBER 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
CONTENTS 1 2 3 APPLICATIONS ....................................................................................... 1 OVERVIEW.............................................................................................. 2 FUNCTIONS AND IMPLEMENTATION.................................................... 4 3.1 3.2 BLOCK DIAGRAM ........................................................................ 4 TQUAD/EQUAD ............................................................................ 5 3.2.1 PM4344 TQUAD................................................................. 6 3.2.2 PM6344 EQUAD ...............................................................11 3.2.3 INTERNAL LOOPBACKS ................................................. 13 3.3 3.4 QDSX .......................................................................................... 14 MICROPROCESSOR INTERFACE ............................................ 15 3.4.1 DECODE LOGIC .............................................................. 17 3.5 LINE SIDE INTERFACE.............................................................. 18 3.5.1 PROTECTION CIRCUITRY.............................................. 18 3.5.2 RESISTOR POPULATION OPTIONS .............................. 20 3.6 3.7 3.8 3.9 POWER AND GROUND CONNECTIONS .................................. 20 CRYSTAL CLOCK ....................................................................... 20 OSCILLATOR Y2......................................................................... 20 FPGA .......................................................................................... 21 3.9.1 MINIMUM REQUIREMENTS............................................ 21 3.9.2 ADDITIONAL FEATURES ................................................ 21 3.9.3 TIMING OPTIONS ............................................................ 22 3.9.4 LOOPBACKS ................................................................... 24
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
3.9.5 VHDL CODE..................................................................... 25 3.10 ALARMS...................................................................................... 27 3.10.1 EQUAD ALARMS ............................................................. 28 3.10.2 TQUAD ALARMS.............................................................. 28 3.10.3 INTERRUPTS................................................................... 28 4 LAYOUT DESCRIPTIONS ..................................................................... 30 4.1 4.2 4.3 4.4 5 COMPONENT PLACEMENT ...................................................... 30 LAYER STACKING AND TRANSMISSION LINE IMPEDANCE CONTROL................................................................................... 31 POWER AND GROUND.............................................................. 32 ROUTING.................................................................................... 33
REFERENCES....................................................................................... 34
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
TABLE OF FIGURES FIGURE 1 HIGH-LEVEL BLOCK DIAGRAM ..................................................... 2 FIGURE 2 BLOCK DIAGRAM ........................................................................... 5 FIGURE 3 MEMORY MAP .............................................................................. 18 FIGURE 4 PROTECTION CIRCUITRY ........................................................... 19 FIGURE 5 FLOW THROUGH TIMING ............................................................ 22 FIGURE 6 COMMON BACKPLANE TIMING .................................................. 23 FIGURE 7 EXTERNAL TIMING....................................................................... 24 FIGURE 8 DIAGNOSTIC LOOPBACKS.......................................................... 24 FIGURE 9 LINE SIDE LOOPBACKS............................................................... 25 FIGURE 10BACKPLANE LOOPBACKS .......................................................... 25 FIGURE 11 DIGITAL CIRCUIT IN FPGA........................................................... 26 FIGURE 12MAIN COMPONENT PLACEMENT DIAGRAM ............................. 30 FIGURE 13PCB CROSS SECTION ................................................................. 31
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iii
RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TQUAD ID REGISTER - ADDRESS: 00CH .................................... 6 TQUAD DEFAULT SETTINGS......................................................... 6 BASE ADDRESSES FOR THE TQUAD AND EQUAD .................... 7 ESF FRAME FORMAT..................................................................... 8 SLC(R)96 FRAME FORMAT .............................................................. 9 SF FRAME FORMAT ....................................................................... 9 T1DM FRAME FORMAT................................................................ 10 EQUAD ID REGISTER - ADDRESS: 00CH ...................................11 EQUAD RECOMMENDED CONFIGURATION.............................. 12
TABLE 10 BASE ADDRESSES FOR THE PM4314 QDSX............................. 14 TABLE 11 QDSX REGISTER CONFIGURATION........................................... 15 TABLE 12 MICROPROCESSOR INTERFACE PIN DESCRIPTIONS ............ 15 TABLE 13 PROTECTION CIRCUITRY ........................................................... 19 TABLE 14 RESISTOR POPULATION OPTIONS ............................................ 20 TABLE 15 LED DISPLAY ................................................................................ 28
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
1
APPLICATIONS * * * * T1/E1 Frame Relay Interfaces T1/E1 ATM Interfaces ISDN Primary Rate Interfaces T1/E1 Channel Banks and Multiplexers
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1
RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
2
OVERVIEW The TQUAD/EQUAD with QDSX reference design demonstrates PMC-Sierra's TQUAD and EQUAD chipsets. This reference design embodies PMC-Sierra's guidelines and suggestions for designing a four port DSX-1/E1 interface card. This design shows the simplicity of combining the TQUAD and EQUAD into one design, capable of interfacing to T1 or E1 signals. The TQUAD and EQUAD are pin-to-pin compatible, allowing both to be designed into the same footprint. By simply interchanging the TQUAD and EQUAD, and changing some resistors, the board can be converted between T1 and E1 mode. The TQUAD/EQUAD with QDSX reference design has both line and system side loopback capabilities. This permits the user to evaluate the performance of PMC-Sierra's TQUAD, EQUAD, and QDSX chipsets in an applications environment. An FPGA provides access to various timing options available within the TQUAD/EQUAD. These timing options allow the backplane to be timed to a number of different sources. The timing may be sourced from on-board oscillators or from clocks recovered within the TQUAD/EQUAD. The following figure gives an overview of the TQUAD/EQUAD with QDSX reference design. Figure 1 High-Level Block Diagram
T1/E 1 line interface
T XD
FPG A
TQ UA D/EQ U AD
QD SX
RXD
Address/Data B us
M icroprocessor Interface
This reference board receives and transmits up to four T1/E1 signals. The line interface circuitry consists of the transformers, connectors, and passive networks
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
necessary to interface the QDSX device to cables carrying G.703-compliant signals. The PM4314 QDSX is a quad line interface unit with integrated DSX-1 and CEPT E1 interfaces. In this reference design, PMC Sierra's QDSX is being used to provide a T1/E1 interface for the four duplex serial data streams. The TQUAD/EQUAD is a quadruple T1/E1 framer. Each individual receiver performs clock recovery (optional), performs jitter attenuation (optional), finds frame alignment, monitors performance, extracts facility datalink and signaling bits, and retimes the signal to a backplane clock via the elastic store. Each individual transmitter receives the signal to be transmitted from the backplane, inserts framing, facility datalink, signaling, and other overhead bits, performs jitter attenuation, and transmits the digital signal to the line side. An on-board LED display indicates alarm conditions detected by the TQUAD/EQUAD. This LED Display is controlled by the microprocessor. The ACTEL A1460A FPGA provides a PRBS data generator, loopback schemes, timing options and extra logic required by the LED display. All necessary signals needed for microprocessor access to the FPGA have been provided. The microprocessor interface carries all the signals required to connect the TQUAD/EQUAD with QDSX reference design to a host 8-bit multiplexed microprocessor bus. This connector provides access to the full set of registers in the TQUAD/EQUAD and QDSX.
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
3
FUNCTIONS AND IMPLEMENTATION The following sections provide a functional description of the components on board.
3.1
Block Diagram The TQUAD/EQUAD with QDSX reference design consists of nine main functional blocks. There are two external interfaces: the T1/E1 Line Interface and the 96-pin microprocessor interface. The FPGA provides system loopbacks, PRBS generation, LED logic, and several timing options. The microprocessor interface provides external access for a microprocessor to initialize and monitor the performance of the TQUAD/EQUAD and the QDSX. The microprocessor has access to the FPGA to control the alarm LEDs and select various operating options. Each individual block is explained below.
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Figure 2
Block Diagram
O scillator
LE D Disp lay
FPGA
Crystal Clock
T1 ~ 37.056 M Hz E1 ~ 49.152 M Hz
TCLKO[4 ] TDP[4] TDN[4]
TCLKI[4 ] TDP[4 ] TDN[4]
TXTIP[4 ] TXRING[4]
TQUAD/EQUAD
RCLKI[4] RDP[4] RDN[4] M icro_Interface RDP[4] RDN[4]
Q DS X
RXTIP[4] RXRING[4] M icro_Interface
E1/T 1 Line Interface/Protection Circuitry
5
BTSIG [4]
BRFPI RF P[4]
BTFP[4 ]
BRFPO[4]
BTCLK [4]
TDLSIG[4]
TDLCLK[4 ]
RDLCLK[4]
RDLSIG[4]
BTPCM [4]
BRPCM [4]
RCLKO[4]
BRSIG[4]
BRCLK
96-pin microprocessor interface
3.2 TQUAD/EQUAD The 128 pin TQUAD and EQUAD chips are pin-to-pin compatible, which allows the two chips to be designed into the same footprint.
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XCLK
RCLKO[4]
XCLK
4 Tx T1/E1 L
4 Rx T1/E1
Decode logic
RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
3.2.1 PM4344 TQUAD The TQUAD is a quadruple T1 framer. Each individual receiver performs clock recovery (optional), performs jitter attenuation (optional), finds frame alignment, monitors performance, extracts facility datalink and signaling bits, and retimes the signal to a backplane clock via the elastic store. Each individual transmitter receives the signal to be transmitted from the backplane, inserts framing, facility datalink, signaling, and other overhead bits, performs jitter attenuation, and transmits the digital signal to the line side. Multiplexing and demultiplexing of the backplane data and signaling bits from the transmit and receive sides of the four T1 framers is supported but not available in this reference design. The full register set of the TQUAD, including Test Mode registers, are accessible to the host microprocessor. For a full description of the TQUAD, refer to the TQUAD Data book. 3.2.1.1 Configuring the TQUAD from Reset The microprocessor must first determine whether the TQUAD/EQUAD with QDSX reference board contains the TQUAD or the EQUAD. As the ID register is the same on both the TQUAD and the EQUAD, Register 006H must be used instead. The bit to check is shown in the following table. Table 1 Bit 4 TQUAD Register - Address: 006H Bit Value 0
After TQUAD power up, a software reset should be performed on the TQUAD to put it in a default state. A software reset is performed by setting the RESET bit (register 0DH) and then clearing it. Table 2 Setting Framing Format Line Code SF B8ZS TQUAD Default Settings Receiver Section Transmitter Section SF AMI
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Setting DS1 Interface
Receiver Section Pins RDP/RDD[x] and RDN/RCLV[x] active as digital inputs RDP[x] and RDN[x] and used for clock and data recovery 1.544MHz data rate BRPCM[x], BRSIG[x] active BRFPO[x] indicates frame pulses
Transmitter Section TDP[x], TDN[x] outputs NRZ data updated on falling TCLKO[x] edge
System Backplane
1.544MHz data rate BTPCM[x] active BTSIG[x] inactive BTFP[x] indicates frame alignment internal XFDL disabled TDLCLK[x] output held low, TDLSIG[x] input ignored Signaling alignment disabled F, CRC, FDL, bit bypass disabled Digital jitter attenuation enabled, with TCLKO[x] referenced to BTCLK[x] All diagnostic modes disabled
Data Link
internal RFDL disabled RDLSIG[x] and RDLCLK[x] outputs held low
Options
ELST not bypassed RFP help low PMON accumulates OOFs (not COFAs)
Timing Options
Not applicable
Diagnostics
All diagnostic modes disabled
In the following tables the "Addr Offset" is the address relative to each framer. The base addresses are given in Table 3. Table 3 Base Addresses for the TQUAD and EQUAD Quadrant 0 1 2 3 Base Address 000H 080H 100H 180H
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
To configure the TQUAD for ESF framing format, after a reset, the registers should be written with the values indicated in Table 4. Table 4 ESF Frame Format Action Write CDRC Configuration Register Write XBAS Configuration Register Addr Offset 10H 44H Data 00H 3XH Effect Select B8ZS line code for receiver Select B8ZS, enable for ESF in transmitter (bits defined by `X' determine the FDL data rate & Zero Code suppression algorithm used) Select ESF, 2 of 4 OOF threshold Select ESF, 2 of 5 OOF threshold Select ESF, 2 of 6 OOF threshold (bits defined by `X' determine the FDL data rate, should be the same as those written to XBAS) Enable 8 out of 10 validation Enable 4 out of 5 validation Select ESF (bits defined by `X' determine the ESF YELLOW data rate, should be the same as those written to FRMR) Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select ESF (bits defined by `X' should be the same as those written to FRMR)
Write FRMR Configuration Register
20H
1XH 5XH 9XH
Write RBOC Enable Register
2AH
00H or 02H
Write ALMI Configuration Register
2CH
1XH
Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
3CH 3EH 3FH 40H
00H 08H 44H 1XH
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
To Configure the TQUAD for SLC(R)96 framing format, after a reset, the registers should be written with the values indicated in Table 5. Table 5 SLC(R)96 Frame Format Action Write CDRC Configuration Register Write XBAS Configuration Register Write FRMR Configuration Register Addr Offset 10H 44H 20H Data 80H 08H 08H 48H 88H Effect Select AMI line code for receiver Select AMI, enable for SLC(R)96 in transmitter Select SLC(R)96, 2 0f 4 OOF threshold Select SLC(R)96, 2 0f 5 OOF threshold Select SLC(R)96, 2 0f 6 OOF threshold Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register 2CH 3CH 3EH 3FH 40H 08H 00H 08H 44H 08H Select SCL(R)96 Enable Inband Code Detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select SLC(R)96
To configure the TQUAD for SF framing format, after a reset, the following registers should be written with the indicated values: Table 6 SF Frame Format Action Write CDRC Configuration Register Write XBAS Configuration Register Addr Offset 10H 44H Data 80H 00H Effect Select AMI line code for receiver Select AMI, enable for SF in transmitter
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Action Write FRMR Configuration Register
Addr Offset 20H
Data 00H 40H 80H
Effect Select SF, 2 of 4 OOF threshold Select SF, 2 of 5 OOF threshold Select SF, 2 of 6 OOF threshold Select SF Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select SF
Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
2CH 3CH 3EH 3FH 40H
00H 00H 08H 44H 00H
To configure the TQUAD for T1DM framing format, after a reset, the registers should be written with the indicated values: Table 7 T1DM Frame Format Action Write CDRC Configuration Register Write XBAS Configuration Register Addr Offset 10H 44H Data 80H 04H or 0CH 04H 44H 84H 04H 0CH Effect Select AMI line code for receiver Select AMI, enable for T1DM in transmitter Select T1DM, 2 of 4 OOF threshold Select T1DM, 2 of 5 OOF threshold Select T1DM, 2 of 6 OOF threshold Select T1DM with standard RED integration Select T1DM with alternate RED integration Write IBCD Configuration Register Write IBCD Activate Code Register 3CH 3EH 00H 08H Enable Inband Code detection Program Loopback Activate Code pattern
Write FRMR Configuration Register
20H
Write ALMI Configuration Register
2CH
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Action Write IBCD Deactivate Code Register Write SIGX Configuration Register 3.2.2 PM6344 EQUAD
Addr Offset 3FH 40H
Data 44H 04H
Effect Program Loopback Deactivate Code pattern Disable robbed bit signaling extraction
The EQUAD is a quadruple E1 framer. Each individual receiver performs clock recovery (optional), performs jitter attenuation (optional), finds frame alignment, monitors performance, extracts facility datalink and signaling bits, and retimes the signal to a backplane clock via the elastic store. Each individual transmitter receives the signal to be transmitted from the backplane, inserts framing, facility datalink, signaling, and other overhead bits, performs jitter attenuation, and transmits the digital signal to the line side. Multiplexing and demultiplexing of the backplane data and signaling bits from the transmit and receive sides of the four E1 framers is supported but not available in this reference design. The full register set of the EQUAD, including Test Mode registers, are accessible to the host microprocessor. For a full description of the EQUAD, refer to the EQUAD Data book. 3.2.2.1 Configuring the EQUAD from reset The microprocessor must first determine whether the TQUAD/EQUAD with QDSX reference board contains the TQUAD or the EQUAD. As the ID register is the same on both the TQUAD and the EQUAD, Register 006H must be used instead. The bit to check is shown in the following table. Table 8 EQUAD Register - Address: 006H Bit 4 Bit Value 1
After EQUAD power up, a software reset should be performed on the EQUAD to put it in a default state. A software reset is performed by setting the RESET bit (register 0DH) and then clearing it. The recommended initial configuration is given in Table 9.
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
The base addresses for the EQUAD are the same as those for the TQUAD, which are given in Table 3. Table 9 EQUAD Recommended Configuration Recommended Configuration
Offset Register Address (hex) 06 09 10 TXSA4EN=1
Default value.
RXSA4EN=0 This allows TS16 to be extracted for D-Channel processing. AMI=X Setting this bit disables the HDB3 decoding. ALGSEL=1 This selects a clock recovery algorithm with the best tolerance of high frequency jitter.
11
LOSE=1 This enables changes in the status of the LOS detection circuit to generate interrupt indications on the EQUAD'S INTB output pin. N1[7:0]=FF The value in this register must be the same as in Register 1AH when the transmit timing reference is at the line rate. N2[7:0]=FF This sets the DJAT transfer function for maximum jitter attenuation. CENT=1 This allows the DJAT FIFO to center itself thereby providing maximum room to absorb phase differences between the input and output transmit clocks. SYNC=0 This bit should be cleared whenever Register 1AH does not contain its default value (2FH). LIMIT=0 This function should be disabled so that the DJAT FIFO does disrupt the DJAT PLL operation. With the hardware connections recommended in this document, the FIFO should never reach a condition where LIMIT would be useful.
19
1A 1B
20
CRCEN=1 the FRMR.
This enables the MFAS alignment circuitry in
CASDIS=1 This disables the CAS multiframe alignment circuitry in the FRMR. REFCRCE=1This enables the CRC error monitor to force a reframe if an excessive CRC error condition is detected.
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Offset Register Address (hex) 21
Recommended Configuration
BIT2C=1 This enables the EQUAD to declare OOF if Bit 2 of TS0 of NFAS frames is received incorrectly for three consecutive frames. OOFE=1 This enables changes in the status of the FAS alignment circuit to generate interrupt indications on the EQUAD'S INTB output pin. OOCMFE=1 This enables changes in the status of the MFAS alignment circuit to generate interrupt indications on the EQUAD'S INTB output pin.
22
23
RRAE=1 This enables changes in the status of the RAI detection circuit to generate interrupt indications on the EQUAD'S INTB output pin. REDE=1 This enables changes in the status of the RED detection circuit to generate interrupt indications on the EQUAD'S INTB output pin. AISE=1 This enables changes in the status of the AIS circuit to generate interrupt indications on the EQUAD'S INTB output pin.
30
IND=1 This enables indirect accessing of the Transmit PerChannel Serial Controller (TPSC) registers within the EQUAD. SIGEN=0 This disables the transmission of ChannelAssociated Signaling in TS16. DLEN=0 This disables the transmission of ChannelAssociated Signaling in TS16. GENCRC=1 multiframe. This enables the generation of the CRC
44
3.2.3 Internal Loopbacks The TQUAD/EQUAD provides three internal loopback modes to aid in network and system diagnostics. The network loopbacks (PAYLOAD and LINE) can be initiated at any time via the microprocessor interface, but are usually initiated once an inband loopback activate code is detected. The system loopback
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
(Diagnostic) can be initiated at any time by the system, via the microprocessor interface, to check the path of the system data through the framer. For more information on internal loopback modes see the TQUAD/EQUAD Data book. 3.3 QDSX The QDSX is a full-featured quadruple T1/E1 line interface unit that provides a G.703-compliant interface for 1544 kbit/s and 2048 kbit/s rates. The full register set of the QDSX, including Test Mode registers, are accessible to the host microprocessor. For a full description of these registers, refer to the QDSX Data book. In this reference design, the QDSX is being used to provide a T1/E1 interface for four duplex T1/E1 serial data streams. 3.3.1.1 Configuring the QDSX from Reset After QDSX power up, a software reset should be performed on the QDSX to put it in a default state. The software reset is performed by setting the RESET bit (register 07H) and then clearing it. The initial configuration is given in Table 10 as well as the offset registers from the base address of each quadrant of the QDSX. The base addresses for the QDSX are given in Table 10. Table 10 Base Addresses for the PM4314 QDSX Quadrant 0 1 2 3 Base Address 000H 040H 080H 0C0H
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Table 11
QDSX Register Configuration Register Configuration
Offset Register Address (hex) 000
RDUAL = 1 Sets the receive section to output dual-rail data. If the XIBC or the PRSG are in the receive path, they will be bypassed. CEPT = 0 CEPT = 1 Receive section configured for T1 applications. Receive section configured for E1 applications.
All CEPT bits in all four quadrants, in both transmit and receive sections, should be set to the same value. 001 TDUAL = 1 data. CEPT = 0 CEPT = 1 Sets the transmit section to receive dual-rail Transmit section configured for T1 applications. Transmit section configured for E1 applications.
Additional features, such as setting the transmit pulse template, are not within the scope of this document. For more information, see the QDSX data book. 3.4 Microprocessor Interface The 96-pin connector carries all the signals required to connect the TQUAD/EQUAD with QDSX reference design to a host 8-bit multiplexed microprocessor bus. The pin description for the Microprocessor interface is given in Table 12. Table 12 Microprocessor Interface Pin Descriptions Type I Pin C1 Function Address latch enable. When high, identifies that address is valid on AD[7:0]. This signal is used for demultiplexing the microprocessor bus. External data access indication. Active high. Active low write enable, active high read enable. Active low hardware RESET. This is connected to all devices providing a hardware RESET pin.
Signal Name ALE
E RWB RSTB
I I I
C2 C3 C4
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Signal Name A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] PA3 PA4 PA5 PA6 PD2 PD3 PD4 PD5 IRQB
Type I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I I I O
Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 Address bus bit 15 Address bus bit 14 Address bus bit 13 Address bus bit 12 Address bus bit 11 Address bus bit 10 Address bus bit 9 Address bus bit 8
Function
Multiplexed address/data bus bit 7 Multiplexed address/data bus bit 6 Multiplexed address/data bus bit 5 Multiplexed address/data bus bit 4 Multiplexed address/data bus bit 3 Multiplexed address/data bus bit 2 Multiplexed address/data bus bit 1 Multiplexed address/data bus bit 0 68HC11 Processor Port A bit 3 68HC11 Processor Port A bit 4 68HC11 Processor Port A bit 5 68HC11 Processor Port A bit 6 Master In Slave Out (MISO) of 68HC11 Port D bit 2 acting as SPI. Pulled up on motherboard. Master Out Slave In (MOSI) of 68HC11 Port D bit 3 acting as SPI. Pulled up on motherboard. Serial Clock (SCK) of 68HC11 Port D bit 4 acting as SPI. Pulled up on motherboard. Slave Select (SS) of 68HC11 Port D bit 5 acting as SPI active low. Pulled up on motherboard. Maskable 68HC11 interrupt. Pulled up on motherboard.
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RELEASED REFERENCE DESIGN PMC-980328 ISSUE 1
PM4344 TQUAD/PM6344 EQUAD
TQUAD/EQUAD REFERENCE DESIGN
Signal Name XIRQB DISB
Type O O
Pin C30 C31
Function Non-Maskable 68HC11 interrupt. Pulled up on motherboard. EVMB memory disable. Pulling this signal low will disable MPU access to the EVMB's on board RAM and EPROM. Pulled up on motherboard Spare Ground +5 Volts
SP GND +5 V 3.4.1 Decode Logic
I GND PWR
C32 A1A28 A29A32
The decode logic functional block provides the chip select decoding and the memory mapping from the microprocessor to the TQUAD/EQUAD with QDSX reference design. The PM1501 Evaluation Motherboard provides address space for external hardware (ie. the TQUAD/EQUAD with QDSX reference design), starting at C000H to CFFFH. The memory map for this design is shown in Figure 3.
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Figure 3
Memory Map
000H TQUAD/EQUAD Normal Mode Registers 200H TQUAD/EQUAD Test Mode Registers 3FFH QDSX Normal Mode Registers 500H 5FFH QDSX Test Mode Registers 600H Not Used 7FFH 800H LED Display LED 400H 4FFH 1FFH
BFFH
C00H
FPGA/Unused
FFFH
3.5
Line Side Interface The line interface circuitry consists of the transformers, connectors and passive networks necessary to interface the QDSX device to cables carrying G.703compliant 1544 kbit/s and 2048 kbit/s signals.
3.5.1 Protection Circuitry Circuitry has been added to provide secondary line protection against faults such as lightning surges, AC power faults and various maintenance related hazards.
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This protection circuitry has been designed to meet both ETS 300 046 and FCC Part 68 Standards. The protection circuit is shown in the following figure. Figure 4 Protection Circuitry
Table 13
Protection Circuitry Description 6V, TVS diode PTC 5V, Surge Rated Diode Array Part LC01-6 TR250-180U SRDA05-4 Manufacturer SEMTECH Raychem SEMTECH
Component U10, U14-20 TR1-TR16 U21-24
The LC01-6 is a low capacitance, surface mount, transient voltage suppressor. This device is designed to protect high speed communication lines from voltage surges caused from electrostatic discharge, electrical fast transients, and induced lightning. The PTCs provide the 120V intra-building AC power cross protection required for customer premises equipment.
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The SRDA05-4 provides voltage clamping within 300 mV of 5V without distorting the output pulse shape. 3.5.2 Resistor Population Options Certain passive circuit elements of the TQUAD/EQUAD with QDSX reference design are specific to either T1 or E1 operation. Table 14 shows the differences in the passive circuit elements of the two modes. Table 14 Resistor Population Options Resistor R11, R30, R32, R34 R9, R15, R16, R17 R21, R22, R24, R26 R10, R12, R13, R14 R73 R74 3.6 22 0 309 93.1 4.7k not populated T1 Mode () 47 2.7 357 121 not populated 4.7k E1 Mode ()
Power and Ground Connections The TQUAD/EQUAD with QDSX reference design card requires a +5V power supply. This power may be supplied by the PM1501 EVMB via the microprocessor interface connector or by an external power supply. Solder bridges are provided to allow connection to the EVMB's power supply.
3.7
Crystal Clock This clock provides timing for many portions of the TQUAD/EQUAD and the QDSX. The high-speed timing for the TQUAD and QDSX combination is sourced from a 37.056 MHz crystal oscillator. The high-speed timing for the EQUAD and QDSX combination is sourced from a 49.152 MHz crystal oscillator.
3.8
Oscillator Y2 This oscillator provides an 2.048MHz clock to the FPGA. It is a clock source that provides extra timing options on the TQUAD/EQUAD with QDSX reference design. This clock may be selected and routed, by the FPGA, to the system side of the TQUAD/EQUAD.
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3.9
FPGA The ACTEL A1460A FPGA provides a PRBS generator, loopback capabilities, logic for alarm LEDs, and several timing options. The code for the FPGA is provided in Appendix D.
3.9.1 Minimum Requirements The system loopback functions, provided by the FPGA, must be programmed to use the TQUAD/EQUAD with QDSX reference design. The backplane signals that must be looped back are described in the following paragraphs. BRPCM[4:1] are the backplane receive PCM serial data streams. These signals must be looped back to BTPCM[4:1]. BRSIG[4:1] are the backplane receive Signaling serial data streams which indicate the extracted robbed-bit signaling information of each PCM timeslot on BRPCM[4:1]. These signals must be looped back to BTSIG[4:1]. The FPGA must select a 1.544 MHz/2.048 MHz clock source for BRCLK to time the receive section. BRCLK is common to all four framers. The TQUAD/EQUAD may be configured to ignore the BRCLK and use the RCLKO[4:1] signal in its place when the Elastic Store is bypassed. A suitable framing pulse must be generated by the FPGA to frame align the received data to the system backplane. A pulse at least 1 BRCLK cycle wide must be provided on BRFPI every 256 bit periods. BRFPI is common to all four framers. BRFPO[4:1] must be looped back to the BTFP[4:1]. BRFPO[4:1] indicates the frame alignment of the BRPCM[4:1] data A 1.544 MHz/2.048 MHz clock must be provided to the BTCLK[4:1] to provide timing to the transmit section of the TQUAD/EQUAD. Other timing options may be selected in the FPGA but are not required for the operation of the TQUAD/EQUAD with QDSX reference design. Additional timing options are described in the Timing Options section. 3.9.2 Additional Features A PRBS data generator has been provided to facilitate line side loopbacks. The PRBS pattern generated is 223-1.
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The FPGA provides timing options such as Flow Through Timing, Common Backplane Timing, and External Timing. 3.9.3 Timing Options The FPGA provides timing options such as Flow Through Timing, Common Backplane Timing, and External Timing. Flow Through Timing uses the 1.544/2.048 MHz clock to source timing for the BTCLK[4..1]. The data streams are stored in the FIFO timed to the BTCLK[4..1]. The BTCLK[4..1] is received by the Jitter Attenuator, where the BTCLK[4..1] is smoothed out, and transmitted as TCLKO[4..1]. Flow Through Timing is shown in Figure 5.
Figure 5
Flow Through Timing
Common Backplane Timing is similar to Flow Through Timing except it uses the same clock to time BTCLK and BRCLK. It allows for use of the 2.048MHz oscillator for timing the backplane (T1 mode only). Common Backplane Timing is shown in Figure 6.
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Figure 6
Common Backplane Timing
External Timing facilitates the use of any N*8 kHz external clock, where N is an integer, to generate the TCLKO[4..1] clock signal. Provided TCLKI[4..1] is jitter free when divided down to 8 kHz, then it is possible to derive TCLKO[4..1] from TCLKI[4..1] when TCLKI[4..1] is a multiple of 8 kHz. The specified maximum frequency for TCLKI[4..1] is 3.096 MHz. External Timing is shown in Figure 7.
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Figure 7
External Timing
3.9.4 Loopbacks Three diagnostic loopbacks are available to aid in network diagnostics and problem isolation. Data generated in the FPGA can be looped back via the TQUAD/EQUAD, QDSX, or physically via the cable. Diagnostic loopbacks are shown in Figure 8. Figure 8 Diagnostic Loopbacks
Also, two line side loopbacks, as shown in Figure 9, are available for looping back external data. External data can be looped back via the TQUAD/EQUAD or QDSX.
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Figure 9
Line Side Loopbacks
As well, two backplane loopbacks are available, as shown in Figure 10. Data can either be looped back via the TQUAD/EQUAD or FPGA. Figure 10 Backplane Loopbacks
3.9.5 VHDL Code The FPGA must be able to loopback data streams, signaling, frame pulses, and clocks. These loopbacks are required for the TQUAD/EQUAD with QDSX reference design to work properly. Additional features have been designed into the FPGA which allow the user to obtain access to the many features of the TQUAD and EQUAD. VHDL, a hardware description language, has been used to create the digital circuit used inside the FPGA. A block diagram of the VHDL code is shown in the following figure.
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Figure 11
Digital Circuit in FPGA
The XCLK, a 37.056/49.152 MHz clock for T1/E1 respectively, is divided by 24 to produce a suitable clock for timing the receive section of the TQUAD/EQUAD.
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The divided clock is also required to generate a framing pulse used in the receive section for frame alignment. The frame pulse is output once every 256 clock cycles for the EQUAD, or once every 193 clock cycles for the TQUAD (thus always producing an 8kHz pulse). DIP Switch 0 is used to select between timing options. A `0' selects Flow Through Timing and a `1' selects Common Backplane Timing. A 223-1 PRBS generator allows the TQUAD/EQUAD with QDSX reference design to loopback the line side T1/E1 signals. The PRBS generator is selected by DIP Switch 1. A `0' selects the receive data, from BRPCM, to be sent to the transmit section, whereas a `1' selects the PRBS data to be sent to the transmit section. DIP Switch 2 is used when the auxiliary oscillator is installed on the board (2.048MHz), in order to time the backplane to it. This feature is only available when using Common Backplane Timing (DIP Switch 0 set to `1'). DIP Switch 3 is used to set TCLKI to either an external oscillator or to hold it low. DIP Switches 4 through 7 are the signaling bits of the backplane. They are converted to serial form within the FPGA and put out on the backplane. Some extra logic is provided to enable microprocessor control of an on board LED display. When chip select 2 and write data byte signals are low and make the transition to high, the data on the multiplexed address-data bus is clocked into flip flops. When a `0' value is clocked into the flip flop, the LED in question turns on. A `1' must be clocked to turn the LED off. The code for the FPGA is provided in Appendix D: VHDL Code. 3.10 Alarms An on-board LED display is available to indicate the status of four alarm conditions: RED Alarm, Alarm Indication Signal (AIS), Out Of Frame (OOF), and Remote Alarm Indication (RAI). The LED display is intended to be controlled by the microprocessor via communication with the FPGA, however the code for this has not been developed at this time. Table 15 shows the intended LEDs and their corresponding alarms.
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Table 15
LED Display LED 1 2 3 4 5 6 Alarm Condition RED Alarm Alarm Indication Signal Out Of Frame Remote Alarm Indication Spare Spare
3.10.1 EQUAD Alarms The EQUAD supports the detection of various alarm conditions such as loss of signal, loss of frame, loss of signaling multiframe, loss of CRC multiframe, reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and timeslot 16 alarm indication signal. The EQUAD detects and indicates the presence of remote alarm and AIS patterns, and also integrates Red and AIS alarms as per industry specifications. 3.10.2 TQUAD Alarms The TQUAD supports the detection of various alarm conditions such as Loss of Signal, Pulse Density Violation, Red Alarm, Yellow Alarm, and AIS alarm. The TQUAD detects the presence of Yellow and AIS patterns and integrates Yellow, Red and AIS alarms as per industry specifications. 3.10.3 Interrupts The only efficient way of processing events that may have a low frequency of occurrence is to use interrupt driven routines (instead of polling). The events (alarm conditions, timers, datalink servicing) on the TQUAD/EQUAD with QDSX reference design will, on average, be low frequency. When the host microprocessor detects an interrupt indication on its external interrupt input pin, it must determine the source of the interrupt. The microprocessor polls the TQUAD/EQUAD and the QDSX to determine the source of the interrupt. Then the appropriate device's registers must be polled to determine the event that caused the interrupt.
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Once the interrupt source has been determined, the microprocessor can jump to a routine specific to that interrupt. The code has not been developed for interrupt handling as of this document's release date.
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4 4.1
LAYOUT DESCRIPTIONS Component Placement The overall placement strategies of the components are: * * Place the analog circuitry away from the digital circuitry. Keep the transformers as close to the bantam connectors as possible. This will insure that the transformer suppresses the common-mode noise riding on the traces coming from the connectors before it can radiate.
The overall placement is as follows: Figure 12
Power
Main Component Placement Diagram
Chassis Ground Plane
Digital G round and Power Planes
FPGA
EQ UA D/ TQ U AD
Q DS X
EQUAD/TQ UAD with QDSX Reference Design 1998 PMC-SIERRA
In addition, the following rules are used: * Noise on an oscillator's power supply will cause jitter on the output, and therefore the oscillators are placed in a quiet digital section. The oscillator itself generates noise that may affect sensitive analog circuits. The oscillators will be placed along the top of the board near the power supply where there is
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Transform ers
Mini Bantam Connectors
O sc Y2
O sc Y1
96-pin Connector
Transform ers
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clean power and so that return currents are not running underneath any sensitive circuitry. * All source termination resistors are placed near the outputs and load termination resistors are placed near the inputs. There are only a few high speed lines on the board that require controlled impedance traces and terminations. All pull down resistors are placed near the output pins. All decoupling capacitors are placed near the power supply pins. The bulk decoupling capacitors are placed near the power entrance, specifically the upper left corner.
* *
4.2
Layer Stacking and Transmission Line Impedance Control The TQUAD/EQUAD Reference Design card has four layers: layers 1 and 4 for signals, layer 2 for ground, and layer 3 for power. The layer configurations are shown below: Figure 13 PCB Cross Section
w t
1 Oz Copper
dielectric r
Ground Plane
h1 h2 h3 t
dielectric r dielectric r
1 Oz Copper 1 Oz Copper
1 Oz Copper
Power Plane
t
where r = relative dielectric constant, nominally 5.0 for G -10 fibre - glass epoxy
t = thickness of the copper, fixed according to the weight of copper selected. For 1 oz copper, the thickness is 1.4 mil. This thickness can be ignored if w is great enough. h1, h2, h3 = thickness of dielectric. w = width of copper
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The PCB related parameters are shown in the following table:
Parameters Board Thickness (mil) dielectric thickness between layers 1 and 2 (mil) (h1) dielectric thickness between layers 2 and 3 (mil) (h2) dielectric thickness between layers 3 and 4 (mil) (h3) Relative dielectric constant Nominal 62 (including copper thickness) 10 33 10 4.2
To reduce signal degradation due to reflection and radiation, the traces that carry high speed signals should be treated as micro strip transmission lines with controlled impedance and matched resistive termination. The trace impedance is calculated using the formula: 87 ae 5.98 x h o x ln e Zo = r + 1.41 0.8 x w + t o
Parameter
r
h1 (mil) t (mil, 2 Oz copper) () W (mil)
Data 4.2 10 2.88 50 16
Given a characteristic impedance Zo, the dielectric thickness h1 is proportional to the trace width. A small h1 will result in the traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board for a given trace impedance and adequate trace width should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. For example, using the same dielectric thickness, copper trace thickness, and dielectric constant, a 16 mil trace has a characteristic impedance of approximately 50 Ohms while a 6 mil trace has a characteristic impedance of 75 Ohms. 4.3 Power and Ground A ground plane and power plane cover the entire board, except for the line interface area. The introduction of ground slots within the ground plane must be
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avoided as they will increase trace inductance and increase crosstalk. These slots can be accidentally created by making clear-out holes too large. The line interface area that connects the bantam connectors to the transformers has its own separate chassis ground plane. This chassis ground plane is formed on the same layer of the board as the main ground and power plane, except is separated from these planes in an entire section of the board, underneath the transformers. Signals will not cross from one ground plane to another, except across the transformers. This setup isolates the T1/E1 lines from the rest of the board. The placement of the digital ground and power planes, as well as the chassis ground plane, can be seen in Figure 12. 4.4 Routing * * * * All power and ground traces are as wide and short as possible to minimize trace inductance. All high speed traces are routed over continuous image planes (power or ground planes). All traces carrying transmit and receive line rate data should be routed on the same side and kept as short as possible. Both signals of a differential pair are of equal length and routed close to each other.
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5
REFERENCES
1. PMC-Sierra, PMC-910501, "PMC Device Evaluation Motherboard Engineering Document", May 1991, Issue 3 2. PMC-Sierra, PMC-950857, Data Book (Issue 4), "PM4314 QDSX Quadruple T1/E1 Line Interface Device" 3. PMC-Sierra, PMC-940910, Data Book (Issue 5), "PM4344 TQUAD Quadruple T1 Framer" 4. PMC-Sierra, PMC-951013, Data Book (Issue 4), "PM6344 EQUAD Quadruple E1 Framer"
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APPENDIX A: BILL OF MATERIALS NO. COMPONENT DESCRIPTION 1 2 3 4 5 6 7 8 9 49FCT805_SOIC-BASE 74HC04BLK_SOIC-BASE 74XXX00_SOIC-HCMOS 74XXX138_SOIC-HCMOS 74XXX139_SOIC-HCMOS 74XXX245_SOIC-HCMOS A1460-208 BANTAM-BASE Package Type REF DES SOIC20W SOIC14 SOIC14 SOIC16 SOIC16 SOIC20W PQFP208 BANTAM U6 U12 U11 U3 U4 U2 U1, U7 U9 J17-J24 Qty 1 1 1 1 1 1 2 1 8 1 4
74XXX541_SOIC-HCMOS, 74HC541 SOIC20W
10 CAPACITOR POL-10UF, 16V, TANT THE 11 CAPACITOR-0.001UF
SMDTANCAP_ C16 C SMDCAP805 C40-C42, C45
12 CAPACITOR-0.01UF, 50V, X7R_805 SMDCAP805 13 CAPACITOR-0.047UF, 50V, X7R_1206
C17-C33, C70, C73, 23 C75, C77, C79, C96 4
SMDCAP1206 C12-C15
14 CAPACITOR-0.1UF, 50V, X7R_1206 SMDCAP1206 C1-C7, C38, C39, 30 C43, C44, C46-C55, C61-C68, C93 15 CAPACITOR-0.47UF, 25V, TANT TEH SMDTANCAP_ C8-C11 A 16 CAPACITOR-0.68UF, 35V, TANT TEH SMDTANCAP_ C34-C37 B 17 CAPACITOR-1UF, 16V, TANT TEH 18 CAPACITOR-47UF, 10V, TANT TEH 19 DIN96_MALE-BASE SMDTANCAP_ C71, C72, C74, A C76, C78, C80 NEC_D C94 AMP_650473- P2 5 4 4 6 1 1
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20 DIPSW8-BASE 21 EQUAD-BASE 22 FUSE__SMD-3.000A, NANO 23 HEADER2_JUMPER-BASE 24 HEADER5_100 MIL-BASE 25 LC01_6_SOIC-BASE 26 LED-SUPER_GREEN, SURFACE MOUNT
DIP16 PQFP128 NANO_SMF JUMPER2 SIP5 SOIC16WB LED_11
SW1 U8 F1 J2 J1 U10, U14-U20 D1-D7 Y2 Y1 P1 U5 R37-R43, R49 R10, R12-R14 R9, R15-R17 R3-R6 R69
1 1 1 1 1 8 7 1 1 1 1 8 4 4 4 1
27 OSC_TTL_DIP-2.048MHZ , 50 PPM, CRYS14 CHA 28 OSC_TTL_DIP-49.152MH Z, 32/50 PPA 29 PWRBLOCK_2-BASE 30 QDSX-BASE 31 RESISTOR-100, 5%, 805 32 RESISTOR-10K, 5%, 805 33 RESISTOR-121, 1%, 805 34 RESISTOR-2.7, 5%, 805 35 RESISTOR-316K, 1%, 805 36 RESISTOR-330, 5%, 805 37 RESISTOR-357, 1%, 805 38 RESISTOR-4.7K, 5%, 805 39 RESISTOR-47, 5%, 805 40 RESISTOR-49.9, 1%, 805 CRYS14 CONN2END PQFP128 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805
R1, R44, R53, R70 4
R21, R22, R24, R26 4 R2, R18, R73, R74 4 R11, R30, R32, R34 4 R7, R8, R19, R20, 12 R23, R25, R27-R29, R31, R33, R64 R35, R36, R45-R48, 25 R50-52, R54-63, R63-68, R71, R72 RN1, RN2 2
41 RESISTOR-75, 1%, 805
SMDRES805
42 RES_ARRAY_15_SMD-10K
SOIC16
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43 RES_ARRAY_8_SMD-10K 44 RES_ARRAY_8_SMD-330 45 RES_ARRAY_8_SMD-4.7K 46 SBRIDGE2 47 SRDA3_3_4 48 T1008-BASE 49 THERMISTOR 50 TST_PT-BASE 51 TST_PT-BASE 52 TST_PT-BASE 53 ZENERDIODE-6.2V_1W
SOIC16 SOIC16 SOIC16 ? SOIC8 YB32 SMDRES805 TST_PT_1 TST_PT_1 TST_PT_1 MLL41
RN3 RN5 RN4 SB1, SB2 U21-U24 T1, T2 TR1-TR16 TP1-TP6 TP21 TP22 D8
1 1 1 2 4 2 16 6 1 1 1
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APPENDIX B: SCHEMATICS
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APPENDIX C: LAYOUT
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APPENDIX D: VHDL CODE
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APPENDIX E: LAYOUT ERROR NOTE: The footprint for parts U10, U14-20 (SEMTECH LC01-6) are too narrow on the PCB. These parts are used for line protection again power surges, and were omitting on the boards built for this reference design.
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PMC-980328 (R1) ref PMC-951013 (R5) Issue date: October 1998
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PMC-980328 (R1) ref PMC-951013 (R5) Issue date: October 1998
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Price & Availability of 1980328

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