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| REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PMC-Sierra, Inc. PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH PM3350 ELAN 8x10 24-Port Ethernet Switch Reference Design PROPRIETARY AND CONFIDENTIAL Released Issue 1: April, 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PMC-Sierra, Inc. PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH CONTENTS REFERENCES ....................................................................................................... ii OVERVIEW ........................................................................................................... 1 FUNCTIONAL DESCRIPTION ............................................................................. 21 Feature List ....................................................................................................2 PM3350 Elan 8x10 .........................................................................................4 IMPLEMENTATION DESCRIPTION ..................................................................... 6 10M Ethernet Switch Circuitry ........................................................................7 Common Components ...................................................................................8 Other Board Components ............................................................................10 Configuration Resistors ................................................................................12 Configuration Resistor Functions .................................................................14 INTERFACE DESCRIPTION............................................................................... 17 RJ45 Pin Definition.......................................................................................17 PCI Expansion Bus Interface .......................................................................18 APPENDIX A: DESIGN CONSIDERATIONS ..................................................... 20 Power Supply Decoupling ............................................................................20 Unused CMOS Inputs ..................................................................................20 EMI Considerations ......................................................................................20 PCI Considerations .....................................................................................21 Component Selection ...................................................................................23 APPENDIX B: BILL OF MATERIALS .................................................................. 25 CONTACTING PMC-SIERRA ............................................................................. 28 ATTACHMENT I: SCHEMATICS 1 Refer to the System Configuration to determine the number of MAC addresses supported by the firmware programmed into the EPROM. The system can be configured to support up to 32k MAC addresses. See the PM3350 datasheet. PMC-Sierra, Inc. CONFIDENTIAL i REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PMC-Sierra, Inc. PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH REFERENCES * * * PMC-Sierra PM3350 Datasheet, Issue 1 (1997) ISO/IEEE 8802.3 CSMA/CD Local Area Networking Specification (1993) Level One Communications, Data Book (1996), "Ethernet PHY Products" PMC-Sierra, Inc. CONFIDENTIAL ii PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH OVERVIEW This document describes an implementation of a 24-port Ethernet Switch design based on PMC-Sierra's PM3350 Elan 8x10. This design, called the 24-port Elan 8x10 Reference Design, embodies PMC-Sierra's guidelines and suggestions for designing an Ethernet switch. This reference design is intended to operate in two modes: 1) Stand-alone mode, where this board provides the complete functionality of a 24-port Ethernet Switch, and 2) This board can interface with other boards, such as the 2-port Fast Ethernet Switch reference design, through the PCI expansion backplane. In addition to the three PM3350 Elan 8x10 devices (each supporting 8 ports), the PM3350 Reference Design incorporates on-board DRAM, EPROM, oscillators, 10BaseT PHY chips (Level One LXT944), 10BaseT magnetics, RJ-45 jacks, status LEDs and other miscellaneous devices to complete the switch design. A complete list of components can be found in the Bill of Materials. The Functional Description gives a list of key features of this reference design. The Implementation Description provides a detailed description of all the major components which are found in the schematics (included as Attachment I). The Interface Description lists the RJ45 and the PCI expansion bus pin definitions. For readers who are interested more additional in-depth considerations for this reference design, the Design Consideration section provides many tips and guidelines on high-speed circuit board design and component selection. Finally, a Bill of Materials and the schematics are included at the end. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH FUNCTIONAL DESCRIPTION The block diagram of this reference design is shown in Figure 1. The following is a summary of the features offered in this switch. Feature List * * Complete 24-port 10BASE-T non-blocking switching Operates i) as a completely stand-alone switch, or ii) in conjunction with other switch cards using the PCI expansion bus, such as the 2-port Fast Ethernet Switch reference design, to create larger switch systems Supports a peak system bandwidth of 1 Gbit per sec (600 Mbit/s sustained) using the PCI expansion bus Filters and switches packets using a locally-maintained database Performs packet switching, IEEE 802.1d compliant transparent bridging, or both Store-and-forward mode with full CRC check. * * * * PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Fig. 1 Reference Design System Block Diagram PCI Bus Edge Connector Bus Arbiter PCI Expansion EPROM Bus System Clocks PMC ELAN 8x10 DRAM DRAM PMC ELAN 8x10 DRAM DRAM PMC ELAN 8x10 DRAM DRAM PM3350 LXT944 Quad PHY LXT944 Quad PHY PM3350 LXT944 Quad PHY LXT944 Quad PHY PM3350 LXT944 Quad PHY LXT944 Quad PHY Magnetics Status LEDs Magnetics Magnetics Magnetics Magnetics Magnetics RJ45 RJ45 RJ45 RJ45 RJ45 RJ45 Port 1-4 Port 5-8 Port 9 - 12 Port 13 - 16 Port 17 - 20 Port 21 - 24 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Fig. 2 Block Diagram FIFO FIFO FIFO 10BaseT MAC 10BaseT MAC 10BaseT MAC 10BaseT MAC 10BaseT MAC 10BaseT MAC 10BaseT MAC Quad Ethernet Interface Adapter Quad Ethernet Interface Adapter 50 MHz Embedded Processor I Cache PCI Expansion Bus D Cache FIFO 10BaseT MAC 10BaseT 10BaseT 10BaseT 10BaseT 10BaseT 10BaseT 10BaseT 10BaseT PCI Bus Interface Multi-Channel DMA Controller FIFO FIFO FIFO FIFO Expansion Registers External Memory Interface EDO DRAM / EPROM PM3350 Elan 8x10 The PM3350 is a highly integrated stand-alone single-chip switching device for Ethernet/IEEE 802.3 switching and bridging applications. The device supports all processing required for switching Ethernet/IEEE 802.3 packets between eight independent half-duplex 10 Mbit/s ports. In addition, a switch built around the Elan 8x10 can be expanded by connecting up to 7 additional devices to the on-chip 1 Gbit/s expansion port, a system clock oscillator for the bus and a simple PAL for bus arbitration. Switch configuration and management can be performed either remotely (inband), via the on-chip SNMP MIB, agent and integrated TCP/UDP/IP stack. The Elan 8x10 chip contains all the required elements of a high-performance Ethernet switch: MAC-layer interfaces, buffer FIFOs, a high-speed DMA engine for fast packet transfers, a local memory interface for up to 16 MB of external buffer memory, a PCI compatible bus master and slave unit for modular expansion, and a powerful switch processing unit that implements the switching and bridging functions. The only additional components required to create a complete 8-port switch are two quad Ethernet Medium Access Unit (MAU) devices, line transformers and a bank of external memory. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH The Elan 8x10 device is implemented in high-density CMOS technology for low cost and high performance. It is available in a 256 ball grid array (BGA) package, and is ideally suited for compact, low-cost desktop, workgroup and departmental Ethernet switching applications. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH IMPLEMENTATION DESCRIPTION The schematic diagram of the 24-Port Elan 8x10 Reference Design is contained in Attachment I. Page 1 of the schematics shows the main functional blocks. The core functionality consists of three identical2 "ports" or "slices" of 10M Ethernet circuitry, each using a PM3350, DRAM memory, and physical interface components (PHY, transceiver, magnetics, etc.) Additionally, the board contains an EPROM for code download, PCI Arbiter, connectors, timing sources and miscellaneous "glue" circuitry. Functional blocks are described below. All of the major components are described for one slice of the 10M Ethernet circuitry. The same description apply to all two slices: * * * Slice (Port) 1- 8: Slice (Port) 9 - 16: Slice (Port) 17 - 24: Sheets 3 - 6 Sheets 7 - 10 Sheets 11 - 14 The components ID's are listed in parenthesis after each component name. 2Identical except for the EPROM which only PM3350 #0 is connected to. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH 10M Ethernet Switch Circuitry PM3350 (U23, U24, U28) [Sheet 3,7,11] Three PM3350 8-port Ethernet switch chips form the core of the 24-port Reference Design. EEPROM (U15) [Sheet 4] One 256K by 8-bit, 150ns 3 EPROM is included. A smaller EPROM (128K x 8-bit) can be used if an unmanaged version of the firmware is used. The board is designed to accommodate a larger EPROM (512K x 8-bit) should it be needed for more software features. The EPROM is used for the PM3350 boot code, switching code, SNMP code (when available), and any special function code (e.g., custom LED display, aging, backpressure, VLAN, etc.). Code is downloaded into the first PM3350 device (U23), which in turn will download the code to the other PM3350 devices in a daisy-chain fashion through the PCI bus. This device has a socket for ease of replacement. DRAM (U14/U17&U13/U16, U21/U22, U27/U29) [Sheet 4,8,12] Two, 256K by 16-bit, 60ns EDO DRAM chips (one MByte total) are used to provide RAM storage for each PM3350. The DRAM is used for MAC address tables, packet buffer storage, and for data structures required during operation. An additional bank of memory is installed in locations U13 and U16 to support managed versions of the switch. Physical Layer Interfaces (U4&U2, U8&U6, U12&U10) [Sheet 5&6, 9&10, 13&14] 3150ns is the closest to the 180ns specified in the ED datasheet. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Six Level One LXT944 devices are used to provide the physical interface for 10BASE-T Ethernet systems. Please refer to a current issue of the Level One Communications Databook for information describing this quad Ethernet physical layer interface device. Line Interface Circuitry (Transformers: U3&U1, U7&U5, U11&U9) [Sheet 5&6, 9&10, 13&14] The line interface circuitry consists of the transformers (four quad magnetics/filter components), and passive networks necessary to interface the LXT944 device to the RJ-45 connectors, and onto UTP5 cables carrying Ethernet 10 BaseT signals. This circuitry reflects recommendations in the Level One data book. Common Components Timing Distribution [Sheet 2] (Y2) - The high-speed timing to the PM3350 devices is sourced from a 50MHz crystal oscillator. (Y1) - The high-speed timing to the PCI bus is sourced from a 40MHz crystal oscillator. PCI Bus Connector (P1) [Sheet 2] There is one edge connector on the board that is connected to the onboard PCI bus expansion port backplane. It is used to interface this board to other reference designs such as the 2-port Fast Ethernet Switch using PM3351. When this reference design is operating in the stand-alone mode, this edge connector is not used. Please refer to the Interface Description section for the pin definitions. Note that this PCI connection is not compliant to the PCI specification, v2.1. This is because of 1) the pin redefinition required for PCI arbitration (see the PCI Arbiter description), and 2) the fact that there are more than one "PCI device load" on a single board attached to the bus. PCI Arbiter (U18) [Sheet 2] The 24-port Reference Design board has one Arbiter CPLD that implements a simple arbiter required by the PCI bus expansion port. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH The PCI Arbiter implements a simple round-robin algorithm to control bus access by the PM3350 devices onto the PCI expansion bus. This arbiter is implemented in a 44PLCC CPLD (e.g. Xilinx XC9572-7-PC44). Please contact PMC-Sierra, Ethernet Division, for information on the implementation of the arbiter. This arbiter assumes sole control on the PCI expansion bus when this reference design board is interfaced to the 2-port Fast Ethernet Switch reference design. Because of this, bus request/grant signals of the PM3351 devices have to be routed through the PCI bus backplane onto this reference design, which is accomplished by re-defining some of the unused pins on the PCI connector. This device has a socket for ease of replacement. When two ELAN Reference Design boards are interfaced the 2-port Fast Ethernet Switch reference design board should have its U43 removed. Reset Debounce (U31) [Sheet 3] The Dallas DS1233 "EconoReset" device is used to provide power-up reset and the reset debounce function. It monitors the status of the power supply (Vcc) and will automatically assert the reset when a threshold is crossed. Reset is maintained active for a minimum time of 350ms. Resistors and Jumpers Three configurations of resistors and jumpers are provided below. Master 24x10 stand alone Open JP3 Open JP6 Open JP9 Open JP12 Install JP8 Open JP1 Install JP2 Install JP5 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Install JP10 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Slave 24x10 with master 24x10 Install Jumper JP3-1 to JP3-2 Install Jumper JP3-3 to JP3-4 Install Jumper JP3-5 to JP3-6 Install Jumper JP6-1 to JP6-2 Install Jumper JP6-3 to JP6-4 Install Jumper JP6-5 to JP6-6 Install Jumper JP9 Install JP12 Install JP8 Install JP1 Install JP2 Install JP5 Install JP10 Remove resistor R83 and replace at R326 Remove resistor R92 and replace at R333 Remove resistor R107 and replace at R378 Remove resistor R272 at top and replace R272 at bottom Remove R307 at top and replace R307 at bottom Remove R317 at bottom and replace R317 at top Remove R314 at bottom and replace R314 at top Remove R370 at top and replace R370 at bottom Remove R366 at bottom and replace R366 at top Remove R99 at bottom and replace R99 at top Remove R98 at top and replace R98 at bottom PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Master 24x100 with slave 2x100 or slave 24x10 Open JP3 Open JP6 Install JP9 Install JP12 Install JP8 Open JP1 Install JP2 Install JP5 Install JP10 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH (JP3) [Sheet 2]: This header designates the PCI signals for REQ that will come from the three PMC3350 devices in route to the arbiter (U1). All jumper positions are normally open and can only be used after the arbiter has been removed. In a 48-port switch Reference Design (or with the 2x100 Reference Design) this secondary board must have jumpers across positions 1-2, 3-4, and 5-6. (JP6) [Sheet 2]: This header designates the PCI signals for GNT that will go to the three PMC3350 devices from the arbiter (U1). All jumper positions are normally open and can only be used after the arbiter has been removed. In a 48-port switch reference design (or with the 2x100 Reference Design) this secondary board must have jumpers across positions 1-2, 3-4, and 5-6 (JP9) [Sheet 2]: This header with the use of a jumper determines the source of the PCI clock. The clock may be sourced from the on-board oscillator (U2) or it may be provided from the PCI bus edge connector. In normal operation it is provided by the on-board clock with the jumper installed (JP4/7/11) [Sheet 3]: These headers are reserved for future use and should not be used. (JP8) [Sheet 3]: This header with the use of a jumper determines the source of the system Reset signal. The Reset is sourced from the on-board switch (S1) only or it may be provided from the PM3350. In normal operation it is provided by the PM3350 with the jumper installed. (JP12) [Sheet 2]: This header with the use of a jumper determines that the reset signal goes out to the PCI bus when installed. (S1) [Sheet 2]: This switch is a master reset for the Reference Design board. Other Board Components RJ-45 Connectors (J1, J2, J3) [Sheet 6,10,14] There are 24 RJ-45 connectors (3 blocks of eight) for connection of Ethernet 10 BaseT segments to the switch. They are configured as a "hub" connection. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH LEDs (D3, D2, D5, D4, D7, D6) [Sheet 5,6,9,10,13,14] There is 1 LED per port, arranged vertically in groups of four. Each LED is a link light corresponding to a port. Power Supply Connections This Reference Design board requires a 5.0V +/- 5% power supply capable of providing a minimum of 4.0 Amps. The regulator U30 provides 3.3V to an island within the 5V power plane. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Configuration Resistors Each "slice" of 10M port circuitry uses a bank of resistors to configure the PM3350 after reset. Resistors, not dip switches, are used to lower the cost. The resistor functions and default values are given below. Function PCIRUN RISCRUN Reserved IMDIS PCI3V Reserved CHIPID [3] CHIPID [2] CHIPID [1] CHIPID [0] RTCDIV [5] RTCDIV [4] RTCDIV [3] RTCDIV [2] RTCDIV [1] RTCDIV [0] MXSEL[1] MXSEL[0] MSLO MDCAS MTYPE3 [2] MTYPE3 [1] MTYPE3 [0] MTYPE2 [2] MTYPE2 [1] MTYPE2 [0] MTYPE1 [2] MTYPE1 [1] MTYPE1 [0] MTYPE0 [2] MTYPE0 [1] MTYPE0 [0] PM3350 0 R264 JP1 R270 R273 R274 JP2 R260 R259 R60 R272 R64 R239 R232 R63 R236 R62 R231 R235 R241 R234 R237 R243 R65 R240 R261 R263 R266 R269 R271 R268 R265 R262 Value 1 open 0 0 0 Installed 0 1 1 0 1 1 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 PM3350 1 R304 R305 R306 R308 R309 JP5 R307 R317 R319 R314 R312 R311 R310 R73 R282 R285 R276 R279 R277 R280 R74 R313 R75 R283 R288 R286 R289 R278 R281 R284 R287 R290 Value 1 0 0 0 0 Installed 0 1 1 1 1 1 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 PM3350 2 R361 R364 R368 R369 R371 JP10 R370 R366 R99 R98 R346 R344 R96 R97 R345 R95 R381 R380 R382 R383 R384 R387 R385 R386 R367 R112 R365 R111 R363 R110 R360 R109 Value 1 0 0 0 0 Installed 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Notes 1) The top row (PCIRUN) correspond to D31, the MSB of the memory data bus 2) RISCRUN of Bank 0 is set to 1, since the EPROM is connected to the ED in this bank. Note: Looking at the top side (component side) of the board, if the board is placed such that the PM3350 devices is at the bottom and with the RJ45 connectors on the top, then the resistor placement is defined as: Top Bottom = Pull-up (High) = Pull-down (Low) PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Configuration Resistor Functions The Configuration Resistors provide the default pull-up/down values on the memory databus, which are read by the PM3350 after reset. 4.7K resistors are used for them. The CHIPID have a custom 3-pin 0805 footprint (one pin for pull-up, one for the signal, one for the pull-down). WARNING: Modifying these resistors may prevent the reference design board from working. Please refer to the PM3350 datasheet for detailed description of these functions. PCIRUN Configuration PCIRUN: This line determines whether the PM3350 runs in master or slave mode. RISCRUN Configuration RISCRUN: This line controls whether the chip runs or halts after reset. IMDIS Configuration IMDIS: Internal memory disable, which controls the bootcode fetch location. High = boot strapped from the external local memory, Low = boot strapped from on-chip ROM. PCI3V Configuration PCI3V: This selects the PCI interface signaling environment. High = 3.3V, Low = 5V. CHIPID Configuration CHIPID: These 4-bits determine the chip's PCI address. This is used to set the second nibble (bits 24 - 27) of the PM3350's address space on the PCI bus. The top nibble (bits 28 - 31) are initialized to zero (0), but can be set by software control if required. The CHIPID's of the 4 banks are set to 6, 7, 8 by default respectively, so as to distinguish them from the CHIPID's of the 4 FED devices on the 4-port Fast Ethernet Switch reference design. 0 and 1 are reserved for other PCI devices that may be connected to the PCI expansion bus. RTCDIV Configuration RTCDIV: These 6-bits determine the setting for the Real-Time Clock Divisor. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH MXSEL Configuration MXSEL: These resistors set the DRAM Row / Column multiplexing MXSEL 00 01 10 11 Column Address Bits 8 9 10 11 DRAM Configurations Supported 64k x N & 128k x N 256k x N & 512k x N 1 Meg x N & 2 Meg x N 4 Meg x N & 8 Meg x N (Note: at the time of this design suitable 64xN and 128xN are difficult to purchase in the market.) MSLO Configuration MSLO: This resistor selects the expected access time of the DRAM. If MSLO is high, 80ns DRAM is expected. If MSLO is low, 60ns DRAM is expected. MDCAS Configuration MDCAS: This resistor selects the type of DRAM used. If MDCAS is high, the memory interface will generate control signals for 2-CAS DRAM's.. If MDCAS is low, it generates signals for single CAS DRAM's. This reference design uses two CAS DRAM's. MTYPE Configuration These twelve resistors per PM3350 are divided into four groups of three bits each. Each bit combination selects one of eight different memory types. These bits are read off the data bus during start-up, and tell the RISC how to access memory. Each group corresponds to one of the four banks of memory. On the Reference Design Board: * * * * Bank 0 is set up to be EDO DRAM, Bank 1 is available on U23. Other PM3350 this bank is unused. Bank 2 is set up as EPROM, Bank 3 is only used on the PM3350 for status LEDS during debug. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH MTYPE 000 001 010 011 100 101 110 111 Memory Type Reserved Reserved Reserved Reserved Reserved EPROM EDO DRAM Reserved Speed N/A N/A N/A N/A N/A 180 nsec 60/80 nsec N/A Two 256K x 16-bit 60ns EDO DRAM's are used for each PM3350 device in this reference design. An additional two 256K x 16-bit 60ns EDO DRAMs are used by the master PM3350 device to support managed versions of the operating firmware. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH INTERFACE DESCRIPTION This section is a detailed description the physical interfaces in this reference design, which include 1) the RJ45 connectors, and 2) the PCI Expansion Bus connector. RJ45 Pin Definition Each of the 24 RJ45 connectors on the reference design have the following pin definition. Signal Name TX+ TX RX + RX Pin 3 6 2 1 I Receive Pair on UTP5 Cable. Type O Description Transmit Pair on UTP5 Cable. The pins are defined such that the port looks like a hub port. This allows a direct cable connection from the switch port to a computer. A crossover cable is needed to connect the switch port to another switch port. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH PCI Expansion Bus Interface Signal Name AD[31:0] Pin B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 B53 A54 B55 A55 B56 A57 A59 B58 B26 B33 B44 A52 A43 Type I/O Description Multiplexed PCI address/data bus, used by the PCI host or the PM3350 to transfer addresses or data. CBE[3:0] I/O Command/Byte-Enable lines. These lines supply a command (during PCI address phases) or byte enables (during data phases) for each bus transaction. PAR I/O Address/data/command parity, supplies the even parity computed over the AD[31:0] and CBE[3:0] lines during valid data phases; it is sampled (when the PM3350 is acting as a target) or driven (when the PM3350 acts as an initiator) one clock edge after the respective data phase. Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this signal indicates that a new transaction is beginning (with an address phase); a LOW-to-HIGH transition indicates that the next valid data phase will end the currently ongoing transaction. FRAME* A34 I/O PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE B35 I/O PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH IRDY* Transaction Initiator (master) ready, used by the transaction initiator or bus master to indicate that it is ready for a data transfer. A valid data phase ends with data transfer when both IRDY* and TRDY* are sampled asserted on the same clock edge. Transaction Target ready, used by the transaction target or bus slave to indicate that it is ready for a data transfer. A valid data phase ends with data transfer when both IRDY* and TRDY* are sampled asserted on the same clock edge. Transaction termination request, driven by the current target or slave to abort, disconnect or retry the current transfer. Device acknowledge: driven by a target to indicate to the initiator that the address placed on the AD[31:0] lines (together with the command on the CBE[3:0] lines) has been decoded and accepted as a valid reference to the target's address space. Once asserted, it is held asserted until FRAME* is deasserted; otherwise, it indicates (in conjunction with STOP* and TRDY*) a target-abort. Device identification (slot) select. Assertion of IDSEL signals the PM3350 that it is being selected for a configuration space access. Bus requests (to bus arbiter). They are used only when external ED/FED devices are connected on the PCI bus. They are asserted by the external devices to request control of the PCI bus. It is intended that a PCI arbiter the PM3350 board have control of bus arbitration. PCI 2.1 specification defines only one Bus Request signal. In this case, these extra Bus Request signals occupy the following unused pins on the PCI connector: B1: -12V (REQ7*), A1: TRST* (REQ6*), A3: TMS (REQ5), A2: +12V (REQ4*), B2: TCK (REQ3*) Bus grant (from bus arbiter). They are used only when external ED/FED devices are connected on the PCI bus. This indicates to the external device that it has been granted control of the PCI bus. It is intended that a PCI arbiter on the PM3350 board have control of bus arbitration. PCI 2.1 specification defines only one Bus Grant signal. In this case, these extra Bus Grant signals occupy the following unused pins on the PCI connector: B7: INTB* (GNT7*), A7: INTC* (GNT6*), B8: INTD* (GNT5*), B10: Reserved(GNT4), A9: Reserved (GNT3*) Interrupt request. This pin signals an interrupt request to the PCI host. Bus parity error signal, asserted by the PM3350 as a bus slave, or sampled by the PM3350 as a bus master, to indicate a parity error on the AD[31:0] and CBE[3:0] lines. System error, used by the PM3350 to indicate to the PCI central resource that there was a parity error on the AD[31:0] and CBE[3:0] lines during an address phase. PCI bus clock; supplies the PCI bus clock signal to the PM3350. PCI bus reset (system reset). Performs a hardware reset of the PM3350 and associated peripherals when asserted. TRDY* A36 I/O STOP* DEVSEL* A38 B37 I/O I/O IDSEL REQ* REQ7* REQ6* REQ5* REQ4* REQ3* GNT* GNT7* GNT6* GNT5* GNT4* GNT3* INTA* PERR* A26 B18 B1 A1 A3 A2 B2 I I A17 B7 A7 B8 B10 A9 A6 B40 O O I/O SERR* B42 OD PCICLK RST* B16 A15 I I Notes: 1) The '*' indicates active-low signals, which corresponds to '#' used in the PCI specification. 2) Pin numbers are listed MSB first PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH APPENDIX A: DESIGN CONSIDERATIONS For those who are interested more additional in-depth considerations for this reference design, this Design Consideration section provides many tips and guidelines on highspeed circuit board design and component selection. Power Supply Decoupling A 0.01uF or 0.1uF decoupling capacitor is also placed as close to each power pin as possible. If noise attenuation is required, a small surface mount series resistor (1 to 10 Ohms) can be added in series with the power pin. Unused CMOS Inputs "Floating" CMOS inputs (those that are left unconnected) may switch unpredictably, causing unwanted noise and power consumption. Therefore, all unused inputs should be connected to their inactive state: to ground or to the power rail (Vcc). Unused bidirectionals should be "pulled" through a series resistor (4.7k or greater) to avoid shortcircuits occurring if the bi-directionals are erroneously configured as outputs. EMI Considerations EMI can be reduced via proper routing, decoupling, power and ground distribution, shielding, and filtering. Most of the items listed below for EMI improvement also lend themselves towards improving system level performance. Routing Guidelines Proper decoupling and termination are effective ways of reducing EMI. The following are some routing guidelines which will help reduce EMI: * * Data lines should be kept away from the clock signals to avoid noise coupling. No high speed signals should be routed near the vicinity of the RJ45 modular jack and the transformer in order to prevent common-mode noise coupling onto the cable. Footprints of capacitors can be placed along signals with fast rise and fall times. In the event that fast edges causes excessive EMI, they can be slowed down (if timing and system level performance are not compromised) using these capacitors. * PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH Power and Ground Planes * * * The power plane should be kept away from the RJ45 modular jack and the transformer to prevent noise coupling. Ensure that power and ground planes of different sections do not overlap in order to prevent noise coupling. Provide a chassis ground plane under the RJ45 modular jack. PCI Considerations The following are PCI specification guidelines for trace lengths. These are not absolute constraints, but good to work toward for proper signal integrity and bus throughput. * Use 0.25 inches for power traces (assuming 20 mil power traces). * The maximum trace lengths for all 32-bit interface signals are limited to 1.5 inches from the top of the card edge connector to the PCI device. * The maximum trace lengths for the PCI CLK signal is limited to 2.5 inches from the top of the card edge connector to the PCI device. (+/- 0.1 inches) The following highlights the way signal traces will be routed to follow the PCI specification 2.1. * First choose to route over either the 5v plane or the 3.3v plane * If a trace would have to cross over 5v and 3.3v islands then route the trace on the secondary side with a reference to the ground plane. * If this is not possible then decouple the 5v to the 3.3v with a 0.01 microFarad cap. The capacitor will be placed within 0.25 inches from the point the signal crosses the split. One capacitor for each four PCI signal lines will be used. PCI Signal Trace Width * Characteristic impedance for signal traces is designated in the PCI Specification to be between 60 and 100 Ohms (Zo). PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH * The following approximation formula may be used for four layer boards (EQ1): 87 5.98 x h x ln Er + 1.41 0.8 + t Er is the dielectric permittivity h is the dielectric thickness between the trace and the next plane down. t is the copper thickness determined by the weight. (2oz ~ 2.88 mil) w is the trace width Z0 = Here is an example that uses 1-oz copper. Given: Zo = 72 Er = 4.6 h = 0.010 inches (10 mil) t = 0.00144 inches (1.44 mil) Results: w ~ 8 mil trace width * The following approximation formula may be used for traces on inner layers between two power planes: (EQ2): Z0 = 60 1.9 x b x ln Er 0.8 x w + t Er is the dielectric permittivity b is the separation between grounds t is the copper thickness determined by the weight. (2oz ~ 2.88 mil) w is the trace width Board Dielectric Permittivity * The estimation of the dielectric relative permittivity leads to a range of 3.13 to 5.0 when traces are on the inner or outer layers. (Estimate based on propagation delay.) The FR-4 material used in this design uses a value of 4.6. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH 24 Port Switch PCB Parameters * This reference design uses an eight layer Printed Circuit Board with 8 mil traces and 7 mil spacing. The power routes use 20 mil trace width. Trace apertures were changed during board fabrication in some cases. The following table gives the parameters chosen during PCB fabrication. Layer Thickness Copper Thickness Finishing Trace Width 7 mils 6 mils 5 mils NA 5 mils 6 mils 7 mils Impedance Estimate Between Layers 1-2 (prepreg) 2-3 (core) 3-4 (prepreg) 4-5 (core) 5-6 (prepreg) 6-7 (core) 7-8 (prepreg) 5 mils 5 mils 6 mils 30 mils 6 mils 5 mils 5 mils Finishes at 2 mils 1.44 mils 1.44 mils 1.44 mils 1.44 mils 1.44 mils Finishes at 2 mils 89 Ohms (EQ1) 83 Ohms (EQ1) 67 Ohms (EQ1) NA 67 Ohms (EQ1) 83 Ohms (EQ1) 89 Ohms (EQ1) Component Selection RJ45 Connector 8-pin 8 position octal RJ45 modular jacks are used in this reference design. In general, there are three types of modular jacks: * * * non-filtered and non-shielded shielded and non-filtered shielded and filtered (capacitive filtering or inductive filtering) Shielding is recommended for EMI considerations. In order for the shielding to be effective, the shield should be electrically connected to the chassis ground via a low impedance connection (i.e. using copper finger stocks or firm mechanical contact with the mounting bracket). Typically, the shielded portion of the jack will extend through the opening in the mounting bracket and make firm mechanical contact with the bracket on all sides. PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH The following vendors carry RJ45 connectors: * * * * Stewart Connectors AMP Kycon Power Dynamics Tel: 717-235-7512 Tel: 800-522-6752 Tel: 800-544-6941 Tel: 201-736-5722 Transformer The transformer used in this reference design is Halo T646-1406NX, a quadtransformer with filtering. Single transformers can also be used if it is more costeffective. The following vendors also carries 10-BASE-T transformers (they are not necessarily footprint compatible): * * * Valor Pulse Engineering Microlinear Tel: 800-318-2567 Tel: 619-674-8100 Tel: 408-433-5200 Oscillator The on-board oscillators provide a timing reference for the PM3350 device, the Level One LXT944, and the PCI bus interface. The oscillator should be +/-100ppm or better. The stability figure of an oscillator should include any variation due to calibration, temperature, voltage, load, aging, shock, and vibration, and is specified over the lift time of the oscillator. Either CMOS or TTL oscillator can be used. The following is a list of vendors that provide these oscillators: * * * * * Motron Industries Connor Winfield Champion Oak Frequency Control Group Ecliptek Tel: 605-665-9321 Tel: 708-851-4722 Tel: 708-451-1000 Tel: 717-486-3411 Tel: 714-433-1200 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH APPENDIX B: BILL OF MATERIALS This table lists the components used in this reference design. Note that compatible components can be substituted, but this is not guaranteed. Please refer to the Component Selection section in Appendix A for suggestions on alternative sources for some of the major components. PM3350 24 Port Reference Design Schematic - Top 16, 1997 TBD Revision: 1.1 Bill Of Materials November 5, 1997 Revised: Thursday, October 12:21:02 Page1 Item Quantity Reference Part PCB Footprint ______________________________________________________________________________ 1 2 18 140 C1, C4, C19, C25, C27, C30, C32, C39, C40, C41, C42, C44, C47, C48, C50, C51, C57, C59 C2, C3, C7, C8, C10, C11, C12, C13, C15, C16, C17, C21, C22, C29, C31, C33, C34, C36, C38, C46, C49, C53, C54, C55, C56, C60, C62, C66, C68, C69, C70, C72, C73, C74, C79, C81, C82, C83, C84, C86, C87, C89, C92, C93, C96, C101, C102, C103, C104, C106, C110, C112, C113, C114, C116, C117, C119, C123, C125, C126, C127, C128, C130, C131, C133, C137, C138, C139, C141, C145, C146, C147, C149, C150, C151, C152, C153, C154, C155, C158, C159, C160, C161, C162, C163, C166, C167, C168, C169, C170, C171, C172, C173, C174, C176, C180, C181, C182, C183, C184, C186, C187, C188, C189, C190, C193, C194, C195, C197, C199, C201, C202, C203, C206, C208, C209, C210, C211, C212, C214, C215, C216, C217, C219, C220, C221, C222, C223, C224, C225, C227, C229, C230, C231, C236, C237, C238, C241, C244, C246 C5, C18, C20, C23, C24, C26, C28, C35, C37, C43, C45, C52, C67, C71, C80, C85, C88, C94, C95, C100, C105, C111, C115, C118, C124, C129, C132, C140, C144, C148, C156, C157, C164, C165, C175, C177, C178, C179, C185, C191, C192, C196, C198, C200, C204, C205, C207, C213, C218, C226, C228, C232, C233, C234, C235, C239, C240, C242, C243, C245 C6, C14 22UF .1uF SC/C SC0805 3 60 .01uF SC0805 4 2 33uF SC/C PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH 5 6 7 1 1 24 C9 C58 C61, C63, C64, C65, C75, C76, C77, C78, C90, C91, C97, C98, C99, C107, C108, C109, C120, C121, C122, C134, C135, C136, C142, C143 D2, D3, D4, D5, D6, D7 D26 JK1 JK2 JP1, JP2, JP5, JP10, JP12, JP8, JP9 JP3, JP6 J1, J2, J3 R1, R2, R6, R7, R13, R14, R19, R20, R25, R26, R34, R35, R124, R125, R134, R146, R153, R154, R169, R170, R190, R191, R199, R200 R5, R8, R9, R15, R16, R17, R18, R21, R27, R29, R30, R33, R36, R37, R41, R42, R53, R60, R98, R99, R155, R259, R260, R272, R307, R314, R317, R319, R366, R370 R44, R45, R46, R47, R48, R49, R50, R51, R52, R54, R55, R56, R57, R58, R117, R118, R119, R120, R121, R122, R138, R205, R206, R207, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R233, R238, R242, R244, R248, R251, R255, R257 R59, R61, R94, R108, R114, R115, R116, R156, R258, R267, R302, R303, R362, R376, R377, R379, R392 R62, R63, R64, R65, R73, R74, R75, R84, R95, R96, R97, R109, R110, R111, R112, R231, R232, R234, R235, R236, R237, R239, R240, R241, R243, R261, R262, R263, R264, R265, R266, R268, R269, R270, R271, R273, R274, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R304, R305, R306, R308, R309, R310, R311, R312, R313, R344, R345, R346, R360, R361, R363, R364, R365, R367, R368, R369, R371, R380, R381, R382, R383, R384, R385, R386, R387 R66, R67, R68, R69, R70, R71, R72, R76, R77, R78, R79, R80, R81, R82, R85, R86, R87, R88, R89, R90, R91, R93, R100, R101, R102, R103, R104, R105, R106, R113, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R315, R316, R318, R320, 560PF 330uF 50V 120pF SC0805 CAP/RADIAL/200 MILS SC0805 9 10 11 12 13 14 18 20 6 1 1 1 7 2 3 24 QUAD_LED 1N4001 GND VCC HEADER 2 HEADER 5X2 RJ45X8 100 LEDX4 DIODE/THROUGH HOLE PAD250 PAD250 HD002 HD016 PHONEJ/8X SR0805 22 30 4.7K SR0805\3P 23 48 390 SR0805 24 25 17 81 2.7K 4.7K SR0805 SR0805 26 77 22 SR0805 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH 27 28 14 48 29 30 31 41 42 44 45 46 48 49 50 51 53 54 55 56 5 6 1 6 6 6 1 1 3 2 1 1 2 2 1 1 R321, R322, R323, R324, R325, R327, R328, R329, R330, R331, R332, R334, R335, R337, R339, R347, R348, R349, R350, R351, R352, R353, R354, R356, R357, R372, R373, R374, R375, R389, R390, R391 R83, R92, R107, R245, R246, R247, R249, R250, R252, R253, R254, R256, R275, R393 R123, R127, R128, R129, R130, R131, R132, R133, R139, R140, R141, R142, R143, R144, R145, R148, R149, R150, R151, R152, R163, R164, R165, R166, R167, R168, R175, R176, R177, R178, R179, R180, R184, R185, R186, R187, R188, R189, R193, R194, R195, R196, R197, R198, R208, R209, R210, R211 R135, R171, R181, R201, R212 R136, R157, R172, R182, R202, R213 SW1 U1, U3, U5, U7, U9, U11 U2, U4, U6, U8, U10, U12 U14, U17, U21, U22, U27, U29 U15 U18 U23, U24, U28 U25, U26 U30 U31 Y1, Y2 Y1, Y2 U15 U18 1K 24.9 SR0805 SR0805 4.5K 7.5K SW PUSHBUTTON TG45-1406NX LXT944QC MT4C16270DL -6 27C020 XC9572 PM3350 74F540 LT1585CT3.3-ND DS1233 CLOCK SOCKET SOCKET SOCKET SR0805 SR0805 HD003 SOL40 PQFP100_0.026PIT CH SOJ40 U32S6 PLCC44 BGA256 TO220 SOT-223/PMC Y005 Y005 U32S6 PLCC44 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 E L AN 8 x1 0 : 2 4 P o rt 1 0 M bit/s S w itc h Memory Page 4 ELAN 8X10 Page 3 Physical Layer Ports 4-7 Page 6 Physical Layer Ports 0-3 Page 5 Physical Layer Ports 12-15 Page 10 Memory Clocks, PCI Bus Page 2 Page 8 ELAN 8X10 Page 7 Physical Layer Ports 8-11 Page 9 Physical Layer Ports 20-23 Page 14 Memory Page 12 ELAN 8X10 Page 11 Physical Layer Ports 16-19 Page 13 P MC -S ierra , I nc . Title E t he rn et P roduc ts P o rt land, O re gon, U S A P M 3350 24 P ort Referenc e Des ign S c hem atic - Top S ize A D at e: D oc um e nt N um b er TB D Thu rs day , O c t obe r 16 , 19 97 S h eet 1 of 15 R ev 1. 1 VCC R254 R252 R256 7 8 9 11 12 13 14 15 16 27 26 25 24 22 20 19 18 17 2 4 6 8 10 REQ_7 REQ_3 REQ_4 REQ_5 REQ_6 R249 R253 R245 R246 R247 R250 R275 28 T P14 FRAME PCI ARBITER U18 I/FI I/FO/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI I/FO/FI I/FO XC9572 I/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO FO/FOE1 FO/FOE0 I/FO/FI I/FO/FI I/FO/FI/MR I/FO/FI I/FO/FI I/FO/FI FO/CLK0 FO/CLK1 42 29 30 33 34 35 36 37 38 39 40 43 44 1 2 3 4 5 6 JP6 1 3 5 7 9 2 4 6 8 10 U25 FRAME GNT _0 GNT _1 GNT _2 T P15 DEVSEL 1 T P13 T RDY 1 T P12 IRDY 1 1 R108 INT A R115 FRAME R376 IRDY R116 T RDY R377 DEVSEL R379 ST OP R114 PERR R392 SERR RESET _0 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K VCC 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K REQ_0 REQ_1 REQ_2 JP3 1 3 5 7 9 PCI_CLK_3 BUFFERED PCI CLOCK Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 R334 R335 R337 R339 R341 R342 R343 22 PCI_CLK_0 22 PCI_CLK_1 22 PCI_CLK_2 22 PCI_CLK_3 NI NI NI 33 MHZ PCI B US CLOC K Y1 R336 R338 R340 NI NI NI HEADER 5X2 HEADER 5X2 5 R389 22 GNT_7 GNT_3 GNT_4 GNT_5 GNT_6 JP12 VCC 2 1 CLK 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 74AC540 CLOCK SW1 JP9 PCI CLK SELECT Manual Reset 2 1 PLACE CLOSE TO PCI FINGERS PULL-UP CLOSE TO PCI FINGERS R84 HEADER 2 RESET DEVSEL ST OP SERR PAR AD15 CBE1 4.7K CBE2 FRAME IRDY T RDY CBE3 AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 INT A PERR AD10 AD9 CBE0 AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD14 AD13 AD11 AD12 AD0 AD1 VCC C48 22uF C47 + 22uF C40 + 22uF C39 + 22uF + P1 PCI_FINGERS A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 A29 B29 A30 B30 A31 B31 A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 B41 A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 B51 A52 B52 A53 B53 A54 B54 A55 B55 A56 B56 A57 B57 A58 B58 A59 B59 A60 B60 A61 B61 A62 B62 PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM 3350 24 Port Refe rence Design Sch em atic - Bus Size B Date: Document Number T BD W ednesday, November 05, 1997 Sheet 2 of 15 Rev 1.1 A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 WR3_0 WR2_0 WR1_0 WR0_0 GWE_0 RD_0 CS3_0 CS2_0 CS1_0 CS0_0 MEMCLK_0 VP R324 R82 R323 R322 R81 R321 R80 R79 R295 R78 R294 R77 R293 R76 R292 R67 R291 R66 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 R298 R297 R70 R299 R301 R69 R296 R68 R300 R71 R72 22 22 22 22 22 22 22 22 22 22 22 M20 L17 L18 L19 L20 K18 K19 J19 J18 H20 J17 H19 H18 G20 G19 H17 G18 F20 F19 F18 A17 C16 D15 B16 A16 C15 B15 A15 C14 D13 B14 A14 C13 D12 B13 C12 B12 A12 D11 C11 B11 A11 C10 B10 B9 C9 A8 D9 B8 C8 A7 B7 E17 D18 C17 D16 D8 D19 B17 E20 E19 F17 E18 V10 C7 D20 J3 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MWN3 MWN2 MWN1 MWN0 MGWE M RD MRAS MCS3 MCS2 MCS1 MCS0 MCLK MINTR MRDY VDD5 U23 PM3350 TCLK7 TXD7 TEN7 RXD7 RCLK7 CD7 COL7 TCLK6 TXD6 TEN6 RXD6 RCLK6 CD6 COL6 TCLK5 TXD5 TEN5 RXD5 RCLK5 CD5 COL5 TCLK4 TXD4 TEN4 RXD4 RCLK4 CD4 COL4 TCLK3 TXD3 TEN3 RXD3 RCLK3 CD3 COL3 TCLK2 TXD2 TEN2 RXD2 RCLK2 CD2 COL2 TCLK1 TXD1 TEN1 RXD1 RCLK1 CD1 COL1 TCLK0 TXD0 TEN0 RXD0 RCLK0 CD0 COL0 LBK CLK20 SYSCLK DBG0 DBG1 DBG2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 NC NC NC P19 P20 N18 M17 N19 M18 M19 T19 T20 R18 R19 R20 P18 N17 V17 U18 T17 U19 U20 T18 R17 V15 Y16 W16 U15 Y17 W17 U16 V13 Y14 W14 U13 V14 Y15 W15 V11 W11 W12 V12 Y13 U12 W13 V8 U9 W8 V9 W9 Y9 U10 V6 W6 Y6 V7 U8 W7 Y7 V16 Y10 W10 C6 B6 A6 A5 B5 D6 C5 A4 B4 D5 C4 D2 E4 D3 TCLK1 TXD7 TEN7 RXD7 RCLK7 CD7 COL7 TXD6 TEN6 RXD6 RCLK6 CD6 COL6 TXD5 TEN5 RXD5 RCLK5 CD5 COL5 TXD4 TEN4 RXD4 RCLK4 CD4 COL4 TCLK0 TXD3 TEN3 RXD3 RCLK3 CD3 COL3 TXD2 TEN2 RXD2 RCLK2 CD2 COL2 TXD1 TEN1 RXD1 RCLK1 CD1 COL1 TXD0 TEN0 RXD0 RCLK0 CD0 COL0 R325 PHYCLK_0 SYSCLK_0 22 TP2 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 HEADER 8X2 VCC U20 D0_0 D1_0 D2_0 D3_0 D4_0 D5_0 D6_0 D7_0 MEMCLK_0 CS3_0 JP4 RESET_0 4 3 2 1 NI 3 4 5 6 7 8 9 10 13 14 1 2 23 11 D1 D2 D3 D4 D5 D6 D7 D8 CLK CLKEN OC1 OC2 OC3 CLR 74AC825 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 22 21 20 19 18 17 16 15 R233 R238 R242 R244 R248 R251 R255 R257 390 D18 390 D19 390 D20 390 D21 390 D22 390 D23 390 D24 390 D25 LED LED LED LED LED LED LED LED VCC 1 2 D1 E3 F4 E2 U3 E1 F3 F1 F2 G3 H4 G1 G2 H3 J4 J2 H2 J1 K4 K2 K3 K1 L3 M2 L2 M3 N1 M4 N2 N3 P1 P2 N4 P3 R2 R1 R3 T1 R4 T2 T3 U1 V4 U2 T4 U5 Y4 W 4 V5 U6 Y5 W 5 AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 REQ_0 GNT_0 PCI_CLK_0 RESET_0 INTA ERST AD21 AD20 AD22 AD23 CBE3 AD18 AD1 AD0 AD2 AD3 AD5 AD4 AD6 AD7 AD8 CBE0 AD9 AD10 AD12 AD11 AD13 AD14 CBE1 AD15 PAR SERR PERR STOP DEVSEL TRDY IRDY FRAME CBE2 AD17 NI 1k R326 R83 VP ERST TST INTA RST PCICLK GNT REQ AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 IDSEL CBE3 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 CBE2 FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR AD15 CBE1 AD14 AD13 AD11 AD12 AD10 AD9 CBE0 AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD0 AD1 JP8 HEADER 2 1 1 Y2 R391 22 PHYCLK VCC CLOCK R393 1K U26 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 74AC540 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 R354 R356 R357 R359 R355 R358 22 50 MH Z S Y S T E M C L OC K CLK 5 SYSCLK_0 22 SYSCLK_1 22 SYSCLK_2 NI PHYCLK_0B NI PHYCLK_1B NI PHYCLK_2B RESET_0 B FF R R SE U E ED E T DS1233 C9 560PF U31 RESET 2 RESET 1 RESET AD19 AD16 TP11 SYSCLOCK_2 TP10 SYSCLOCK_1 TP9 SYSCLOCK_0 PMC-Sierra, Inc. Title Ethernet Products Portland, Oregon, USA PM 3350 24 P ort R efer ence Desi g n Sc hematic ED 0 Size C Date: Docum Number ent TBD Wednesday, November 05, 1997 Sheet 3 of 15 Rev 1.1 VCC Configu ra tion Resisto rs R264 R270 4.7K D31_0 4.7K D29_0 4.7K D28_0 4.7K D27_0 4.7K D21_0 4.7K D20_0 4.7K D19_0 4.7K D18_0 4.7K D17_0 4.7K D16_0 4.7K D15_0 4.7K D14_0 4.7K D13_0 4.7K D12_0 4.7K D11_0 4.7K D10_0 4.7K D9_0 4.7K D8_0 4.7K D7_0 4.7K D6_0 4.7K D5_0 4.7K D4_0 4.7K D3_0 4.7K D2_0 4.7K D1_0 4.7K D0_0 4.7K 4.7K R60 R272 D23_0 D22_0 4.7K R259 D24_0 4.7K R260 D25_0 HEADER 2 HEADER 2 D30_0 2.7K R59 2.7K R258 JP1 1 2 R267 2.7K R61 2.7K JP2 1 2 RISC Run (Master High/Slave Low) VCC FIRM VCC EDO DRAM U17 WR3_0 WR2_0 CS0_0 RD_0 GWE_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 28 29 14 27 13 26 25 24 23 22 19 18 17 16 CASH CASL RAS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 MT 4C16270DL-6 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 EDO DRAM U16 WR3_0 WR2_0 CS1_0 RD_0 GWE_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 28 29 14 27 13 26 25 24 23 22 19 18 17 16 CASH CASL RAS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 NI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 R273 R274 R64 R239 R232 R63 R236 R62 R231 R235 D26_0 U14 WR1_0 WR0_0 CS0_0 RD_0 GWE_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 28 29 14 27 13 26 25 24 23 22 19 18 17 16 CASH CASL RAS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 MT 4C16270DL-6 U15 A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 27C020 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 U13 WR1_0 WR0_0 CS1_0 RD_0 GWE_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 28 29 14 27 13 26 25 24 23 22 19 18 17 16 CASH CASL RAS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 NI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 R241 R234 R237 R243 R65 R240 R261 R263 R266 R269 R271 D7 D6 D5 D4 D3 D2 D1 D0 21 20 19 18 17 15 14 13 D0_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 CS2_0 RD_0 R268 R265 R262 EPROM 22 CE 24 OE PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM 3 350 24 Po rt Refere nce Design Sch em atic - M em ory0 Size B Date: Docum ent Number T BD Wednesday, November 05, 1997 Sheet 4 of 15 Rev 1.1 U3 U4 LXT944QC T CLK0 T XD3 TEN3 RXD3 RCLK3 CD3 COL3 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 2.7K 74 24 TCLK T XD1 T XEN1 RXD1 RCLK1 CD1 COL1 T XD2 T XEN2 RXD2 RCLK2 CD2 COL2 T XD3 T XEN3 RXD3 RCLK3 CD3 COL3 T XD4 T XEN4 RXD4 RCLK4 CD4 COL4 LOOPBK SYSCLK LEDCFN RBIAS T EST MD0 MD1 LINK1 LINK2 LINK3 LINK4 DSQE PDN PQFP100_0.026PIT CH 95 T POP1 96 T PON1 10 T PIP1 9 T PIN1 93 T POP2 92 T PON2 8 T PIP2 7 T PIN2 89 T POP3 90 T PON3 6 T PIP3 5 T PIN3 87 T POP4 86 T PON4 4 T PIP4 3 T PIN4 18 LEDL1 17 LEDC1 16 LEDR1 15 LEDT 1 23 LEDL2 22 LEDC2 21 LEDR2 20 LEDT 2 60 LEDL3 59 LEDC3 58 LEDR3 57 LEDT 3 65 LEDL4 64 LEDC4 63 LEDR4 62 LEDT 4 R10 NI D3 3 4 1 2 6 5 8 7 R47 R215 R46 R207 390 390 390 390 R140 R139 R6 R141 R142 R134 R143 R144 R7 R145 R152 R146 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 VCC C78 120pF C77 120pF C76 120pF C75 120pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 T X1+ CT 1 T X1RX1+ RX1T X2+ CT 2 T X2RX2+ RX2T X3+ CT 3 T X3RX3+ RX3T X4+ CT 4 T X4RX4+ RX4TG45-1406NX T X1+ NC1 T X1RX1+ RX1T X2+ NC2 T X2RX2+ RX2T X3+ NC3 T X3RX3+ RX3T X4+ NC4 T X4RX4+ RX438 37 36 40 39 35 34 33 32 31 28 27 26 30 29 25 24 23 22 21 T X+3 T X-3 RX+3 RX-3 T X+2 T X-2 RX+2 RX-2 T X+1 T X-1 RX+1 RX-1 T X+0 T X-0 RX+0 RX-0 T XD2 TEN2 RXD2 RCLK2 CD2 COL2 T XD1 TEN1 RXD1 RCLK1 CD1 COL1 VCC T XD0 TEN0 RXD0 RCLK0 CD0 COL0 R156 PHYCLK_0 R147 NI QUAD_LED R161 NI R159 NI PHYCLK_0B R12 NI 73 72 75 76 77 78 68 R157 28 36 44 52 7.5K 4.7K 4.7K 4.7K R16 R15 R155 NI Phy Clock 20MHz U33 CLK 5 R388 NI PHYCLK NI PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM3350 24 Port Reference Design Schematic - Phy0-3 Size B Date: Document Number T BD Wednesday, November 05, 1997 Sheet 5 of 15 Rev 1.1 U1 U2 LXT 944QC T CLK1 T XD7 T EN7 RXD7 RCLK7 CD7 COL7 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 4.5K 74 24 T CLK T XD1 T XEN1 RXD1 RCLK1 CD1 COL1 T XD2 T XEN2 RXD2 RCLK2 CD2 COL2 T XD3 T XEN3 RXD3 RCLK3 CD3 COL3 T XD4 T XEN4 RXD4 RCLK4 CD4 COL4 LOOPBK SYSCLK LEDCFN RBIAS DSQE T EST MD0 MD1 LINK1 LINK2 LINK3 LINK4 PDN LEDL4 LEDC4 LEDR4 LEDT4 PQFP100_0.026PIT CH 95 T POP1 96 T PON1 10 T PIP1 9 T PIN1 93 T POP2 92 T PON2 8 T PIP2 7 T PIN2 89 T POP3 90 T PON3 6 T PIP3 5 T PIN3 87 T POP4 86 T PON4 4 T PIP4 3 T PIN4 LEDL1 LEDC1 LEDR1 LEDT1 LEDL2 LEDC2 LEDR2 LEDT2 LEDL3 LEDC3 LEDR3 LEDT3 18 17 16 15 23 22 21 20 60 59 58 57 65 64 63 62 R3 NI D2 3 4 1 2 6 5 8 7 R206 R45 R205 R44 390 390 390 390 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R127 R123 R1 R128 R129 R2 R131 R130 R124 R132 R133 R125 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 VCC C65 120pF C64 120pF C63 120pF C61 120pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 T X1+ CT1 T X1RX1+ RX1T X2+ CT2 T X2RX2+ RX2T X3+ CT3 T X3RX3+ RX3T X4+ CT4 T X4RX4+ RX4T G45-1406NX T X1+ NC1 T X1RX1+ RX1T X2+ NC2 T X2RX2+ RX238 37 36 40 39 35 34 33 32 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 J1 8H 7H 6H 5H 4H 3H 2H 1H 8G 7G 6G 5G 4G 3G 2G 1G 8F 7F 6F 5F 4F 3F 2F 1F 8E 7E 6E 5E 4E 3E 2E 1E 8D 7D 6D 5D 4D 3D 2D 1D 8C 7C 6C 5C 4C 3C 2C 1C 8B 7B 6B 5B 4B 3B 2B 1B 8A 7A 6A 5A 4A 3A 2A 1A RJ45X8 PHONEJ/8X T XD6 T EN6 RXD6 RCLK6 CD6 COL6 28 T X3+ 27 NC3 26 T X3- 30 RX3+ 29 RX3T X4+ NC4 T X4RX4+ RX425 24 23 22 21 T XD5 T EN5 RXD5 RCLK5 CD5 COL5 VCC T XD4 T EN4 RXD4 RCLK4 CD4 COL4 R135 PHYCLK_0 R4 NI QUAD_LED R11 NI R137 NI PHYCLK_0B R126 NI 75 76 77 78 68 73 72 R136 28 36 44 52 7.5K T X+3 T X-3 RX+3 RX-3 T X+2 T X-2 RX+2 RX-2 T X+1 T X-1 RX+1 RX-1 T X+0 T X-0 RX+0 RX-0 4.7K 4.7K 4.7K R5 R8 R9 PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM 3350 24 Port Reference Design Schematic - Phy4-7 Size B Date: Document Number T BD Wednesday, November 05, 1997 Sheet 6 of 15 Rev 1.1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 WR3_1 WR2_1 WR1_1 WR0_1 GWE_1 RD_1 CS3_1 CS0_1 MEMCLK_1 VP R330 R88 R329 R87 R331 R328 R86 R327 R85 22 22 22 22 22 22 22 22 22 R318 R316 R91 R320 R332 R90 R315 R89 R93 22 22 22 22 22 22 22 22 22 M20 L17 L18 L19 L20 K18 K19 J19 J18 H20 J17 H19 H18 G20 G19 H17 G18 F20 F19 F18 A17 C16 D15 B16 A16 C15 B15 A15 C14 D13 B14 A14 C13 D12 B13 C12 B12 A12 D11 C11 B11 A11 C10 B10 B9 C9 A8 D9 B8 C8 A7 B7 E17 D18 C17 D16 D8 D19 B17 E20 E19 F17 E18 V10 C7 D20 J3 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MWN3 MWN2 MWN1 MWN0 MGWE MRD MRAS MCS3 MCS2 MCS1 MCS0 MCLK MINT R MRDY VDD5 U24 PM3350 T CLK7 T XD7 T EN7 RXD7 RCLK7 CD7 COL7 T CLK6 T XD6 T EN6 RXD6 RCLK6 CD6 COL6 T CLK5 T XD5 T EN5 RXD5 RCLK5 CD5 COL5 T CLK4 T XD4 T EN4 RXD4 RCLK4 CD4 COL4 T CLK3 T XD3 T EN3 RXD3 RCLK3 CD3 COL3 T CLK2 T XD2 T EN2 RXD2 RCLK2 CD2 COL2 T CLK1 T XD1 T EN1 RXD1 RCLK1 CD1 COL1 T CLK0 T XD0 T EN0 RXD0 RCLK0 CD0 COL0 LBK CLK20 SYSCLK DBG0 DBG1 DBG2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 NC NC NC P19 P20 N18 M17 N19 M18 M19 T 19 T 20 R18 R19 R20 P18 N17 V17 U18 T 17 U19 U20 T 18 R17 V15 Y16 W16 U15 Y17 W17 U16 V13 Y14 W14 U13 V14 Y15 W15 V11 W11 W12 V12 Y13 U12 W13 V8 U9 W8 V9 W9 Y9 U10 V6 W6 Y6 V7 U8 W7 Y7 V16 Y10 R347 W10 C6 B6 A6 A5 B5 D6 C5 A4 B4 D5 C4 D2 E4 D3 T CLK3 T XD15 T EN15 RXD15 RCLK15 CD15 COL15 T XD14 T EN14 RXD14 RCLK14 CD14 COL14 T XD13 T EN13 RXD13 RCLK13 CD13 COL13 U19 D0_1 D1_1 D2_1 D3_1 D4_1 D5_1 D6_1 D7_1 3 4 5 6 7 8 9 10 13 14 1 2 23 11 D1 D2 D3 D4 D5 D6 D7 D8 CLK CLKEN OC1 OC2 OC3 CLR 74AC825 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 22 21 20 19 18 17 16 15 R138 R224 R225 R226 R227 R228 R229 R230 390 D1 390 D11 390 D12 390 D13 390 D14 390 D15 390 D16 390 D17 LED LED LED LED LED LED LED LED VCC T XD12 T EN12 RXD12 RCLK12 CD12 MEMCLK_1 COL12 CS3_1 T CLK2 T XD11 T EN11 RXD11 RESET _0 RCLK11 CD11 COL11 T XD10 T EN10 RXD10 RCLK10 CD10 COL10 T XD9 T EN9 RXD9 RCLK9 CD9 COL9 T XD8 T EN8 RXD8 RCLK8 CD8 COL8 22 PHYCLK_1 SY SCLK_1 JP7 4 3 2 1 NI T P4 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 COL15 COL14 COL13 COL12 COL11 COL10 COL9 COL8 HEADER 8X2 VCC ERST T ST INT A RST PCICLK GNT REQ AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 IDSEL CBE3 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 CBE2 FRAME IRDY T RDY DEVSEL ST OP PERR SERR PAR AD15 CBE1 AD14 AD13 AD11 AD12 AD10 AD9 CBE0 AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD0 AD1 D1 E3 F4 E2 U3 E1 F3 F1 F2 G3 H4 G1 G2 H3 J4 J2 H2 J1 K4 K2 K3 K1 L3 M2 L2 M3 N1 M4 N2 N3 P1 P2 N4 P3 R2 R1 R3 T1 R4 T2 T3 U1 V4 U2 T4 U5 Y4 W4 V5 U6 Y5 W5 AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 REQ_1 GNT _1 PCI_CLK_1 RESET _0 INT A ERST AD22 AD23 CBE3 AD16 AD18 AD19 AD21 AD1 AD0 AD2 AD3 AD5 AD4 AD6 AD7 AD8 CBE0 AD9 AD10 AD12 AD11 AD13 AD14 CBE1 AD15 PAR SERR PERR ST OP DEVSEL T RDY IRDY FRAME CBE2 VP PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM 33 50 24 Po rt Referen ce Design Schem atic - ED1 AD20 NI 1k R333 R92 AD17 Size B Date: Document Number T BD Wednesday, November 05, 1997 Sheet 7 of 15 Rev 1.1 VC C E DO DRA M U 22 W R 3 _1 W R 2 _1 C S 0_1 R D _1 G W E _1 A 8_1 A 7_1 A 6_1 A 5_1 A 4_1 A 3_1 A 2_1 A 1_1 A 0_1 28 29 14 27 13 26 25 24 23 22 19 18 17 16 C ASH C ASL R AS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D 31 _1 D 30 _1 D 29 _1 D 28 _1 D 27 _1 D 26 _1 D 25 _1 D 24 _1 D 23 _1 D 22 _1 D 21 _1 D 20 _1 D 19 _1 D 18 _1 D 17 _1 D 16 _1 Configuration Res is tors R 30 4 R 30 5 R 30 6 R 30 8 R 30 9 4. 7 K D 31 _1 4. 7 K D 30 _1 4. 7 K D 29 _1 4. 7 K D 28 _1 4. 7 K D 27 _1 4. 7 K R 30 7 4. 7 K R 31 7 R 31 2 R 31 1 R 31 0 R 73 R 28 2 R 28 5 4. 7 K D 21 _1 4. 7 K D 20 _1 4. 7 K D 19 _1 4. 7 K D 18 _1 4. 7 K D 17 _1 4. 7 K D 16 _1 4. 7 K D 15 _1 4. 7 K D 14 _1 4. 7 K D 13 _1 4. 7 K D 12 _1 4. 7 K D 11 _1 4. 7 K D 10 _1 4. 7 K D 9_ 1 4. 7 K D 8_ 1 4. 7 K D 7_ 1 4. 7 K D 6_ 1 4. 7 K D 5_ 1 4. 7 K D 4_ 1 4. 7 K D 3_ 1 4. 7 K D 2_ 1 4. 7 K D 1_ 1 4. 7 K D 0_ 1 P MC -S ierra, In c . Tit le E th erne t P rod uc t s P ort la nd, O rego n, U S A H EAD ER 2 D 26 _1 R 30 3 2. 7 K JP5 1 2 R 30 2 2. 7 K FIRM VC C 4. 7 K R 31 9 4. 7 K R 31 4 D 23 _1 D 22 _1 D 25 _1 D 24 _1 MT4 C 162 70D L -6 U 21 W R 1 _1 W R 0 _1 C S 0_1 R D _1 G W E _1 A 8_1 A 7_1 A 6_1 A 5_1 A 4_1 A 3_1 A 2_1 A 1_1 A 0_1 28 29 14 27 13 26 25 24 23 22 19 18 17 16 C ASH C ASL R AS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D 15 _1 D 14 _1 D 13 _1 D 12 _1 D 11 _1 D 10 _1 D 9_ 1 D 8_ 1 D 7_ 1 D 6_ 1 D 5_ 1 D 4_ 1 D 3_ 1 D 2_ 1 D 1_ 1 D 0_ 1 R 27 6 R 27 9 R 27 7 R 28 0 R 74 R 31 3 R 75 R 28 3 R 28 8 R 28 6 R 28 9 R 27 8 R 28 1 R 28 4 R 28 7 R 29 0 MT4 C 162 70D L -6 P M 3350 24 P ort Referenc e Des ign S c hem atic - M em ory 1 S ize A D at e: D oc um e nt N um b er TB D W e dn es d ay , N o v e m be r 0 5, 199 7 S hee t 8 of 15 R ev 1. 1 U7 U8 LXT 94 4Q C TC L K2 TXD 11 TE N 11 R XD 11 R C LK 11 C D 11 C O L 11 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 4. 5K 74 24 T C LK T XD 1 TXE N 1 R XD 1 R C L K1 C D1 C O L1 T XD 2 TXE N 2 R XD 2 R C L K2 C D2 C O L2 T XD 3 TXE N 3 R XD 3 R C L K3 C D3 C O L3 T XD 4 TXE N 4 R XD 4 R C L K4 C D4 C O L4 LO O P BK LED CF N SY S C LK MD0 MD1 LE D L4 LED C4 LED R4 LE D T4 PQ F P 10 0_ 0 .02 6 PI TC H TP O P1 TP O N1 T PI P1 T PI N 1 TP O P2 TP O N2 T PI P2 T PI N 2 TP O P3 TP O N3 T PI P3 T PI N 3 TP O P4 TP O N4 T PI P4 T PI N 4 LE D L1 LED C1 LED R1 LE D T1 LE D L2 LED C2 LED R2 LE D T2 LE D L3 LED C3 LED R3 LE D T3 95 96 10 9 93 92 8 7 89 90 6 5 87 86 4 3 18 17 16 15 23 22 21 20 60 59 58 57 65 64 63 62 R 22 NI D5 3 4 1 2 6 5 8 7 Q U AD _ LE D R 32 NI R 2 19 R 51 R 2 18 R 50 3 90 3 90 3 90 3 90 R 1 68 R 1 67 R 19 R 1 75 R 1 76 R 20 R 1 78 R 1 77 R 1 69 R 1 79 R 1 80 R 1 70 24 .9 24 .9 1 00 24 .9 24 .9 1 00 24 .9 24 .9 1 00 24 .9 24 .9 1 00 C 1 09 1 20 pF C 1 08 1 20 pF C 1 07 1 20 pF C 99 1 20 pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 TX1+ C T1 TX1 R X1+ R X1 TX2+ C T2 TX2 R X2+ R X2 TX3+ C T3 TX3 R X3+ R X3 TX4+ C T4 TX4 R X4+ R X4 TX1+ N C1 TX1 R X1+ R X1 TX2+ N C2 TX2 R X2+ R X2 TX3+ N C3 TX3 R X3+ R X3 TX4+ N C4 TX4 R X4+ R X4 38 37 36 40 39 35 34 33 32 31 28 27 26 30 29 25 24 23 22 21 T X+ 11 T X- 11 R X+ 11 R X- 11 T X+ 10 T X- 10 R X+ 10 R X- 10 TX+9 TX-9 R X+9 R X-9 TX+8 TX-8 R X+8 R X-8 TXD 10 TE N 10 R XD 10 R C LK 10 C D 10 C O L 10 T XD 9 TE N9 R XD 9 R C L K9 C D9 C O L9 VC C T G 45 -1 40 6 N X VC C T XD 8 TE N8 R XD 8 R C L K8 C D8 C O L8 R 1 81 P H Y C LK _1 R 23 NI R 1 83 NI R BI AS 68 PH Y C LK _ 1B 73 72 75 76 77 78 28 36 44 52 R 1 82 7. 5K 4. 7K 4. 7K 4. 7K R 1 74 N I R 27 R 29 R 30 L IN K1 L IN K2 L IN K3 L IN K4 D SQ E T E ST PD N P MC - Sie rr a, In c . T itle E th er ne t Pr od uc ts Po rt la nd , O r eg on , U SA PM3350 24 Port Reference Design Schematic- Phy8-11 S ize B D a te : D o c um e nt N u m b e r TB D S W ed ne s da y , N o v e m be r 05 , 19 97 he et 9 of 15 R ev 1 .1 U5 U6 LXT 944QC T CLK3 T XD15 T EN15 RXD15 RCLK15 CD15 COL15 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 4.5K 74 24 T CLK T XD1 T XEN1 RXD1 RCLK1 CD1 COL1 T XD2 T XEN2 RXD2 RCLK2 CD2 COL2 T XD3 T XEN3 RXD3 RCLK3 CD3 COL3 T XD4 T XEN4 RXD4 RCLK4 CD4 COL4 LOOPBK SY SCLK LEDCFN RBIAS T EST DSQE MD0 MD1 LINK1 LINK2 LINK3 LINK4 PDN LEDL4 LEDC4 LEDR4 LEDT 4 PQFP100_0.026PIT CH T POP1 T PON1 T PIP1 T PIN1 T POP2 T PON2 T PIP2 T PIN2 T POP3 T PON3 T PIP3 T PIN3 T POP4 T PON4 T PIP4 T PIN4 LEDL1 LEDC1 LEDR1 LEDT 1 LEDL2 LEDC2 LEDR2 LEDT 2 LEDL3 LEDC3 LEDR3 LEDT 3 95 96 10 9 93 92 8 7 89 90 6 5 87 86 4 3 18 17 16 15 23 22 21 20 60 59 58 57 65 64 63 62 R158 NI D4 3 4 1 2 QUAD_LED R24 NI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 6 5 8 7 R217 R49 R216 R48 390 390 390 390 40 39 38 37 36 35 34 33 R149 R148 R153 R150 R151 R13 R164 R163 R154 R166 R165 R14 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 C98 120pF C97 120pF C91 120pF C90 120pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 VCC T X1+ CT 1 T X1RX1+ RX1T X2+ CT 2 T X2RX2+ RX2T X3+ CT 3 T X3RX3+ RX3T X4+ CT 4 T X4RX4+ RX4T G45-1406NX T X1+ NC1 T X1RX1+ RX1T X2+ NC2 T X2RX2+ RX2T X3+ NC3 T X3RX3+ RX3T X4+ NC4 T X4RX4+ RX438 37 36 40 39 35 34 33 32 31 28 27 26 30 29 25 24 23 22 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 J2 8H 7H 6H 5H 4H 3H 2H 1H 8G 7G 6G 5G 4G 3G 2G 1G 8F 7F 6F 5F 4F 3F 2F 1F 8E 7E 6E 5E 4E 3E 2E 1E 8D 7D 6D 5D 4D 3D 2D 1D 8C 7C 6C 5C 4C 3C 2C 1C 8B 7B 6B 5B 4B 3B 2B 1B 8A 7A 6A 5A 4A 3A 2A 1A RJ45X8 PHONEJ/8X T XD14 T EN14 RXD14 RCLK14 CD14 COL14 T XD13 T EN13 RXD13 RCLK13 CD13 COL13 VCC T XD12 T EN12 RXD12 RCLK12 CD12 COL12 R171 PHY CLK_1 R160 NI R173 NI PHY CLK_1B R162 NI 75 76 77 78 68 73 72 R172 28 36 44 52 7.5K T X+11 4.7K 4.7K 4.7K T X-10 RX+10 RX-10 T X+9 T X-9 RX+9 RX-9 T X+8 T X-8 RX+8 RX-8 T X-11 RX+11 RX-11 T X+10 R21 R17 R18 PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM3 350 24 Port Re ference Design Schem atic - Ph y12-15 Size B Date: Document Number T BD Wednesday, Novem ber 05, 1997 Sheet 10 of 15 Rev 1.1 A8_2 A7_2 A6_2 A5_2 A4_2 A3_2 A2_2 A1_2 A0_2 D31_2 D30_2 D29_2 D28_2 D27_2 D26_2 D25_2 D24_2 D23_2 D22_2 D21_2 D20_2 D19_2 D18_2 D17_2 D16_2 D15_2 D14_2 D13_2 D12_2 D11_2 D10_2 D9_2 D8_2 D7_2 D6_2 D5_2 D4_2 D3_2 D2_2 D1_2 D0_2 WR3_2 WR2_2 WR1_2 WR0_2 GWE_2 RD_2 CS3_2 CS0_2 MEMCLK_2 VP R374 R102 R373 R101 R375 R372 R100 R103 R348 22 22 22 22 22 22 22 22 22 R351 R350 R106 R352 R353 R105 R349 R104 R113 22 22 22 22 22 22 22 22 22 M20 L17 L18 L19 L20 K18 K19 J19 J18 H20 J17 H19 H18 G20 G19 H17 G18 F20 F19 F18 A17 C16 D15 B16 A16 C15 B15 A15 C14 D13 B14 A14 C13 D12 B13 C12 B12 A12 D11 C11 B11 A11 C10 B10 B9 C9 A8 D9 B8 C8 A7 B7 E17 D18 C17 D16 D8 D19 B17 E20 E19 F17 E18 V10 C7 D20 J3 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MWN3 MWN2 MWN1 MWN0 MGWE MRD MRAS MCS3 MCS2 MCS1 MCS0 MCLK MINT R MRDY VDD5 U28 PM3350 T CLK7 T XD7 T EN7 RXD7 RCLK7 CD7 COL7 T CLK6 T XD6 T EN6 RXD6 RCLK6 CD6 COL6 T CLK5 T XD5 T EN5 RXD5 RCLK5 CD5 COL5 T CLK4 T XD4 T EN4 RXD4 RCLK4 CD4 COL4 T CLK3 T XD3 T EN3 RXD3 RCLK3 CD3 COL3 T CLK2 T XD2 T EN2 RXD2 RCLK2 CD2 COL2 T CLK1 T XD1 T EN1 RXD1 RCLK1 CD1 COL1 T CLK0 T XD0 T EN0 RXD0 RCLK0 CD0 COL0 LBK CLK20 SY SCLK DBG0 DBG1 DBG2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 NC NC NC P19 P20 N18 M17 N19 M18 M19 T 19 T 20 R18 R19 R20 P18 N17 V17 U18 T 17 U19 U20 T 18 R17 V15 Y 16 W16 U15 Y 17 W17 U16 V13 Y 14 W14 U13 V14 Y 15 W15 V11 W11 W12 V12 Y 13 U12 W13 V8 U9 W8 V9 W9 Y9 U10 V6 W6 Y6 V7 U8 W7 Y7 V16 Y 10 R390 W10 C6 B6 A6 A5 B5 D6 C5 A4 B4 D5 C4 D2 E4 D3 T CLK5 T XD23 T EN23 RXD23 RCLK23 CD23 COL23 T XD22 T EN22 RXD22 RCLK22 CD22 COL22 T XD21 T EN21 RXD21 RCLK21 CD21 COL21 T XD20 D0_2 T EN20 D1_2 RXD20 D2_2 RCLK20 D3_2 CD20 D4_2 COL20 D5_2 T CLK4 D6_2 T XD19 D7_2 T EN19 RXD19 MEMCLK_2 RCLK19 CS3_2 CD19 COL19 T XD18 T EN18 RXD18 RCLK18 CD18 COL18 T XD17 T EN17 RXD17 RCLK17 CD17 COL17 T XD16 T EN16 RXD16 RCLK16 CD16 COL16 22 PHY CLK_2 SY SCLK_2 JP11 4 3 2 1 NI RESET _0 3 4 5 6 7 8 9 10 13 14 1 2 23 11 VCC U32 D1 D2 D3 D4 D5 D6 D7 D8 CLK CLKEN OC1 OC2 OC3 CLR 74AC825 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 22 21 20 19 18 17 16 15 R54 R55 R117 R118 R119 R120 R121 R122 390 D8 390 D9 390 D10 390 D27 390 D28 390 D29 390 D30 390 D31 LED LED LED LED LED LED LED LED T P5 CD23 CD22 CD21 CD20 CD19 CD18 CD17 CD16 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16 HEADER 8X2 VCC ERST T ST INT A RST PCICLK GNT REQ AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 IDSEL CBE3 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 CBE2 FRAME IRDY T RDY DEVSEL ST OP PERR SERR PAR AD15 CBE1 AD14 AD13 AD11 AD12 AD10 AD9 CBE0 AD8 AD7 AD6 AD4 AD5 AD3 AD2 AD0 AD1 VP D1 E3 F4 E2 U3 E1 F3 F1 F2 G3 H4 G1 G2 H3 J4 J2 H2 J1 K4 K2 K3 K1 L3 M2 L2 M3 N1 M4 N2 N3 P1 P2 N4 P3 R2 R1 R3 T1 R4 T2 T3 U1 V4 U2 T4 U5 Y4 W4 V5 U6 Y5 W5 AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 REQ_2 GNT _2 PCI_CLK_2 RESET _0 INT A AD20 AD22 AD23 CBE3 ERST AD19 AD1 AD0 AD2 AD3 AD5 AD4 AD6 AD7 AD8 CBE0 AD9 AD10 AD12 AD11 AD13 AD14 CBE1 AD15 PAR SERR PERR ST OP DEVSEL T RDY IRDY FRAME CBE2 AD17 AD16 PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA NI R378 1k R107 PM 335 0 2 4 Port Re fe ren ce Design Sche matic - ED2 AD21 AD18 Size B Date: Docum ent Number T BD Wednesday, November 05, 1997 Sheet 11 of 15 Rev 1.1 VC C Configuration Res is tors R 36 1 R 36 4 4.7K D 31 _2 4.7K D 30 _2 4.7K D 29 _2 4.7K D 28 _2 4.7K D 27 _2 4 . 7 K R 37 0 4 . 7 K R 36 6 R 34 6 R 34 4 R 96 R 97 R 34 5 R 95 4.7K D 21 _2 4.7K D 20 _2 4.7K D 19 _2 4.7K D 18 _2 4.7K D 17 _2 4.7K D 16 _2 4.7K D 15 _2 4.7K D 14 _2 4.7K D 13 _2 4.7K D 12 _2 4.7K D 11 _2 4.7K D 10 _2 4.7K D 9_ 2 4.7K D 8_ 2 4.7K D 7_ 2 4.7K D 6_ 2 4.7K D 5_ 2 4.7K D 4_ 2 4.7K D 3_ 2 4.7K D 2_ 2 4.7K D 1_ 2 4.7K D 0_ 2 E t he rn e t P ro d uc t s P o rt lan d , O re go n, U S A H EAD ER 2 D 26 _2 R 36 2 2.7K J P 10 1 2 R 94 2.7K FIRM VC C 4 . 7 K R 99 4 . 7 K R 98 D 23 _2 D 22 _2 D 25 _2 D 24 _2 E DO DRA M U 27 W R 3 _2 W R 2 _2 C S 0_ 2 R D _2 G W E_2 A 8 _2 A 7 _2 A 6 _2 A 5 _2 A 4 _2 A 3 _2 A 2 _2 A 1 _2 A 0 _2 28 29 14 27 13 26 25 24 23 22 19 18 17 16 C ASH C ASL R AS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D 31 _2 D 30 _2 D 29 _2 D 28 _2 D 27 _2 D 26 _2 D 25 _2 D 24 _2 D 23 _2 D 22 _2 D 21 _2 D 20 _2 D 19 _2 D 18 _2 D 17 _2 D 16 _2 R 36 8 R 36 9 R 37 1 MT4 C 1 6 27 0D L -6 U 29 W R 1 _2 W R 0 _2 C S 0_ 2 R D _2 G W E_2 A 8 _2 A 7 _2 A 6 _2 A 5 _2 A 4 _2 A 3 _2 A 2 _2 A 1 _2 A 0 _2 28 29 14 27 13 26 25 24 23 22 19 18 17 16 C ASH C ASL R AS OE WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 39 38 37 36 34 33 32 31 10 9 8 7 5 4 3 2 D 15 _2 D 14 _2 D 13 _2 D 12 _2 D 11 _2 D 10 _2 D 9_ 2 D 8_ 2 D 7_ 2 D 6_ 2 D 5_ 2 D 4_ 2 D 3_ 2 D 2_ 2 D 1_ 2 D 0_ 2 R 38 1 R 38 0 R 38 2 R 38 3 R 38 4 R 38 7 R 38 5 R 38 6 R 36 7 R 11 2 R 36 5 R 11 1 R 36 3 R 11 0 R 36 0 R 10 9 MT4 C 1 6 27 0D L -6 P MC -S ie rra, I n c . Tit le P M 3350 24 P ort Referenc e Des ign S c hem atic - M em ory 2 S ize A D at e: D oc um en t N um b er TB D W ed ne s da y , N ov e m b er 0 5 , 19 9 7 S h ee t 12 of 15 R ev 1.1 U 11 U 12 LXT9 44 Q C TCLK 4 T XD 1 9 T EN 1 9 R XD 1 9 R C LK 1 9 CD 19 C O L1 9 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 4 .5K 74 24 TC LK TXD 1 T XE N 1 R XD 1 R CLK1 CD1 CO L1 TXD 2 T XE N 2 R XD 2 R CLK2 CD2 CO L2 TXD 3 T XE N 3 R XD 3 R CLK3 CD3 CO L3 TXD 4 T XE N 4 R XD 4 R CLK4 CD4 CO L4 LO O P BK L ED C F N SY SC LK MD 0 MD 1 L ED L 4 L ED C 4 L ED R 4 L ED T 4 PQ F P1 00 _0 .02 6P IT C H T PO P 1 T PO N 1 TP IP 1 TP IN 1 T PO P 2 T PO N 2 TP IP 2 TP IN 2 T PO P 3 T PO N 3 TP IP 3 TP IN 3 T PO P 4 T PO N 4 TP IP 4 TP IN 4 L ED L 1 L ED C 1 L ED R 1 L ED T 1 L ED L 2 L ED C 2 L ED R 2 L ED T 2 L ED L 3 L ED C 3 L ED R 3 L ED T 3 95 96 10 9 93 92 8 7 89 90 6 5 87 86 4 3 18 17 16 15 23 22 21 20 60 59 58 57 65 64 63 62 R 38 NI 3 4 1 2 D7 6 5 8 7 R 22 3 R 58 R 22 2 R 57 R 19 6 R 19 5 R 19 9 R 19 7 R 19 8 R 34 R 20 8 R 20 9 R 20 0 R 21 0 R 21 1 R 35 2 4. 9 2 4. 9 10 0 2 4. 9 2 4. 9 10 0 2 4. 9 2 4. 9 10 0 2 4. 9 2 4. 9 10 0 C 14 3 120 pF C 14 2 120 pF C 13 6 120 pF C 13 5 120 pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 VCC 39 0 39 0 39 0 39 0 T X1 + C T1 T X1 R X1 + R X1 T X2 + C T2 T X2 R X2 + R X2 T X3 + C T3 T X3 R X3 + R X3 T X4 + C T4 T X4 R X4 + R X4 TG 45 -14 06 N X T X1 + NC1 T X1 R X1 + R X1 T X2 + NC2 T X2 R X2 + R X2 T X3 + NC3 T X3 R X3 + R X3 T X4 + NC4 T X4 R X4 + R X4 38 37 36 40 39 35 34 33 32 31 28 27 26 30 29 25 24 23 22 21 TX+1 9 TX-1 9 R X+1 9 R X-1 9 TX+1 8 TX-1 8 R X+1 8 R X-1 8 TX+1 7 TX-1 7 R X+1 7 R X-1 7 TX+1 6 TX-1 6 R X+1 6 R X-1 6 T XD 1 8 T EN 1 8 R XD 1 8 R C LK 1 8 CD 18 C O L1 8 T XD 1 7 T EN 1 7 R XD 1 7 R C LK 1 7 CD 17 C O L1 7 VCC T XD 1 6 T EN 1 6 R XD 1 6 R C LK 1 6 CD 16 C O L1 6 R 21 2 P H Y C LK _ 2 R 40 NI Q U AD _L ED R 43 NI R 21 4 NI R B IAS 68 PH Y C L K_ 2B 73 72 75 76 77 78 28 36 44 52 R 21 3 7 .5K 4 .7K 4 .7K 4 .7K R 20 4 N I R 41 R 42 R 53 LIN K 1 LIN K 2 LIN K 3 LIN K 4 DS QE TE S T PDN P M C - Sie rra , I nc . T itl e Et he rne t Pro du c t s P ort lan d, O r eg on , U SA PM3350 24 Port Reference Design Schematic - Phy16-19 S iz e B D a te : D o c u m e nt N um be r T BD S W ed ne s d ay , N ov em b er 05 , 1 99 7 he et 13 of 15 R ev 1. 1 U9 U10 LXT 944QC T CLK5 T XD23 T EN23 RXD23 RCLK23 CD23 COL23 25 26 27 29 30 31 32 34 35 37 38 39 40 42 43 45 46 47 48 50 51 53 54 55 56 4.5K 74 24 T CLK T XD1 T XEN1 RXD1 RCLK1 CD1 COL1 T XD2 T XEN2 RXD2 RCLK2 CD2 COL2 T XD3 T XEN3 RXD3 RCLK3 CD3 COL3 T XD4 T XEN4 RXD4 RCLK4 CD4 COL4 LOOPBK SYSCLK LEDCFN RBIAS T EST DSQE MD0 MD1 LINK1 LINK2 LINK3 LINK4 PDN LEDL4 LEDC4 LEDR4 LEDT 4 PQFP100_0.026PIT CH 95 T POP1 96 T PON1 10 T PIP1 9 T PIN1 93 T POP2 92 T PON2 8 T PIP2 7 T PIN2 89 T POP3 90 T PON3 6 T PIP3 5 T PIN3 87 T POP4 86 T PON4 4 T PIP4 3 T PIN4 LEDL1 LEDC1 LEDR1 LEDT 1 LEDL2 LEDC2 LEDR2 LEDT 2 LEDL3 LEDC3 LEDR3 LEDT 3 18 17 16 15 23 22 21 20 60 59 58 57 65 64 63 62 R28 NI D6 3 4 1 2 6 5 8 7 R221 R56 R220 R52 390 390 390 390 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R185 R184 R190 R186 R187 R25 R189 R188 R191 R193 R194 R26 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 24.9 24.9 100 C134 120pF C122 120pF C121 120pF C120 120pF 3 4 5 1 2 6 7 8 9 10 13 14 15 11 12 16 17 18 19 20 VCC T X1+ CT 1 T X1RX1+ RX1T X2+ CT 2 T X2RX2+ RX2T X3+ CT 3 T X3RX3+ RX3T X4+ CT 4 T X4RX4+ RX4T G45-1406NX T X1+ NC1 T X1RX1+ RX1T X2+ NC2 T X2RX2+ RX238 37 36 40 39 35 34 33 32 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 J3 8H 7H 6H 5H 4H 3H 2H 1H 8G 7G 6G 5G 4G 3G 2G 1G 8F 7F 6F 5F 4F 3F 2F 1F 8E 7E 6E 5E 4E 3E 2E 1E 8D 7D 6D 5D 4D 3D 2D 1D 8C 7C 6C 5C 4C 3C 2C 1C 8B 7B 6B 5B 4B 3B 2B 1B 8A 7A 6A 5A 4A 3A 2A 1A RJ45X8 PHONEJ/8X T XD22 T EN22 RXD22 RCLK22 CD22 COL22 28 T X3+ 27 NC3 26 T X3- 30 RX3+ 29 RX3T X4+ NC4 T X4RX4+ RX425 24 23 22 21 T XD21 T EN21 RXD21 RCLK21 CD21 COL21 VCC T XD20 T EN20 RXD20 RCLK20 CD20 COL20 R201 R31 NI QUAD_LED R39 NI PHYCLK_2 R203 NI PHYCLK_2B R192 NI 75 76 77 78 68 73 72 R202 28 36 44 52 7.5K T X+19 4.7K 4.7K 4.7K T X-18 RX+18 RX-18 T X+17 T X-17 RX+17 RX-17 T X+16 T X-16 RX+16 RX-16 T X-19 RX+19 RX-19 T X+18 R37 R33 R36 PMC-Sierra, Inc. T itle Ethernet Products Portland, Oregon, USA PM3 350 24 Port Re ference Design Schem atic - Ph y20-23 Size B Date: Document Number T BD Wednesday, Novem ber 05, 1997 Sheet 14 of 15 Rev 1.1 J K1 GN D 1 1N4001 VP VP VP C192 . 01uF D 26 C200 . 01uF C204 . 01uF AL M U C 19 22uF J K2 VC C 1 VC C VP C 58 + 330uF 50V C178 . 01uF C207 . 01uF C196 . 01uF C191 . 01uF R D A C P M UN C O E T B NA N J K A I L A O T L S O A N A AC S C179 . 01uF C177 . 01uF + C206 . 1uF C 14 33uF T AN T C 32 C211 . 1uF 22uF + + C210 . 1uF C 51 22uF + + C209 . 1uF C 44 22uF C208 . 1uF + C230 . 1uF C 25 22uF C238 . 1uF C195 . 1uF C237 . 1uF C194 . 1uF C193 . 1uF C203 . 1uF C190 . 1uF 3 1 2 C202 . 1uF C189 . 1uF C201 . 1uF C188 . 1uF VC C GN D VP VP U 30 LT 1585CT -3. 3-N D 4.6A R g l o p d n p a c n ec . e u at r a o l ne o n t F l p d p m r a s c nd r s e u l a ri a y nd e o a y id . C6 33uF T AN T T P1 GN D 1 + C231 . 1uF C 27 22uF C 15 . 1uF C229 . 1uF T P3 GN D 1 1 + VP VP VP T P 16 T P 7 GN D GN D C235 . 01uF C233 . 01uF C205 . 01uF 1 1 1 T P8 GN D C239 . 01uF C 20 . 01uF C 16 . 1uF C236 . 1uF C 82 . 1uF C 93 . 1uF C102 . 1uF C126 . 1uF C150 . 1uF C 21 . 1uF C 22 . 1uF C 60 . 1uF C199 . 1uF C223 . 1uF C221 . 1uF C180 . 1uF C197 . 1uF C212 . 1uF C244 . 1uF C187 . 1uF C 18 . 01uF C232 . 01uF C234 . 01uF C228 . 01uF T P6 GN D VC C C 67 C217 . 1uF C 71 C222 . 1uF C 94 C2 . 1uF C 66 . 1uF VP VP VP C 43 . 01uF C 45 . 01uF C 24 . 01uF C151 . 1uF C166 . 1uF C219 . 1uF C241 . 1uF C 55 . 1uF C 34 . 1uF C 49 . 1uF C 29 . 1uF C 30 C 52 . 01uF C 31 . 1uF C8 . 1uF C 72 . 1uF C 10 . 1uF C 70 . 1uF C 35 . 01uF C 23 . 01uF C5 . 01uF C 73 . 1uF C7 . 1uF C 74 . 1uF C 28 . 01uF C 26 . 01uF C 69 . 1uF C 68 . 1uF . 01uF . 01uF . 01uF VC C VC C C156 . 01uF C157 22uF + . 01uF C 53 . 1uF C 54 . 1uF C246 . 1uF C 62 . 1uF C 33 . 1uF C 56 . 1uF C 12 . 1uF C 13 . 1uF C 11 . 1uF C164 C 50 22uF + C 59 22uF + C 42 22uF + C 41 22uF + C153 C4 22uF + C1 22uF + C 57 C167 . 1uF C138 . 1uF 22uF + C155 . 1uF . 1uF C159 . 1uF C154 . 1uF C152 . 1uF C158 . 1uF . 01uF C144 . 01uF C140 . 01uF C148 . 01uF C137 . 1uF C145 . 1uF C139 . 1uF C141 . 1uF C149 . 1uF C147 . 1uF C146 . 1uF VC C VC C VC C VC C VC C VC C VC C VC C C129 . 01uF C132 . 01uF T it le S ize C Docum ent Number TB D W ednes day, Novem ber 05, 1997 S heet 15 of 15 R ev 1.1 Dat e: C124 . 01uF C123 . 1uF C131 . 1uF C127 . 1uF C133 . 1uF C130 . 1uF C128 . 1uF C125 . 1uF C111 . 01uF C115 . 01uF C118 . 01uF C113 . 1uF C117 . 1uF C119 . 1uF C116 . 1uF C114 . 1uF C112 . 1uF C110 . 1uF C100 . 01uF C105 . 01uF C 95 . 01uF C 92 . 1uF C101 . 1uF C103 . 1uF C170 . 1uF C 96 . 1uF C106 . 1uF C104 . 1uF C 88 . 01uF C 80 . 01uF C 85 . 01uF C 83 . 1uF C 79 . 1uF C 81 . 1uF C 84 . 1uF C 86 . 1uF C 87 . 1uF C 89 . 1uF C242 . 01uF C243 . 01uF C245 . 01uF C214 . 1uF C 36 . 1uF C182 . 1uF C 17 . 1uF C181 . 1uF C 46 . 1uF C3 . 1uF C213 . 01uF C198 . 01uF C240 . 01uF C227 . 1uF C224 . 1uF C225 . 1uF C171 . 1uF C172 . 1uF C169 . 1uF C 38 . 1uF C218 . 01uF C226 . 01uF C 37 . 01uF C173 . 1uF C186 . 1uF C184 . 1uF C183 . 1uF C220 . 1uF C216 . 1uF C215 . 1uF C165 . 01uF C175 . 01uF C185 . 01uF C162 . 1uF C168 . 1uF C161 . 1uF C160 . 1uF C163 . 1uF C176 . 1uF C174 . 1uF P ortland, O regon, US A E t hernet P roduc ts P M C-S ierra, Inc . PM 3350 24 Por t R efer ence D esig n Sc hematic - Boar d Power PMC-Sierra, Inc. REFERENCE DESIGN PMC-970391 ISSUE 1 ADVANCE PM3350 ELAN 8x10 24-PORT 10 MBIT/S ETHERNET SWITCH CONTACTING PMC-SIERRA PMC-Sierra, Inc. Ethernet Products Division 9400 SW Gemini Dr. Beaverton, OR 97008 Telephone: 503 520-1800 Facsimile: 503 520-1700 Document Information: Product Information: Applications information: Web Site: document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com ____________________________________________________________________________________________ Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of thirdparty rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1998 PMC-Sierra, Inc. PMC-970391 Issue 1 Printed in USA Issue date: April 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 |
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