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DATA SHEET
MICRONAS
VSP 94x2A PRIMUS Powerful Scan-Rate Converter including Multistandard Color Decoder Version B13/B14
Edition Aug. 16, 2004 6251-552-1DS
MICRONAS
VSP 94x2A
Contents Page 4 5 7 7 7 7 8 9 9 12 13 14 14 15 15 15 16 16 16 16 16 16 17 17 17 19 19 21 21 21 22 24 24 25 26 26 26 27 27 28 28 29 30 30 30 32 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6. 2.2.7. 2.2.8. 2.2.9. 2.2.10. 2.2.11. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.4. 2.4.1. 2.4.1.1. 2.4.2. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.5.1. 2.5.5.2. 2.5.5.3. 2.5.5.4. 2.5.5.5. 2.5.6. 2.5.7. 2.6. 2.6.1. Title Introduction Features Functional Description CVBS Front-end Source Select Signal Levels and Gain Control Clamping Synchronization Chroma Decoder Luminance Processing RGB Front-end Source Select Signal Magnitudes and Gain Control Clamping Digital Prefiltering RGB YUV Matrix Contrast, Brightness and Saturation Control of Input Signal Soft Mix Static Switch mode Static Mixer mode Dynamic Mixer mode FBL Activity and Overflow Detection Input Processing Horizontal Prescaler Noise Reduction Noise Measurement Letterbox Detection Output Processing Horizontal Postscaler Panorama Mode Operation Modes Display Processing Peaking Digital Color Transition Improvement (DCTI) Coarse and Fine Delay Oversampling and DAC Output-Sync Controller HOUT Generator VOUT Generator BLANK Generator Background Generator Window Function Digital 656 Input Digital 656 Output Clock Concept Line-locked Clock Generator
DATA SHEET
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DATA SHEET
VSP 94x2A
Contents, continued Page 34 34 34 40 46 52 105 105 106 109 110 112 114 114 117 119 119 121 123 125 126 Section 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 5. 5.1. 6. Title I2C Bus Interface I2C Bus Slave Address I2C Bus Format I2C Bus List in Alphabetical Order I2C Bus Command Table I2C Bus Command Description Specifications Outline Dimensions Pin Connections and Short Descriptions for VSP 9402 and VSP 94121) Differing Pin Connections and Short Descriptions for VSP 9412 Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics General Characteristics I2C Bus Characteristics Application Circuit Application Overview Data Sheet History
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VSP 94x2A
Powerful Scan-Rate Converter including Multistandard Color Decoder Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The VSP 94x2A (PRIMUS) is a new component of the Micronas MEGAVISION(R) IC set in a CMOS embedded DRAM technology. The VSP 94x2A comprises all main functions of a digital featurebox in one monolithic IC. The number of features is limited in favor of a lowcost solution, but no trade-off has been made concerning picture quality. Table 1-1: PRIMUS' versions Version 9402A (B13) 9412A (B14)
1)
DATA SHEET
The family is ideally suited to work in conjunction with the deflection processors SDA 9380 (9402/32) and DDP 3315C (9412/42). In combination with the 'digital TV decoder' MDE 9500, double-scan iDTV is possible. The package is upward pin-compatible to other medium-range and high-end devices of the VSP 94xy family. A 50/60 Hz derivative is also available (9432, 9442). The device comprises a digital multistandard color decoder, an RGB interface with fast-blank capability (SCART), digital ITU656 input, scaling units including panorama, embedded DRAM for upconversion, picture improvements, temporal noise reduction, as well as A/D and D/A converters.
Scan Rate Conversion 100i/120i 100i/120i
Digital Input ()1)
Digital Output ()1)
Analog Output
Input and output cannot be used at same time (pin sharing)
Table 1-2: Hardware Compatibility and Suited Backend ICs Hardware Compatible 1) DDP 3315C VSP 9402A, VSP 9405B, VSP 9435B VSP 9407B, VSP 9437B VSP 9412A, VSP 9415B, VSP 9445B VSP 9417B, VSP 9447B VSP 9425B, VSP 9427B
1)
Suited Backend IC SDA 9380
(No ITU656 input possible)
With some restrictions. Please refer to pin description and/or respective application note
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DATA SHEET
VSP 94x2A
- Scan-rate-conversion * Simple interlaced modes (100/120 Hz): AABB, AAAA, BBBB (9402A/9412A only) * No scan-rate-conversion modes (50/60 Hz): AB, AA, BB (9432A/9442A only) - Flexible output sync controller * Flexible positioning of the output signal * Flexible programming of the output sync raster * `Blank signal' generation - Signal manipulations * Still field * Insertion of colored background * Windowing * Vertical chrominance shift for improved VCR picture quality - Sharpness improvement * Digital color transition improvement (DCTI) * Peaking (luminance) - Three D/A converters * 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output * 72 MHz clock frequency * Two-fold oversampling for anti-imaging * Simplification of external analog postfiltering - 1920 active pixel/per line in default configuration - I2C-bus control (400 kHz) * Selectable I2C address - 1.8 V 5% and 3.3 V 5% supply voltages - PMQFP80-1 package
1.1. Features - Integrated video matrix switch * Up to seven CVBS inputs, up to two Y/C inputs, * Three CVBS outputs (Y/C inputs signals are combined to CVBS output format) * 9 bit amplitude resolution for CVBS, Y/C A/D converter * AGC (Automatic Gain Control) - Multi-standard color decoder * PAL/NTSC/SECAM including all substandards * Automatic recognition of chroma standard * Only one crystal necessary for all standards - RGB-FBL or YUV-H-V input * 8 bit amplitude resolution for RGB or YUV * 8 bit amplitude resolution for FBL or H - ITU656 support (version dependent, refer to next chapter) * ITU656 input/output * DS656 output (double-scan `656-like' output) - Letterbox detection - Noise reduction * Temporal noise reduction * Field-based temporal noise reduction for luminance and chrominance * Different motion detectors for luminance and chrominance or identical * Flexible programming of the temporal noise reduction parameters * Automatic measurement of the noise level - Horizontal scaling of the 1fH signal * Split-screen possible with additional PiP or Text processor - Flexible digital horizontal scaling of the 2fH signal * Scaling factors: 3, ..., 0.75 including 16:9 compatibility * 5 zone panorama generator - Embedded memory * On-chip memory controller * Embedded DRAM core for field memory * SRAM for PAL/SECAM delay line - Data format 4:2:2 - Flexible clock and synchronization concept * Horizontal line-locked or free-running mode * Vertical locked or free-running mode
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bin1 41 YUV
(26) U Y U,V Insert (30) (34) (33) UVin V
Down Sampling
Main
GAIN ADCG or Bypass
(25)
Anti-alias, Deskew
Clamping Correction
fbl1
U,V Saturation
37
(13)
(18)
(22)
2
Soft-mix UV Noise Reduction
(37)
Channel Mux (31) Hprescaler H/VAcquisition
Yin (38)
Y Noise Reduction
data buffer
data buffer
6
h50 v
14 69 70 18 20
cvbso1 v50
cvbso2 cvbso3
reset
xout
xin
63
62
61
24
cvbs1 52
Clamped, filterd sync signal 648 MHz clk
GAIN
AGC generator
xtal Oscillator Divider
(20.25, 40.5 MHz) 23 17 Output Sync BLANK (9)
cvbs2 53 Sync
(6) clamping signals to ADCs
ADC1 vout hout H V Y Delay
(8) (10) (36, 72 MHz) U,V Y (11)
CVBS/Y 216 MHz clk Line-locked (40)
(2)
Notch Deskew LL-PLL Divider 648 MHz DTO Line-locked Clocks
Freerunning Clocks
27
cvbs3 54 Delay Control
(PAL/SECAM) (7)
(4)
Output Sync Controller
clkout
VSP 94x2A
cvbs4 55
Source Select
GAIN
Fig. 1-1: Block Diagram
1H Delay Letterbox Detection
(55) Read Control (39) (58)
75
cvbs5 56
Input Sync
(1)
ADC2
C
Color Decoder
(3)
(5)
YCSEL
cvbs6 57
Output Data Controller Memory Controller
941xA, only
cvbs7 58
CLAMP
i656iclk
76
rin1
Y
39
GAIN RGB
Y Brightness Contrast
eDRAM
ADCR
Anti-alias, Deskew
Clamping Correction
i656i0
77
gin1 40
(12)
(17)
(21)
Noise Measure ment (32)
i656i1
78
i656i2
79
rin2 4:2:2
46
Source Select 4:4:4
i656i3
80
(16)
GAIN ADCB
(28) F (27) (29) FB
Anti-alias, Deskew
Clamping Correction
i656i4
1
gin2 47 Offset, Gain
(14)
(19)
(23)
i656i5
2
bin2 48
GAIN ADCF
Anti-alias, Deskew
i656i6
3
fbl2
38
(15)
(20)
CLAMP to 656decoder
i656i7
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Panorama Generator (43) Background Generator (57)
656clk 9
CLKB36
656io0 32
GAIN Peaking
(45)
940xA, only Coarse Delay 4:4:4 DCTI
(46) (49)
656io1 31
Hpostscaler
(42)
PRIMUS (B13/B14) VSP 94x2A
Pixel Mixer
(44)
8:8:8
(50)
Y DAC (52) OFFSET Fine Delay GAIN U DAC (53) OFFSET
2
ayout
656io2 30
656io3 22
ITU656 Decoder
656io4 21
(41)
79
auout
656io5 16 IC Interface
(56)
BLANEN
BLANK
8
656io6 15
ITU656 Encoder
(51)
GAIN V DAC (54)
76
CLKF20
TestController, Memory Bist
avout
656io7 10
19 6 13
CLKF2PAD
(55)
Line-locked or Freerunning
OFFSET
74
8
71
7
656hin/ 656vin/ clkf20 blank adr/tdi sda scl
tclk
tms
DATA SHEET
Micronas
DATA SHEET
VSP 94x2A
can be looped back to output CVBSO1-3 (CVBOSEL1, CVBOSEL2, CVBOSEL3). A signal addition is performed to output a CVBS signal even when separate Y/C signals are used at input. Inputs that are not used are roughly clamped to fit in the allowed voltage region. For stand-by operation (powerdown mode), A/D and D/A converter are switched off by STANDBY keeping the source-selector operational. 2.1.2. Signal Levels and Gain Control To adjust to different CVBS input voltages a digitally working automatic gain control is implemented. Input voltages in the range between 0.6 to 1.8 Vpp can be applied to the CVBS inputs. For best signal-to-noise ratio the maximum available CVBS amplitude is recommended. The AGC behavior can be chosen from four possible modes (AGCMD) (see Table 2-1). Table 2-1: AGC Modes AGCMD 00 AGC Operation Mode AGC uses the height of the sync pulse as a reference and additionally reduces amplification when ADC overflows AGC uses the height of the sync pulse as a reference AGC uses only ADC overflows AGC is disabled and the ADC fits to the values given in AGCADJ1
2. Functional Description All I2C bus registers mentioned are printed in bold and italics (e.g. YCDEL). 2.1. CVBS Front-end The CVBS front-end consists of the color decoding circuit itself, a sync processing circuit for generation of H/ V signals out of the CVBS signal, and the luminance processing. The main task of the luminance processing is to remove the color carrier by means of a notch filter. For PAL and SECAM operation a baseband delay line is used for U and V signals. This can be used as comb filter in NTSC operation (only for chrominance). The RGB input can either be used as an overlay for the CVBS channel (RGB+FBL) or as a full master channel (RGB+H/V). The overlay is done by means of a softmix and can be used e.g. for `SCART' connector. This block contains a matrix (for RGB signals) which is switched off for YUV (e.g. YPbPr) input signals. A CBS (contrast, brightness, saturation) control makes the input signal adjustable. 2.1.1. Source Select Fig. 2-1 shows the analog front-end. The analog CVBS signal can be fed to the inputs CVBS1...7 of VSP 94x2A (amplitude 0.5...1.5 Vpp). One signal is selected via CVBSEL1 and fed to the first ADC. A second signal is selected via CVBSEL2 and fed to the other ADC. CVBS4&5 or CVBS6&7 are intended to be use as separate Y/C inputs (YCSEL). After clamping to the back porch both signals are AD-converted with an amplitude resolution of 9 bit. The AD conversion is done using a 20.25 MHz freerunning stable crystal clock. Before the A to D conversion the signals are lowpass filtered to avoid antialias effects. Three inputs
01 10 11
CVBS 1 CVBS 2 CVBS 3 CVBS 4 / Y1 CVBS 5 / C1 CVBS 6 / Y2 CVBS 7 / C2
C C C C C C C 1 / 9 1 / 9 1 / 9 1 / 9 1 / 9
Clamping pulse of ADC_CVBS1 or ADC_CVBS2. Shifting of signal to required input voltage range for CVBSO1..3
Filter
Filter
Buffer
Buffer C
Buffer
ADC_CVBS1
ADC_CVBS2
CVBSO1
CVBSO2
CVBSO3
Fig. 2-1: Input Selection Micronas 7
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VSP 94x2A
DATA SHEET
511 442 SRY(1V nom.) 144 16 0
upper headroom white CR (1.2V nom.)
511 446 SRC(0.89 V nom.)
upper headroom
100% chroma
75% chroma
burst
256
black
Fig. 2-2: CVBS, Y and C Amplitude Characteristics. When using the sync height based AGC mode, the A/D gain increases or decreases depending on the incoming signal. When using overflow detection only, the gain is set to maximum and is reduced whenever an 'overflow' occurs. The signal is low pass filtered so that chrominance and noise are not used for detection. The threshold can be adjusted by PWTHD. A setting of '11' equals 511 and means an overflow of the ADC. Other settings react for a lower level. The gain only becomes higher when a change of the channel is detected or is manually reset by AGCRES. AGCFRZE holds the current AGC value. A manual setting of the ADCs gain control is possible using the parameters AGCADJ1 and AGCADJ2. The conversion range (CR) is bigger than the signal range (SRY, SRC) leaving a headroom for overshoots (see Fig. 2-2). .
1.9 1.8 1.7 1.6 1.5 Conversion Range [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 8 16 24 32 40 48 56 64
CLMPST1S CLMPD2S CLMPST2 CLMPD2 CLMPST1S CLMPD1S CLMPST1 CLMPD1
Gain Control Characteristic
Fig. 2-3: CVBS ADC Characteristic
burst
64 0
lower headroom
2.1.3. Clamping The timing of the clamping (pulse) control signals for the analog inputs are derived from its corresponding CVBS input signal. The clamping algorithm works with a split measurement pulse and a clamping pulse. The measurement pulse is used to detect the clamping error. The clamping pulse is used to enable current sources for reducing the detected clamping errors. The start and length of the measurement signals are independently adjustable for both channels (CLMPST1, CLMPD1, CLMPST2, CLMPD2). The same applies for the clamping signals (CLMPST1S, CLMPD1S, CLMPST2S, CLMPD2S). Clamping and measurement signals for RGB channel are not separate. Clamping for these ADC are controlled by CLMPST2S and CLMPD2S only. Clamping can be suppressed for some lines by CLMPLOW and CLMPHIGH to ignore copyprotection information. No external sync signals are required.
Measurement ADC1 Clamping ADC1
Measurement ADC2
AGCADJ1, AGCADJ2 (IC)
Measurement and Clamping RGBF Clamping ADC2
Fig. 2-4: Clamping Signals
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DATA SHEET
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Table 2-2: Clamping Adjustment
Signal CLMPST1 CLMPD1 CLMPST1S CLMPD1S CLMPST2 CLMPD2 CLMPST2S CLMPD2S Description Measurement pulse start for ADC1 Measurement pulse duration for ADC1 Clamping pulse start for ADC1 Clamping pulse duration for ADC1 (Measurement pulse start for ADC2) (Measurement pulse duration for ADC2) Measure and clamp start for RGBF-ADC (clamping start for ADC2) Measure and clamp duration for RGBF-ADC (clamping duration for ADC2
2.1.4. Synchronization After elimination of the high frequent components of the CVBS signal by a low pass filter, horizontal and vertical sync pulses are separated. Horizontal sync pulses are generated by a digital phase locked loop. The time constant can be adjusted between fast and slow behavior in four steps (PLLTC) to accommodate different input sources (e.g. VCR). The time-constant can be changed during normal operation without visible picture degradation. A fine tuning of the PLL time constant can be done by NSRED. Additional weak input signals from a satellite dish ('fish') become more stable when SATNR is enabled. Vertical sync pulses are separated by integration of equalizing pulses. A vertical flywheel mode improves vertical sync separation for weak signals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs may be gated by VTHRL and VTHRH to reject invalid v-syncs (independently adjustable for 50 and 60 Hz sources) if no input signal is connected the device switches to a freeruning mode. The device can be configured to switch-on background color when no or only a weak signal is applied (NOSIGB). 50 Hz or 60 Hz operation for sync separation may be forced separately or selected to work automatically (FLNSTRD).
2.1.5. Chroma Decoder The digital multistandard chroma decoder is able to decode NTSC and PAL signals with a subcarrier frequency of 3.58 MHz and 4.43 MHz (PAL B*/N/ 60,NTSC M/4.4) as well as SECAM signals with automatic standard detection. Alternatively a standard can be forced. The demodulation is done with a regenerated color-carrier. To enable a factory adjustment of the crystal frequency, the frequency of the regenerated subcarrier can be adjusted via SCADJ. For this purpose the crystal deviation (SCDEV) can be read out via I2C after chroma PLL locking (indicated by SCOUTEN) and can be stored in C ROM for SCADJ. For test purposes, CPLLOF allows the opening of the chroma PLL loop. For adjustment to the specific operational area an automatic norm detection is selectable. Available 50 Hz color standards are PAL B, PAL N and SECAM. Available 60 Hz color standards are NTSC M, PAL M, PAL60 and NTSC44. For each line standard, one or more color standards can be enabled for automatic chroma standard detection. Please refer to Table 2- 3: and Table 2-4: for allowed combinations. The standard detection process can be set to slow or fast behavior (LOCKSP). In slow behavior, 25 fields are used to detect the standard, whereas 15 fields are used in fast behavior. If the detection was not successful during this time frame, the system will switch to the next enabled TV Standard.
* PAL B is representative for PAL B/G/H/I/N PAL60 and NTSC44 are nonstandard signals which are generated by some VCR or DVD player
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Table 2-3: Allowed combinations for color-standard search (50 Hz)
Standard (50 Hz) None PAL N PAL B SECAM Automatic PAL BG / SECAM D2 0 0 0 1 1 CSTAND D1 D0
DATA SHEET
ACCFRZ holds the current ACC value. The maximum amplification of the ACC can be limited by ACCLIM. This results a smooth attenuation of color intensity for weak color carrier (see Fig. 2-5).
0 0 1 0 1
0 1 0 0 0
U,V
+0dB
CON
color off
Table 2-4: Allowed combinations for color-standard search (60 Hz)
Standard (60 Hz) PAL M NTSC M NTSC44 Automatic PAL M / NTSC M Automatic NTSC M / NTSC44/PAL60 D6 0 0 1 0 1 CSTAND D5 0 1 0 1 1 D4 1 0 0 1 0 D3 0 0 0 0 0(!)
+6dB
-4dB
CKILL ACCLIM
attenuation of color-carrier
PAL, NTSC operation
U,V
+0dB
CONS
color off +6dB -4dB
CKILLS
attenuation of color-carrier
In addition, a standard can be forced as well. AMSTD50 selects whether PAL B or SECAM is tried first in the automatic routine. AMSTD60 selects whether NTSC44/PAL60 or NTSC M is tried first. Both bits can also be set for automatic detection, then the last detected chroma standard will be used. For SECAM detection, a choice between different recognition levels is possible (SCMIDL, SCMREL) and the evaluated burst position is shiftable (BGPOS). Color standard (STDET), line standard (LNSTDRD) and color killer status (CKSTAT) can be read out. An Automatic Chroma Control (ACC) produces a stable output for input chroma variations from (approximately) -30 dB to +6 dB compared to nominal burst value. The ACC reference value is programmable for NTSC and PAL independently (NTSCREF, PALREF) to ensure correct color saturation. With ACCFIX, the ACC is disabled and a constant value (dependent on NTSCREF and PALREF) is used instead.
SECAM operation
Fig. 2-5: Color Killer Adjustment
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DATA SHEET
VSP 94x2A
Damping (dB)
If the chrominance signal is below an adjustable threshold (CKILL (PAL; NTSC) or CKILLS (SECAM)) the color is switched off. To prevent on / off switching, a hysteresis is given by CON or CONS which is the value of switching on the color. COLON switches on the color under any circumstance. The output of the color decoder can be set to UV or CrCb data by CRCB. For NTSC only, the color impression (tint) can be adjusted by the Hue Control between -88 and 90 in steps of 0.7 (HUE). Low chrominance values (+/- 1...3 LSB) may be deleted by UV-coring (UVCOR). The Chroma bandwidth can be adjusted by CHRF. The setting value of CHRF has no linear impact to the chroma bandwidth. The frequency response of the Chroma bandfilter are shown in Figure 2-7. Also a filter with asymmetrical characteristic around the color carrier is available (IFCOMP) (Figure 2-7). For SECAM mode, the de-emphasis filter can be adjusted by DEEMPFIR and DEEMPIIR. The bell filter can be adjusted by BELLFIR and BELLIIR. The delay between Y and C is well aligned and can also be adjusted in steps of 50 ns (YCDEL). No picture shifting occurs when switching between different color standards (e.g. SECAM -> PAL). A delay-line is implemented for PAL and SECAM signals. It acts as a simple chrominance comb-filter for NTSC and can be disabled by COMB. This improves the vertical chroma resolution, but cross-color remains.
5 0 5 10 15 20 25 30 35 40 0
Chroma filter
CHRF='001000' CHRF='001100' CHRF='001001' CHRF='111001'
0.5 1 1.5 2 Frequency (MHz) 2.5
CHRF='001110'
3 3.5 4
Fig. 2-6: Chroma Filter Characteristics
10 5 0
IFCOMP='000'
IF Prefilter
3.58 4.433
IFCOMP='100'
Damping (dB)
5 10 15 20 25 30
IFCOMP='010' IFCOMP='011'
IFCOMP='001'
0
1
2
3 Frequency (MHz)
4
5
6
Fig. 2-7: IF Prefilter
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VSP 94x2A
2.1.6. Luminance Processing A luminance notch filter is implemented to separate the chroma information from the luminance. Depending on the color standard, one out of three different notch characteristics is chosen (`PAL', `NTSC', `SECAM') automatically. For PAL and Secam the respective notch filters have 5 different characteristics each. The luminance notch filter for NTSC can be set to 4 different filter response curves. They can be selected by NTCHSEL. Alternatively, no notch should be used for Y/C input (NOTCHOFF). The filter characteristics can be found in Figure 2-8. In SECAM operation, the notch filter can be fixed to one frequency or toggle between 4.4 MHz and 4.25 MHz depending on the transmitted color (Dr, Db) (SECNTCH). A simple lowpass-filter can be enabled by LPPOST to further reduce high-frequency noise component from the CVBS signal.
5 0 5 attenuation [dB] 10 15 20 25 30
'000'
DATA SHEET
characteristic for SECAM (4.25 MHz)
4.25
NTCHSEL=
'100' '001' '010' '011'
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
frequency [MHz]
Fig. 2-10: Filter Characteristics for SECAM (SECNTCH='01', 4.25 MHz)
5 0 5
characteristic for Y/C
LPPOST=0 LPPOST=1
5 0 5 attenuation [dB] 10 15 20 25 30
attenuation [dB]
characteristic for NTSC
3.58
NTCHSEL= 'x00' 'x01' 'x10' 'x11'
10 15 20 25 30
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
frequency [MHz]
Fig. 2-11: Filter Characteristics for Y/C mode.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
frequency [MHz]
Fig. 2-8: Filter Characteristics for NTSC, PAL M and PAL N
The black level can be shifted by the parameter LMOFST. This is required to compensate 7.5 IRE offsets in some input signals (e.g. NTSC) The positive or negative offset is added to the Y signal before scaling.
BLANKING
BLACK LMOFST='10' LMOFST='00' LMOFST='11' LMOFST='01'
BLANKING
BLACK LMOFST='10' LMOFST='00' LMOFST='11' LMOFST='01'
5 0 5 attenuation [dB] 10
characteristic for PAL
4.43
NTCHSEL= '000' '100'
Input signals without 7.5IRE offset
'010'
Input signals with 7.5IRE offset
15 20 25 30
'011' '001'
Fig. 2-12: Adjustment of `Black' to `Blankingvalue' at Analog Output.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
frequency [MHz]
Fig. 2-9: Filter Characteristics for PAL B/G, NTSC44, PAL60
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DATA SHEET
VSP 94x2A
YUV including sync or H/V signals. This can be used, for example, for a DVD player or set-top-box. When using H sync from a non CVBS input (e.g. separate Hsync) this must be indicated by HINP. The usage of separate V sync must be set by VINP. The delay of luminance and fast-blank can be adjusted by YFDEL, and chrominance can be delay adjusted by UVDEL. If necessary, a fine adjustment of the fast blank can be set by the parameter FBLDEL.
2.2. RGB Front-end An analog RGB input port for an external RGB or YUV source is available. The incoming signal is clamped to the back porch by a clamping pulse. As the memory is only able to store a 4:2:2 picture, the YUV input signal is downconverted to 4:2:2. There are two operation modes available. The first one uses this input as an overlay input (soft mix). The RGB or YUV signal must then be synchronized to the main CVBS/YC signal. The second so called independent mode uses RGB / Table 2-5: Possible input signals for RGB Front-end Input Signal RGB YUV RGB YUV RGB YUV RGB (incl. sync) YUV (incl. sync)
1)
FBLIN CVBS1) CVBS1) H1) H1) FBL FBL
VIN
Sync Separation Sync on CVBS Sync on CVBS
Remark
Hinp 1 1
Vinp 0 0 1 1 0 0 0 0
V V
Sync on H Sync on H Synchron to CVBS/YC Synchron to CVBS/YC Sync on G (maybe on R/B) Sync on Y
E.g. set-top-box E.g. set-top-box Soft mix Soft mix No external sync No external sync e.g. DVD
1 1 0 0 1 1
Instead of FBL input, CVBS input can be used when Hinp=0
from VINP pin
from CVBS Source select
ADC2
AGCADJ2
256 Data 2
HINP
AGCADJ1
AGCMD
0 1
from CVBS Source select
ADC1
CLMPV1 CLAMPSIGNALS 1
Sync processing
ADCSEL VINP
from RGB Source select
ADCR
AGCADJR CLMPVRB
0
1
DATAR
R Processing
to soft-mix
RBOFFSET
CLAMPSIGNALS2
from RGB Source select
ADCG
AGCADJG CLMPVG
DATAG
G Processing
to soft-mix GOFFSET
from RGB Source select
ADCB
AGCADJB CLMPVRB
DATAB
B Processing
to soft-mix
RBOFFSET
from RGB Source select
ADCF
AGCADJF DCLMPF
DATAF
F Processing
to soft-mix
Fig. 2-13: Signal and Clamping Organization Micronas 13
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2.2.1. Source Select Two inputs are available. The choice between the first or second input is made by RGBSEL.
DATA SHEET
2.2.2. Signal Magnitudes and Gain Control The gain adjustment of the four ADCs can be done with the parameters AGCADJR, AGCADJG, AGCADJB, AGCADJF
255 229
upper headroom
255 229
upper headroom
80 16 0
lower headroom
16 0
lower headroom
Fig. 2-14: Y/RGBF Amplitude Characteristics (with or without sync)
255 240 212 255 240 212 CRUV = 0.8 Vpp
upper headroom
upper headroom
100% U SRUV = 0.7 Vpp
100% V 75% V SRUV = 0.7 Vpp CRUV = 0.8 Vpp
DC Gain Control Characteristic
1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2
128 75% U 44 16 0
lower headroom
128
44 16 0
lower headroom
Fig. 2-15: UV Amplitude Characteristics
1.6 1.5 1.4 1.3 Conversion Range [V]
Gain Control Characteristic
CRY = 0.84 Vpp
ADC output=255 conversion range
1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0 8 16 24 32 40 48 56 64
Conversion Range [V]
1.2
CRY = 1.2 Vpp
SRY = 0.7 Vpp
SRY = 1 Vpp
ADC output=0
AGCADJR, AGCADJG, AGCADJB, AGCADJF (IC)
0
8
16
24
32
40
48
56
64
AGCADJF (IC)
Fig. 2-16: RGB ADC Characteristic, Fast-blank ADC with Clamping (DCLMPF=0)
Fig. 2-17: Fast-blank ADC Characteristic without Clamping (DCLMPF=1)
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DATA SHEET
VSP 94x2A
Table 2-6: Configurations of input signals
Mode YUV, sync on Y YUV, sync on H,V RGB, sync on G RGB, sync on RGB RGB, sync on H,V RGB with fast-blank, synchron to CVBS YUV with fast-blank, synchron to CVBS CLMPVG 80 16 80 80 16 16 16 CLMPVRB 128 128 16 80 16 16 128 GOFST 64 0 64 64 0 0 0 RBOFST 128 128 0 64 0 0 128 DCLMPF Don't care 0 (clamping enabled) Don't care Don't care 0 (clamping enabled) 1 (clamping disabled) 1 (clamping disabled)
2.2.3. Clamping When using the dynamic softmix-mode with fast-blank, clamping of fast-blank input must be disabled by DCLMPF. The analog clamping value of red and blue input (V and U resp.) can be adjusted by CLMPVRB. The analog clamping value of green input (Y resp.) can be adjusted by CLMPVG. Depending on the input signal format (YUV, RGB, sync signal or not) these bits must be set accordingly. On the digital side, a correction of the analog clamping value must be performed to reconstruct the blacklevel. This is achieved by RBOFST and GOFST. (see Table 2-6 on page 15) 2.2.4. Digital Prefiltering A digital prefiltering can be enabled. A band limitation is required, because the following deskewing filter performs best at frequencies of below 14 MHz. The filtering is performed in all four channels and can be disabled by AABYP. For signal conversion to 4:2:2, an additional chrominance lowpass can be enabled by CHRSF. The deskewing filter can be disabled by SKEWSEL. This is necessary when using the H50-pin in connection with a Micronas picture-in-picture device (e.g. SDA 938x, SDA 948x, SDA 958x). In this application, the RGB input (in1, in2, in3) of the PiP can not be used for other RGB/YUV signals (e.g. `SCART' is not possible). As there is a pixel skew on H50, this pin is NOT suited to synchronize any IC, except for the above mentioned PiP ICs Fig. 2-18: Digital Prefiltering of RGB Input 2.2.5. RGB YUV Matrix RGB or YUV signals are selected by YUVSEL. The matrix coefficients are set according to ITU recommendations.
10
RGB-prefiltering
0 attenuation [dB]
3
10
20
30
40
0
5
10 Frequency [MHz]
15
20
Y R 0,299 0,587 0,114 U = G - 0,147 - 0,289 0,436 V B 0,615 - 0,515 - 0,100
Fig. 2-19: RGB to YUV Matrix
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2.2.6. Contrast, Brightness and Saturation Control of Input Signal The YUV signal can be manipulated in order to fit to the main channel. The contrast can be adjusted between 0 and 1.97 in 64 steps (CONADJ). The brightness is adjustable in 255 steps (BRTADJ). Due to the independent chroma adjustment of U and V (64 steps each, USATADJ, VSATADJ), UV as well as CrCb input signals can both be displayed correctly. 2.2.7. Soft Mix The soft-mixer circuit consists of a Fast Blank (FB) processing block supplying a mixing factor k (0... 128) achieving the output function:
DATA SHEET
k = MIXGAIN ( 31 - FBLOFFST ) + 32
All necessary limitation and rounding operations are built-in to fit the range: 0 k 128 Considering MIXGAIN=3, k is obtained by
k = 158 - 3 FBLOFFST
[ limited to 0 and 128]
The mixing is only controlled by FBLOFFST. In the static mixer mode as well as in the previously mentioned static switch mode, the softmixer operates independently of the analog fast blank input. 2.2.10. Dynamic Mixer mode In the dynamic mixer mode, the mixer is controlled by the Fast Blank signal. The VSPA provides a linear mixing coefficient
YUV main ( 128 - k ) + YUV inserted k YUVmix = -------------------------------------------------------------------------------------------128
k= `0' means that only the main signal is fed through to the output. k= `128' means that only the inserted signal becomes visible. The soft mixer supports four modes that are selected by MIXOP and SMOP. Table 2-7: RGB operation modes
MIXOP 00 SMOP 0 Soft Mix mode Dynamic Soft Mix (DECTWO must be set to '1') 00 1 Static Soft Mix (DECTWO must be set to '1') 01 10 11 x x x Only RGB/YUV path visible Only CVBS path visible (Reserved)
MIXGAIN ( FB - FBLOFFST 2 ) k = ----------------------------------------------------------------------------------- + 64 2
The dynamic mode is used for mixing which is dependent on FB input. FB is the preprocessed digitized fastblank input in the range from 0...127. FBL manipulation is done both for luminance and chrominance FBL signal. Fast blank is delay adjustable by FBLDEL in the range of -2...4 clock cycles. 2.2.11. FBL Activity and Overflow Detection It is important to know whether the FBL input is used or not. Therefore a detection circuit gives information via the I2C bus to the microcontroller. The circuit uses the FBL value as input. If it is greater than a threshold for one or five clock cycles (FBLCONF), the I2C register FBLACTIVE is set. This register is reset after a read access by the microcontroller. PFBL, PG, PR, PB indicate an overflow of the corresponding ADC (upper limit: ADC= 255) exceeding 5 clock cycles duration.
2.2.8. Static Switch mode In its simplest and most common application the softmixer is used as a static switch between YUVmain and YUVinsert. This for instance the adequate way to handle a DVD component signal. By using MIXOP, k is internally set to 0 or 128 respectively. 2.2.9. Static Mixer mode The signal YUVmain and the component signal YUVinsert may also be statically mixed. In this environment, k is manually controlled via FBLOFFSET and MIXGAIN. 16
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DATA SHEET
VSP 94x2A
2.3. Input Processing
5
UV decimation filter
3
HSYNC Complete picture area NALPFIP (not active lines input)
0 5 Attenuation (dB) 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VSYNC
Active picture
ALPFIP (Active lines input)
5
Frequency (MHz)
NAPPLIP (not active pixel per line input)
APPLIP (active pixel per line input)
Fig. 2-22: UV-decimation Filter Characteristic for Standard Operation (Decimation=1.5) 2.3.2. Noise Reduction The Fig. 2-23 shows a block diagram of the temporal noise reduction. The structure of the temporal motion adaptive noise reduction is the same for luminance as for chrominance signal. Noise reduction is enabled by NRON. The output of the motion detector is weighted using the parameters TNRCLC and TNRCLY. The look-up table input value range is separated into 8 segments. It is possible to freely program different behavior of the noise reduction by using predefined curve characteristic for each segment. The curve characteristics can be programmed by the parameters TNRSxY for luminance and TNRSxC for chrominance. The curve-start is defined by TNRSSY (TNRSSC) at the end of the last segment (Figure 2-24). The overall curve is now constructed by connecting the end of segment 6 to the beginning of segment 7 and so on. Negative values of Ky (Kc) are not possible and clipped to zero. For chrominance, the result of the luminance motion detector or a separate chorminance motion detector can be used (TNRSEL).
Fig. 2-20: Image Format before Memory 2.3.1. Horizontal Prescaler The main application of the horizontal prescaler is the conversion of the number of pixels coming form the 40.5/20.25 MHz pixel clock domain down to the number of pixels stored in the memory (factor 2/3). Generally the number of incoming pixels can be decimated by a factor between 1 and 64 in a granularity of 2 output pixels. The horizontal scaler reduces the number of incoming pixels by subsampling. To prevent the introduction of alias distortion low pass filters are used for luminance and chrominance processing (Fig. 2-22). In case of ITU656 input, the lowpass filter must be disabled by HAAPRESC. The horizontal prescaler consists of two main subsampling stages. The first stage is a scaler for rational decimation factors in a range of 1 to 2, controlled by HSCPRESC. The second stage decimates in integer steps (1,2,3,4...32), controlled by HDCPRESC.
5 0 5 Attenuation [dB] 10 15 20 25 30 35 40 0 1.25 2.5
Y-decimation filter
3.75
5 Frequency [MHz]
6.25
7.5
8.75
10
Fig. 2-21: Y-decimation Filter Characteristics for Standard Operation (Decimation=1.5)
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DATA SHEET
Yin Ydelay
Motion Detection Y
LUT Y
Ky
Yin Ydelay
Noise Reduction Y
Yout
TNRCLY TNRABS TNRCLC UVin UVdelay
TNRSxY NRON TNRSxC TNRSEL UVin Kuv
Kc
Motion Detection C
LUT C
UVdelay
Noise Reduction C
UVout
Fig. 2-23: Temporal Noise Reduction
TNRSx=0000
TNRSx=0001
TNRSx=0010
TNRSx=0011
TNRSx=0100
TNRSx=0101
TNRSx=0110
TNRSx=0111
TNRSx=1000
TNRSx=1001
TNRSx=1010
TNRSx=1011
TNRSx=1100
TNRSx=1101
TNRSx=1110
TNRSx=1111
Fig. 2-24: Segments of LUT
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DATA SHEET
VSP 94x2A
segment 4 segment 5 segment 6 segment 7 Ky/Kc segment 0 segment 1 segment 2 segment 3 15 14 13 TNRSSY, 12 TNRSSC 11 10 9 8 7 6 5 4 3 TNRSY 2 0001 1111 1111 0100 0100 0100 0000 0000 , 1 TNRSC 0 0 4 8 12 20 28 36 48 64 motion
Fig. 2-25: Predefined Curve Characteristics for LUT 2.3.3. Noise Measurement The noise measurement algorithm can be used to change the parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. This is done by the TV- microcontroller which reads the noise level (NOISEME), and sends different parameter sets to the temporal noise reduction registers of the VSP 94x2A depending on this value (0 = no noise, 126 = strong noise). Value 127 indicates an overflow status which means that the measurement failed. The value is determined by averaging over several fields. The line taken for noise measurement is selected by NMLINE. When NOISEME contains updated data which were not read so far, NMSTATUS is set. NMSTATUS is reset when read. The measurement position can be adjusted (NMPOS) as well as the sensitivity (NMSENSE). 2.3.4. Letterbox Detection A drawback of wide screen 16:9 TV sets are the black bars at the left and the right side on the screen, if displaying a 4:3 source on a 16:9 screen with correct aspect ratio. In case of letterbox source material also black bars at the top and bottom exist. With the help of an expansion algorithm it is possible to expand the letterbox picture vertically and horizontally in such a way, that the letterbox picture will fill the complete screen without loosing information. To do so, the information about the active part of the letterbox picture is necessary. Active part means the information about the first active line and the last active line of the letterbox picture. The figure below shows the principle of this idea. The WSS (Wide Screen Signal) signal contains some information about the picture format (4:3 or 14:9 or 16:9), but not all existing formats are covered and not all signals contain WSS. Therefore a separate algorithm is necessary which delivers the necessary information. The figure below shows the concept of the letterbox detection algorithm. One part of the algorithm is dedicated hardware and located in the VSP 94x2A another part is software and located in the RAM of the TV microcontroller. The part located in VSP 94x2A is called measurement part. The measurement part delivers 5 signals to the controller part.Based on the delivered information the controller part calculates an expansion and a vertical pan factor and sends these values back to the VSP 94x2A for manipulation of the video signal.
4:3 Letterbox Picture
Expanded Letterbox Picture
Fig. 2-26: Handling of Letterbox Pictures on 16:9 Tubes
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DATA SHEET
Hardware (940x) LBSLAA Measurement Part LBELAA LBFORMAT LBSUBTITLE LBTOPTITLE
zooming parameters YUVin
Software
Y
Controller part
Horizontal and/or Vertical Resizing
YUVout
Fig. 2-27: HW/SW Partitioning The letterbox detection block works only at a data rate of 13.5 MHz. Due to the fact, that the input data rate at channel-mux output can be 13.5 MHz, 20.25 MHz or 40.5 MHz, the input signal has to be downsampled. Depending on the I2C bus register LBSUB different modes are possible (Downsample 1, 1.5, 3). As digital 656input data are already in 13.5 MHz format, no downsampling should be used (LBSUB=0). For CVBS, YUV and RGB signals (if DECTWO=1) a downsampling of 1.5 (LBSUB=2) is required. In principle the input picture is separated in one upper and one lower part. The measurement windows are defined by the parameters LBVWSTUP, LBVWENDUP (upper vertical measurement window), LBVWSTLO, LBVWENDLO (lower measurement window) and LBHWST, LBHWEND (horizontal measurement window). A controller software and its description is available upon request.
2*LBVWSTUP
2* LBVWENDUP
2*LBVWSTLO
4*LBHWST 4* LBHWEND
Fig. 2-28: Measurement Windows
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2* LBVWENDLO
DATA SHEET
VSP 94x2A
2.4.1.1. Panorama Mode The picture can be geometrically distorted in horizontal direction for an improved impression in the case of expansions of 4:3 pictures to a 16:9 ratio tube. It is enabled by HPANON. The idea behind this panorama mode is to keep the middle part of the picture in a 4:3 ratio and to stretch the left and the right to fill the entire width of the 16:9 screen. For the adjustment of the expansion process, the picture is divided into 5 segments. For each of these segments the increment value for the expansion factor can be defined separately. Each end of a segment can be defined individually in a granularity of two output pixels. For every segment an increment value can be defined (HINC0...HINC4) which indicates the amount of decimation/expansion. One LSB is equivalent to an offset of 0.125 to HSCPRESC per double pixel. This means that with HINC, HSCPRESC is altered in the range from -32...31.875 per double pixel. The segments are distributed among the maximum number of pixels, which is adjusted by PPLOP. The first four segments are defined by (HSEG1...HSEG4). The last one goes from HSEG4 to PPLOP.
2.4. Output Processing 2.4.1. Horizontal Postscaler After main memory, the display processing is performed using a different clock. In this way a decoupling of input and output clocks is achieved. The conversion to the display clock is done by an interpolation filter. This can be used for horizontal expansion in the range of 1...4 in steps of 2 pixels (HSCPOSC). Due to increased clock frequency in the backend part, the realized horizontal scaling factor depends on backend clock frequency. Usually (36 MHz operation), the horizontal expansion factors result as 0.75...16. This ensures that the factor 0.75 gives no loss of resolution (to show a 4:3 picture on a 16:9 tube). When using DS656 output, neither horizontal compression nor horizontal panorama is possible due to 27 MHz clock. Table 2-8: Horizontal expansion factors
HSCPOSC Horizontal Filter Expansion 4 1.33 1 Overall Expansion CLKB36= 27 MHz 4 1.33 1 CLKB36= 36 MHz 3 1 0.75
1024 (min.) 3072 4095
INC_VAL 31.875 HINC0 HINC1 HINC2 0 HINC3 HINC4 output pixels
Because of the nonlinear characteristic and integer number of pixel, sometimes different HSCPOSC values result in the same decimation factors.
-32 0 HSEG1 HSEG2 HSEG3 HSEG4 max.
HSCALE
3.5 1024 3
Horizontal Postscaler
4095 3
4095 compression
3072
expansion
Overall Expansion 2.5 2
HSCPOSC (IC)
1024
1.5
0
1 0.5 0.75
HSEG1
HSEG2
HSEG3
HSEG4
max.
output pixels
Fig. 2-30: Visualization of Panorama Segments
0 1000 2000 HSCPOSC(IC) 3000 4000
Fig. 2-29: Expansion Factor of Horizontal Postscaler Dependent on HSCPOSC
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Table 2-9: Examples of Panorama Mode Function HSCPOSC HSEG1 HSEG2 HSEG3 HSEG4 HINC0 HINC1 HINC2 HINC3 HINC4 APPLOP Panorama 2099d 96d 192d 288d 384d 40d 20d 000d 492d 472d 960d Extreme Pan. 1023d 96d 192d 288d 384d 85d 43d 000d 469d 427d 960d Lens 3999d 96d 192d 288d 384d 472d 492d
FRAME
DATA SHEET
Table 2-9 on page 22) describes the different scan rate conversion algorithms of VSP 94x2A and the corresponding raster sequences. Fig. 2-32 on page 23 explains the 50/60 Hz interlaced to the 100/120 Hz interlaced conversion including the field signal, the raster organization and the memory timing for AABB. A still field can be displayed using FREEZE command. For the improvement of VCR signals, the chrominance can be shifted one line upwards by CHRSHFT
FRAME/FIELD
FIELD A odd lines
000d 20d 40d 960d
Content of picture
FIELD B even lines
2.4.2. Operation Modes There are four operation modes defined. The first mode is simple AABB, where each stored field in the memory is displayed double times on the TV screen. The second and third mode are AAAA and BBBB, in which only one field phase will be displayed on the TV screen. There is also a fourth mode AAAA mode with raster possible. Fig. 2-31 explains the picture and the display raster. The interlaced input signal (e.g. 50 Hz PAL or 60 Hz NTSC) is composed of a field A (odd lines) and a field B (even lines). An - Input signal, field A at time n, Bn - Input signal, field B at time n The field information describes the picture content. The output signal, which could contain different picture contents (e.g. field A, field B), can be displayed with the display raster or . (An,) - Output signal, field A at time n, displayed as raster , (An,) - Output signal, field A at time n, displayed as raster ,
DISPLAY LINE-SCANNING PATTERN
TV Display raster odd lines Display line-scanning pattern
even lines
Display line-scanning pattern
Tube, Display raster
Fig. 2-31: Explanation of Field and Display Linescanning Pattern
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DATA SHEET
VSP 94x2A
Table 2-10: Operation modes for scan-rate conversion Input Field A STOPMODE 00 01 10 11 Scan-Rate Conversion AABB mode AAAA mode AAAA mode BBBB mode Output Field Phase 0 An, An, An, Bn-1, Output Field Phase 1 An, An, An, Bn-1, Input Field B Output Field Phase 2/0 Bn, An, An, Bn, Output Field Phase 3/1 Bn, An, An, Bn,
Line number of memory
An
Bn
An+1
Write
time An+1
OPDEL
An
An
Bn
Bn
An+1
Read
raster_org
n n n n n+1 n+1
field
Fig. 2-32: 50/60 Hz Interlaced to 100/120 Hz Interlaced Conversion (AABB)
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2.5. Display Processing The display processing part contains an integrated triple 9-bit DAC and performs digital enhancements and manipulations of the digital video component signal. Fig. 2-35 shows the block diagram of the display processing part. 2.5.1. Peaking The luminance peaking filter improves the overall frequency response of the luminance channel. It consists of two filters working in parallel. They have high pass (HP) and band pass (BP) characteristics. Their gain factors are programmable separately (BCOF, HCOF). Values greater than 4 peak the signal, whereas values less than 4 attenuate the signal. The high pass and the band pass filters are equipped with a common coring algorithm. It is optimized to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio. Therefore no artifacts are produced. Coring can be switched off (YCOR). The Fig. 2-34 shows the block diagram of the peaking block.
DATA SHEET
The peaking filter clock frequency is CLKB36=36 MHz (27 MHz). The maximum signal frequency of the picture stored in the memory is 6.75 MHz. Due to a peaking after postscaler, the frequency range of the peaking filter varies with the expansion factor of the postscaler.
15
Peaking filter characteristic
BCOF
10
HCOF
gain[dB]
5
0
5
0
0.1
0.2
0.3
0.4
0.5
normalized Frequency (B)
Fig. 2-33: Peaking Filter: Bandpass and Highpass filter
BP
GAINB coring
HP
Peak_in
GAINH
Peak_out
AP
Fig. 2-34: Block Diagram Peaking
9402/9432 only
YCOR, HCOF, BCOF
COARSEDEL
CHROMAMP
FINEDEL
PKLY, PKLU, PKLV,
Yin
Peaking
Delay
Y
Coarse Delay 8:8:8
Fine Delay
DAC
ayout auout avout
656out 656clk
U Cin
DCTI 4:4:4
DAC
V
THRESHC, ASCENTCTI
DAC
8 ITU656 Encoder
SHIFTUV, DPOUT656
Fig. 2-35: Block Diagram of Display Processing 24 Micronas
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DATA SHEET
VSP 94x2A
2.5.2. Digital Color Transition Improvement (DCTI) A digital algorithm is implemented to improve horizontal transitions of the chrominance signals resulting in a better picture sharpness. A correction signal proportional to the slope of the detected horizontal transition of the input signal is added to the original input signal. The amplitude of the correction signal is adjustable by the I2C bus parameter ASCENTCTI. The IC bus parameter THRESHC modifies the sensitivity of the DCTI circuit. High values of THRESHC result in an improvement of significant color transitions only.
Table 2-11: Conversion table between HCOF/BCOF and GAINHP/GAINBP BCOF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GAINBP -1 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.50 3.00 4.00 HCOF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GAINHP -1 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.50 3.00 4.00
Table 2-12: Peaking filter adaption for 36 MHz or 27 MHz operation Expansion Factor of Postscaler Corresponding Frequency of Input Signal for Center Frequency Bandpass (B=0.25) CLKB36=36 MHz/27 MHZ 0.75 ... 1 ... 3 3.375 MHz / 2.5 MHz ... 4.5 MHz / 3.375 MHz ... 13.5 MHz / 10.125 MHz Corresponding Frequency of Input Signal for Center Frequency Highpass (B=0.5) CLKB36=36 MHz/27 MHZ 6.75 MHz / 5.06 MHz ... 9 MHz / 6.75 MHz ... 27 MHz / 20.25 MHz
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2.5.3. Coarse and Fine Delay Before digital-to-analog conversion an adjustment of the phase of the luminance is performed. A coarse delay from -8 to +7 in steps of 1 pixel CLKB36 (~28 ns) is possible (COARSEDEL). FINEDEL shifts the luminance one CLKB72 (~14 ns) pixel. This can be used to compensate delays, if the external processing of Y and UV produces different delays (e.g. external lowpass filtering). 2.5.4. Oversampling and DAC After conversion into 8:8:8 format (CLKB72=72 MHz), three 9-bit digital-to-analog converters are used for analog YUV output. This twofold-oversampling generates 1920 active pixels per line (when using recommended settings) and simplifies the external postfiltering. The output voltage is determined by PKLY, PKLU and PKLV and can be set in a range of 0.4 V ...1.9 V (fullscale). 8 bits of the luminance D/A converter are used for the entire signal. The 9th bit is used for over- and undershoots caused by the peaking to prevent or reduce clipping artifacts. As the CTI block seldomly produces such overshoots, a full-scale operation can be activated by CHROMAMP. The output voltages may be calculated by:
DATA SHEET
PKLY 128 LSB upper headroom for peaking 9 bit conversion range 0V
max. 0.9 V
max. 1.9 V
240 LSB normal signal range
16 LSB
'black'
128 LSB lower headroom for peaking
PKLU PLLV CHROMAMP=1 9 bit conversion range
max. 0.95 V
max. 1.9 V
CHROMAMP=0 'no color'
Fig. 2-36: DAC Output Signals
PKLY VoltageY = 1.56V -------------- + 0.36V signalY 256
2.5.5. Output-Sync Controller The output sync controller generates horizontal and vertical synchronization signals for the scanrate-converted output signal. The number of pixels per line is 4*PPLOP. The default value of 288 results in 1152 pixels/line. With CLKB= 36 MHz, the horizontal output frequency is 31.25 kHz, which is twice the PAL horizontal frequency. Out of these pixels, 16*APPLOP are displayed as active picture area, which are 960 by default. The position on the screen depends on the NAPPLOP. It marks the picture area not active in horizontal direction and moves the active picture in horizontal direction. The number of lines per field is 2*LPFOP. This value is only used in the vertical freeruning mode. In vertical locked mode, the number of lines per field is derived from the CVBS signal itself and not adjustable. The active and non-active picture areas are marked by ALPFOP and NALPFOP, respectively. Both generators have a so called `locked-mode' and `freeruning-mode'. Not all combinations of these modes make sense. Table 2-13 on page 27 shows ingenious configurations.
160....400 signalY = ----------------------512
[for unpeaked signals max.]
signalY = 0....511 ----------------512
[for peaked signals max.]
PKLU, V VoltageU, V = 1.56V ---------------------- + 0.36V CHROMAMP signalUV 256
signalUV = 128....384 ----------------------512
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DATA SHEET
VSP 94x2A
derived from the CVBS signal, to enable a soft transition to locked mode (PDGSR, LPFOPFF). This synchronization is only possible when the number of CVBS input lines corresponds to the programmed value of LPFOP.
LPFOP (lines output)
HSYNC Complete picture area NALPFOP (not active lines output) ALPFOP (Active lines output)
Active picture
APPLOP (active pixel per line output) PPLOP (pixel per line output)
When no or very weak signal is connected to the CVBS input, the IC can be configured to automatically switch into freerunning mode. This stabilizes the display which may contain OSD information, e.g. during channel-tune. The configuration, whether the IC switches to H-freerun, V-freerun or both can be configured by AUTOFRRN 2.5.5.1. HOUT Generator The HOUT generator has two operation modes, which can be selected by the parameter HOUTFR. The HOUT signal is active high for 64 clock cycles (CLKB36). In the freerunning-mode the HOUT signal is generated depending on the PPLOP parameter. In the locked-mode the HOUT signal is locked on the incoming H-Sync signal derived from CVBS. The polarity of the HOUT signal is programmable by the parameter HOUTPOL. 2.5.5.2. VOUT Generator The VOUT generator has two operation modes, which can be selected by the parameter VOUTFR. In the freerunning-mode (VOUTFR=1) the VOUT signal is generated depending on the LPFOP parameter. In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal derived from CVBS, delayed by some lines (OPDEL). During one incoming V-Sync signal, two VOUT pulses have to be generated. The polarity of the VOUT signal is programmable by the parameter VOUTPOL. The VOUT signal is active high for two output lines..
Fig. 2-37: Image Format behind Memory For freerun mode the backend part works stand alone without analyzing the input signals. The clock domains, input data part and output data part of the IC, are not synchronized to each other. If the output processing works in the freerun mode, the output signals of the OSC are generated depending on I2C-bus settings. For locked mode the backend part works with a line locked clock. This means that the front-end and the backend of the IC are synchronized to each other. The generation of the controlling signals depends on output signals from the front-end. This mode will be the default and the most used mode for standard TV applications. With activated vertical freerun mode the phase of the generated vsync signal has no correlation to the incoming vsync signal. A hard switch from freerun mode to locked mode would therefore cause visible synchronization problems in the deflection unit of the TV set concerning the vertical picture positioning. To avoid these problems a circuit is implemented which synchronizes the freerunning vsync signal to the vsync
Table 2-13: Ingenious configurations of the HOUT and VOUT generator Mode `H-and-V-locked' mode `H-freerunning / V-locked' mode `H-and V freerunning' mode HOUTFR 0 1 1 VOUTFR 0 0 1
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2.5.5.3. BLANK Generator The BLANK signal is used to horizontally and vertically mark active picture area. It is enabled by BLANEN and its polarity can be chosen by BLANPOL and VBLANPOL. Referred to hsync, the start is given by BLANDEL and its length is given by BLANLEN, both adjustable with 4 pixel resolution. Referred to vsync, the start is given by VBLANDEL and its length is given by VBLANLEN, both adjustable in 1 lines resolution. 2.5.5.4. Background Generator This generator is able to realize an automatic closing and opening of the displayed picture. This means that with every picture the displayed colored background, defined by UBORDER, VBORDER and YBORDER will get bigger or smaller. The original picture data will Table 2-14: Display line scanning pattern sequence Display Line Scanning Pattern Sequence aaaa bbbb aabb abab 1. to 2. 312 313 312 312.5 2. to 3. 313 312 312.5 312.5 3. to 4. 312 313 313 312.5
DATA SHEET
be replaced by the background values and vice versa. There is also the possibility to realize a fixed border via the IC bus (BORDPOSH and BORDPOSV). 4096 different colors are available. BORDPOSH and BORDPOSV also influence the window generation. This means the automatic opening and closing of the picture will start or end at the position which is defined with these values. The border is calculated with the following formula: The horizontal border on the left side of the TV screen is 2*BORDPOSH and 2*BORDPOSH on the right side of the TV screen. This means, that 4*BORDPOSH pixels are overwritten with border values. The same applies to the vertical direction. 4*BORDPOSV lines in total are overwritten with background values. BORDERV decides whether upper or lower or both borders are displayed. BORDERH decides whether left or right or both borders are displayed.
4. to 5.(1.) 313 312 312.5 312.5
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WINDHDR. To change from close" to open" or vice versa only the WINDHDR parameter has to be toggled. The speed of the window can be defined by the WINDHSP parameter. Fig. 2-39 shows the functionality of the vertical window function. All settings are also available in vertical direction. All I2C parameters exist for both directions (e.g. WINDHON and WINDVON for horizontal and vertical window enabling). Combinations of both window functions (horizontal and vertical) are also possible.
2.5.5.5. Window Function Fig. 2-38 shows the functionality of the horizontal window function. The window can be closed or opened. The windowing feature can be enabled by the WINDHON parameter. The WINDHST and the WINDHDR parameter determine, what status (opened or closed) the window has, and what can be done with the window (open or close). With each enabling of the window function by the WINDHON parameter, the status of the window will be as defined by WINDHST and
Fig. 2-38: Horizontal Windowing
close window
open window
Fig. 2-39: Vertical Windowing
close window
open window
Fig. 2-40: Horizontal and Vertical Windowing
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2.5.6. Digital 656 Input The IC decodes a digital 8 bit@27 MHz data stream according to ITU.BT656 standard. The configuration is set by EN_656. and DPOUT656. Table 2-15: 656 input / output selection EN_656 0 0 1 1 DPOUT656 0 1 0 1 656 Operation Input disabled/ output disabled Input disabled/ output enabled Input enabled/ output disabled Input enabled/ output disabled (9412A only) 2.5.7. Digital 656 Output
DATA SHEET
Dependent on version (single- or double-scan), the output data format corresponds to CCIR 656 (8-bit bus at a data rate of 27 MHz) or has double-scan format (8-bit bus at a data rate of 54 MHz). There all frequencies and data-rates are doubled compared to standard CCIR656 specification. Double scan format is intended to be used with a suited backend device, e.g. DDP3315C. Timing reference codes (SAV, EAV) are inserted according to the specification. The output can be enabled by DPOUT656. The output should be set to 720 pixels per line (APPLOP) and the display clock should be set to 27/54 MHz (refer to Chapter 2.6.). The chrominance information can be inverted by CHRMSIG656. HOUT and VOUT pins may be used in parallel. 2.6. Clock Concept A single 20.25 MHz crystal at fundamental mode is used as clock reference. All other clocks are derived from this source. The CVBS front-end works with 20.25 MHz, the RGB front-end works with 40.5 MHz, the oversampling DACs use CLKB72 and the memory and all parts behind the memory are clocked with CLKB36. The frequency of CLKB36 and CLKB72 is adjustable and depends on application. With analog output, CLKB72 is usually 72 MHz and with digital output, CLKB72 is usually 54 MHz. CLKB72 is always twice of CLKB36. Three different clock concepts are supported. The difference is the behavior in clocking the memory output. The front-end part of the VSP 94x2A uses a freeruning but crystal-stable clock (CLKF). After deskewing, an orthogonal picture is written into the memory. The read out is done using the (CLKB) clock. The horizontal sync-signal output (HOUT) is derived from a counter running with CLKB. The VOUT is directly derived from the input vertical signal, which is generated by the sync-separation block. This `H-freerunning-V-locked mode' is only possible together with a DC coupled deflection controller. In `H-and-V-locked mode' CLKB is line-locked to the incoming signal. The freerunning YUV picture data and the internal H signal are converted to the linelocked domain. Now HOUT and the sync signal in the 1fH domain are directly coupled. In case of `H-and-V-freerunning mode' the HOUT and VOUT signals are derived from counters running with CLKB. There is no connection to the incoming signal. This mode can be used for stable pictures when no signal is applied (e.g. channel search with OSD insertion).
Four input modes are supported: Table 2-16: 656 modes IMODE 00 656 Operation Full ITU mode (automatic) Information about active picture is taken from data-stream 01 Full ITU mode (manual) Information about active picture is taken from APPLIPI, NAPPLIPI, ALPFIPI, NALPFIPI 10 11 ITU656 only data, H/V-sync according PAL/NTSC ITU656 only data, H/V-sync according ITU656
To adjust the input to sources, which deviate from the standard, the field information may be inverted (F_POL) and the chrominance format can be chosen between unsigned and 2's complement format (CFORMAT). The polarity of H an V can be inverted by H_POL and V_POL respectively. Dependent on version, the digital input must be selected by ITUPRTSEL (pins i656i or 656io).
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with this sampling clock. The clock output can be disabled by CLKOUTON. Additionally a 20.25 MHz clock can be output to pin 74 (656hin/clkf20) to supply other ICs (e.g. PiP) with the same clock (CLKF2PAD). When enabled, 656-input with separate H/V-sync is not possible. For 656-output operation, CLKB36 is given to pin 9 (656clk).
The selection between freerunning and locked clocks may be forced or selected to be dependent on PLL conditions. Please refer to Fig. 2-41 A clock output of 27 MHz (single-scan version:13.5 MHz) is possible (pin 27:clkout). This clock is 3/4 of CLKB36. HOUT and VOUT are in line Table 2-17: Clock system Name Clock Nominal Frequency
`H-/Vlocked' Mode FR FR LL LL LL
`H-freerunningV-locked' Mode FR FR FR FR FR
`H-/Vfreerunning' Mode FR FR FR FR FR
CLKF20 CLKF40 CLKB36 CLKB72 CLKB27
CVBS front-end RGB front-end, input processing Output and display processing Oversampling, DAC CLKOUT-pin
20.25 MHz 40.5 MHz 9402: 36 MHz (analog out) 9412: 27 MHz (digital out) 9402: 72 MHz 9412: 54 MHz 9402: 27 MHz 9412: 20.25 MHz
Front-end PLL
CVBS
STAB=0 and AUTOFREERUN=1x
Freerun Generator
freerunning clocks SETSTABLL
0 1 0 1 1 0
HOUTFR
yes no
CLKBxx
LL-PLL
locked clocks STABLL
(indicates PLL stability)
Fig. 2-41: Conditions for Freerunning/Locked Switching
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2.6.1. Line-locked Clock Generator The clock generation system derives all clocks from one 20.25 MHz crystal oscillator clock source. An internal PLL multiplies this oscillator frequency by 32, generating a clock of 648 MHz which is used as reference for all clocks needed. Line-locked horizontal sync pulses are generated by a digital phase locked loop. The time constant can be adjusted between fast and slow behavior (KPL, KIL) to accommodate different backend ICs. The PLL control can be frozen up to 15 lines before V-sync (FION) for a duration up to 15 lines (FILE). This may be used to reduce disturbances by h-phase errors which are produced by VCR's. The output frequency for the 100/120 Hz version dependent on IICINCR is
DATA SHEET
A freerunning frequency is also generated which may be selected alternatively. The freerunning frequency for the 100/120 Hz version dependent on FRINC is
f displayfr = FRINC 103Hz
Normally, IICINCR and FRINC are equal or nearly the same. The value is internally divided by two for the 50/ 60 Hz versions. The number of pixels generated by the PLL is given by PPLIP. For line-locked clock generation the following equation must be fulfilled:
f displayll = IICINCR 103Hz
PPLIP = 2 PPLOP
20.25 MHz
xtal oscillator
frequency divider
FRINC
CLKF40 CLKF20
PLL
648MHz
FR-DTO
frequency divider M U X
CLKB27 CLKB36 CLKB72
ADC
interpolation
syncseparation
phase detector
loop filter
LL-DTO
frequency divider
analog CVBS
IICINCR
line-locked
locked or freerunning selection
Fig. 2-42: Line-locked Clock Ceneration
nominal 50Hz operation (analog out)
13.5 / 18 27 / 36 MHz
nominal 50Hz operation (digital out) nominal 100Hz operation (analog out) nominal 100Hz operation (digital out)
Fig. 2-43: Allowed Operation Area for Clock Generation 32 Micronas
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The PLL settings for different operation modes can be seen in Table 2-18. Dependent on input signal (50 Hz or 60 Hz), the linelocked clock is changing slightly (e.g. from 27 MHz to 27.18 MHz). To have no artifacts when switching between locked and freerun operation, it is possible to change the FRINC parameter, after the input TV standard has been detected safely. In case the IC is operating in horizontal locked OR freerunning mode only, this adaptivity is not required.
Table 2-18: Recommended LL-PLL settings for normal TV-application Operation 100/120 Hz (analog out) 100/120 Hz (digital out) 50/60 Hz (analog out) 50/60 Hz (digital out) Input 50 Hz 60 Hz 50 Hz 60 Hz 50 Hz 60 Hz 50 Hz 60 Hz 1728 864 262144 2304 1152 349525 1728 864 262144 PPLIP*4 2304 PPLOP*4 1152 IICINCR 349525 FRINCR 349525 351953 262144 263892 349525 351953 262144 263892 CLKB36 [MHz] 36 36.25 27 27.18 18 18.125 13.5 13.59 fH[kHz] 31.250 31.468 31.250 31.468 15.625 15.734 15.625 15.734
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3. I2C Bus Interface 3.1. I2C Bus Slave Address When pin 19 (adr/tdi) is connected to Vss, the VSP 94x2A reacts on the first I2C address (B0h for write access and B1h for read access). The second address (B2h and B3h) is active, when pin 19 is connected to Vdd. Table 3-1: I C bus slave addresses B0h and B1h Write Address1: B0h 10110000 Read Address1: B1h 10110001
2
DATA SHEET
The transmitted data is internally stored in registers. The registers are located in four different clock domains. The Table 3-5 on page 35 shows the four different clock domains of the VSP 94x2A. The clock domains are called CP - CVBS processing block (20.25 MHz domain, clkf20), FP - Front end processing block (40.5 MHz domain, clkf40), BP - Back end processing block (36.0 MHz domain, clkb36) and PP PLL processing block (36.0 MHz domain, clkf36). The registers themselves are grouped in an I2C bus interface block, one in each domain. The transmitted data is received by the I2C bus kernel. The I2C bus kernel itself is located in the CP domain. This means that the working frequency is 20.25 MHz. The data is transmitted to the I2C bus interface blocks via an internal serial bus. For the write process, the I2C bus master has to write a `don't care' byte to the subaddress FFh (store command). This makes the register values available to the four I2C bus interface blocks (except for the not-takeover registers, which are used immediately). In order to have a defined time step for the several blocks in the different domains, the data are made valid with internal V-syncs, depending on the different clock domains. The subaddresses, where the data are made valid with the V-sync signal of the 20.25 MHz domain are indicated in the overview of the subaddresses with "V20". The others are called "V40", "V36F" and "V36B" accordingly.
Table 3-2: I2C bus slave addresses B2h and B3h Write Address2: B2h 10110010 Read Address2: B3h 10110011
3.1.1. I2C Bus Format The VSP 94x2A I2C bus interface acts as a slave receiver and a slave transmitter and provides two different access modes (write, read). All modes run with a subaddress auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission.
Table 3-3: Write S 1 0 1 1 0 0 x 0 A Subaddress A Data Byte A ***** A P
S: Start condition SR: Repeated Start condition A: Acknowledge P: Stop condition NA: Not Acknowledge
Table 3-4: Read Subaddress Data Byte Data Byte NA
S
1
0
1
1
0
0
x
0
A
A
SR
1
0
1
1
0
0
x
1
A
A
P
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ferent blocks, the data is made valid with the same VSync related signals mentioned above for the write process. Clock
CLKF20 CLKF20 CLKF20 CLKF40 CLKF40 CLKF40 CLKF40 CLKF40 CLKF36 CLKF36 CLKB36 CLKB36 CLKB36 CLKB36 CLKB36 CLKB72 CLKB36
Table 3-5: I2C bus clock domains Domain
CP CP-CD CP-PP CP-I2C FP FP-PRE FP-MC FP-RGB FP-TNR FP-I2C PP PP PP-I2C BP BP-DP BP-PM BP-ODC BP-ODC/MC BP-POS BP-DAC BP-I2C
Description
CVBS frontend LL-PLL I2C read Prescaler Memory-controller RGB Frontend Temporal noise reduction I2C read LL-PLL I2C read Display processing Pixel-Mixer Output data control Output data control/ memory-controller Postscaler DAC processing I2C read
The VSP 94x2A distinguishes between two different types of read-registers. The behavior of the "normal" read registers does not differ from the behavior of the write registers. Only the direction of the data flow is opposite. The "rs typ" read registers behave differently. They can be only set (means value 1) by the internal blocks using the rising edge of a corresponding signal. After reading by the I2C bus master, the registers will be automatically reset (means value 0) by the I2C bus kernel/interface. For example the register NMSTATUS belongs to the "rs typ" read registers. NMSTATUS signalizes a new value for NOISEME. So if NMSTATUS is read as `0' the current noise measurement has not been updated. If the NMSTATUS is read as `1' a new noise measurement value can be read. All other "rs typ" read registers work in the same way. The "rs typ" read registers will be marked in the overview with the short cut "rstyp" or will have the additional hint "Note: reset automatically when read/write" in the detailed I2C bus command description. By default all registers are made valid by the internal VSync related signals and, in addition, a store command has to be sent for write registers. The registers, which should also be made available immediately as for writing and reading, are marked with the short cut NTO (No take over mechanism). Registers which need a hand-shake mechanism between the I2C bus interface and the different blocks are marked with the shortcut HS (Hand shake mechanism). This means that all bits of the registers are used when the last register is written. After PPLIP9-2 is written, PPLIP1-0 must be written to allow these bits to have effect. The registers for the write parameter STOPMODE are directly connected to the read registers of the parameter SMMIRROR. So it is possible to check the I2C bus protocol by writing and reading to the register STOPMODE and SMMIRROR, respectively. The transmitted data is internally stored in registers. Writing to or reading from a non-existant register is permitted and does not generate a fault by the IC. After switching on the IC, all bits of the VSP 94x2A are set to defined states, (refer to Table 3-6). POR is set after reset to pin 24. It stays `1', until it is cancled via software PORCNCL. This can be used to decide during TV operation, whether to program all registers (e.g. after power failure reset) or only altered ones (normal TV operation).
The I2C parameter V20STAT, V40STAT and V36BSTAT reflect the state of the register values. If these bits are read as `1', then the store command was sent, but the data is not made available yet. If these bits are `0' then the data was made valid and a new write or read cycle can start. The bits V20STAT, V40STAT and V36BSTAT may be checked before writing or reading new data, otherwise data can be lost by overwriting. No V36FSTAT register exist. To make the register values available to the four I2C bus interface immediately after sending, the I2C bus master has to write a `don't care' byte to the subaddress FEh (store command). For the read process, the I2C bus master must not send a store command. In order to have a defined time step for the I2C bus interface blocks in the different domains, where the data will be available from the dif-
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DATA SHEET
sda scl cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 cvbso1 cvbso2 cvbso3 b/u1 g/y1 r/v1 fbl/hin1 b/u2 g/y2 r/v2 fbl/hin2 vin
S o u r c e S e l e c t S o u r c e S e l e c t
xout
xin
36.0F MHz
ADC AGC ADC PP (PLL processing block)
72,0 MHz 27,0 MHz 36,0B MHz
vout hout OUT 27.0
20,25 MHz
CP (CVBS CD processing block) IC
40,5 MHz
OSC M C BP - (Back end processing block) 2 HPOSTSCALE PICIMPROVE DELAY ODC
HPRESCALE
RGB
ADC ADC ADC ADC
M C FP (Front end processing block) 1
TNR
O u t 7 2
DAC DAC DAC
ayout auout avout
VSP 94x2A
hout50 vout50
Fig. 3-1: I2C Bus Clock Domains
Table 3-6: I2C bus characterization Subaddress 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h Default AAh CAh B0h C8h 16h 10h 20h 01h F0h 3Eh 00h A0h 00h 90h 80h 00h 20h R/W W W W W W W W W W W W W W W W W W Take-over V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 Subaddress 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh Default 44h 00h FFh 1Fh F4h 44h 00h FFh AAh AAh 05h 00h 60h 60h 90h 00h 04h R/W W W W W W W W W W W W W W W W W W Take-over V40 V40 V40 V40 V40 V40 V40 V40 NTO NTO NTO/HS NTO/rstyp NTO NTO NTO NTO/HS NTO
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Table 3-6: I2C bus characterization, continued Subaddress 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch Default 20h 00h 00h 00h 00h 00h 00h 16h 00h 03h 1Fh F4h 00h 00h 26h 3Ch 01h 00h 04h 40h 20h 9Ch AAh 00h 18h 0Bh 00h 00h 00h 00h 00h R/W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W Take-over V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V40 V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V20 V36B V36B V36B V36B V36B Subaddress 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah Default 00h 00h 2Dh 44h 94h 20h 00h 00h 01h 00h E0h 01h 80h 80h 80h 44h 40h C0h 5Ch 66h 40h 40h 00h 00h A5h 5Fh 0Fh 00h 00h 3Ch 03h R/W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W Take-over NTO V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20
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Table 3-6: I2C bus characterization, continued Subaddress 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h (no autoincrement) 83h 84h (no autoincrement) 85h 86-93h 94h-95h 96h 97h (spare) (spare) R V40 Default 00h 55h 0Bh 00h 00h 00h 00h 00h 00h 3Fh 3Fh 00h 00h 1Ch 1Ch FCh 77h 02h 6Ch 00h 15h 00h 00h 00h R/W W W W W W W W W W W W W W W W W W W W W W W W W R R R R Take-over V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 NTO NTO no/rstyp NTO Subaddress 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h B2h B3h B4h B5h(no autoincrement) B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h D0h D1h D2h E0h Default 07h 07h 1Ch 5Ch 00h 00h E4h 00h 00h 00h 7Fh 40h 00h FFh 43h (spare) 00h 00h 00h 00h (spare) AAh AAh 05h (spare) 00h 00h 00h 00h 00h 00h W W W W W W W W W W W W W R/W W W W W W W W W W W W W W W W
DATA SHEET
Take-over V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20 V20
V40 V40 V40 V40
NTO NTO NTO
V40 V40 V36 V36 V36 V40
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Table 3-6: I2C bus characterization, continued Subaddress 98h 99h A0h A1h A2h A3h A4h B0h B1h EAh EBh ECh EDh EEh EFh F0-F6h F7h-FDh FEh FFh Take-over mechanism NTO V20 V40 V36B HS No take-over mechanism Take-over with V-sync in 20 MHz domain Take-over with V-sync in 40 MHz domain Take-over with V-sync in back-end 36.0 MHz domain Handshake mechanism required (spare) W W Register types W R Rrstyp Write register Read register Reset register after reading 00h 00h FFh FFh 00h 10h 00h 00h 00h 00h 00h 00h 00h Default R/W R R W W W W W W W W W W W W W R Take-over V36B V20 NTO NTO NTO NTO NTO V20 V20 V40 V40 V40 V40 V40 V40 NTO Subaddress E1h E2h E3h E4h E5h E6h E7h E8h E9h Default 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W W W W W W W W W W Take-over V40 V40 V40 V40 V40 V40 V40 V40 V40
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3.1.2. I2C Bus List in Alphabetical Order Name
AABYP ACCFIX ACCFRZ ACCLIM ADCSEL ADLCK ADLCKCC ADLCKSEL AFPROC AGCADJ1 AGCADJ2 AGCADJB AGCADJCV AGCADJF AGCADJG AGCADJR AGCFRZE AGCMD AGCRES AGCTHD ALPFIP ALPFIPI ALPFOP AM50O AM60O AMSTD50 AMSTD60 APENSEL APPLIP APPLIPI APPLOP ASCENTCTI AUTOFRRN
DATA SHEET
Name
BCOF BELLFIR BELLIIR BGPOS BLANDEL BLANEN BLANLEN BLANPOL BORDERH BORDERV BORDPOSH BORDPOSV BRTADJ CDELHPOS CFORMAT CHRF CHRMSIG656 CHROMAMP CHROMSIGN CHRSF CHRSHFT CKILL CKILLS CKSTAT CLKF2PAD CLKOUTINV CLKOUTON CLKOUTSEL CLKOUTSEL72 CLKT CLMPD1 CLMPD1S CLMPD2 CLMPD2S
Subaddress
31h 7Dh 7Dh 47h 07h 36h 08h 36h 45h 45h 35h 34h 0Ah 4Fh 18h 5Eh 55h 57h 57h 0Bh 3Dh 60h 61h 88h 16h 4Fh 30h 4Fh 4Dh 2Eh 6Bh 7Bh 6Ch 7Bh
Subaddress
0Ch 5Bh 5Bh 7Ah 0Ch 81h 81h 81h 4Dh 67h 68h 16h 90h 17h 15h 14h 68h 67h 68h B0h 05h B8h 32h 90h 90h B1h B1h 05h 01h B9h 3Dh 30h 32h
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VSP 94x2A
Name
CLMPHIGH CLMPLOW CLMPST1 CLMPST1S CLMPST2 CLMPST2S CLMPVG CLMPVRB CLPSTGY CLRANGE COARSEDEL COLON COMB CON CONADJ CONS CPLLOF CPLLRES CRCB CSTAND CVBOSEL1 CVBOSEL2 CVBOSEL3 CVBSEL1 CVBSEL2 DCLMPF DECTWO DEEMPFIR DEEMPIIR DEEMPSTD DETHPOL DETVPOL DISALLRES DISCHCH
Subaddress
69h 6Ah 6Dh 78h 6Eh 79h 10h 0Dh 6Bh 5Dh 32h 5Bh 5Fh 5Ch 0Bh 5Bh 82h 80h 5Bh 5Fh 6Ah 70h 70h 6Fh 6Fh 10h 0Bh B5h B5h 82h 88h 88h 80h 6Ch
Name
DISRES DPOUT656 EIA770 EN_656 ENLIM F_POL FBLACTIVE FBLCONF FBLDEL FBLOFFST FEMAG FHDET FHFRRN FIELDBINV FILE FINEDEL FIOFFOFF FION FKOI FKOIHYS FLDINV FLINE FLNSTRD FMOD FOFFST FREEZE FREQSEL FRFIX FRINC FSWFTL GOFST GRADELAA GRADISSTABLE H_POL
Subaddress
27h 56h 7Ch 18h 7Eh 18h 83h 0Dh 0Dh 0Ch B1h 6Ch 71h 54h 2Eh 32h 54h 2Dh 2Ch 2Ch 6Bh 6Bh 7Eh 29h C1h 3Fh 7Ch 1Ah BCh D0h 0Eh F3h F2h 18h
Micronas
Aug. 16, 2004; 6251-552-1DS
41
VSP 94x2A
DATA SHEET
Name
HAAPRESC HCOF HDCPRESC HDTOTEST HINC0 HINC1 HINC2 HINC3 HINC4 HINCREXT HINP HORPOS HORWIDTH HOUTDEL HOUTFR HOUTPOL HPANON HPOL HRES HSCPOSC HSCPRESC HSEG1 HSEG2 HSEG3 HSEG4 HSPPL HSWIN HTESTW HUE HWID IFCOMP IFCOMSTR IICINCR IMODE
Subaddress
09h 31h 05h 2Eh 48h 49h 4Ah 4Bh 4Ch 29h 6Dh 3Ah 38h 3Eh 41h 41h 4Fh 6Ch 28h 4Eh 01h 50h 51h 52h 53h C0h 29h 2Ah 63h 2Eh 7Ah 82h 25h 18h
Name
INT ISHFT ITUPRTSEL KD2 KIL KINL KOIH KOIWID KPL KPNL LB43SENS LBACTIVITY LBASDEL LBELAA LBFORMAT LBFS LBGFBDEL LBGRADDET LBGRADRST LBGSDEL LBHISTBLA LBHIWHITE LBHSDEL LBHWEND LBHWST LBNGFEN LBSLAA LBSTABILITY LBSTATUS LBSUB LBSUBTITLE LBTHDNBNG LBTHDNBNHA LBTOPTITLE
Subaddress
89h 7Eh 16h 29h A1h A1h 2Ah 2Ah A0h A0h E9h ECh EFh F0h F2h E6h EDh E0h EAh EEh E4h E3h EAh E2h E7h E9h F0h E9h 85h EAh F2h E9h EBh F2h
42
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Name
LBVWENDLO LBVWENDUP LBVWSTLO LBVWSTUP LIMEN LIMII LIMIP LIMLR LMOD LMOFST LNL LNSTDRD LOCKSP LPBLACK LPCDEL LPFIPMD LPFLD LPFOP LPFOPFF LPPOST LPWHITE MINV MIXGAIN MIXOP MLL MVP MVPG NALPFIP NALPFIPI NALPFOP NAPIPPHI NAPPLIP NAPPLIPI NAPPLOP
Subaddress
E1h E6h E5h E8h 2Ch A3h A2h A4h 29h 5Dh 2Dh 89h 47h F5h 72h 2Fh 8Ah 43h 3Ch 62h F5h 92h 0Fh 0Dh 09h B2h B2h 04h BAh 45h 17h 02h B7h 3Fh
Name
NMLINE NMPOS NMSENSE NMSTATUS NOGRADFOUND NOISEME NOSIGB NOSYNC NOTCHOFF NRON NRPIXEL NSRED NTCHSEL NTSCREF OPDEL OSCPD PALDEL PALDET PALID PALIDL0 PALIDL1 PALIDL2 PALINC1 PALINC2 PALREF PB PDGSR PFBL PG PKLU PKLV PKLY PLLTC POR
Subaddress
19h 1Ah 1Ah 85h F2h 84h 6Dh 3Ch 5Ch 1Ah 8Bh 72h/7Eh 80h 64h 44h 7Ch 47h 8Ch 88h 75h 74h 82h 82h 82h 65h 85h 3Fh 85h 85h 59h 5Ah 58h 6Eh 8Ch
Micronas
Aug. 16, 2004; 6251-552-1DS
43
VSP 94x2A
DATA SHEET
Name
PORCNCL PPLIP PPLOFF PPLOP PR PWADJCNT PWTHD RBOFST RDCTRLDIS REFRON REFRPER REFTRIM REFTRIMCV REFTRIMCVRD REFTRIMEN REFTRIMRD REFTRIMRGB REFTRIMRGBRD REV RGBSEL SATNR SCADJ SCDEV SCMIDL SCMREL SCOUTEN SDB SDR SECACC SECACCL SECDIV SECINC1 SECINC2 SECNTCH
Subaddress
80h 2Bh 3Ch 41h 85h 93h 5Dh 0Eh 45h 41h 41h 76h 77h 8Eh 72h 8Dh 77h 8Eh F6h 0Fh 72h 66h 89h 79h 7Fh 88h B2h 5Eh 7Fh 81h 7Fh 7Fh 7Fh 5Ch
Name
SETSTABLL SHAPERDIS SHIFTUV SKEWSEL SLLTHD SLLTHDV SLLTHDVP SLS SMMIRROR SMOP STAB STABLL STANDBY STDET STOPMODE SUBTITLE SWITCHTO43 SYNFTHD THRESHC THRSEL TNRABS TNRCLC TNRCLY TNRS0C TNRS0Y TNRS1C TNRS1Y TNRS2C TNRS2Y TNRS3C TNRS3Y TNRS4C TNRS4Y TNRS5C
Subaddress
2Ch 7Ch 56h 0Eh 66h B1h 78h 8Fh/F6h 87h 0Eh 8Ch 86h 11h 88h 3Fh F2h F2h 82h 30h 78h 1Ah 24h 24h 20h 1Bh 20h 1Bh 21h 1Ch 21h 1Ch 22h 1Dh 22h
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Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Name
TNRS5Y TNRS6C TNRS6Y TNRS7C TNRS7Y TNRSEL TNRSSC TNRSSY TOPTITLE TRAPBLU TRAPRED TSTSHAPERI UBORDER UPBLACK UPWHITE USATADJ UVCOR UVDEL V_POL V20STAT V36BSTAT V40STAT V656DEL VBLANDEL VBLANLEN VBLANPOL VBORDER VDEL_EN VDELF_EN VDETIFS VDETITC VERSION VFLYMD VFLYWHL
Subaddress
1Dh 23h 1Eh 23h 1Eh 1Ah 1Fh 1Fh F2h 80h 80h 7Ch 37h F5h F5h 10h 5Ch 13h 18h 99h 98h 96h 4Dh D0h D0h D0h 37h 55h 03h 5Dh B2h 8Fh/F6h 8Ch 7Dh
Name
VFLYWHLMD VINMTHD VINP VLENGTH VLP VOUTFR VOUTPOL VPOL VSATADJ VSHIFT VSIGNAL VSLPF VTHRH50 VTHRH60 VTHRL50 VTHRL60 WINDHDR WINDHON WINDHSP WINDHST WINDVDR WINDVON WINDVSP WINDVST WRCTRLDIS Y2RGB YBORDER YCDEL YCOR YCSEL YFDEL YUVSEL
Subaddress
81h 2Fh 72h 91h 7Eh 41h 41h 62h 11h 73h 18h C1h 75h B4h 74h B3h 3Bh 3Bh 3Bh 3Bh 39h 39h 39h 39h 09h 12h 36h 62h 30h 6Bh 12h 0Eh
Micronas
Aug. 16, 2004; 6251-552-1DS
45
VSP 94x2A
3.1.3. I2C Bus Command Table Table 3-7: I2C register overview
Sub add (Hex) Data Byte D7 D6 D5 D4 D3 Input Processing
00h 01h 02h 03h 04h 05h 06h APPLIP[8:1] APPLIP[0] HSCPRESC[4:0] VDELF_EN NALPFIP APENSEL ALPFIP[7:0] NALPFIP8 ALPFIP[9:8] HDCPRESC NAPPLIP6[6:0] HSCPRESC [11:5] NAPPLIP[9:7]
DATA SHEET
D2
D1
D0
07h 08h 09h
BLANDEL BLANLEN WRCTRLDIS HAAPRESC MLL
RGB Front-end
0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h ITUPRTSEL NAPIPPHI1 IMODE CLKF2PAD NAPIPPHI0 BRTADJ DECTWO ADCSEL CLMPVRB1 YUVSEL RGBSEL CLMPVG STANDBY1 Y2RGB CHRSF AABYP CLMPVRB0 SMOP MIXGAIN DCLMPF STANDBY0 USATADJ VSATADJ YFDEL UVDEL AGCADJR AGCADJG AGCADJB AGCADJF VSIGNAL CFORMAT F_POL H_POL V_POL EN_656 CONADJ FBLOFFST FBLDEL SKEWSEL RBOFST MIXOP GOFST FBLCONF
Noise Reduction
19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh NMLINE [7:0] NMPOS TNRS0Y TNRS2Y TNRS4Y TNRS6Y TNRSSY NMSENSE NMLINE [8] TNRS1Y TNRS3Y TNRS5Y TNRS7Y TNRSSC TNRABS NRON TNRSEL
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DATA SHEET
VSP 94x2A
Table 3-7: I2C register overview, continued
Sub add (Hex)
20h 21h 22h 23h 24h
Data Byte D7
TNRS0C TNRS2C TNRS4C TNRS6C TNRCLY
D6
D5
D4
D3
TNRS1C TNRS3C TNRS5C TNRS7C TNRCLC
D2
D1
D0
Line-locked Clock PLL
25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh HSWIN KOIWID PPLIP[9:2] SETSTABLL FION CLKT HWID HDTOTEST FILE LPFIPMD VINMTHD FRFIX LIMEN FKOI FKOIHYS PPLIP[1:0] LNL KOIH KD2 HTESTW HINCREXT LMOD IICINCR[18:11] IICINCR[10:3] DISRES IICINCR[2:0] HRES FMOD
Display Processing
30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h YCOR HCOF AUTOFRRN ALPFOP[7:0] BORDPOSV BORDPOSH [7:0] BLANPOL UBORDER HORWIDTH[7:0] WINDVSP HORPOS WINDHSP1 NOSYNC CHRSHFT HOUTDEL NAPPLOP[9:8] NAPPLOP PPLOP[9:8] PPLOP[7:0] LPFOP REFRPER REFRON HOUTPOL VOUTPOL HOUTFR VOUTFR PDGSR FREEZE STOPMODE HOUTDEL[9:8] WINDHSP0 PPLOFF APPLOP WINDHST WINDHDR WINDHON LPFOPFF HORPOS[10:8] WINDVST WINDVDR WINDVON HORWIDTH[10:8] BLANEN BORDPOSH[9:8] YBORDER VBORDER ALPFOP[9:8] CLKOUTON THRESHC BCOF FINEDEL COARSEDEL ASCENTCTI
Micronas
Aug. 16, 2004; 6251-552-1DS
47
VSP 94x2A
Table 3-7: I2C register overview, continued
Sub add (Hex)
44h 45h 46h
DATA SHEET
Data Byte D7
OPDEL[7:0] BORDERV NALPFOP BORDERH RDCTRLDIS LPFOP8 NALPFOP8 OPDEL[8]
D6
D5
D4
D3
D2
D1
D0
Panorama Scaler
47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h HINC0 [7:0] HINC1 [7:0] HINC2 [7:0] HINC3 [7:0] HINC4 [7:0] V656DEL HSCPOSC [7:0] CDELHPOS HSEG1 HSEG2 HSEG3 HSEG4 FIOFFOFF CHRMSIG656 FIELDBINV VDEL_EN HSEG2 [10:8] HSEG4 [10:8] HSEG1 [10:8] HSEG3 [10:8] CLKOUTSEL CLKOUTINV HPANON HSCPOSC [11:8] AFPROC CLKOUTSEL272 HINC4 [8] HINC3 [8] HINC2 [8] HINC1 [8] HINC0 [8] PALDEL.1 PALDEL.0 LOCKSP BGPOS
DAC Control
56h 57h 58h 59h 5Ah SHIFTUV CHROMSIGN PKLY PKLU PKLV DPOUT656 CHROMAMP
CVBS Front-end
5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h CONS CON PWTHD SDR COMB CKILL CKILLS VPOL HUE NTSCREF PALREF SLLTHD SCADJ LPPOST YCDEL CSTAND CLRANGE CHRF COLON UVCOR LMOFST CRCB NOTCHOFF ACCFIX SECNTCH VDETIFS ACCFRZ
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DATA SHEET
VSP 94x2A
Table 3-7: I2C register overview, continued
Sub add (Hex)
67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h FLNSTRD SECACC PORCNCL ADLCK SYNFTHD SECDIV NTCHSEL ADLCKSEL ADLCKCC IFCOMSTR VFLYWHLMD PALIDL2 CPLLOF BELLFIR ENLIM SECINC1 ISHFT SECINC2 CPLLRES DISALLRES SECACCL DEEMPSTD PALINC1 PALINC2
Data Byte D7
AGCMD AGCRES CLMPHIGH CVBOSEL1 FLINE HPOL1 NOSIGB PLLTC CVBSEL2 CVBOSEL2 FHFRRN REFTRIMEN VSHIFT PALIDL1 PALIDL0 REFTRIM REFTRIMCV SLLTHDVP SCMIDL ACCLIM CLMPD2S EIA770 SHAPERDIS CLMPD1S OSCPD BELLIIR NSRED2 VLP SCMREL TRAPBLU TRAPRED TSTSHAPERI FREQSEL1 FREQSEL0 VFLYWHL THRSEL CLMPST1S CLMPST2S IFCOMP REFTRIMRGB VTHRL50 VTHRH50 SATNR VINP NSRED LPCDEL FLDINV HPOL0 HINP CLPSTGY FHDET CLMPST1 CLMPST2 CVBSEL1 CVBOSEL3 YCSEL DISCHCH CLMPLOW CLMPD1 CLMPD2 AGCFRZE
D6
D5
AGCADJ1 AGCADJ2
D4
D3
D2
D1
D0
Read Register
83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh DETHPOL LNSTDRD LPFLD NRPIXEL DETVPOL INT STDET SCDEV SCOUTEN SMMIRROR PALID CKSTAT NOISEME LBSTATUS PFBL PG PB PR NMSTATUS STABLL FBLACTIVE
Micronas
Aug. 16, 2004; 6251-552-1DS
49
VSP 94x2A
Table 3-7: I2C register overview, continued
Sub add (Hex)
8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 96h 97h 98h 99h MINV PWADJCNT AM50O AM60O VLENGTH AGCADJCV POR REFTRIMRD REFTRIMCVRD REFTRIMRGBRD SLS VERSION
DATA SHEET
Data Byte D7 D6 D5 D4 D3
VFLYMD
D2
STAB
D1
D0
PALDET
V40STAT
V36BSTAT V20STAT
PP
A0h A1h A2h A3h A4h KPNL[3:0] KINL[3:0] LIMIP LIMII KPNL[4] KPL[4] KINL[4] KIL[4] LIMLR KPL[3:0] KIL[3:0]
CVBS Front-end
B0h B1h B2h B3h B4h B5h DEEMPIIR SDB VTHRL60 VTHRH60 DEEMPFIR AGCTHD SLLTHDV MVPG FEMAG AMSTD60 MVP VDETITC AMSTD50
ITU Input
B7h B8h B9h BAh NAPPLIPI ALPFIPI APPLIPI [7:0] APPLIPI[8] NALPFIPI
LL-PLL
BCh BDh BEh FRINC[18:11] FRINC[10:3] FRINC[2:0]
C0h C1h
HSPPL FOFFST VSLPF
50
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DATA SHEET
VSP 94x2A
Table 3-7: I2C register overview, continued
Sub add (Hex) Data Byte D7 D6 D5 D4 D3 D2 D1 D0
D0h D1h D2h
VBLANDEL [9:8] VBLANDEL [7:0] VBLANLEN [7:0]
VBLANPOL
FSWFTL
VBLANLEN [9:8]
Letterbox Detection
E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh LBSTABILITY LBSUB1 LB43SENS LBSUB0 LBGRADDET LBVWENDLO LBHWEND LBHIWHITE LBHISTBLA LBMASLA LBFS LBVISUON LBVWSTLO LBVWENDUP LBHWST LBVWSTUP LBNGFEN LBGRADRST LBTHDNBNG LBHSDEL LBTHDNBNHA LBACTIVITY LBGFBDEL LBGSDEL LBASDEL
Letterbox Read
F0h F1h F2h F3h F4h F5h LBSLAA LBELAA LBFORMAT GRADELAA[8] GRADELAA[7:0] LPBLACK UPBLACK LPWHITE UPWHITE LBSUBTITLE GRADSLAA LBTOPTITLE GRADISSTABLE TOPTITLE SUBTITLE NOGRADFOUND SWITCHTO43
F6h FEh
VERSION take-over-indication (immediately)
SLS
REV
FFh
take-over-indication (after V-pulse)
Micronas
Aug. 16, 2004; 6251-552-1DS
51
VSP 94x2A
3.1.4. I2C Bus Command Description Underlined values are initialized at power-on. Some bits are intended to not be user adjustable. Mandatory and recommended settings are available from Micronas in a separate document (Application Note: I2C Settings). Table 3-8: I2C bus command description Bit Name Description
DATA SHEET
Subaddress 00h D7-D0 APPLIP8-1 [FP-PRE] Active Pixel Per Line Number of pixels to be stored in memory Granularity: 2 pixel `000000000': 0 pixel `101010101': 682 pixel `111111111': 1022 pixel
Subaddress 01h D7 D6-D0 APPLIP0 [FP-PRE] HSCPRESC11-5 [FP-PRE] Belongs to 00h Control Signal For HSCALE In Horizontal Pre-scaler `000000000000': subsampling factor by scaler stage is 1 `100000000000': subsampling factor is 1.5 (720 pixel) `100101010110': subsampling factor is 1.583 (682 pixel) `111111111111': subsampling factor is 2 (540 pixel)
Subaddress 02h D7-D3 D2-D0 HSCPRESC4-0 [FP-PRE] NAPPLIP9-7 [FP-PRE] Belongs to 01h Not Active Pixel Per Line Granularity: 2 clock cycles (~50 ns) `0000000000': 0 clock cycles `0001001000': 144 clock cycles (~7.2 s) `1111111111': 2046 clock cycles (~51 s)
Subaddress 03h D7 VDELF_EN [FP-PRE] NAPPLIP6-0 [FP-PRE] Vertical pulse delay frontend `0': no delay `1': delayed Belongs to 02h
D6-D0
Subaddress 04h D7-D0 NALPFIP7-0 [FP-PRE] Not Active Lines Per Field (Input Processing) `000000000': 0 lines `000010110': 22 lines `111111111': 511 lines
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 05h D7 APENSEL [FP-PRE] NALPFIP8 [FP-PRE] ALPFIP9-8 [FP-PRE] Active Pixel Enable Select 0: count clock cycles (recommended for CVBS/RGB input) 1: count active pixels (recommended for ITU656 input) Belongs to 04h Active Lines Per Field `0000000000': no active line `0100100000': 288 active lines `1111111111': 1023 active lines Horizontal Pre-Scaler Decimates By `0000': 1 `0001': 2 `0010': 3 `0011': 4 `0100': 6 `0101': 8 `0110': 12 `0111': 16 `1000': 24 `1001': 32
D6 D5-D4
D3-D0
HDCPRESC
Subaddress 06h D7-D0 ALPFIP7-0 Belongs to 05h
Subaddress 07h D7-D0 BLANDEL Blanking signal delay Delay in pixels from hsync to active edge of blank signal: Blank_start=4*BLANDEL `00000000': no delay `00000001': 4 pixel delay `11111111': 1020 pixel delay
Subaddress 08h D7-D0 BLANLEN Blanking signal length Length in pixels from start of active blank signal: Blank_length=4*BLANLEN `00000000': no pixel `11110000': 960 pixel `11111111': 1020 pixel length
Micronas
Aug. 16, 2004; 6251-552-1DS
53
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 09h D6 WRCTRLDIS [FP-MC] HAAPRESC [FP-MC] Memory Write Control Circuit Disable `0': enabled `1': disabled Horizontal Anti Alias Filter `00': filter bypassed `01': force characteristic weak `10': force characteristic strong `11': automatic characteristic (weak or strong) Note: For normal CVBS/RGB full-screen, filter should be set to weak or automatic characteristic. For ITU656 full-screen input, filter should be bypassed. Strong characteristic is for split-screen and PiP only. Minimum Line Length effective number of clock periods: 600 + MLL*128 1110: corresponds to 2392 clock periods
D5-D4
D3-D0
MLL [FP-MC]
Subaddress 0Ah D7-D0 BRTADJ [FP-RGB] Brightness Adjustment of RGB/YUV input `10000000': -128 LSB (darkest picture) `00000000': 0 `01111111': +127 LSB (brightest picture)
Subaddress 0Bh D7 DECTWO [FP-RGB] Decimation by 2 decimation of RGB/YUV signal before soft-mix `0': no decimation `1': decimation by 2 Additional Chroma subsampling filter `0': disabled `1': enabled Contrast Adjustment of RGB/YUV input `000000': 0 `000001': 1/32 `100000': 1 `111111': 63/32
D6
CHRSF [FP-RGB] CONADJ [FP-RGB]
D5-D0
Subaddress 0Ch D7 ADCSEL [FP-RGB] AABYP [FP-RGB] FBLOFFST [FP-RGB] Select ADC for sync signal conversion `0': use ADC_G `1': use ADC_FBL Bypass RGB/YUV Antialiasfilter `0': use filter `1': bypass Fast Blank Offset Correction `000000': 0 LSB offset `111111': 63 LSB offset
D6
D5-D0
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 0Dh D7-D6 CLMPVRB [FP-RGB] Clamping Value Red and Blue ADC `00': 16 (B/R signal without sync) `01': 80 (B/R signal with sync) `10': 128 (U/V signal) `11': (reserved) Fast Blank Delay vs. RGB/YUV Input granularity: 25 ns `000': -50 ns delay `010': no delay `110': +100 ns delay `111': (reserved) Mixing Configuration `00': enable Soft-Mix `01': only RGB path visible `10': only CVBS path visible `11': (reserved) Configuration of FBLACTIVE signal `0': react after one clock (25 ns) active FBL input `1': react after 5 clock (125 ns) active FBL input
D5-D3
FBLDEL [FP-RGB]
D2-D1
MIXOP [FP-RGB]
D0
FBLCONF [FP-RGB]
Subaddress 0Eh D7 YUVSEL [FP-RGB] SMOP [FP-RGB] SKEWSEL [FP-RGB] RBOFST [FP-RGB] YUV or RGB Input Selection `0': YUV expected `1': RGB expected Softmix Operation Mode `0': dynamic `1': static SKEW Correction for RGB/YUV Channel `0': SKEW correction enabled `1': SKEW correction disabled (for PiP3, PiP4 only) Clamping Correction for R/B ADC `000': 0 (R/B, no pedestal offset visible) `001': 16 `010': 64 (R/B with sync, no pedestal offset visible) `011': 80 `100': 127 (UV negative pedestal offset) `101': 128 (UV) `110': 129 (UV positive pedestal offset) `111': (reserved) Clamping correction for G ADC `00': 0 (G/Y, no pedestal offset visible) `01': 16 `10': 64 (G/Y with sync, no pedestal offset visible) `11': 80
D6
D5
D4-D2
D1-D0
GOFST [FP-RGB]
Micronas
Aug. 16, 2004; 6251-552-1DS
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 0Fh D7 RGBSEL [FP-RGB] MIXGAIN [FP-RGB] Input selection `0': use RGB/YUV input1 `1': use RGB/YUV input2 Gain of Fast Blank Signal `1000000': -64 `0000000': 0 `0111111': +63 Note: For proper operation in dynamic softmix mode, absolute value of MIXGAIN must be bigger than 2 (e.g. 3)
D6-D0
Subaddress 10h D7 CLMPVG [FP-RGB] DCLMPF [FP-RGB] USATADJ [FP-RGB] Clamping Value G ADC `0': 16 `1': 80 Clamping Fast Blank input `0': enable clamping `1': disable clamping (DC coupling) U Saturation Adjustment `000000': 0 `000001': 1/32 `100000': 1 `111111': 63/32
D6
D5-D0
Subaddress 11h D7-D6 STANDBY [FP-RGB] Standby Mode `00': all analog cores active `01': RGB/FBL ADCs in Stand-By mode `10': RGB/FBL and CVBS ADCs and DACs in Stand-By mode `11': DACs in Stand-By mode V Saturation Adjustment `000000': 0 `000001': 1/32 `100000': 1 `111111': 63/32
D5-D0
VSATADJ [FP-RGB]
Subaddress 12h D7 Y2RGB [FP-RGB] YFDEL [FP-RGB] Y to RGB (for YUV mode) 0: use Y from green ADC 1: use Y from CVBS ADC Y/FBL Delay Adjustment Granularity: 50 ns `000000': no delay `111111': 3.15 s
D5-D0
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 13h D5-D0 UVDEL [FP-RGB] UV Delay Adjustment Granularity: 50 ns `000000': no delay `111111': 3.15 s
Subaddress 14h D5-D0 AGCADJR [FP-RGB] Conversion Range Adjustment Red `000000': 0.5 V input signal `111111': 1.5 V input signal
Subaddress 15h D5-D0 AGCADJG [FP-RGB] Conversion Range Adjustment Green `000000': 0.5 V input signal `111111': 1.5 V input signal
Subaddress 16h D7 ITUPRTSEL [FP-RGB] CLKF2PAD [FP-RGB] AGCADJB [FP-RGB] ITU port selection 0: first input (656io) 1: second input (i656i) Frontend clock is given to pin 74 `0' pin 74 is used as h-input for ITU656 `1': CLKF20 (20.25 MHz) is given to pin 74 Conversion Range Adjustment Blue `000000': 0.5 V input signal `111111': 1.5 V input signal
D6
D5-D0
Subaddress 17h D7-D6 D5-D0 NAPIPPHI [FP-RGB] AGCADJF [FP-RGB] CbYCrY-phase shift `0': no phase shift Conversion Range Adjustment Fast Blank `000000': 0.5 V input signal `111111': 1.5 V input signal
Micronas
Aug. 16, 2004; 6251-552-1DS
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 18h D7-D6 IMODE [FP-RGB] Input format `00': full ITU mode (automatic) `01': full ITU mode (manual) `10': ITU656 only data, H/V-sync according PAL/NTSC `11': ITU656 only data, H/V-sync according ITU656 Input signal `0': interlaced `1': non interlaced Chrominance data format `0': unsigned `1': 2s complement Field polarity `0': Field A=0, Field B=1 `1': Field A=1, Field B=0 H656 polarity `0': H656 active low `1': H656 active high V656 polarity `0': V656 active low `1': V656 active high ITU656-Input Interface `0': analog input enabled (CVBS/RGB) `1': ITUI enabled
D5
VSIGNAL [FP-RGB] CFORMAT [FP-RGB] F_POL [FP-RGB] H_POL [FP-RGB] V_POL [FP-RGB] EN_656 [FP-RGB]
D4
D3
D2
D1
D0
Subaddress 19h D7-D0 NMLINE7-0 [FP-TNR] Line For Noise Measurement 0d: line 2 1d: line 3 311d: line 1 (PAL) 261d: line 1 (NTSC) lines 3-260 are not standard dependent
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 1Ah D7-D6 NMPOS [FP-TNR] Noise Measurement analyze window position 00: 6.3 s 01: 12.6 s 10: 18.9 s 11: 23.7 s Noise Measurement sensitivity 00: *1 01: *2 10: *4 11: *8 Belongs to 19h Motion Detector Works on Absolute Values: `0': absolute values not calculated `1': absolute values calculated Temporal Noise Reduction `0': disabled `1': enabled Chrominance Motion Values From: `0': luminance motion detector `1': separate chrominance motion detector
D5-D4
NMSENSE [FP-TNR]
D3 D2
NMLINE8 [FP-TNR] TNRABS [FP-TNR] NRON [FP-TNR] TNRSEL [FP-TNR]
D1
D0
Subaddress 1Bh D7-D4 D3-D0 TNRS0Y [FP-TNR] TNRS1Y [FP-TNR] TNR Curve Characteristic of Luma Segment 0 default value: 0001 TNR Curve Characteristic of Luma Segment 1 default value: 1111
Subaddress 1Ch D7-D4 D3-D0 TNRS2Y [FP-TNR] TNRS3Y [FP-TNR] TNR Curve Characteristic of Luma Segment 2 default value: 1111 TNR Curve Characteristic of Luma Segment 3 default value: 0100
Subaddress 1Dh D7-D4 D3-D0 TNRS4Y [FP-TNR] TNRS5Y [FP-TNR] TNR Curve Characteristic of Luma Segment 4 default value: 0100 TNR Curve Characteristic of Luma Segment 5 default value: 0100
Subaddress 1Eh D7-D4 D3-D0 TNRS6Y [FP-TNR] TNRS7Y [FP-TNR] TNR Curve Characteristic of Luma Segment 6 default value: 0000 TNR Curve Characteristic of Luma Segment 7 default value: 0000
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 1Fh D7-D4 D3-D0 TNRSSY [FP-TNR] TNRSSC [FP-TNR] TNR Start Value of Luma LUT default value: 1111 TNR Start Value of Chroma LUT default value: 1111
Subaddress 20h D7-D4 D3-D0 TNRS0C [FP-TNR] TNRS1C [FP-TNR] TNR Curve Characteristic of Chroma Segment 0 default value: 0001 TNR Curve Characteristic of Chroma Segment 1 default value: 1111
Subaddress 21h D7-D4 D3-D0 TNRS2C [FP-TNR] TNRS3C [FP-TNR] TNR Curve Characteristic of Chroma Segment 2 default value: 1111 TNR Curve Characteristic of Chroma Segment 3 default value: 0100
Subaddress 22h D7-D4 D3-D0 TNRS4C [FP-TNR] TNRS5C [FP-TNR] TNR Curve Characteristic of Chroma Segment 4 default value: 0100 TNR Curve Characteristic of Chroma Segment 5 default value: 0100
Subaddress 23h D7-D4 D3-D0 TNRS6C [FP-TNR] TNRS7C [FP-TNR] TNR Curve Characteristic of Chroma Segment 6 default value: 0000 TNR Curve Characteristic of Chroma Segment 7 default value: 0000
Subaddress 24h D7-D4 TNRCLY [FP-TNR] TNRCLC [FP-TNR] TNR Luminance Classification `0000': strong noise reduction `1111': slight noise reduction TNR Chrominance Classification `0000': strong noise reduction `1111': slight noise reduction
D3-D0
Subaddress 25h D7-D0 IICINCR18-11 [PP] Set HDTO frequency Granularity=103 Hz 33981d (minimum: nominal pixel clock= 3.5 MHz) 349525d (nominal pixel clock= 36 MHz) 388362d (maximum: nominal pixel clock= 40 MHz)
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 26h D7-D0 IICINCR10-3 [PP] Belongs to 25h
Subaddress 27h D3 DISRES [PP] IICINCR2-0 [PP] Reset of LL-PLL watchdog `0': reset disabled `1': reset enabled Belongs to 25h
D2-D0
Subaddress 28h D0 HRES [PP] Reset of LL-HPLL `0': no reset `1': reset Note: reset automatically when written
Subaddress 29h D7-D4 HSWIN [PP] Width of Noise Suppression Window of LL-HPLL `0000': 28 s `0001': 24 s `0010': 20 s `0011': 16 s `0100': 12 s `0101': 8 s `0110': 4 s `0111': dynamic windowing. `1000': 30 s `1001': 27 s `1010': 26 s `1011': 22 s `1100': 18 s `1101': 14 s `1110': 10 s `1111': 6 s Phase Detector Steepness `0': steepness for normal TV operation mode `1': steepness for operations where PPLIP is less than 288d HDTO testmode `0': normal mode `1': line-locked-clocks derived from frontend line-length Selects line locked mode `0': line locked-clocks derived from HPLL `1': line-locked-clocks derived from frontend line-length Selects freerun mode `0': freerun-clocks derived from crystal `1': freerun-clocks derived from HDTO Adjustable frequency is only possible when set to `1'. When set to `0', Backend clock is always 36 MHz (9432/42: 18 MHz)
D3
KD2 [PP] HINCREXT [PP] LMOD [PP] FMOD [PP]
D2
D1
D0
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 2Ah D7-D6 KOIWID [PP] Window-Width of coincidence detector `00': 32 pixel (= 0.9 s for TV application) `01': 64 pixel (= 1.8 s for TV application) `10': 128 pixel (= 3.6 s for TV application) `11': 256 pixel (= 7.2 s for TV application) Hysteresis of coincidence detector `00': 0 lines `01': 8 lines `10': 16 lines `11': 32 lines Test bits for HPLL 00: default
D5-D4
KOIH [PP]
D3-D0
HTESTW [PP]
Subaddress 2Bh D7-D0 PPLIP9-2 [PP] Pixel per Line Input (Input-Processing) Granularity=4 pixel `175d': 700 (minimum) `576d': 2304 `963d': 3852 (maximum)
Subaddress 2Ch D7 SETSTABLL [PP] FRFIX [PP] LIMEN [PP] FKOI [PP] FKOIHYS [PP] PPLIP1-0 [PP] Stability Signal of LL_HPLL `0': STABLL is generated by the HPLL `1': STABLL is forced to 1 Freerunning clocks `0': from fixed clock divider `1': from freerunning DTO (adjustable clocks) Limiter enable `0': A32 behavior for LIMIP and LIMII `1': normal LIMII and LIMIP characteristic Force Coincidence Bit `0': coincidence bit dynamically changed `1': coincidence bit forced to 1 Force coincidence hysteresis bit `0': coincidence hysteresis bit dynamically changed `1': coincidence hysteresis bit forced to 1 Belongs to 2Bh
D6
D4
D3
D2
D1-D0
Subaddress 2Dh D7-D4 FION [PP] LNL [PP] Increment Freeze before V-sync `0': no freeze `15': freeze starts 15 lines before V-sync Dynamic Time Constant Control `0': linear mode `1': non linear mode
D0
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 2Eh D7-D6 CLKT [PP] Switch clkf20 and clkf40 to pads cvbs1 or bin2 (test only) `00': no clock `01': cvbs1 is output of clkf40 `10': bin2 is output of clkf20 `11': cvbs1 is output of clkf40 and bin2 is output of clkf20 Minimum width of H-sync `0': 60*Tclkllf36 `1': 15*Tclkllf36 Test-bit for HPLL `0': normal mode `1': test mode Increment Freeze duration `0': no freeze `15': increment is frozen for 15 lines
D5
HWID [PP] HDTOTEST [PP] FILE [PP]
D4
D3-D0
Subaddress 2F D1 LPFIPMD [BP-DP] VINMTHD [BP-DP] Lines per field method 0: backend 1: frontend Vertical ODC line counting 0: field delay 1: frame delay
D0
Subaddress 30h D7-D6 YCOR [BP-DP] Luminance Coring `00': off `01': 2 `10': 4 `11': 8 Clkout Pad: `0': off (tristate) `1': on Slope of DCTI function `000': 255 (DCTI off) `001': 2 `010': 3 `011': 4 `100': 6 `101': 8 `110': 10 `111': 12 Gain of DCTI function `00': 1/4 `01': 1/2 `10': 1 `11': 2
D5
CLKOUTON [BP-DP] THRESHC [BP-DP]
D4-D2
D1-D0
ASCENTCTI [BP-DP]
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 31h D7-D4 HCOF [BP-DP] Peaking: High-Pass Filter Adjustments `0000': 0 `0001': 1/4 ... `0100': 1 ... `1100': 12/4 `1101': 14/4 `1110': 16/4 `1111': 20/4 Peaking: Band-Pass Filter Adjustments `0000': 0 `0001': 1/4 ... `0100': 1 ... `1100': 12/4 `1101': 14/4 `1110': 16/4 `1111': 20/4
D3-D0
BCOF [BP-DP]
Subaddress 32h D7-D6 AUTOFRRN [BP-DP] Automatic freerun when sync-separartion not stable `00': disabled (keep H/V locked, if selected) `01': use vertical freerun `10': use horizontal freerun `11': use horizontal and vertical freerun Active Lines Per Field Output `0000000000': 0 (minimum) `0100100000': 288 (default) `1111111111': 1023 (maximum) Luminance Fine Delay output `0': no delay `1': +1 CLKB72 (13.9 ns for TV signal) Luminance Coarse Delay output Granularity: 1 CLKB36 (27.8 ns for TV signal) `000': -4 CLKB36 `100': no delay `111': +3 CLKB36
D5-D4
ALPFOP9-8 [BP-DP]
D3
FINEDEL [BP-DP] COARSEDEL [BP-DP]
D2-D0
Subaddress 33h D7-D0 ALPFOP7-0 [BP-PM] Belongs to 32h
Subaddress 34h D7-D0 BORDPOSV [BP-PM] Borderposition Vertical Granularity: 2 lines `00000000': no border `11111111': border at 512 lines at top and bottom
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 35h D7-D0 BORDPOSH7-0 [BP-PM] Borderposition Horizontal Granularity: 2 pixel `0000000000': no border `1111111111': border at 2048 pixel on left and right
Subaddress 36h D7 BLANPOL [BP-PM] BLANEN [BP-PM] BORDPOSH 9-8 [BP-PM] YBORDER [BP-PM] Blanking signal polarity `0': active high `1': active low Blanking signal enable `0': disabled (pin 8 can be used as 656vin) `1': enabled Belongs to 35h Luminance Value for Border `0000': sub black `0001': black `1111': white
D6
D5-D4 D3-D0
Subaddress 37h D7-D4 UBORDER [BP-PM] Chrominance (U) Value for Border `1000': `0000': `no color' U `0111': Chrominance (V) Value for Border `1000': `0000': `no color' V `0111':
D3-D0
VBORDER [BP-PM]
Subaddress 38h D7-D0 HORWIDTH7-0 [BP-PM] Horizontal Picture Width Granularity: 2 pixel `00000000000': no display `00111100000': 960 pixel `11111111111': 4094 pixel Note: Should be set equal to APPLOP (3Dh)
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 39h D7-D6 WINDVSP [BP-PM] Vertical Windowing: Speed `00': slow `01': medium `10': fast `11': very fast Vertical Windowing: Start `0': window is closed `1': window is open Vertical Windowing: Direction `0': open the vertical window `1': close the vertical window Vertical Windowing: Enable `0': off `1': on Belongs to 38h
D5
WINDVST [BP-PM] WINDVDR [BP-PM] WINDVON [BP-PM] HORWIDTH 10-8 [BP-PM]
D4
D3
D2-D0
Subaddress 3Ah D7-D0 HORPOS7-0 [BP-PM] Horizontal Position inside active picture area Granularity: 2 pixel `00000000000': most left display position `11111111111': most right display position
Subaddress 3Bh D7-D6 WINDHSP [BP-PM] Horizontal Windowing: Speed `00': slow `01': medium `10': fast `11': very fast Horizontal Windowing: Start `0': window is closed `1': window is open Horizontal Windowing: Direction `0': open the horizontal window `1': close the horizontal window Horizontal Windowing: Enable `0': off `1': on Belongs to 3Ah
D5
WINDHST [BP-PM] WINDHDR [BP-PM] WINDHON [BP-PM] HORPOS10-8 [BP-PM]
D4
D3
D2-D0
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 3Ch D7 NOSYNC [BP-ODC] PPLOFF [BP-ODC] No horizontal synchronization `0': horizontal synchronization `1': no horizontal synchronization Synchronization offset (for switching from hor. freerun mode to locked mode) Granularity: 4 pixel `000': 0 (disabled) `010': 8 `111': 28 Lines per field offset: (for switching from vertical freerun mode to locked mode) Granularity: 2 lines `0000': 0 (disabled) `0110':12 `1111': 31
D6-D4
D3-D0
LPFOPFF [BP-ODC]
Subaddress 3Dh D7 CHRSHFT [BP-O/M] Chrominance Shift shifts the chrominance signal `0': no shift `1': one line upward Active Pixel Per Line Output: Granularity: 16 pixel `0000000': 0 pixel `0111100': 960 pixel `1111111': 2032 pixel
D6-D0
APPLOP [BP-O/M]
Subaddress 3Eh D7-D0 HOUTDEL7-0 [BP-ODC] H Sync output Delay: Granularity: 4 pixel `0000000000': no delay `0000000001': 4 pixel delay `1111111111': 4092 pixel delay
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 3Fh D7-D6 NAPPLOP9-8 [BP-O/M] Not Active Pixel Per Line Output: Granularity: 4 pixel `0000000100': 16 not active pixel `1111111111': 4092 not active pixel Switch for Vsync transfer algorithm: `0': Vsync transfer algorithm is enabled `1': Vsync transfer algorithm is disabled Freeze picture `0': live `1': frozen (data writing disabled) Operation mode for scan rate conversion: `00': AABB (Raster ) `01': AAAA (Raster ) `10': AAAA (Raster ) `11': BBBB (Raster ) Belongs to 3Eh
D5
PDGSR [BP-O/M] FREEZE [BP-O/M] STOPMODE [BP-O/M]
D4
D3-D2
D1-D0
HOUTDEL9-8 [BP-O/M]
Subaddress 40h D7-D0 NAPPLOP7-0 [BP-ODC] Belongs to 3Fh
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 41h D7-D6 PPLOP9-8 [BP-O/M] Pixel Per Line Output: Granularity:4 `0000000000': 0 pixel `0100100000': 1152 pixel `1111111111': 4092 pixel Refresh period of the memory `0': ~5 ms `1': ~2,5 ms Refresh on `0': no memory refresh `1': memory refresh active HOUT polarity: `0': high active `1': low active VOUT polarity: `0': high active `1': low active HOUT freerun `0': locked mode `1': freerun mode VOUT freerun `0': locked mode `1': freerun mode
D5
REFRPER [BP-O/M] REFRON [BP-O/M] HOUTPOL [BP-O/M] VOUTPOL [BP-O/M] HOUTFR [BP-O/M] VOUTFR [BP-O/M]
D4
D3
D2
D1
D0
Subaddress 42h D7-D0 PPLOP7-0 [BP-O/M] Belongs to 41h
Subaddress 43h D7-D0 LPFOP7-0 [BP-ODC] Lines Per Field Output: Only used for freerun mode Granularity: 2 lines `000000000': no lines `010011100': 312 lines `111111111:' 1022 lines
Subaddress 44h D7-D0 OPDEL7-0 [BP-ODC] V delay for output operation: `000000000': no delay `010101010': 170 lines `111111111': 511 lines
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 45h D7-D6 BORDERV [BP-O/M] Border V `00': both borders are displayed `01': only lower border is displayed `10': only upper border is displayed `11': (reserved) Border H `00': both borders are displayed `01': only right border is displayed `10': only left border is displayed `11': (reserved) Memory read control circuit disable `0': enabled `1': disabled Belongs to 43h Not Active Lines Output NALPFOP-1 lines are not active lines. `000000001': all lines active `000011001': 24 lines not active `111111111': 510 lines not active Belongs to 44h
D5-D4
BORDERH [BP-O/M]
D3
RDCTRLDIS [BP-O/M] LPFOP8 [BP-O/M] NALPFOP8 [BP-O/M]
D2 D1
D0
OPDEL8 [BP-O/M]
Subaddress 46h D7-D0 NALPFOP7-0 [BP-ODC] Belongs to 45h
Subaddress 47h D6-D5 PALDEL [CP-CD] LOCKSP [CP-CD] PAL/NTSC delay vs. SECAM (chrominance) `00': PAL/NTSC most left `11': PAL/NTSC most right Duration Of Chroma PLL Search `00': 25 fields `01': 20 fields `10': 17 fields `11': 15 fields Burstgate Delay (SECAM only) Granularity: 200 ns `000': most left (-400 ns) `011': 200 s delay `111': most right (+1 us)
D4-D3
D2-D0
BGPOS [CP-CD]
Subaddress 48h D7-D0 HINC0_7-0 [BP-POS] Horizontal Post-Scaler Increment 0 `100000000': -32 pixel `000000000': 0 pixel `011111111': 31.875 pixel
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 49h D7-D0 HINC1_7-0 [BP-POS] Horizontal Post-Scaler Increment 1 `100000000': -32 pixel `000000000': 0 pixel `011111111': 31.875 pixel
Subaddress 4Ah D7-D0 HINC2_7-0 [BP-POS] Horizontal Post-Scaler Increment 2 `100000000': -32 pixel `000000000': 0 pixel `011111111': 31.875 pixel
Subaddress 4Bh D7-D0 HINC3_7-0 [BP-POS] Horizontal Post-Scaler Increment 3 `100000000': -32 pixel `000000000': 0 pixel `011111111': 31.875 pixel
Subaddress 4Ch D7-D0 HINC4_7-0 [BP-POS] Horizontal Post-Scaler Increment 4 `100000000': -32 pixel `000000000': 0 pixel `011111111': 31.875 pixel
Subaddress 4Dh D7 V656DEL [BP-POS] V656 delay 0: identical delay for modification 1: field 0 is one line shorter Note: has only effect when AFPROC=1 Active Field Processing for 656V generation 0: inverted active field used as v-sync output 1: v-sync modifies end of active video Output clock select 0: CLKOUT depends on CLKOUTSEL 1: CLKOUT is identical to clkb72 Belongs to 4Ch Belongs to 4Bh Belongs to 4Ah Belongs to 49h Belongs to 48h
D6
AFPROC [BP-POS] CLKOUTSEL72 [BP-POS] HINC4_8 [BP-POS] HINC3_8 [BP-POS] HINC2_8 [BP-POS] HINC1_8 [BP-POS] HINC0_8 [BP-POS]
D5
D4 D3 D2 D1 D0
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 4Eh D7-D0 HSCPOSC7-0 [BP-POS] Horizontal Scaling Factor For Post Scaler `010000000000': factor is 4 `101101010101': factor is 1.407 (682 960) `110000000000': factor is 4/3 (720 960) `111111111111': factor is 1
Subaddress 4Fh D7 CDELHPOS [BP-POS] CLKOUTSEL [BP-POS] Chrominance delay 0: no delay 1: half-pixel delay Output clock select 0: CLKOUT is identical to clkb27 1: CLKOUT is identical to clkb36 Note: HSYNC, VSYNC, BLANK are transferred to selected clock CLKOUT inversion 0: no inverted CLKOUT 1: inverted CLKOUT Panorama Mode enable `0': panorama mode disabled `1': panorama mode enabled Belongs to 4Eh
D6
D5
CLKOUTINV [BP-POS] HPANON [BP-POS] HSCPOSC 11-8 [BP-POS]
D4
D3-D0
Subaddress 50h D7-D0 HSEG1_7-0 [BP-POS] Beginning of Segment 1 for Panorama Mode Granularity: 2 pixel `00000000000': 0 pixel behind picture start `11111111111': 4094 pixel behind picture start
Subaddress 51h D7-D0 HSEG2_7-0 [BP-POS] Beginning of Segment 2 for Panorama Mode Granularity: 2 pixel `00000000000': 0 pixel behind picture start `11111111111': 4094 pixel behind picture start
Subaddress 52h D7-D0 HSEG3_7-0 [BP-POS] Beginning of Segment 3 for Panorama Mode Granularity: 2 pixel `00000000000': 0 pixel behind picture start `11111111111': 4094 pixel behind picture start
Subaddress 53h D7-D0 HSEG4_7-0 [BP-POS] Beginning of Segment 4 for Panorama Mode Granularity: 2 pixel `00000000000': 0 pixel behind picture start `11111111111': 4094 pixel behind picture start
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 54h D7 FIOFFOFF [BP-POS] FIELDBINV [BP-POS] HSEG2_10-8 [BP-POS] HSEG1_10-8 [BP-POS] Fieldoffset for ITU656 NTSC signals `0': disabled `1': enabled Backend field inversion `0': no inversion `1': inversion Belongs to 51h Belongs to 50h
D6
D5-D3 D2-D0
Subaddress 55h D7 CHRMSIG656 [BP-POS] VDEL_EN [BP-POS] HSEG4_10-8 [BP-POS] HSEG3_10-8 [BP-POS] Chrominance format for 656 output `0': (R-Y), (B-Y) output `1': -(R-Y), -(B-Y) output Vertical pulse delay backend (test only) `0': no delay `1': delayed Belongs to 53h Belongs to 52h
D6
D5-D3 D2-D0
Subaddress 56h D7 SHIFTUV [BP-DAC] Shift UV subsampling at digital output `0': take first UV couple `1': take second UV couple VSP9432/42 only Enable digital 656 Output `0': disable output `1': enable output
D6
DPOUT656 [BP-DAC]
Subaddress 57h D7 CHROMSIGN [BP-DAC] CHROMAMP [BP-DAC] Chrominance sign `0': (R-Y), (B-Y) output `1': -(R-Y), -(B-Y) output Chrominance amplification `0': amplification=1 `1': amplification=2
D6
Subaddress 58h D7-D0 PKLY [BP-DAC] Voltage Level for Y DAC Output `00000000': 0.4 V `10000000': 1.0 V `11111111': 1.9 V including peaking overshoots. 0.9 V for white max.
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VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 59h D7-D0 PKLU [BP-DAC] Voltage Level for U DAC Output `00000000': 0.4 V `10000000': 1.0 V `11111111': 1.9 V
Subaddress 5Ah D7-D0 PKLV [BP-DAC] Voltage Level for V DAC Output `00000000': 0.4 V `10000000': 1.0 V `11111111': 1.9 V
Subaddress 5Bh D7-D5 CONS [CP-CD] Color Switched On (SECAM) at level=CKILLS+CONS `000': min value `010': default `111': max value Force Color On `0': color depends on color decoder status `1': color always on Choice of UV or CrCb output 00: UV color space 01: CrCb color space 10: modified CrCb color space (SECAM only; PAL & NTSC: same as setting `01') Fix ACC to Nominal Value `0': ACC is working `1': ACC is fixed Freeze ACC `0': ACC is working `1': ACC is frozen
D4
COLON [CP-CD] CRCB [CP-CD]
D3-D2
D1
ACCFIX [CP-CD] ACCFRZ [CP-CD]
D0
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 5Ch D7-D5 CON [CP-CD] Color Switched On (PAL/NTSC) at level=CKILL+CON `000': min value `010': default `111': max value Chrominance coring `00': off `01': 1LSB `10': 2LSB `11': 3LSB Luminance notch-filter `0': notch-filter enabled `1': notch-filter bypassed Selection of Notch filter behavior in SECAM mode `00': 4.406 MHz `01': 4.250 MHz `10': 4.33 MHz `11': 4.406 / 4.25 dependent on transmitted color
D4-D3
UVCOR [CP-CD]
D2
NOTCHOFF [CP-CD] SECNTCH [CP-CD]
D1-D0
Subaddress 5Dh D7-D6 PWTHD [CP-CD] Selection Of `Peak-White' Threshold `00': 448 `01': 470 `10': 500 `11': 511 Chroma lock-range `00': 425 Hz `01': 463 Hz `10': 505 Hz `11': 550 Hz Luminance Offset in color decoder during visible picture `00': no offset `01': -32 LSB ( -7.5 IRE) `10':+32 LSB (+7.5 IRE) `11': -16 LSB (-3.75 IRE) Note: A 7.5 IRE offset is added during blanking in display processing. When choosing `10', the luminance offset is equal to the offset of the CVBS input as in both picture and blanking the same 7.5 IRE offset is used. Vertical Sync-Detection Slope `0': normal `1': slow
D5-D4
CLRANGE [CP-CD]
D3-D2
LMOFST [CP-CD]
D1
VDETIFS [CP-CD]
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 5Eh D7-D6 SDR [CP-CD] Secam Dr adjustment 00: 191 01: 194 10: 197 11: 200 Chroma Bandwidth selects chroma bandwidth `011100': nominal bandwidth
D5-D0
CHRF [CP-CD]
Subaddress 5Fh D7 COMB [CP-CD] CSTAND [CP-CD] Delay Line `0': use delay line `1': do not use delay line (only suited for NTSC) Color Standard Assignment `0000000': no color standard chosen `0000001': PAL N `0000010': PAL B `0000100': SECAM `0001000': PAL 60 `0010000': PAL M `0100000': NTSC M `1000000': NTSC 44 For allowed combinations please refer to chapter (see Section 2.1.5. on page 9) `1100110': PALB/SECAM/NTSCM/NTSC44/PAL60
D6-D0
Subaddress 60h D7-D0 CKILL [CP-CD] Chroma Level For Color Off (PAL/NTSC) `00000000': high burst amplitude `01000000': default `11111111': low burst amplitude
Subaddress 61h D7-D0 CKILLS [CP-CD] Chroma Level For Color Off (SECAM) `00000000': low burst amplitude `01000000': default `11111111': high burst amplitude
76
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 62h D7-D6 VPOL [CP-CD] V Polarity at VINP `00': use Vsync `01': use inverted Vsync `10': autodetect polarity `11': (reserved) Additional Filtering of Luminance `0': no filtering `1': filtering Luminance Delay `10000': 800 ns `0000': no delay `01111': -700 ns
D5
LPPOST [CP-CD] YCDEL [CP-CD]
D4-D0
Subaddress 63h D7-D0 HUE [CP-CD] Hue Control (Tint) `10000000': -89 `00000000': 0 `01111111': +88
Subaddress 64h D7-D0 NTSCREF [CP-CD] ACC Reference Adjustment (NTSC) `00000000': low reference value `10100101': nominal value `11111111': high reference value
Subaddress 65h D7-D0 PALREF [CP-CD] ACC Reference Adjustment (PAL) `00000000': low reference value `01011111': nominal value `11111111': high reference value
Subaddress 66h D7-D6 SLLTHD [CP-CD] Slicing Level Threshold H `00': no offset `01': small negative `10': small positive `11': large positive (adaptive) Subcarrier Adjustment `000000': -262 ppm `001111': 0 ppm `111111': 840 ppm
D5-D0
SCADJ [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
77
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 67h D7-D6 AGCMD [CP-CD] AGC method `00': sync amplitude and peak white `01': sync amplitude only `10': peak white only `11': fixed to value AGCADJ1 Automatic Gain Adjustment ADC1 `000000': 0.6 V input signal `111111': 1.8 V input signal
D5-D0
AGCADJ1 [CP-CD]
Subaddress 68h D7 AGCRES [CP-CD] AGCFRZE [CP-CD] AGCADJ2 [CP-CD] AGC reset `0': no reset `1': reset freeze AGC (ADC_CVBS) `0': normal operation `1': freeze AGC at current value Automatic Gain Adjustment ADC2 `000000': 0.6 V input signal `111111': 1.8 V input signal
D6
D5-D0
Subaddress 69h D7-D0 CLMPHIGH [CP-CD] Vertical End Of Clamping Pulse Granularity: 2 `00000000': line 256 `00111100': line 376 `11111111': line 766
Subaddress 6Ah D7-D4 CVBOSEL1 [CP-CD] Output select 1 for pin cvbso1 `0000': CVBS1 `0001': CVBS2 `0010': CVBS3 `0011': CVBS4 or Y1 `0100': CVBS5 or C1 `0101': CVBS6 or Y2 `0110': CVBS7 or C2 `0111': Y1 + C1 `1000': Y2 + C2 Vertical Start Of Clamping Pulse `0000': line 0 `0011': line 6 `1111`: line30
D3-D0
CLMPLOW [CP-CD]
78
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 6Bh D7 FLINE [CP-CD] FLDINV [CP-CD] CLPSTGY [CP-CD] YCSEL [CP-CD] CLMPD1 [CP-CD] Mode Selection `0': interlace input `1': progressive input Field Inversion `0': no inversion `1': inversion Clamping strategy `0': back-porch clamping `1': sync-tip-clamping Y/C select `0': CVBS input `1': Y/C input Measurement duration ADC1 Granularity: 200 ns `0000': 0 s `0111': 1.4 s `1111': 3 s
D6
D5
D4
D3-D0
Subaddress 6Ch D7-D6 HPOL [CP-CD] H Polarity at HINP `00': use Hsync `01': use inverted Hsync `10': autodetect polarity `11': (reserved) Automatic Multisync capability `0': disabled `1': enabled Channel-change signal for color decoder `0': color-decoder not reset after channel-change `1': color-decoder reset after channel-change Measurement duration ADC2 Granularity: 200 ns `0000': 0 s `0111': 1.4 s `1111': 3 s
D5
FHDET [CP-CD] DISCHCH [CP-CD] CLMPD2 [CP-CD]
D4
D3-D0
Micronas
Aug. 16, 2004; 6251-552-1DS
79
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 6Dh D7 NOSIGB [CP-CD] HINP [CP-CD] CLMPST1 [CP-CD] No signal behavior `0': noisy screen when out of sync `1': colored background insertion instead Horizontal Pulse Detection `0': from CVBS ADC1 `1': from RGBF ADC Measurement start ADC1 `000000': 0 s `011100': 5.6 s `111111': 12.8 s
D6
D5-D0
Subaddress 6Eh D7-D6 PLLTC [CP-CD] Time constant HPLL (VCR...TV) `00': very fast `01': fast `10': slow `11': very slow Measurement start ADC2 `000000': 0 s `011100': 5.6 s `111111': 12.8 s
D5-D0
CLMPST2 [CP-CD]
Subaddress 6Fh D7-D4 CVBSEL2 [CP-CD] Input select for ADC2 `0000': CVBS1 `0001': CVBS2 `0010': CVBS3 `0011': CVBS4 or Y1 `0100': CVBS5 or C1 `0101': CVBS6 or Y2 `0110': CVBS7 or C2 `0111': Y1 + C1 `1000': Y2 + C2 `1111': disabled Input select for ADC1 `0000': CVBS1 `0001': CVBS2 `0010': CVBS3 `0011': CVBS4 or Y1 `0100': CVBS5 or C1 `0101': CVBS6 or Y2 `0110': CVBS7 or C2 `0111': Y1 + C1 `1000': Y2 + C2 `1111': disabled
D3-D0
CVBSEL1 [CP-CD]
80
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 70h D7-D4 CVBOSEL2 [CP-CD] Output select for pin cvbso2 `0000': CVBS1 `0001': CVBS2 `0010': CVBS3 `0011': CVBS4 or Y1 `0100': CVBS5 or C1 `0101': CVBS6 or Y2 `0110': CVBS7 or C2 `0111': Y1 + C1 `1000': Y2 + C2 Output select for pin cvbso3 `0000': CVBS1 `0001': CVBS2 `0010': CVBS3 `0011': CVBS4 or Y1 `0100': CVBS5 or C1 `0101': CVBS6 or Y2 `0110': CVBS7 or C2 `0111': Y1 + C1 `1000': Y2 + C2
D3-D0
CVBOSEL3 [CP-CD]
Subaddress 71h D7-D0 FHFRRN [CP-CD] Free Running Frequency Of Horizontal PLL `00000000': 384 clocks (52.7 kHz) `11100100': 1296 clocks (15.625 kHz) `11111111': 1404 clocks (14.423 kHz)
Micronas
Aug. 16, 2004; 6251-552-1DS
81
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 72h D7 REFTRIMEN [CP-CD] SATNR [CP-CD] VINP [CP-CD] NSRED1-0 [CP-CD] Reference Value enable `0': use fuses `1': uses programmed value Noise reduction for satellite signal `0': disabled `1': enabled Vertical Pulse Detection `0': from CVBS signal `1': from V-input pin Noise Reduction For Horizontal PLL `000': 1/16 `001': 1/8 `010': 1/4 `011': 1/2 `100': 1 `101': 2 `110': 4 `111': 8 MSB is at address 7Eh, D2 Window Shift For Fine Error Calculation `100': -4 clock cycles `000': no offset `011': +3 clock cycles
D6
D5
D4-D3
D2-D0
LPCDEL [CP-CD]
Subaddress 73h D7-D0 VSHIFT [CP-CD] Field Detection Window Shift `00000000': no shift `11111111': shifted by 2048
Subaddress 74h D7 PALIDL1 [CP-CD] VTHRL50 [CP-CD] PAL/NTSC Identification Level 1 `0': less sensitive (192) `1': more sensitive (64) Vertical Window Noise Suppression Opening Opening= 4*VTHRL50 0000000: opening in first line 1111111: opening in line 508
D6-D0
Subaddress 75h D7 PALIDL0 [CP-CD] VTHRH50 [CP-CD] PAL/NTSC Identification Level 0 `0': less sensitive `1': more sensitive Vertical Window Noise Suppression Closing Closing= 312+4*VTHRH50 0000000: closing in line 312 1111111: closing in line 820 When VINP (72h) is set, 50 Hz values are taken for opening and closing values.
D6-D0
82
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 76h D7-D0 REFTRIM [CP-CD] Reference Value Bandgap `01000000': low reference `00000000': medium reference `01111111': high reference `1XXXXXXX': reference disabled, resistor used
Subaddress 77h D7-D4 REFTRIMCV [CP-CD] REFTRIMRGB [CP-CD] Reference Value ADC CVBS (antialiasfilter) `0000': narrow `1111': wide Reference Value ADC RGBF (antialiasfilter) `0000': narrow `1111': wide
D3-D0
Subaddress 78h D7 SLLTHDVP [CP-CD] THRSEL [CP-CD] CLMPST1S [CP-CD] Vertical Slicing Level Threshold Polarity `0': positive `1': negative H Slicing level threshold `0': 50 % `1': 37 % Clamping start for ADC1 `000000': 0 s `011100': 5.6 s `111111': 12.8 s
D6
D5-D0
Subaddress 79h D7-D6 SCMIDL [CP-CD] SECAM identification level `00': 128 `01': 64 `10': 96 `11': 80 Clamping start ADC2 `000000': 0 s `011100': 5.6 s `111111': 12.8 s
D5-D0
CLMPST2S [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
83
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 7Ah D7-D3 ACCLIM [CP-CD] IFCOMP [CP-CD] ACC-limitation for weak signals `00000': strong limitation `11111': no limitation IF compensation filter `000': pal prefiltering `001': pal prefiltering + IF `010': prefiltering `011': IF 6dB `100': flat Note: `000' or `001' are not suited for 3.58 MHz subcarrier color standards (PAL M, PAL N, NTSC M)
D2-D0
Subaddress 7Bh D7-D4 CLMPD2S [CP-CD] Clamping duration for ADC2 Granularity: 200 ns `0000': 0 s `0111': 1.4 s `1111': 3.0 s Clamping duration for ADC1 Granularity: 200 ns `0000': 0 s `0111': 1.4 s `1111': 3.0 s
D3-D0
CLMPD1S [CP-CD]
Subaddress 7Ch D5 EIA770 [CP-CD] EIA 770 support `0': standard TV signals expected `1': progressive signals expected timing according to EIA 770.1 or EIA 770.2 when `1' Power Down Of Crystal Oscillator Shaper `0': normal operation `1': power down active Power Down Of Crystal Oscillator Amplifier `0': normal mode `1': power down mode Testmode Control Of Crystal Oscillator `0': normal operation (shaper active) `1': external clock input (shaper replaced) Amplifier Current Setting Of Oscillator Pad `00': 100 A `01': 590 A `10': 235 A `11': 1730 A
D4
SHAPERDIS [CP-PP] OSCPD [CP-PP] TSTSHAPERI [CP-PP] FREQSEL [CP-PP]
D3
D2
D1-D0
84
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 7Dh D6-D4 BELLFIR [CP-CD] Bell filter FIR component `000': -116 `001': -113 `010': -110 `011': -108 `100': -106 `101': -104 `110': -102 `111': -100 Bell filter IIR component `000': 8 `001': 9 `010': 10 `011': 11 `100': 12 `101': 13 `110': 14 `111': 16 Vertical Flywheel `0': disabled `1': enabled
D3-D1
BELLIIR [CP-CD]
D0
VFLYWHL [CP-CD]
Subaddress 7Eh D7-D6 FLNSTRD [CP-CD] Force line standard at CVBS/RGB frontend `00': automatic `01': force 50 Hz `10': force 60 Hz `11': (reserved) Enable limiter `0': disabled `1': enabled I-adjustment for horizontal PLL `00': *1 `01': *2 `10': *4 `11': *8 Belongs to 72h Lowpass for vertical sync-separation `00': none `01': weak `10': medium `11': strong
D5
ENLIM [CP-CD] ISHFT [CP-CD]
D4-D3
D2 D1-D0
NSRED2 [CP-CD] VLP [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
85
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 7Fh D7 SECACC [CP-CD] SECDIV [CP-CD] SECINC1 [CP-CD] Secam acceptance `0': disabled `1': enabled Secam Divider `0': divide by 4 `1': divide by 2 Secam increment 1 `00': 2 `01': 3 `10': 4 `11': 5 Secam increment 2 `00': 1 `01': 2 `10': 3 `11': 4 Secam rejection level `00': 320 `01': 384 `10': 352 `11': 1024
D6
D5-D4
D3-D2
SECINC2 [CP-CD]
D1-D0
SCMREL [CP-CD]
86
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 80h D7 PORCNCL [CP-CD] Reset control bit cancel `0': no operation `1': reset POR bit (8Ch) after use, PORCNCL must be set to `0' again Luminance Notch selection `000': sharp notch `001': medium 1 `010': medium 2 `011': broad notch `100': broad steep notch (PAL, SECAM only) Force Chroma PLL reset `0': no reset `1': reset chroma PLL after use, CPLLRES must be set to `0' again Disable all chroma resets `0': resets allowed `1': resets disabled may only be used if ONE color standard is selected Notchfrequency for 4,250 MHz `0': 4.25 MHz `1': 4.2 MHz has only effect in SECAM mode Notchfrequency for 4,406 MHz `0': 4.406 MHz `1': 4.356 MHz has only effect in SECAM mode
D6-D4
NTCHSEL [CP-CD]
D3
CPLLRES [CP-CD]
D2
DISALLRES [CP-CD]
D1
TRAPBLU [CP-CD]
D0
TRAPRED [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
87
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 80h D7 PORCNCL [CP-CD] Reset control bit cancel `0': no operation `1': reset POR bit (8Ch) after use, PORCNCL must be set to `0' again Luminance Notch selection `000': sharp notch `001': medium 1 `010': medium 2 `011': broad notch `100': broad steep notch (PAL, SECAM only) Force Chroma PLL reset `0': no reset `1': reset chroma PLL after use, CPLLRES must be set to `0' again Disable all chroma resets `0': resets allowed `1': resets disabled may only be used if ONE color standard is selected Notchfrequency for 4,250 MHz `0': 4.25 MHz `1': 4.2 MHz Note: has only effect in SECAM mode Notchfrequency for 4,406 MHz `0': 4.06 MHz `1': 4.356 MHz Note: has only effect in SECAM mode
D6-D4
NTCHSEL [CP-CD]
D3
CPLLRES [CP-CD]
D2
DISALLRES [CP-CD]
D1
TRAPBLU [CP-CD]
D0
TRAPRED [CP-CD]
88
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 81h D7 ADLCK [CP-CD] ADLCKSEL [CP-CD] ADLCKCC [CP-CD] VFLYWHLMD[CPCD] Additional lock-detection `0': no used `1': used Additional lock-detection selection `0': PALID `1': PALDET Additional lock-detection color-killer `0': do not use lock signal `1': use lock-signal Vertical Flywheel Mode `00': CHECK FOR CORRECT STANDARD `01': 3 lines deviation allowed `10': 4 lines deviation allowed, no check for interlace `11': 5 lines deviation allowed, no check for interlace Secam Acceptance level `000': 100 `001': 84 `010': 64 `011': 32 `100': 70 `101': 76 `110': 90 Note: must be enabled by SECACC (7Fh) to have an effect
D6
D5
D4-D3
D2-D0
SECACCL [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
89
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 82h (no auto-increment) D7-D6 SYNCFTHD [CP-CD] SYNCF threshold 00: 4 lines 01: 3 lines 10: 2 lines 11: 1 line 2nd IF compensation filter `0': disabled `1': enabled PAL/NTSC identifikation level 2 `0': less sensitive `1': more sensitive Chroma PLL Open `0': normal operation `1': chroma PLL opened Deemphase Filtering For Standard Detection `0': weak `1': strong PAL/NTSC Detection: Increment 1 `0': +3 `1': +2 PAL/NTSC Detection: Increment 2 `0': -1 `1': -2 do not use PALINC2=1 in combination with PALINC1=1
D5
IFCOMPSTR [CP-CD] PALIDL2 [CP-CD] CPLLOF [CP-CD] DEEMPSTD [CP-CD] PALINC1 [CP-CD] PALINC2 [CP-CD]
D4
D3
D2
D1
D0
Subaddress 83h (Read-only) D0 FBLACTIVE [CP-I2C] Activity At FBL Input `0': no activity `1': activity reset automatically when read
Subaddress 84h (Read-only, no auto-increment)) D6-D0 NOISEME [FP-TNR] Noise level of the input signal 0000000: no noise 1111110: strong noise 1111111: strong noise or measurement failed Note: no autoincrement possible
90
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 85h (Read-only) D5 LBSTATUS [FP-TNR] Status bit for letter box detection: 0: No new value available 1: New value from Letter Box Detection available Note: reset automatically when read Indicates Overflow at FBL Input `0': no overflow `1': overflow Note: reset automatically when read Indicates Overflow at GREEN Input `0': no overflow `1': overflow Note: reset automatically when read Indicates Overflow at BLUE Input `0': no overflow `1': overflow Note: reset automatically when read Indicates Overflow at RED Input `0': no overflow `1': overflow Note: reset automatically when read Indicates New Value of the Noise Measurement 0: NOISEME has not been updated 1: New value of NOISEME available Note: reset automatically when read
D4
PFBL [FP-TNR]
D3
PG [FP-TNR]
D2
PB [FP-TNR]
D1
PR [FP-TNR]
D0
NMSTATUS [FP-TNR]
Subaddress 86h (Read-only) D0 STABLL [PP] Shows LL-HPLL Lock Status `0': LL_HPLL is not locked `1': LL_HPLL is locked
Subaddress 87h (Read-only) D1-D0 SMMIRROR [BP-O/M] Operation mode for scan rate conversion: `00': AABB (Raster ) `01': AAAA (Raster ) `10': AAAA (Raster ) `11': BBBB (Raster )
Micronas
Aug. 16, 2004; 6251-552-1DS
91
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 88h (Read-only) D7 DETHPOL [CP-CD] DETVPOL [CP-CD] STDET [CP-CD] Detected Polarity Of HSync `0': negative `1': positive Detected Polarity Of V Sync `0': negative `1': positive Detected Color Standard `000': non standard or standard not detected `001': NTSC M `010': PAL M `011': NTSC44 `100': PAL60 `101': PAL N `110': SECAM `111': PAL B/G SCDEV valid indication `0': SCDEV not valid `1': SCDEV valid PAL identification (algorithm 1) `0': not PAL `1': PAL Colorkill status `0': color off `1': color on
D6
D5-D3
D2
SCOUTEN [CP-CD] PALID [CP-CD] CKSTAT [CP-CD]
D1
D0
Subaddress 89h (Read-only) D7 LNSTDRD [CP-CD] INT [CP-CD] SCDEV [CP-CD] Line Standard detection `0': 60 Hz `1': 50 Hz Interlace Detection `0': progressive input `1': interlace input Deviation Of Clock System or Color Carrier `100000': max. negative deviation `000000': no deviation `011111': max. positive deviation
D6
D5-D0
Subaddress 8Ah (Read-only) D7-D0 LPFLD [CP-CD] Nr. of lines per field for input signal lines= 256+LPFLD*2 `00000000': 256 lines or less `11111111': 766 lines or more
92
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 8Bh (Read-only) D7-D0 NRPIXEL [CP-CD] Pixel number of input signal Granularity: 4 `00000000': 384 or less `11111111': 1404 or more PIXEL=4*NRPIXEL+384
Subaddress 8Ch (Read-only) D7 POR [CP-CD] Reset indication a reset at pin 24 (reset) sets POR. POR is reset with PORCNCL (80h) `0': no reset appeared `1': reset appeared Vertical Flywheel mode locked 0: unlocked 1: locked VFLYWHL must be enabled to give a result Status of horizontal synchronization `0': sync separation not locked `1': sync separation locked and stable PAL identification (algorithm 2) `0': not PAL `1': PAL
D3
VFLYMD [CP-CD]
D2
STAB [CP-CD] PALDET [CP-CD]
D0
Subaddress 8Dh (Read-only) D7-D0 REFTRIMRD [CP-CD] Reference Value Bandgap `01000000': low reference `00000000': medium reference `01111111': high reference `1XXXXXXX': reference disabled, resistor used Note: contains fused value only when REFTRIMEN (72h)=0.
Subaddress 8Eh (Read-only) D7-D4 REFTRIMCVRD [CP-CD] Reference Value CVBS ADC `0000': narrow `1111': wide Note: contains fused value only when REFTRIMEN (72h)=0. Reference Value RGB ADC `0000': narrow `1111': wide Note: contains fused value only when REFTRIMEN (72h)=0.
D3-D0
REFTRIMRGBRD [CP-CD]
Micronas
Aug. 16, 2004; 6251-552-1DS
93
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress 8Fh (Read-only, NOT compatible to 940X family) D3 SLS [CP-I2C] VERSION [CP-I2C] Line Standard At Device Output `0': 100 Hz (VSP 9402A, VSP 9412A) `1': 50 Hz (VSP 9432A, VSP 9442A) Version Of VSP 94XX Family `001': VSP 94x5B `010': VSP 94x2A `011': VSP 94x7B `101': VSP 94x9C others: reserved
D2-D0
Subaddress 90h (Read-only) D7 AM50O [CP-I2C] AM60O [CP-I2C] AGCADJCV [CP-I2C] Last detected Standard 50 Hz `0': PAL or none `1': SECAM Last detected Standard 60 Hz `0': NTSC M or none `1': NTSC44 or PAL60 AGC value for ADC1 000000: smallest input range 111111: biggest input range
D6
D5-D0
Subaddress 91h (Read-only) D6-D0 VLENGTH [CP-I2C] Length of vertical pulse 0000000: short v 1111111: long v
Subaddress 92h (Read-only) D7-D0 MINV [CP-I2C] Measured sync amplitude 00000000: smallest sync 11111111: largest sync
Subaddress 93h (Read-only) D4-D0 PWADJCNT [CP-I2C] Peak White adjust counter 00000: no PW reduction 11111: largest PW reduction
Subaddress 96h (Read-only) D0 V40STAT [FP-I2C] V Status bit of 40.5 MHz domain `0': New write or read cycle can start `1': No new write or read cycle can start
Subaddress 98h (Read-only) D0 V36BSTAT [BP-I2C] V Status bit of backend 36 MHz domain `0': New write or read cycle can start `1': No new write or read cycle can start
94
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress 99h (Read-only) D0 V20STAT [CP-I2C] V Status bit of 20.25 MHz domain `0': New write or read cycle can start `1': No new write or read cycle can start
Subaddress A0h D7-D4 D3-D0 KPNL [PP] KPL [PP] Proportional factor for loop filter if HPLL is not locked same values as in locked condition (KPL) Proportional factor for loop filter if HPLL is locked) 00000: 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111:16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7
Micronas
Aug. 16, 2004; 6251-552-1DS
95
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress A1h D7-D4 D3-D0 KINL [PP] KIL [PP] Integrational factor for loop filter if HPLL is not locked same values as in locked condition (KIL) Integrational factor for loop filter if HPLL is locked 00000: 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111:16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7
Subaddress A2h D7-D0 LIMIP [PP] Limiter Control for P-part for increased dynamic range LIMIT_P= 16*LIMIP `00000000': 0 `11111110': 4064 `11111111': no limitation
Subaddress A3h D7-D0 LIMII [PP] Limiter Control for I-part for increased dynamic range LIMIT_I= 16*LIMII `00000000': 0 `11111110': 4064 `11111111': no limitation
96
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress A4h D7 D6 D5 D4 D3-D0 KPNL4 [PP] KPL4 [PP] KINL4 [PP] KIL4 [PP] LIMLR [PP] Refer to A0h Refer to A0h Refer to A1h Refer to A1h Limit LL-PLL lock-in range 0000: full lock-in range of 5.85 % 0001: lock in range limited to 3.8 % 0010: lock in range limited to 2.55 % 0011: lock in range limited to 1.27 % 0100: ock in range limited to 0.63 % 0101: lock in range limited to 0.32 % 0110: lock in range limited to 0.19 % 0111: lock in range limited to 0.13 % 1000: lock in range limited to 5 % 1001: lock in range limited to 4.5 % 1010: lock in range limited to 3.1 % 1011: lock in range limited to 2.1 % 1100: lock in range limited to 1.5 % 1101: lock in range limited to 1 % 1110: (reserved) 1111: (reserved)
Subaddress B0 D6-D5 AGCTHD [CP-CD] AGC hysterisys 00: broad 01: medium 1 10: medium 2 11: small Fine Error characteristic 00000: smallest gain 10000: default (equal to A32 version) 11111: largest gain
D4-D0
FEMAG [CP-CD]
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress B1 D6-D4 SLLTHDV [CP-CD] Slicing Level Threshold V `000': no offset `001': 4 `010': 8 `011':12 `101': adaptive (limited to 4) `110': adaptive (limited to 8) `111': adaptive (limited to 12) polarity is selected by SLLTHDVP (78h) Automatic standard detection priority 60 Hz 00: NTSC M 01: NTSC44/PAL60 10: (reserved) 11: automatic Automatic standard detection priority 50 Hz 00: PAL B 01: SECAM 10: (reserved) 11: automatic
D3-D2
AMSTD60 [CP-CD]
D1-D0
AMSTD50 [CP-CD]
Subaddress B2 D7-D6 SDB [CP-CD] Secam Db adjustment 00: -55 01: -58 10: -61 11: -64 Vertical Pulse gating 0: disabled 1: enabled Vertical length measurement with vertical pulse detection 0: disabled 1: enabled Vertical Detection Integration Time Constant 000: 400 clock cycles 001: 375 clock cycles 010: 350 clock cycles 011: 300 clock cycles 100: 250 clock cycles 101: 225 clock cycles 110: 200 clock cycles 111: automatic
D4
MVPG [CP-CD] MVP [CP-CD] VDETITC [CP-CD]
D3
D2-D0
Subaddress B3 D6-D0 VTHRL60 [CP-CD] Vertical Window Noise Suppression Opening Opening=4*VTHRL60M 0000000: opening in first line 1111111: opening in line 508
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress B4 D6-D0 VTHRH60 [CP-CD] Vertical Window Noise Suppression Closing Closing=262+4*VTHRH60M 0000000: closing in line 262 1111111: closing in line 770
Subaddress B5 D7-D5 DEEMPIIR [CP-CD] Deemphase filter IIR component `000': 5 `001': 6 `010': 7 `011': 8 `100': 9 `101': 10 `110': (reserved) `111': (reserved) Deemphase filter FIR component `0000': 16 `0101': 21 `1111': 31
D3-D0
DEEMPFIR [CP-CD]
Subaddress B7 D7-D0 NAPPLIPI [FP-RGB] Not active pixels from HSYNC to input data for ITU Delay=NAPPLIPI * 2 + NAPIPPHI
Subaddress B8 D7-D0 ALPFIPI [FP-RGB] Active lines per field for ITU Active lines=ALPFIPI * 2 (int) 144: 288 active lines
Subaddress B9 D7-D0 APPLIPI [FP-RGB] Active pixels per line for ITU Active pixels=APPLIPI * 2 (int) 360=720 lines
Subaddress BA D7 APPLIPI[8] [FP-RGB] NALPFIPI [FP-RGB] Active pixels per line for ITU Active pixels=APPLIPI * 2 (int) 360=720 lines Not active lines per field for ITU (int) 20= 20 lines
D6
Subaddress BCh D7-D0 FRINC18-11 [PP] Set HDTO freerunning frequency Granularity=103 Hz 33981d (minimum: nominal pixel clock= 3.5 MHz) 349525d (nominal pixel clock= 36 MHz) 388362d (maximum: nominal pixel clock= 40 MHz)
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress BD D7-D0 FRINC10-3 [PP] Belongs to BCh
Subaddress BE D2-D0 FRINC2-0 [PP] Belongs to BCh
Subaddress C0 D7-D0 HSPPL [FP-RGB] Hsync shift shift=HSPPL * 4 00000000: default
Subaddress C1 D7 FOFST [FP-RGB] VSLPF [FP-RGB] Offset of active field at interlaced mode (line offset): 0: NALPFIPI+1 at field A, NALPFIPI at field B 1: NALPFIPI at field A, NALPFIPI+1 at field B Vsync shift shift=VSLPF * 4 0000000: default
D2-D0
Subaddress D0 D7-D6 D5 VBLANDEL [BP-PM] VBLANPOL [BP-PM] FSWFTL [BP-PM] VBLANLEN [BP-PM] Refer to D1h Vertikal Blank Signal Polarity 0: positive 1: negative Stability Signal of LL_HPLL `0': STABLL is generated accoding to SETSTABLL `1': STABLL is forced to 1 (hout synchronization enabled) Refer to D2h
D2
D1-D0
Subaddress D1 D7-D0 VBLANDEL[7:0] [BP-PM] Vertical Delay in lines from vsync to active edge of blank signal: Blank_start=1*VBLANDEL `0000000000': no delay `1111111111': 1023 lines delay
Subaddress D2 D7-D0 VBLANLEN [BP-PM] Vertical Length in lines from start of active blank signal: Blank_length=4*VBLANLEN `00000000': no line `11111111': 1020 lines
Subaddress E0 D7-D0 LBGRADDET [FP-RGB] Threshold for gradient detected (int) 50: default
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress E1 D7-D0 LBVWENDLO [FP-RGB] Vertical measure window lower end (int) 150: default, [in lines (*2) related to VSYNC]
Subaddress E2 D7-D0 LBHWEND [FP-RGB] Horizontal measure window end (int) 180: default, [in active pixels (*4) related to HSYNC]
Subaddress E3 D7-D0 LBHIWHITE [FP-RGB] Histogram white (int) 50: default
Subaddress E4 D7-D0 LBHISTBLA [FP-RGB] Histogram black (int) 25: default
Subaddress E5 D7 D6-D0 LBMASLA [FP-RGB] LBVWSTLO [FP-RGB] Set to 1 Vertical measure window lower start (int) 96: default], [in lines (*2) related to VSYNC]
Subaddress E6 D7 LBFS [FP-RGB] LBVWENDUP [FP-RGB] Field subsampling mode 0: A+B fields 1: only A field Vertical measure window upper end (int) 73: default], [in lines (*2) related to VSYNC]
D6-D0
Subaddress E7 D7 LBVISUON [FP-RGB] LBHWST [FP-RGB] Visualisation of letter box results 0: disabled 1: enabled Horizontal measure window start (int) 36: default, [in active pixels (*4) related to HSYNC]
D6-D0
Subaddress E8 D5-D0 LBVWSTUP [FP-RGB] Vertical measure window upper start (int) 20: default], [in lines (*2) related to VSYNC]
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress E9 D7 LBSTABILITY [FP-RGB] LB43SENS [FP-RGB] LBNGFEN [FP-RGB] LBTHDNBNG [FP-RGB] Stability flag 0: continuous format update 1: Format update only once Sensitivity to 4:3 switch 0: off 1: on No gradient found 0: disabled 1: enabled Threshold for darkness-brightness, gradient only (int) 15: default]
D6
D5
D4-D0
Subaddress EA D7-D6 LBSUB [FP-RGB] Subsampling mode 0x: 13.5 MHz (1, e.g. digital 656 input) 10: 20.25 MHz source (1.5, for CVBS, YUV and RGB) 11: 40.5 MHz source (3) Reset of gradient method 0: no reset 1: reset Histogram stability delay (int)10=default
D5
LBGRADRST [FP-RGB] LBHSDEL [FP-RGB]
D4-D0
Subaddress EB D4-D0 LBTHDNBNHA [FP-RGB] Threshold for darkness-brightness, histogram, activity (int)30=default
Subaddress EC D4-D0 LBACTIVITY [FP-RGB] Activity (int) 5: default]
Subaddress ED D4-D0 LBGFBDEL [FP-RGB] Gradient fall back delay value (int) 11: default]
Subaddress EE D4-D0 LBGSDEL [FP-RGB] Gradient stability delay value (int) 10: default]
Subaddress EF D4-D0 LBASDEL [FP-RGB] Activity stability delay (int) 10: default]
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DATA SHEET
VSP 94x2A
Table 3-8: I2C bus command description, continued Bit Name Description
Subaddress F0 (read only) D7 D6-D0 LBELAA [FP-RGB] LBSLAA [FP-RGB] Refer to F1h Letter box detection: Start line of active area LBSLAA is measured in relation to VSYNC
Subaddress F1 (read only) D7-D0 LBELAA [FP-RGB] Letter box detection: End line of active area LBELAA is measured in relation to VSYNC
Subaddress F2 (read only) D7 LBFORMAT [FP-RGB] LBSUBTITLE [FP-RGB] LBTOPTITLE [FP-RGB] GRADISSTABLE [FP-RGB] TOPTITLE [FP-RGB] SUBTITLE [FP-RGB] NOGRADFOUND [FP-RGB] SWITCHTO43 [FP-RGB] Letter box detection: Format 0: 4:3 format 1: other format (letter box) Letter box detection: Subtitle flag 0: no subtitle 1: subtitle available Letter box detection: Toptitle flag 0: no toptitle 1: toptitle available Letter box detection: gradient is stable internal value, only for test purposes LBD: upper area contains high activity internal value, only for test purposes LBD: lower area contains high activity internal value, only for test purposes LBD: no gradient found internal value, only for test purposes LBD: switch to 4:3 format internal value, only for test purposes
D6
D5
D4 D3 D2 D1 D0
Subaddress F3 (read only) D7 D6-D0 GRADELAA [FP-RGB] GRADSLAA [FP-RGB] Refer to F4h LBD: Gradient start line of active area internal value, only for test purposes
Subaddress F4 (read only) D7-D0 GRADELAA [FP-RGB] LBD: Gradient end line of active area internal value, only for test purposes
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Table 3-8: I2C bus command description, continued Bit Name Description
DATA SHEET
Subaddress F5 (read only) D3 D2 D1 D0 LPBLACK [FP-RGB] UPBLACK [FP-RGB] LPWHITE [FP-RGB] UPWHITE [FP-RGB] LBD: lower area contains medium brightness level internal value, only for test purposes LBD: upper area contains medium brightness level internal value, only for test purposes LBD: lower area contains high brightness level internal value, only for test purposes LBD: upper area contains high brightness level internal value, only for test purposes
Subaddress F6h (Read-only, compatible to 940X family) D7-D5 VERSION [CP-I2C] Version Of VSP 94xxX Family: `001': VSP 94x5B `010': VSP 94x2A `011': VSP 94x7B `101': VSP 94x9C others: reserved Line Standard At Device Output `0': 100 Hz (VSP 9402A, VSP 9412A) `1': 50 Hz (VSP 9432A, VSP 9442A) Revision of VSP94x2A `000': A23 or below `001': A31 or A32 `010': B13 or B14
D4
SLS [CP-I2C] REV [CP-I2C]
D3-D1
Subaddress FEh FE Subaddress FFh FF Any value to this subaddress executes previous I2C protocolls according to the take-over-mechanism (dedicated v-pulse, V20, V40, V36) Any value to this subaddress executes previous I2C protocolls immediately
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DATA SHEET
VSP 94x2A
4. Specifications 4.1. Outline Dimensions
Fig. 4-1: PMQFP80-1: Plastic Metric Quad Flat Package, 80 leads, 14 x 14 x 2 mm3 Ordering code: VK Weight approximately 0.96 g
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4.2. Pin Connections and Short Descriptions for VSP 9402 and VSP 94121)
1)
DATA SHEET
For VSP 9412, the pin connections differ for pins: 1, 2, 3, 75, 76, 77, 78, 79 ,80 (see Section 4.3. on page 109).
Pin No. 1 2 3 4 5 6 7 8
Pin Name VDDDACY AYOUT VSSDACY VSSD2 VDDD2 SDA TMS 656VIN/BLANK1)
Type S/I O/I S/I S S I/O I I/O
Connection
(If not used)
Short Description DAC (Y) Y output DAC (Y) Supply voltage for digital (0 V digital) Supply voltage for digital (1.8 V digital) I2C-Bus data Testmode select (Connected to vdd33)
Connect to Vss and disable blank Leave open Leave open
Separate V input for 656 / BLANK output
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
656CLK 656IO7 VSSP2 VDDP2 SCL V2) 656IO6 656IO5 HOUT H503) ADR / TDI V504) 656IO4 656IO3 VOUT RESET VDDP3 VSSP3
I/O I/O S S I I I/O I/O O O I O I/O I/O O I S S
Digital input / output clock Digital input / output (MSB) Supply voltage for digital (0 V pad) Supply voltage for digital (3.3 V pad) I2C-Bus clk
Connect to Vss Leave open Leave open Leave open Leave open
Vertical pulse for RGB input Digital input / output Digital input / output Horizontal output (Single or double scan, dependent on version) Hout 50 Hz (with skew) I2C address / test data in
Leave open Leave open Leave open Leave open
Vout 50 Hz Digital input / output Digital input / output Vertical output (Single or double scan, dependent on version) Reset input (Reset when low) Supply voltage for digital (0 V pad) Supply voltage for digital (3.3 V pad)
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DATA SHEET
VSP 94x2A
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Pin Name CLKOUT VDDD3 VSSD3 656IO2 656IO1 656IO0 VSSD4 VDDD4 VDDAFBL VSSAFBL FBL1 FBL2 RIN1 GIN1 BIN1 VDDARGB VSSARGB VDD33RGB VSS33RGB RIN2 GIN2 BIN2 VSSD55) VDDAC1 VSSAC1 CVBS1
Type O S S I/O I/O I/O S S S S I I I I I S S S S I I I S S S I
Connection
(If not used)
Short Description Output clock (27 MHz nom.) Supply voltage for DRAM (1.8 V digital) Supply voltage for digital (0 V digital)
Leave open
Leave open Leave open Leave open
Digital input / output Digital input / output Digital input / output (LSB) Supply voltage for digital (0 V digital) Supply voltage for digital 1.8 V digital Supply voltage for FBL (1.8 V) Supply voltage for FBL (0 V)
Connect to Vss Connect to Vss Connect to Vss Connect to Vss Connect to Vss
Fast Blank input 1 (H1) (Analog input) Fast Blank input 2 (H2) (Analog input) R or V in1 (Analog input) G or Y in1 (Analog input) B of U in1 (Analog input) Supply voltage for RGB (1.8 V) Supply voltage for RGB (0 V) Supply voltage RGB (3.3 V) Supply voltage RGB (0 V)
Connect to Vss Connect to Vss Connect to vss Connect to Vss
R or V in2 (Analog input) G or Y in2 (Analog input) B of U in2 (Analog inpu) Supply voltage for digital (0 V) Supply voltage CVBS1 (1.8 V) Supply voltage CVBS1 (0 V)
Connect to Vss
CVBS input (Analog input)
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DATA SHEET
Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Pin Name CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VDD33C VSS33C CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20
Type I I I I I I S S O O O S S S S S O I I S S I/O
Connection
(If not used)
Short Description CVBS input (Analog input) CVBS input (Analog input) CVBS input or Y1 (Analog input) CVBS input or C1 (Analog input) CVBS input or Y2 (Analog input) CVBS input or C2 (Analog input) Supply voltage CVBS (3.3 V) Supply voltage CVBS (0 V)
Connect to Vss Connect to Vss Connect to Vss Connect to Vss Connect to Vss Connect to Vss
Leave open Leave open Leave open
CVBS output 3 (Analog output) CVBS output 2 (Analog output) CVBS output 1 (Analog output) Supply voltage CVBS2 (1.8 V) Supply voltage CVBS2 (0 V) Supply voltage for digital (1.8 V digital) Supply voltage for digital (0 V digital) Supply voltage for PLL (1.8 V) Crystal connection 2 Crystal connection 1 Testclock Supply voltage for digital (3.3 V pad) Supply voltage for digital (0 V pad)
Connect to Vss and disable clock Leave open Leave open Leave open
Separate H input for 656 / 20.25 clock output
75 76 77 78 79
VDDDACV AVOUT VSSDACV VDDDACU AUOUT
S/I O/I S/I S/I O/I
DAC (V) (27 MHz nom.) V output DAC (V) DAC (U) U output
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DATA SHEET
VSP 94x2A
Pin No. 80
1) 2) 3) 4) 5)
Pin Name VSSDACU
Type S/I
Connection
(If not used)
Short Description DAC (U)
In VSP 9402, A31 (and higher) and in VSP 94xxA/B/C, this pin is shared by 656vin and blank. In VSP 94xxB and VSP 94xxC, this pin is shared by v and intr (C800 controller output). In VSP 94xxB and VSP 94xxC, this pin is shared by h50 and irq (Data-slicer-interrupt). In VSP 94xxB and VSP 94xxC, this pin is shared by v50 and blank. This pin is not used and not bonded in VSP 9402A. The use of this pin in VSP 94xxB/C will be VSS. For upgradability, it is recommended to not leave this pin open.
4.3. Differing Pin Connections and Short Descriptions for VSP 9412 Pin No. 1 2 3 75 76 77 78 79 80 Pin Name I656I5 I656I6 I656I7 I656ICLK I656I0 I656I1 I656I2 I656I3 I656I4 Type S/I O/I S/I S/I O/I S/I S/I O/I S/I Connection
(If not used)
Short Description 656 input 656 input 656 input (MSB) 656 input clock 656 input (LBS) 656 input 656 input 656 input 656 input
Leave open
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4.4. Pin Configurations
VSSAC1 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VDD33C VSS33C VDDAC1 VSSD5 BIN2 GIN2 RIN2 VSS33RGB VDD33RGB VSSARGB VDDARGB BIN1
DATA SHEET
CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20 VDDDACV AVOUT VSSDACV VDDDACU AUOUT VSSDACU
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 33 32
GIN1 RIN1 FBL2 FBL1 VSSAFBL VDDAFBL VDDD4 VSSD4 656IO0 656IO1 656IO2 VSSD3 VDDD3 CLKOUT VSSP3 VDDP3 RESET VOUT 656IO3 656IO4
VSP 9402 A
31 30 29 28 27 26 25 24 23 22
21 10 11 12 13 14 15 16 17 18 19 20
VDDACY AYOUT VSSDACY VSSD2 VDDD2 SDA TMS 656VIN/BLANK 656CLK 656IO7 V SCL VDDP2 VSSP2 H50 HOUT 656IO5 656IO6
V50 ADR/TDI
Fig. 4-2: PMQFP80-1 Package (Version VSP 9402A)
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DATA SHEET
VSP 94x2A
VSSAC1 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VDD33C VSS33C
VDDAC1 VSSD5 BIN2 GIN2 RIN2 VSS33RGB VDD33RGB VSSARGB VDDARGB BIN1
CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20 I656ICLK I656I0 I656I1 I656I2 I656I3 I656I4
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 33 32
GIN1 RIN1 FBL2 FBL1 VSSAFBL VDDAFBL VDDD4 VSSD4 656IO0 656IO1 656IO2 VSSD3 VDDD3 CLKOUT VSSP3 VDDP3 RESET VOUT 656IO3 656IO4
VSP 9412 A
31 30 29 28 27 26 25 24 23 22
21 10 11 12 13 14 15 16 17 18 19 20
I656I5 I656I6 I656I7 VSSD2 VDDD2 SDA TMS 656VIN/BLANK 656CLK 656IO7 V SCL VDDP2 VSSP2 H50 HOUT 656IO5 656IO6
V50 ADR/TDI
Fig. 4-3: PMQFP80-1 Package (Version VSP 9412A)
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4.5. Pin Circuits
VDDP
DATA SHEET
VSSP PIN
OUT
PIN
VSSB
Fig. 4-4: Supply Pins (Ground): VSSDACY, VSSDACU, VSSDACV, VSS33C, VSS33RGB, VSSP1, VSSP2, VSSP3
Fig. 4-8: Digital Output Pins: H50, V50, CLKOUT, HOUT, VOUT
VDDP PIN
VDDP
PIN
IN
VSSB
Fig. 4-5: Supply Pins (Power 3.3 V): VDDDACY, VDDDACU, VDDACV, VDD33C, VDD33RGB, VDDP1, VDDP2, VDDP3
Fig. 4-9: Digital Input Pins: V, TMS, ADR/TDI, RESET
VDDP
REF (int.)
OSCCLK
IN OUT
XIN
XOUT
PIN
Fig. 4-6: Input/Output Pins (Crystal connection): XIN, XOUT
Fig. 4-10: I2C bus Pins: SDA, SCL
VDD PIN
VDDP
VSS PIN VSSB
OUT
500
IN
Fig. 4-7: Supply Pins (Power 1.8 V and Ground): VDDAC1, VSSAC1, VDDAC2, VSSAC2, VDDARGB,VSSARGB, VDDAFBL, VSSAFBL, VDDAPLL, VDDD1, VSSS1, VDDD2, VSSS2, VDDD3, VSSS3, VDDD4, VSSS4
PIN
Fig. 4-11: Digital Input/Output Pins: 656IOX,656CLK, 656HIN/CLKF20, 656VIN/BLANK
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DATA SHEET
VSP 94x2A
VDDDACx
VDD
display DAC PIN 150
PIN
300k
500
1V
Fig. 4-12: Analog Output Pins: AYOUT, AUOUT, AVOUT
Fig. 4-14: Analog Input Pins: CVBS1...CVBS7 (if cvbsx is not connected to any ADC)
VDD
VDD
PIN
500 500
OUT
IN
PIN
Fig. 4-13: Analog Input Pins: RIN1, RIN2, GIN1, GIN2, BIN1, BIN2, FBL1, FBL2, CVBS1...CVBS7 (if cvbsx is connected to any ADC)
Fig. 4-15: Analog Output Pins: CVBSO1...CVBSO3
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4.6. Electrical Characteristics Abbreviations tbd = to be defined vacant= not applicable positive current values means current flowing into the chip 4.6.1. Absolute Maximum Ratings
DATA SHEET
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operations of the device at these conditions in not implied Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min TA1) TC TS PMAX VDD1 Ambient Temperature PMQFP80-1 Case Temperature PMQFP80-1 Storage Temperature Maximum Power Dissipation 3) PMQFP80-1 Supply Voltages1 VDDDx, VDDAFBL VDDARGB VDDAC1 VDDAC2 VDDAPLL VDDPx, VDD33C, VDD33RGB, VDDACU, VDDACV Groups of internally conected power supply pins: {VSSDx, VSSPx}, {VDDDx}, {VDDPx}, {VDDACU/V} -0.3 -10 -10 -65 Limit Values Max 70 2) 105 125 1500 24) 5) C C C mW V Unit
LDD2
Supply Voltages2
-0.3
3.64) 5)
V
VSUP
Internally Conected Power Supplies have to be connected externally with an impedance of less than 0.05
V
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DATA SHEET
VSP 94x2A
Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min VSUP Voltage Differences between not internally connected supply pins of the same nominal supply voltage Groups of independant grounds: {VSSDx; VSSPx}, {VSSARGB, VSSAFBL, VSS33RGB}, {VSSAC1, VSSAC2, VSS33C}, {VSSDACx}, Groups of independant 1.8 V supply voltages: {VDDDx}, {VDDAC1, VDDAC2}, {VDDARGB, VDDAFBL}, {VDDAPLL} Groups of independant 3.3 V supply voltages {VDDPx}, {VDDACU/V}, {VDD33C}, {VDD33RGB} VI Input Voltage 2) All input pins with reference to their relevant VDD All digital inputs with pull-up All digital inputs with pull-down All output pins with reference to their relevant VDD I2C pads I2C pads Digital outputs 30.1 -0.3 VDD+0.3 V -0.3 Limit Values Max 0.3 V Unit
II_low II_high VO
Input Current at 0.4 V Input Current at 2.4 V Output Voltage 3)
55 57 -0.3
157 230 VDD2+0.3
A A V
IO_low (I2C) IO_high(I2C) IO_low
Output Sink Current (at 0.4 V) Output Source Current (at 2.4 V) Output Sink Current (at 0.4 V)
10.3
36 (open drain) 58.8
mA mA mA
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VSP 94x2A
Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min IO_high
1) 2) 3) 4) 5)
DATA SHEET
Limit Values Max 97.1
Unit
Output Source Current (at 2.4 V)
Digital outputs
31.7
mA
Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption allowed for this package A power-optimized board layout is recommended. The case temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application. Package limit VDD2 (3.3 V nom.) must always be higher than VDD1 (1.8 V nom.) -0.3 V (even during power-up) The deviation among all VDD1 or VDD2 supplies may never exceed 0.3 V.
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DATA SHEET
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4.6.2. Recommended Operating Conditions Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behaivior, reduce reliability and lifetime of the device. All voltage listed are referenced to ground except where noted. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Symbol
Parameter
Pin Name Min
Limit Values Typ 25 35 Max 70 1) 85 700
Unit
TA TC PMAX VDDxx
Ambient Operating Temperature PMQFP80-1 Case Operating Temperature PMQFP80-1 Maximum Power Dissipation PMQFP80-1 Supply voltages (3.3 V) VDDP1, VDDP2, VDDP3, VDDACY, VDDACU, VDDACV, VDD33C, VDD33RGB VDDAC1, VDDAC2, VDDARGB, VDDAFBL, VDDAPLL; VDDD1; VDDD2;VDDD3; VDDD4 TMS, ADR/TDI, V, TCLK, RESET, 656VIN/BLANK, 656HIN/, 656IOX, 656CLK, I656IX, I656ICLK RESET AYOUT, AUOUT, AVOUT
0
C C mW V
3.14
3.3
3.47
VDDxx
Supply voltages (1.8 V)
1.71
1.8
1.89
V
Vin,L Vin,H
Input voltage low Input voltage high
1.0 1.7
V V
tRES RL CL
Active time reset Load resistance Load capacitance
1.3 10 tbd
s k pF
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DATA SHEET
Symbol
Parameter
Pin Name Min
Limit Values Typ 1.2 1.2 1.2 0.3 100 47 0.1 Max 1.8 1.5 1.5
Unit
Vi,CVBS Vi,RGB Vi,FBL
Analog CVBS input voltage Analog RGB input voltage Analog FBL input voltage Analog chroma input voltage (burst) Input coupling capacitors CVBS Input coupling capacitors RGB/FBL Source resistance
CVBS1, CVBS2, CVBS3, CVBS4, CVBS5, CVBS6, CVBS7, RIN1, RIN2, GIN1, GIN2, BIN1, BIN2, FBL1, FBL2
0.6 0.5 0.5
V V V V nF nF k
Crystal Specification fxtal fmax/fxtal f/fxtal CL RS C1 C0 CL,EXT
1) 2) 3) 4)
Frequency (fundamental)3) Maximum permissible frequency deviation3) Recommended permissible frequency deviation4) Load capacitance Series resistance Motional capacitance Parallel capacitance External load capacitance to ground
XIN, XOUT
20.248 -100 -40
20.25
20.252 100
MHz ppm ppm pF
0 13 tbd
40
25 30
W fF pF pF
20 7 13
A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the Recommended Operating Conditions must not be exceeded at worst case conditions of the application PMAX variation: User-determined by application circuit for I/O's Values outside this range may cause color decoding failures. After (subcarrier) adjustment // including temperature and aging deviations
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DATA SHEET
VSP 94x2A
4.6.3. Characteristics For Min./Max. values: at TA = 0 to 70C, fCLOCK =20.25MHz, VSUP3.3V = 3.14 to 3.47 V, VSUP1.8V = 1.71 to 1.89V at TA = 25C, fCLOCK = 20.25MHz, VSUP3.3V = 3.14 to 3.47 V, VSUP1.8V = 1.71 to 1.89V
For typical values:
4.6.3.1. General Characteristics
Symbol
Parameter
Pin Name Min.
LImit Values
Typ. 220 65 74 36 0.61 0.27 0.8 Max.
Unit
Test Conditions
IDDtot 1.8 V Average total supply current IDDtot 3.3 V Average total supply current IDDPD 1.8 V IDDPD 3.3 v Ptot PtotPD Average supply current in power-down-mode Average supply current in power-down-mode Total power dissipation Total power dissipation in power-down-mode
mA mA mA mA W W STANDBY= `10' STANDBY= `10' STANDBY= `10'
Digital Inputs CI Input capacitance Input leakage current TMS, ADR/TDI, V, TCLK, RESET, 656VIN/ BLANK, 656HIN/, 656IOX, 656CLK, I656IX, I656ICLK 7 -10 10 pF A Incl. leakage current of SDA output stage
Digital Outputs VOH VOL IOH IOL Output voltage high Output voltage low Output current high Output current low H50, V50, CLKOUT, HOUT, VOUT 2.5 Vdd2 0.6 V V mA mA
Clock Outputs t CLKOUT cycle time CLKOUT duty cycle t 656CLK cycle time 656CLK duty cycle 656CLK 40 CLKOUT 40 37 60 37 60 ns % ns %
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DATA SHEET
Symbol
Parameter
Pin Name Min.
LImit Values
Typ. Max.
Unit
Test Conditions
Analog CVBS Front-end Input leakage current CI Input capacitance Input clamping error |ICLP| DNL INL CT BW Vin Acvbso Input clamping current Differential nonlinearity Integral nonlinearity Crosstalk between CVBS inputs Bandwidth Input voltage CVBS output amplification CVBSO1, CVBSO2, CVBSO3 CVBS1, CVBS2, CVBS3, CVBS4, CVBS5, CVBS6, CVBS7 -100 7 -1 1 100 nA pF LSB A -0.5 -1 -50 7 0.6 0.9 1.2 1.8 1.1 0.5 1 LSB LSB dB MHz V Settled state Dependent on clamping error Nominal conditions Nominal conditions fsig<5 MHz -3 dB Clamping inactive
Analog RGBF Front-end Input leakage current CI CVBS input capacitance Input clamping error |ICLP| DNL INL CT BW Vin Input clamping current Differential nonlinearity Integral nonlinearity Crosstalk between RGB inputs Bandwidth Input voltage -0.5 -1 -50 10 0.5 1.2 1.5 0.5 1 RIN1, RIN2, BIN1, BIN2, GIN1, GIN2, FBL1, FBL2 -100 7 -1 1 100 nA pF LSB A LSB LSB dB MHz V -3 dB Settled state Dependent on clamping error Nominal conditions Nominal conditions Clamping inactive
Digital To Analog Converters DNL INL UOL UOH Differential nonlinearity Integral nonlinearity Full range output voltage Full range output voltage Output matching -3 AUOUT, AUOUT, AVOUT -1 -2 0.4 1.9 3 1 2 LSB LSB V V % Nominal conditions Nominal conditions Nominal conditions PKLY/ U/V=min Nominal conditions PKLY/ U/V=max
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DATA SHEET
VSP 94x2A
Symbol
Parameter
Pin Name Min.
LImit Values
Typ. Max.
Unit
Test Conditions
Color Decoder/Synchronization and Luminance Processing fHf Horizontal PLL pull-in-range ACC range AGC range fSC Chroma PLL pull-in-range -30 -7.5 500 4.9 +6 +2 % dB dB Hz Nominal crystal frequency Based on 15625 kHz
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. 4.6.3.2. I2C Bus Characteristics
Symbol
2
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Fast I C Bus (All Values are Referred to Min(VIH) and Max(VIL)) Cb tR, tF tBUF fSCL tLOW tHIGH tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO Capacitive load/bus line SDA/SCL rise/fall times Inactive time before start of transmission I2C clock frequency SCL low time SCL high time Set-up time start condition Hold time start condition Set-up time DATA Hold time DATA Set-up time stop condition SDA SCL SDA/SCL 20+$ 1300 0 1300 600 600 600 100 0 600 900 400 400 300 pF ns ns kHz ns ns ns ns ns ns ns $=0.1 Cb/pF
I2C Bus pins VIHr VIL Threshold rise Threshold fall SDA, SCL 2.08 1.8 V V
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DATA SHEET
t
f
t HIGH t LOW
tR
t SU;STO
SU;STA
tHD;STA t SP tAA
t HD;DAT
t SU;DAT
SDA IN
t AA
t BUF
SDA OUT
Fig. 4-16: I2C bus timing data
IC selectable
VSP 940xA VSP 940xB VSP 943xB analog output
VSP 940xA VSP 940xB VSP 943xB
analog output
single-scan 656 input (port 1)
single-scan 656 output (943x) or double-scan 656 output (940x)
Fig. 4-17: Signal Flow 940x
VSP 941xA VSP 941xB VSP 944xB single-scan 656 input (port 2) single-scan 656 output (944x) or double-scan 656 output (941x)
Fig. 4-18: Signal flow 941x, 944x, 942x
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DATA SHEET
VSP 94x2A
5. Application Circuit
L1 10 H +1V8 C39 10 F L2 10 H +1V8 C38 10 F C37 100nF C36 100nF C35 100nF C34 100nF C33 100nF 20.25MHz C32 100nF C31 100nF
+3.3V
34 33 28 29 5 4 66 67 42 43 68 64 65 50 51 35 36 71 19 7 74 8 C29 47nF C28 47nF C27 47nF C25 47nF C24 47nF C23 47nF C22 -- / 47 nF
C21 100 nF C20 100 nF C19 100 nF C18 100 nF C17 100 nF C16 100 nF C15 100 nF
vddd4 vssd4 vddd3 vssd3 vddd2 vssd2 vddd1 vssd1 vddargb vssargb vddapll vddac2 vssac2 vddac1 vssac1 vddafbl vssafbl tclk adr/tdi tms IC1
vddp3 vssp3 vddp2 vssp2 vddp1 vssp1 vdd33c vss33c vdd33rgb vss33rgb vdddacy vssdacy vdddacu vssdacu vdddacv vssdacv (reserved)
25 26 12 11 72 73 59 60 44 45 1 3 78 80 75 77 49 C47 100nF C46 100nF C45 100nF C44 100nF C43 100nF C42 100nF C41 100nF C40 100nF
L3 10 H C49 10 F +3.3 V
L4 10 H C48 10 F +3.3 V
J1
656HIN
656ICLK 656IN7 656IN6 656IN5 656IN4 656IN3 656IN2 656IN1 656IN0
BLANK
J3
656VIN R21...R27: 8x 75 RIN2 GIN2 BIN2 FBL2 RIN1 GIN1 BIN1 HIN1/FBL1 VIN1 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1
J2
I2C Address
B2h B0h
C30 100nF
656hin/clkf20 656vin/blank rin2 gin2 bin2 fbl2 rin1 gin1 bin1 fbl1 v cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 scl sda reset xin 70
VSP 9402A
656clk 656io7 656io6 656io5 656io4 656io3
stepping 656io2
9 10 15 16 21 22 30 31 32 27 17 23 2 79 76 61 62 63 18 20
46 47 48 38 39 40 41 37 14 58 57 56 55 54 53 52 13 6 24
MQFP80
656OCLK 656OUT7 656OUT6 656OUT5 656OUT4 656OUT3 656OUT2 656OUT1 656OUT0 CLKOUT HOUT VOUT
B13
656io1 656io0 clkout hout vout ayout auout avout cvbso3 cvbso2 cbbso1 h50 v50
CVBSO3 CVBSO2 CVBSO1 H50 V50
R1...R7: 7x 75 +3V3
xout 69
Q1 20M25 R9 3k3 C5 22pF* C6 22pF*
+5V R20 51
T1 SCL T2 SDA
SN7002 SN7002
R8 3k3
R21 51 C52 33 F C53 33 F C54 33 F Y100 U100 V100
*values are PCB and crystal dependent
R19 51
only for 5V IC master RESET
T3 T4 T5 3*BC807
buffer not necessary when short connection to backend-processor
Fig. 5-1: VSP 9402A
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DATA SHEET
L1 10 H +1V8 C39 10 F L2 10 H +1V8 C38 10 F C37 100nF C36 100nF C35 100nF C34 100nF C33 100nF 20.25MHz C32 100nF C31 100nF
+3.3V
34 33 28 29 5 4 66 67 42 43 68 64 65 50 51 35 36 71 19 7 74 8 C29 47nF C28 47nF C27 47nF C25 47nF C24 47nF C23 47nF C22 -- / 47 nF
C21 100 nF C20 100 nF C19 100 nF C18 100 nF C17 100 nF C16 100 nF C15 100 nF
vddd4 vssd4 vddd3 vssd3 vddd2 vssd2 vddd1 vssd1 vddargb vssargb vddapll vddac2 vssac2 vddac1 vssac1 vddafbl vssafbl tclk adr/tdi tms IC1
vddp3 vssp3 vddp2 vssp2 vddp1 vssp1 vdd33c vss33c vdd33rgb vss33rgb vdddacy vssdacy vdddacu vssdacu vdddacv vssdacv (reserved)
25 26 12 11 72 73 59 60 44 45 1 3 78 80 75 77 49 C47 100nF C46 100nF C45 100nF C44 100nF C43 100nF C42 100nF C41 100nF C40 100nF
L3 10 H C49 10 F +3.3 V
L4 10 H C48 10 F +3.3 V
J1
656HIN
BLANK
J3
656VIN R21...R27: 8x 75 RIN2 GIN2 BIN2 FBL2 RIN1 GIN1 BIN1 HIN1/FBL1 VIN1 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1
J2
I2C Address
B2h B0h
C30 100nF
VSP 9412A 656clk 9
656io7 10 656io6 15 656io5 16 656io4 21 656io3 22 656io2 30
stepping
656hin/clkf20 656vin/blank rin2 gin2 bin2 fbl2 rin1 gin1 bin1 fbl1 v cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 scl sda reset xin 70 MQFP80
656OCLK 656OUT7 656OUT6 656OUT5 656OUT4 656OUT3 656OUT2 656OUT1 656OUT0 CLKOUT HOUT VOUT 656ICLK 656IN7 656IN6 656IN5 656IN4 656IN3 656IN2 656IN1 656IN0
46 47 48 38 39 40 41 37 14 58 57 56 55 54 53 52 13 6 24
B14
656io1 31 656io0 32 clkout 27 hout 17 vout 23 i656iclk 75 i656i7 3 i656i6 2 i656i5 1
i656i4 80 i656i3 79 i656i1 77 i656i0 76 xout 69 Q1 20M25 i656i2 78
R1...R7: 7x 75 +3V3
T1 SCL T2 SDA
SN7002 SN7002
R8 3k3
R9 3k3
C5 22pF*
C6 22pF*
*values are PCB and crystal dependent
only for 5V IC master RESET
Fig. 5-2: VSP 9412A
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DATA SHEET
VSP 94x2A
5.1. Application Overview
RGB H, V
RGB
DVD
YUV
Camcorder
YC CVBS
SDA 9402 PRIMUS
CLK RGB YUV
VCR
Tuner IF
CVBS H, V
SDA 9380 EDDC M U X
HD, VD, EW
CVBS, YC CVBS
SDA 6000 M2 SDA 5550 TVTPro
RGB, FBL, COR
Fig. 5-3: Application Overview with SDA 9380
RGB H, V
MPEG
digital656
RGB
DVD
YUV
VSP 9412A PRIMUS
CLK RGB DS656
Camcorder
YC CVBS
VCR
Tuner IF
CVBS H, V
DDP 3315C/ HD, VD, DDP 3316C EW
CVBS, YC CVBS
SDA 6000 M2 SDA 5550 TVTPro
RGB, FBL, COR
Fig. 5-4: Application Overview with DDP 3315C/DDP 3316C Micronas 125
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6. Data Sheet History 1. Preliminary Data Sheet: "VSP 94x2A-B13/B14 Powerful Scan-Rate Converter including Multistandard Color Decoder", July 26, 2002, 6251-552-4PD. Fourth release of the preliminary data sheet. Mayor changes: - New I2C registers added 2. Data Sheet: "VSP 94x2A-B13/B14 Powerful Scan-Rate Converter including Multistandard Color Decoder", Aug. 16, 2004, 6251-552-1DS. First release of the data sheet. Major changes: - Version VSP 9432A and VSP 9442A omitted - Section 4. Specification updated - Application diagrams updated - Subadress 7Bh updated
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-552-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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