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VND5025AK-E
Double channel high side driver with analog current sense for automotive applications
Features
Max transient supply voltage Operating voltage range Max On-State resistance (per ch.) Current limitation (typ) Off state supply current
1. Typical value with all loads connected
VCC RON ILIMH IS
41V
PowerSSO-24TM
VCC 4.5 to 36V 25 m 41 A 2 A(1)
Description
The VND5025AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology, intended for driving resistive or inductive loads with one side connected to ground, and suitable for driving LEDs. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Main - In-rush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive - Package: ECOPACK(R) Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protection - Undervoltage shut-down - Overvoltage clamp - Load current limitation - Self-limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down - Reverse battery protection - Electrostatic discharge protection Table 1. Device summary
Package PowerSSO-24TM Tube
Tape and Reel VND5025AKTR-E
VND5025AK-E
June 2007
Rev 3
1/31
www.st.com 1
VND5025AK-E
Contents
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 23
3.1.1 3.1.2 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 23 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 24
3.2 3.3 3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 C I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25
4
Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of tables
VND5025AK-E
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense (8V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/33
VND5025AK-E
List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)14 Figure 6. IOUT/ISENSE vs IOUT (see Table 10 for details) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 17. On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18. On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 20. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 25. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 27. Maximum turn off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25 Figure 28. PowerSSO-24TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 29. Rthj-amb vs PCB copper area in open box free air condition ( one channel ON). . . . . . . . 26 Figure 30. PowerSSO-24TM thermal impedance junction to ambient single pulse (one channel ON) . 27 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24TM . . . . . . . . . . . . . . . . . 27 Figure 32. PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 33. PowerSSO-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 34. PowerSSO-24TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/33
Block diagram and pin description
VND5025AK-E
1
Block diagram and pin description
Figure 1. Block diagram
VCC CLAMP GND INPUT1 LOGIC
UNDERVOLTAGE OUTPUT1 PwCLAMP 1 DRIVER 1 ILIM 1 PwrLIM 1 IOUT1 VDSLIM 1 OVERTEMP. 1 DRIVER 2 ILIM 2 VDSLIM 2 OVERTEMP. 2 IOUT2 PwrLIM 2 K2 PwCLAMP 2 OUTPUT2 CURRENT SENSE2 CURRENT SENSE1
INPUT2
K1
CS_DIS
Table 2.
Pin functions
Name VCC Battery connection Power output Ground connection; must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible; controls output switch state Analog current sense pin; delivers a current proportional to the load current Active high CMOS compatible pin to disable the current sense pin Function
OUTPUT1,2 GND INPUT1,2 CURRENT SENSE1,2 CS_DIS
6/33
VND5025AK-E Figure 2. Configuration diagram (top view)
VCC GND N.C. INPUT2 N.C. INPUT1 N.C. CURRENT SENSE1 N.C. CURRENT SENSE2 CS_DIS. VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
Block diagram and pin description
OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1
Table 3.
Suggested connections for unused and N.C. pins
Current Sense N.R.(1) Through 1k resistor N.C. X X Output X N.R. Input X Through 10k resistor CS_DIS X Through 10k resistor
Connection / Pin Floating To Ground 1. Not recommended
7/33
Electrical specification
VND5025AK-E
2
Electrical specification
Figure 3. Current and voltage conventions
IS VCC ICSD CS_DIS VCSD VIN1 VIN2 GND IIN1 INPUT1 IIN2 INPUT2 OUTPUT1 ISENSE1 CURRENT SENSE1 OUTPUT2 ISENSE2 CURRENT SENSE2 VSENSE2 IGND VOUT2 IOUT2 VSENSE1 VOUT1 IOUT1 VF VCC
Note:
VFn = VOUTn - VCC during reverse battery condition
2.1
Absolute maximum ratings
Table 4.
Symbol VCC -VCC -IGND IOUT - IOUT IIN ICSD -ICSENSE VCSENSE EMAX(1) DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current -1 to 10 DC current sense disable input current DC reverse CS pin current Current sense maximum voltage Maximum switching energy (single pulse) (L = 0.8mH; RL = 0; Vbat = 13.5V; Tjstart = 150C; IOUT = IlimL(Typ.) ) 200 VCC - 41 to +VCC 140 V mJ mA
Absolute maximum ratings
Parameter Value 41 V 0.3 200 Internally limited A 24 mA Unit
8/33
VND5025AK-E Table 4.
Symbol
Electrical specification Absolute maximum ratings (continued)
Parameter Electrostatic Discharge (Human Body Model: R = 1.5k; C = 100pF) - Input - Current sense - CS_DIS - Output - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value Unit
VESD
4000 2000 4000 5000 5000 750 -40 to 150
V V V V V V C
VESD Tj Tstg
-55 to 150
1. See Section 3.4 for details.
2.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter Max Value 1.35 C/W See Figure 29 Unit
Rthj-case Thermal resistance junction-case (MAX) (with one channel ON) Rthj-amb Thermal resistance junction-ambient (MAX)
2.3
Electrical characteristics
8VSymbol VCC VUSD VUSDhyst
Power section
Parameter Operating supply voltage Undervoltage shutdown Undervoltage shutdown hysteresis IOUT = 3A; Tj = 25C Test conditions Min Typ Max Unit 4.5 13 3.5 0.5 25 50 35 41 46 2(2) 3 52 5(2) 6 V A mA m 36 4.5 V
RON
On state
resistance(1)
IOUT = 3A; Tj = 150C IOUT = 3A; VCC = 5V; Tj = 25C
Vclamp
Clamp voltage
IS = 20 mA Off State; VCC = 13V; Tj = 25C; VIN = VOUT = VSENSE = VCSD = 0V On State; VCC = 13V; VIN = 5V; IOUT = 0A
IS
Supply current
9/33
Electrical specification Table 6.
IL(off) VF
VND5025AK-E Power section (continued)
Off state output current(1) Output - VCC diode voltage(1)
VIN = VOUT = 0V; VCC = 13V; Tj = 25C VIN = VOUT = 0V; VCC = 13V; Tj = 125C -IOUT = 4A; Tj = 150C
0 0
0.01
3 A 5 0.7 V
1. For each channel 2. PowerMOS leakage included
Table 7.
Symbol td(on) td(off)
Switching (VCC = 13V; Tj = 25C)
Parameter Turn-on delay time Turn-off delay time Test conditions RL = 4.3 (see Figure 8) RL = 4.3 Min Typ 35 s 50 (see Figure 21) V/s (see Figure 22) 0.45 mJ 0.35 Max Unit
(dVOUT/dt)on Turn-on voltage slope (dVOUT/dt)off Turn-off voltage slope WON WOFF Switching energy losses during tWON Switching energy losses during tWOFF
RL = 4.3 (see Figure 8)
10/33
VND5025AK-E Table 8.
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH VCSD(hyst) VCSCL
Electrical specification Logic input
Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current CS_DIS hysteresis voltage CS_DIS clamp voltage ICSD = 1mA ICSD = -1mA VCSD = 2.1V 0.25 5.5 -0.7 7 V VCSD = 0.9V 1 2.1 10 IIN = 1mA IIN = -1mA VIN = 2.1V 0.25 5.5 -0.7 0.9 A V A 7 V VIN = 0.9V 1 2.1 10 Test conditions Min Typ Max 0.9 Unit V A V A
Table 9.
Symbol ILIMH ILIML TTSD TR TRS THYST
Protection and diagnostics(1)
Parameter DC short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp Output voltage drop limitation IOUT = 2A; VIN = 0; L = 6mH IOUT = 0.20.1A; Tj = -40C to +150C (see Figure 9) Test conditions VCC = 13V 5V < VCC < 36V VCC = 13V; TR < Tj < TTSD 150 TRS + 1 135 7 16 175 TRS + 5 C 200 Min 29 Typ 41 57 A Max Unit
VDEMAG
VCC - 41 VCC - 46 VCC - 52
V
VON
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
11/33
Electrical specification Table 10.
Symbol KLED K0
VND5025AK-E Current sense (8V < VCC < 16V)
Parameter IOUT/ISENSE IOUT/ISENSE Test conditions Min Typ Max Unit
IOUT = 0.05A; VSENSE = 0.5V; VCSD = 0V; 1450 3300 5180 Tj = -40C to 150C IOUT = 0.5A; VSENSE = 0.5V; VCSD = 0V; Tj = -40C to 150C IOUT = 2A; VSENSE = 4V; VCSD = 0V; Tj = -40C Tj = 25C to 150C IOUT = 2A; VSENSE = 4V; VCSD = 0V; Tj = -40C to 150C IOUT = 3A; VSENSE = 4V; VCSD = 0V; Tj = -40C Tj = 25C to150C IOUT = 3A; VSENSE = 4V; VCSD = 0V; Tj = -40C to 150C IOUT = 10A; VSENSE = 4V; VCSD = 0V; Tj = -40C Tj = 25C to 150C IOUT = 10A; VSENSE = 4V; VCSD = 0V; Tj = -40C to 150C IOUT = 0A; VSENSE = 0V; VCSD = 5V; VIN = 0V; Tj = -40C to 150C VCSD = 0V; VIN = 5V; Tj = -40C to 150C IOUT = 2A; VSENSE = 0V; VCSD = 5V; VIN = 5V; Tj = -40C to 150C 1720 3020 4360
K1
IOUT/ISENSE
1940 2810 3740 2230 2810 3390 -10 +10 %
dK1/K1(1)
Current sense ratio drift
K2
IOUT/ISENSE
2250 2790 3450 2400 2790 3180 -7 +7 %
dK2/K2(1)
Current sense ratio drift
K3
IOUT/ISENSE
2610 2760 2970 2650 2760 2870 -3 +3 %
dK3/K3(1)
Current sense ratio drift
ISENSE0
Analog sense leakage current
0 0
1 2
A A
0 5
1
A
VSENSE
Max analog sense output voltage
IOUT = 3A; VCSD = 0V
VSENSEH
Analog sense output voltage in VCC = 13V; RSENSE = 3.9k overtemperature condition Analog sense output current in VCC = 13V; VSENSE = 5V overtemperature condition
V 9
ISENSEH
8
mA
12/33
VND5025AK-E Table 10.
Symbol
Electrical specification Current sense (8V < VCC < 16V) (continued)
Parameter Test conditions Min Typ Max Unit
tDSENSE1H
Delay response V < 4V, 0.5 < I < 10A time from falling I SENSE= 90% of I OUT SENSEMAX edge of CS_DIS SENSE (see Figure 4) pin Delay response V < 4V, 0.5 < I < 10A time from rising I SENSE= 10% of I OUT SENSE SENSEMAX edge of CS_DIS (see Figure 4) pin Delay response time from rising edge of INPUT pin VSENSE < 4V, 0.5 < IOUT < 10A ISENSE = 90% of ISENSEMAX (see Figure 4)
50
100
tDSENSE1L
5
20
tDSENSE2H
70
300 s
Delay response time between rising edge of tDSENSE2H output current and rising edge of current sense Delay response time from falling edge of INPUT pin
VSENSE < 4V, ISENSE = 90% of ISENSEMAX, IOUT = 90% of IOUTMAX, IOUTMAX = 3A (see Figure 5)
110
tDSENSE2L
VSENSE < 4V, 0.5 < IOUT < 10A ISENSE = 10% of ISENSEMAX (see Figure 4)
100
250
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT CS_DIS
LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L
13/33
Electrical specification Figure 5.
VND5025AK-E Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)
VIN
tDSENSE2H
t IOUT
IOUTMAX
90% IOUTMAX
t ISENSE
ISENSEMAX
90% ISENSEMAX
t
14/33
VND5025AK-E Figure 6. IOUT/ISENSE vs IOUT (see Table 10 for details)
Electrical specification
IOUT/ISENSE
4000
3500
Max at -40C
3000
Max 25C to 150C Typ 25C
2500
Min 25C to 150C Min at -40C
2000
1500
1000
500
0 2 3 4 5 6 7 8 9 10
IOUT (A)
Figure 7. Maximum current sense ratio drift vs load current(a)
dk/k(%)
IOUT (A)
a. Parameter guaranteed by design; it is not tested
15/33
Electrical specification Table 11. Truth table
Conditions Normal operation H L Overtemperature H L Undervoltage H L Short circuit to GND (RSC 10m) L H L Short circuit to VCC Negative output voltage clamp H H L L L L H Input L Output L
VND5025AK-E
Sense (VCSD = 0V)(1) 0 Nominal 0 VSENSEH 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0
1. If the VCSD is high, the SENSE output is at a high impedance; its potential depends on leakage currents and external circuit.
16/33
VND5025AK-E Figure 8.
VOUT
Electrical specification Switching characteristics
tWon tWoff
80% dVOUT/dt(on) tr 10%
90% dVOUT/dt(off) tf t
INPUT td(on) td(off)
t
Figure 9.
Output voltage drop limitation
VCC - VOUT Tj = 150oC Tj = 25oC Tj = -40oC
Von IOUT
Von/Ron(T)
17/33
Electrical specification Table 12.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b
(2)
VND5025AK-E Electrical transient requirements
Test levels(1) III -75V +37V -100V +75V -6V +65V IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Burst cycle/pulse repetition time Min 0.5s 0.2s 90ms 90ms Max 5s 5s 100ms 100ms 2 ms, 10 50s, 2 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2 Delays and Impedance
ISO 7637-2: 2004E Test pulse 1 2a 3a 3b 4 5b(2)
Test level results III C C C C C C VI C C C C C C
Class C E
Contents All functions of the device performed as designed after exposure to disturbance. One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground.
18/33
VND5025AK-E Figure 10. Waveforms
NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT
Electrical specification
UNDERVOLTAGE VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT VUSDhyst
SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT < Nominal < Nominal
OVERLOAD OPERATION
TR TTSD TRS
Tj INPUT CS_DIS
LOAD CURRENT
ILIMH ILIML VSENSEH
SENSE CURRENT Current limitation Power limitation Thermal cycling
SHORTED LOAD
NORMAL LOAD
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Electrical specification
VND5025AK-E
Figure 11. Off state output current
Iloff (uA)
0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 -50 -25 0 25 50 75 100 125 150 175
Figure 12. High level input current
Iih(uA)
5
Off State Vcc= 13V Vin= Vout= 0V
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25
Vin= 2.1V
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
Figure 13. Input clamp voltage
Vicl (V)
7 6.75
Figure 14. Input high level
Vih (V)
4 3.5
I 1mA in=
6.5 6.25 6 5.75 5.5 5.25 5 -50 -25 0 25 50 75 100 125 150 175 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 15. Input low level
Vil (V)
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Figure 16. Input hysteresis voltage
Vhyst (V)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VND5025AK-E
Electrical specification
Figure 17. On state resistance vs Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30
Figure 18. On state resistance vs VCC
Ron (mOhm)
80 70 60 50 40 30 20
I out= 3A Vcc= 13V
Tc= 150C Tc=125C Tc=25C Tc=-40C
20 10 0 -50 -25 0 25 50 75 100 125 150 175 10 0 0 5 10 15 20 25
30
35
40
Tc (C)
Vcc (V)
Figure 19. Undervoltage shutdown
Vusd (V)
16 14 12
Figure 20. ILIMH vs Tcase
Ilimh (A)
100 90 80 70
Vcc= 13V
10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 21. Turn-on voltage slope
(dVout/dt)on (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 22. Turn-off voltage slope
(dVout/dt)off (V/ms)
1000 900
Vcc= 13V Rl= 4.3Ohm
800 700 600 500 400 300 200 100 0 -50 -25
Vcc= 13V Rl= 4.3Ohm
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
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Electrical specification
VND5025AK-E
Figure 23. CS_DIS high level voltage
Vcsdh (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 24. CS_DIS low level voltage
Vcsdl (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 25. CS_DIS clamp voltage
Vcsdcl (V)
8 7.5
I csd= 1mA
7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
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VND5025AK-E
Application information
3
Application information
Figure 26. Application schematic
+5V
VCC Rprot CS_DIS Dld C Rprot INPUT OUTPUT Rprot CURRENT SENSE GND
CEXT
RSENSE
VGND
RGND
DGND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against reverse battery.
3.1.1
Solution 1: resistor in the ground line (RGND only)
This first solution can be used with any type of load. The following formulas indicate how to dimension the RGND resistor: 1. 2. RGND 600mV / (IS(on)max) RGND (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (-VCC)2 / RGND This resistor can be shared among several different HSDs. Please note that the value of this resistor is calculated with formula (1), where IS(on)max becomes the sum of the maximum onstate currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground, the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This
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Application information
VND5025AK-E
shift varies depending on how many devices are ON in the case of several high-side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor, then ST suggests to utilize the following Solution 2.
3.1.2
Solution 2: diode (DGND) in the ground line
If the device drives an inductive load, insert a resistor (RGND = 1k) in parallel to DGND. This small signal diode can be safely shared among several different HSDs. Also in this case, the presence of the ground network produces a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2:2004E table.
3.3
C I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert an in-line resistor (Rprot) to prevent the C I/Os pins from latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak = -100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k Recommended values: Rprot = 10k, CEXT = 10nF
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VND5025AK-E
Application information
3.4
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn off current versus inductance (for each channel)
ILMAX (A)
100
A B
10
C
1 0.1 1 10 100
L (mH)
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
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Package and thermal data
VND5025AK-E
4
4.1
Package and thermal data
PowerSSO-24TM thermal data
Figure 28. PowerSSO-24TM PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area = 77mm x 86mm, PCB thickness = 1.6mm, Cu thickness = 70m (front and back side), Copper areas: from minimum pad layout to 8cm2).
Figure 29. Rthj-amb vs PCB copper area in open box free air condition ( one channel ON)
RTHj_amb(C/ W)
55 50 45 40 35 30 0 2 4 6 8 10
PCB Cu heatsink area (cm^ 2)
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VND5025AK-E
Package and thermal data Figure 30. PowerSSO-24TM thermal impedance junction to ambient single pulse (one channel ON)
ZTH (C/ W) 1000
100
Footprint 2 cm2
10
8 cm2
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = t p T
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24TM(b)
b. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered
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Package and thermal data Table 13. Thermal parameters
Footprint 0.28 0.9 6 7.7 9 28 0.28 0.9 0.001 0.003 0.025 0.75 1 2.2 0.001 0.003 4 5 9 17 2
VND5025AK-E
Area/Island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) R7 (C/W) R8 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) C7 (W.s/C) C8 (W.s/C)
8
8 10
9 17
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VND5025AK-E
Package and packing information
5
5.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2
Package mechanical data
Figure 32. PowerSSO-24TM package dimensions
Table 14.
PowerSSO-24TM mechanical data
Millimeters
Symbol Min A A2 1.9 1.9 Typ Max 2.22 2.15
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Package and packing information Table 14. PowerSSO-24TM mechanical data
Millimeters Symbol Min a1 b c D E e e3 G G1 H h L N X Y 3.9 6.1 0.55 10.1 0 0.34 0.23 10.2 7.4 0.8 8.8 0.4 Typ
VND5025AK-E
Max 0.07 0.46 0.32 10.4 7.6
0.1 0.06 10.5 0.4 0.85 10 4.3 6.5
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VND5025AK-E
Package and packing information
5.3
Packing information
Figure 33. PowerSSO-24TM tube shipment (no suffix)
Base Qty Bulk Qty Tube length (0.5) A B C (0.1) All dimensions are in mm.
A
C B
49 1225 532 3.5 13.8 0.6
Figure 34. PowerSSO-24TM tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Qty Bulk Qty A (max) B (min) C (0.2) F G (+2 / -0) N (min) T (max)
1000 1000 330 1.5 13 20.2 24.4 100 30.4
TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm.
Start Top cover tape No components Components 500mm min No components
W P0 (0.1) P D (0.05) D1 (min) F (0.1) K (max) P1 (0.1)
24 4 12 1.55 1.5 11.5 2.85 2
End
500mm min Empty components pockets sealed with cover tape. User direction of feed
31/33
Revision history
VND5025AK-E
6
Revision history
Table 15.
Date 11-Apr-2006
Document revision history
Revision 1 Initial release Reformatted. Table 4 on page 8: EMAX entries updated. Table 6 on page 9 : VF test conditions updated. Table 7 on page 10: Tj condition set to 25C" Table 10 on page 12: dK1/K1, dK2/K2 and dK3/K3, tDSENSE2H added, tDSENSE2H values updated and note added. Figure 5: Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) on page 14 added. Figure 6: IOUT/ISENSE vs IOUT (see Table 10 for details) on page 15 updated. Figure 7: Maximum current sense ratio drift vs load current on page 15 added. Table 12 on page 18: Test Level values III and IV for test pulse 5b in and notes updated. Section 3.4: Maximum demagnetization energy (VCC = 13.5V) on page 25 added. ECOPACK(R) packages information added. Table in Figure 2 on page 7 updated. Section 3.2 on page 24: ISO T/R 7637/1 updated to ISO 76372:2004E. Figure 30 on page 27: Pulse calculation formula added. Disclaimer replaced. Figure 31: Thermal fitting model of a double channel HSD in PowerSSO-24TM : note added Changes
30-Mar-2007
2
01-Jun-2007
3
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VND5025AK-E
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