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| w w w .D at Sh a et e 4U . om c MICROCOMPUTER MN102L00 MN102L2503/25A/25D/ 25Z/25G/F25Z/490A/62D/ 62F/62G LSI User's Manual w w w .D t a S a e h t e Pub.No.22262-010E U 4 .c m o w w w .D at Sh a et e 4U . om c PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotypes and product names written in this manual are trademarks or registered trademarks of their corresponding corporations. The MN102LF25Z is manufactured and sold under the License Agreement with BULL CP8 Inc., and the use of the MN102LF25Z into the IC card is not allowed. Request for your special attention and precautions in using the technical information and semiconductors described in this manual. (1) The approval of the Japanese Government is required for the export of any products and technologies listed in this manual which are subjected to the provisions of the Foreign Exchange and Foreign Trade Law. The contents of this manual are subject to change without notice to improve design, function, or performance. Matsushita Electronics assumes no responsibility or liability for damages or for infringements of patents or other rights arising from use of the information in this manual. The contents of this manual may not be copied or reproduced without permission in writing from Matsushita Electronics. This manual describes standard specifications. Obtain the latest product standard specifications before you design, purchase, or use. (2) (3) (4) (5) For inquiries regarding this manual or any Matsushita semiconductor, please contact one of the sales offices listed at the end of this manual or the sales department of Matsushita Electronics Corporation. About This Manual This manual is intended for assembly-language programming engineers. It describes the internal configuration and hardware functions of the MN102L25x series microcontrollers. Text Conventions This manual contains titles, sub-titles, special notes and warnings. Supplementary comments appear in the sidebar. Key Information This note describes key points of an operation. Warning Please read and follow these instructions to prevent damage or reduced performance. Finding Desired Information This manual provides four methods for finding desired information quickly and easily. (1) An index for the front of the manual for finding each section. (2) A table of contents at the front of the manual for finding desired titles. (3) A list of figures at the front of the manual for finding illustrations and charts by names. (4) A chapter name is located at the upper corner of each page. Related Manuals s MN10200 Series Linear Addressing Version LSI User Manual (Describes the MN10200 series specifications) s MN10200 Series Linear Addressing Version Instruction Manual (Describes the instruction set) s MN10200 Series Linear Addressing Version C Compiler User Manual Usage Guide (Describes the installation, commands, and options for the C complier) s MN10200 Series Linear Addressing Version C Compiler User Manual Language Description (Describes the syntax for the C complier) s MN10200 Series Linear Addressing Version C Compiler User Manual Library Reference (Describes the standard libraries for the C complier) s MN10200 Series Linear Addressing Version Cross Assembler User Manual Language Description (Describes the assembler syntax and notation) s MN10200 Series Linear Addressing Version C Source Code Debugger User Manual (Describes the use of the C source code debugger) s MN10200 Series Linear Addressing Version PanaXSeries Installation Manual (Describes the installation of the C complier, cross-assembler, and C source code debugger and the procedures for using the in-circuit emulator) Questions and Comments Please send your questions, comments and suggestions to the semiconductor design center closest to you. See the last page of this manual for a list of addresses and telephone numbers. Contents 0 1 2 3 4 5 6 7 8 9 Chapter 1 General Description Chapter 2 Bus Interface Chapter 3 Interrupts Chapter 4 Timers Chapter 5 Serial Interface Chapter 6 Analog Interface Chapter 7 ATC Chapter 8 Ports Chapter 9 Appendix Contents 0 1 2 3 4 5 6 7 8 9 10 11 Contents Chapter 1 1-1 1-1-1 1-1-2 1-1-3 1-2 1-3 1-4 1-5 General Description 2 2 2 5 8 10 12 13 23 Introduction ............................................................................. Features ................................................................................. Overview ................................................................................ General Description .................................................................................... Basic Specifications ................................................................................... Block Diagram ............................................................................................ Pin Description ........................................................................................... 1-4-1 List of Pin Functions ............................................................... External Dimensions ................................................................................... Chapter 2 2-1 2-1-1 2-1-2 2-1-3 2-2 2-2-1 2-2-2 2-2-3 2-2-4 Bus Interface 26 26 32 36 40 40 42 48 50 Overview ................................................................................ Control Registers ................................................................... ROM Burst Mode Timing ........................................................ Memory Expansion Mode (Address/Data Separated Mode) .. External Memory Connection Examples (Address/Data Separated Mode) ............................................ Memory Expansion Mode (Address/Data Shared Mode) ....... External Memory Connection Examples (Address/Data Shared Mode) ................................................. Bus Interface ............................................................................................... External Memory Connection Examples ..................................................... Chapter 3 3-1 3-2 3-1-1 3-2-1 3-2-2 3-3 Interrupts 56 56 58 58 58 60 60 62 Overview ................................................................................ External Pin Interrupts ............................................................ NMI Interrupts ......................................................................... Interrupts ..................................................................................................... External Interrupts ...................................................................................... Interrupt Setup Examples ........................................................................... 3-3-1 External Pin Interrupt Setup ................................................... 3-3-2 Watchdog Timer Interrupt ....................................................... Chapter 4 4-1 4-1-1 4-1-2 4-1-3 4-2 4-2-1 4-2-2 4-2-3 4-3 Timers 66 66 74 75 80 80 82 85 88 88 90 93 96 98 100 102 104 106 Overview ................................................................................ Control Registers .................................................................... Timer Block Diagrams ............................................................ Event Counter Using 8-bit Timer ............................................ Clock Output Using 8-bit Timer .............................................. Interval Timer Using 8-bit Timer ............................................. Timers ......................................................................................................... 8-bit Timer Setup Examples ....................................................................... 16-bit Timer Setup Examples ..................................................................... 4-3-1 Event Counter Using 16-bit Timer .......................................... 4-3-2 4-3-3 4-3-4 4-3-5 4-3-6 4-3-7 4-3-8 4-3-9 PWM Output Using 16-bit Timer ............................................. Two-phase PWM Output Using 16-bit Timer .......................... One-phase Capture Input Using 16-bit Timer ...................... Two-phase Capture Input Using 16-bit Timer ......................... Two-phase Encoder Input (4x) Using 16-bit Timer .................. One-shot Pulse Output Using 16-bit Timer ............................ External Count Direction Control Using 16-bit Timer ............. External Reset Control Using 16-bit Timer ............................. Chapter 5 5-1 5-1-1 5-1-2 5-1-3 5-2 Serial Interface 110 110 111 113 116 116 120 121 Overview ................................................................................. Control Registers .................................................................... Serial Interface Connection .................................................... Serial Interface ............................................................................................ Serial Interface Setup Examples ................................................................. 5-2-1 Serial Transmission in Asynchronous Mode Using Timer 2 ... 5-2-2 5-2-3 Serial Reception in Synchronous Mode Using Timer 2 .......... Serial Transmission/Reception in I C Mode Using Timer 3 .... 2 Chapter 6 6-1 6-1-1 6-1-2 6-2 6-2-1 6-2-2 Analog Interface 124 124 129 130 130 132 Overview ................................................................................ Control Registers .................................................................... One Channel A/D Conversion Using AN2 Pin ........................ Multiple Channel A/D Conversion Using AN2 to AN0 Pins .... Analog Interface .......................................................................................... Analog Interface Setup Examples .............................................................. 6-1-2 6-2 6-2-1 6-2-2 Control Registers .................................................................... One Channel A/D Conversion Using AN2 Pin ........................ Multiple Channel A/D Conversion Using AN2 to AN0 Pins .... 129 130 130 132 Analog Interface Setup Examples .............................................................. Chapter 7 7-1 7-1-1 7-2 ATC 136 136 138 139 139 Overview ................................................................................ ATC ............................................................................................................ 7-1-2 Control Registers .................................................................... ATC Setup Examples ................................................................................. 7-2-1 Serial Reception ..................................................................... Chapter 8 8-1 8-1-1 8-1-2 8-2 8-3 8-2-1 Ports 142 142 150 158 158 159 159 Overview ................................................................................ Control Registers .................................................................... Overview ................................................................................ Ports ........................................................................................................... Byte Swap Registers .................................................................................. Pullup Control Register ............................................................................... 8-3-1 Overview ................................................................................ Chapter 9 9-1 Appendix 162 162 179 205 205 262 264 266 276 278 Electrical Characteristics ............................................................................ 9-1-1 Electrical Characteristics 5 V ............................................................ 9-1-2 Electrical Characteristics 3 V ............................................................ 9-2 Data Appendix ............................................................................................ 9-2-1 9-2-2 9-2-3 List of Special Registers ......................................................... Address Map .......................................................................... List of Pin Functions ............................................................... 9-3 9-4 9-5 MN102L00 Series Linear Address Edition Instructions .............................. Initialization Program .................................................................................. EPROM Version ......................................................................................... 9-5-1 9-5-2 9-5-3 9-6 9-6-1 9-6-2 9-6-3 9-6-4 9-6-5 9-6-6 9-6-7 9-6-8 9-6-9 9-6-10 9-6-11 Overview ................................................................................ Connecting Adaptor Socket ................................................... Programming .......................................................................... Overview ................................................................................ Flash EEPROM Programming ............................................... PROM Writer Mode ................................................................ Onboard Serial Programming Mode ....................................... Hardware Used in Serial Programming Mode ........................ Connecting Onboard Serial Programming Mode .................... System Configuration for Onboard Serial Programming ........ Onboard Serial Programming Mode Setup ............................ Branch to User Program ......................................................... Serial Interface for Onboard Serial Programming ................. PROM Writer/Onboard Serial Programming .......................... 278 279 282 292 292 293 293 294 294 296 297 299 301 302 303 Flash EEPROM Version ............................................................................. List of Figures Figure 1-1-1 Figure 1-1-2 Figure 1-1-3 Figure 1-3-1 Figure 1-4-1 Figure 1-4-2 Figure 1-4-3 Figure 1-4-4 Figure 1-4-5 Figure 1-5-1 Figure 2-1-1 Figure 2-1-2 Figure 2-1-3 Figure 2-1-4 Figure 2-1-5 Figure 2-1-6 Figure 2-1-7 Figure 2-1-8 Figure 2-1-9 Figure 2-1-10 Figure 2-2-1 Figure 2-2-2 Figure 2-2-3 Figure 2-2-4 Figure 2-2-5 Figure 2-2-6 Figure 2-2-7 Figure 2-2-8 Address Space ....................................................................... Interrupt Controller Configuration ........................................... Interrupt Servicing Sequence ................................................. Block Diagram ........................................................................ Pin Configuration .................................................................... OSCI, OSCO Connection Example ........................................ XI, XO Connection Example ................................................... Reset Pin Connection Example .............................................. WAIT Signal Control Circuit Connection Example .................. External Dimensions .............................................................. Address Space ....................................................................... Bus Controller ......................................................................... Memory Expansion Mode (Address/Data Shared Pin Configuration) .............................. Memory Expansion Mode (Address/Data Separated Pin Configuration) ......................... Processor Mode (Address/Data Shared Pin Configuration) .............................. Processor Mode (Address/Data Separated Pin Configuration) ......................... Single-chip Mode .................................................................... ROM Timing for Burst Mode (4 bytes for Page Size) ............. ROM Burst Mode Access Timing ........................................... Access Timing Memory Connection Example during ROM Burst Mode ......................................................... Memory Connection Example with 16-bit Bus Width (Address/Data Separated Mode) ............................................ Memory Connection Example with 8-bit Bus Width (Address/Data Separated Mode) ............................................ No Wait Access Timing with 16-bit Bus Width ....................... 1 Wait Access Timing with 16-bit Bus Width .......................... Handshake Access Timing with 16-bit Bus Width .................. No Wait Access Timing with 8-bit Bus Width ......................... 1 Wait Access Timing with 8-bit Bus Width ............................ Handshake Access Timing with 8-bit Bus Width .................... 5 7 7 10 12 22 22 22 22 23 26 27 28 28 29 29 30 36 37 38 42 43 44 44 45 45 46 46 Figure 2-2-9 Figure 2-2-10 Figure 2-2-11 Figure 2-2-12 Figure 2-2-13 Figure 2-2-14 Figure 2-2-15 Figure 2-2-16 Access Timing During Bus Request (Address/Data Separated Mode) ............................................ Memory Connection Example with 16-bit Bus Width (Address/Data Shared Mode) ................................................. Memory Connection Example with 8-bit Bus Width (Address/Data Shared Mode) ................................................. Fixed Wait Access Timing with 16-bit Bus Width ................... Handshake Access Timing with 16-bit Bus Width .................. Fixed Wait Access Timing with 8-bit Bus Width ..................... Handshake Access Timing with 8-bit Bus Width .................... Access Timing During Bus Request (Address/Data Shared Mode) ................................................ External Pin Interrupt Timing .................................................. Watchdog Timer Interrupt Timing ........................................... Event Counter Timing ............................................................. Timer Output, Interval Timer Timing ....................................... PWM Output Timing (Timer 6 and Timer 7) ........................... PWM Output Timing (Data Write) (Timer 6 and Timer 7) ....... Two-phase Timer Output Timing (Timer 6 and Timer 7) ........ One-shot Pulse Output Timing (Timer 6 and Timer 7) ........... One-phase Capture Input Timing (Timer 6 and Timer 7) ....... Two-phase Capture Input Timing (Timer 6 and Timer 7) ....... Two-phase Encoder (4x) Timing ............................................ Two-phase Encoder (1x) Timing (Timer 6 and Timer 7) ....... External Count Direction Control Timing (Timer 6 and Timer 7) ............................................................. External Count Reset Control (Two-phase Encoder) Timing (Timer 6 and Timer 7) ............................................................. Timer 0 Block Diagram ........................................................... Timer 1 Block Diagram ........................................................... Timer 2 Block Diagram ........................................................... Timer 3 Block Diagram ........................................................... Timer 4 Block Diagram ........................................................... Timer 5 Block Diagram ........................................................... 71 71 75 75 76 76 77 77 50 51 52 52 53 53 54 61 63 68 68 68 69 69 69 70 70 70 71 47 Figure 3-3-1 Figure 3-3-2 Figure 4-1-1 Figure 4-1-2 Figure 4-1-3 Figure 4-1-4 Figure 4-1-5 Figure 4-1-6 Figure 4-1-7 Figure 4-1-8 Figure 4-1-9 Figure 4-1-10 Figure 4-1-11 Figure 4-1-12 Figure 4-1-14 Figure 4-1-15 Figure 4-1-16 Figure 4-1-17 Figure 4-1-18 Figure 4-1-19 Figure 4-1-20 Figure 4-1-21 Figure 4-2-1 Figure 4-2-2 Figure 4-2-3 Figure 4-2-4 Figure 4-2-5 Figure 4-3-1 Figure 4-3-2 Figure 4-3-3 Figure 4-3-4 Figure 4-3-5 Figure 4-3-6 Figure 4-3-7 Figure 4-3-8 Figure 4-3-9 Figure 4-3-10 Figure 4-3-11 Figure 5-1-1 Figure 5-1-2 Figure 5-1-3 Figure 5-1-4 Figure 5-1-5 Figure 5-2-1 Figure 5-2-2 Figure 5-2-3 Figure 6-1-1 Figure 6-1-2 Figure 6-1-3 Figure 6-1-4 Figure 6-1-5 Figure 6-1-6 Figure 6-1-7 Figure 6-2-1 Timer 6 Block Diagram ........................................................... Timer 7 Block Diagram ........................................................... Event Counter Timing ............................................................. Clock Output Configuration (1) ............................................... Clock Output Timing ............................................................... Clock Output Configuration (2) ............................................... Interval Timer Timing .............................................................. Event Counter Timing ............................................................. PWM Timing ........................................................................... PWM Timing in Double Buffer Mode ...................................... Two-phase PWM Timing ........................................................ Two-phase PWM Timing in Double Buffer Mode ................... One-phase Capture Timing .................................................... Two-phase Capture Timing .................................................... Two-phase Encoder Input Timing .......................................... One-shot Pulse Output Timing ............................................... External Count Direction Control Timing ................................ External Reset Control Timing ................................................ Serial Interface Configuration ................................................. SCnSTR Change Timing ........................................................ Asynchronous Connection ...................................................... Synchronous Connection ....................................................... I2C Mode Connection ............................................................. Asynchronous Transmission Configuration ............................ Bit Transmission Timing in Asynchronous Mode .................... Transmission/Reception in I C Mode ..................................... Analog Interface Configuration ............................................... A/D Conversion Timing ........................................................... One Channel/Single Conversion Timing ................................ Multiple Channels/Single Conversion Timing ......................... One Channel/Continuous Conversion Timing ........................ Multiple Channels/Continuous Conversion Timing ................. Ananlog Interface Block Diagram ........................................... One Channel A/D Conversion ................................................ 2 78 78 81 82 84 85 87 89 92 92 94 95 97 99 101 103 105 107 110 112 113 113 114 116 118 122 124 125 126 126 127 127 128 130 Figure 6-2-2 Figure 6-2-3 Figure 7-1-1 Figure 7-2-1 Figure 7-2-2 Figure 8-2-1 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 Figure 9-8 Figure 9-9 Figure 9-10 Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-5-1 Figure 9-5-2 Figure 9-5-3 Figure 9-5-4 Figure 9-5-5 Multiple Channel A/D Conversion ........................................... A/D Conversion Timing ........................................................... ATC Operations ..................................................................... Serial Reception Data Transfer .............................................. Last Data Transfer Timing ...................................................... Byte Swap Register ................................................................ System Clock Timing ............................................................. Reset Timing .......................................................................... Data Transfer Signal Timing (Address/Data Separated Mode, Without Wait) ............................................. Data Transfer Signal Timing (Address/Data Separated, With Wait) ............................................................ Data Transfer Signal Timing (Address/Data Shared Mode, Without Wait) .................................................. Data Transfer Signal Timing (Address/Data Shared, With Wait) ................................................................ Data Transfer Signal Timing (Burst ROM Interface) .............. Bus Authority Request Signal Timing ..................................... Interrupt Signal Timing ........................................................... Serial Interface Signal Timing 1 (Synchronous Serial Transmission: Transfer in Progress) ............................ Serial Interface Signal Timing 2 (Synchronous Serial Transmission: Transfer End Timing at SBT Input) ................. Serial Interface Signal Timing 3 (Synchronous Serial Transmission: Transfer End Timing at SBT Output) .............. Serial Interface Signal Timing 4 (Synchronous Serial Reception) .............................................................................. Timer/Counter Signal Timing .................................................. Memory Map During EPROM Parallel Mode .......................... Pin Configuration of Adaptor Socket ...................................... EPROM Pin Configuration ...................................................... Adaptor Socket-MN102LP25x Pin Connection ....................... Word Program Timing ............................................................ 132 133 137 140 140 158 197 197 198 199 200 201 202 203 203 203 203 204 204 204 278 279 280 281 285 Figure 9-5-6 Figure 9-5-7 Figure 9-5-8 Figure 9-5-9 Figure 9-6-1 Figure 9-6-2 Figure 9-6-3 Figure 9-6-4 Figure 9-6-5 Figure 9-6-6 Figure 9-6-7 Figure 9-6-8 Figure 9-6-9 Figure 9-6-10 Figure 9-6-11 Figure 9-6-12 Figure 9-6-13 Word Program Flow ............................................................... Page Program Timing ............................................................. Page Program Flow ............................................................... High-Temperature Test Flow ................................................. Memory Map for Flash EEPROM Version .............................. Flash EEPROM Program Flow ............................................... 8-bit Serial Interface Block Diagram for Serial Writer ............. Flash EEPROM Memory Space ............................................. Pin Configuration During Serial Programming ....................... System Configuration for Onboard Serial Writer .................... Target Board-Serial Writer Connection .................................. Timing for Onboard Serial Programming Mode ...................... Load Program Start Flow ....................................................... Reset Service Routine Flow ................................................... Interrupt Service Routine Flow ............................................... Data Transfer Timing .............................................................. Programming Flow ................................................................. 286 289 290 291 292 293 294 295 296 297 297 299 300 301 301 302 303 List of Tables Table 1-1-1 Table 1-2-1 Table 1-3-1 Table 1-4-1 Table 2-1-1 Table 2-1-2 Table 3-1-1 Table 4-1-1 Table 4-1-2 Table 5-1-1 Table 5-1-2 Table 5-1-3 Table 5-1-4 Table 5-1-5 Table 5-1-6 Table 5-1-7 Table 5-1-8 Table 5-1-9 Table 5-1-10 Memory Modes ....................................................................... Basic Specifications ............................................................... Block Functions ...................................................................... List of Pin Functions ............................................................... CS Signal Generation ............................................................. List of Bus Interface Control Registers ................................... List of Interrupt Control Registers ........................................... Timer Function ........................................................................ List of Timer Control Registers ............................................... Serial Interface Features ....................................................... List of Serial Interface Control Registers ................................ Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 20 MHz) ............................................. Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 19.6608 MHz) .................................... Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 17.2032 MHz) .................................... Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 16 MHz) ............................................. Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 14 MHz) ............................................. Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 12 MHz) ............................................. Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 10 MHz) ............................................. Baud Rate Setup Example in Asynchronous Mode (External Oscillation at 8 MHz) ............................................... 5 8 11 13 27 32 56 66 74 110 111 115 115 115 115 115 115 115 115 Table 6-1-1 Table 6-1-2 Table 7-1-1 Table 7-1-2 Table 8-1-1 Table 8-1-2 Table 8-1-2 Table 9-5-1 Table 9-6-1 A/D Converter Functions ........................................................ List of A/D Conversion Control Registers ............................... ATC Functions ........................................................................ List of ATC Control Registers ................................................. Port Functions ........................................................................ List of Port Control Registers .................................................. Pullup Control Registers ......................................................... Operating Mode Selection ...................................................... Clock Frequency ..................................................................... 125 129 136 138 142 150 159 282 298 0 Chapter 1 General Description 1 2 3 4 5 6 7 8 9 Chapter 1 General Description 1-1 General Description 1-1-1 Introduction The MN10200 series linear addressing version designs the new architecture for C-language programming based on a detailed analysis for embedded applications. This improves the system architecture in speed and function to meet the requirements in user systems including miniaturization and low power consumption. The 16-bit MN102L (P, F) 25x series contains various peripheral functions and memory interfaces for supporting four chip select (CS) signals and Burst ROM. This improves high real-time control performance in a wide variety of fields including printers, electric instruments, audiovisual equipment, electric appliances, automobiles, robotics and computer peripheral devices. This series adapts a load/store architecture method for computing within registers and a harvard architecture method for separating instructions bus and operand bus. Using one byte/one machine cycle basic instructions reduces code size and improves compiler efficiency. [Model Explanation] MN102 L P xx G ROM/RAM sizes 25G 128 KB/5 KB 25Z 128 KB/3 KB 25D 64 KB/3 KB 25A 32 KB/3 KB 2503 0 KB/3 KB 62G 128 KB/5 KB 62F 96 KB/5 KB 62D 64 KB/5 KB Model Number Internal ROM P: OTP F: Flash None: Mask ROM Core Version 16-bit 10200 Series MN102L490A Input Level TTL of MN102L2503 pins Refer to "9-2-3 List of Pin Functions" for details. 1-1-2 Features This series contains a flexible and optimized hardware architecture as well as a simple and efficient instruction set. This allows economy and speed. This section describes the features of this series CPU. 1. Linear Addressing for Large Systems The MN10200 series contains up to 16 Mbytes of linear address space. The CPU provides an effective development environment without detecting borders between address spaces. The hardware architecture is also optimized for large systems. The memory is not divided into instruction areas and data areas so that operations can share instructions. 2 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description 2. Single-byte Basic Instruction Length The MN10200 series has replaced general registers with eight internal CPU registers divided four address registers (A0 - A3) and four data registers (D0-D3). The register specification fields are four bits or less, and the code sizes of the frequently used basic instructions including register- to-register operations and load/store operations are one byte. 15 Conventional Register Assignment 8 7 0 Register Specification Field 7 0 Register Specification Field New Register Assignment 1 Cycle 3. High-speed Pipeline Processing The MN10200 series executes instructions in a 3-stage pipeline: fetch, decode and execute. This allows the MN10200 series to execute instructions of single byte in one machine cycle (100 ns with a 20-MHz oscillator). Instruction 1 Fetch Decode Address Calculation Execute Instruction 2 Fetch Decode Address Calculation Execute 4. Simple Instruction Set The MN10200 series uses an instruction set of 36 instructions, designed specially for the programming model for embedded applications. To compress the code size, instructions have a variable length of one byte to five bytes. The most frequently used instructions in C-language compiler are single byte. 5. High-speed Interrupt Response The MN10200 series suspends instruction execution even during the execution of the instruction with long execution cycles. After an interrupt occurs, the program moves to the interrupt service routine within 11 cycles or less. The MN10200 series improves real-time control performance using the interrupt handler which adjusts interrupt servicing speed depending on user requirements. Main Program Instruction 1 Interrupt Service Routine Instruction 2 Interrupt Request Instruction 3 Instruction 4 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 3 Chapter 1 General Description 6. Flexible Interrupt Control Structure The interrupt controller divides into eight groups (of them, group 0 is reserved for NMI) and supports a maximum of four vectors for each group in total of 26 vectors. Each group can be set to one of seven priority levels. This provides the software design flexibility and control. The CPU is compatible with software from previous Panasonic peripheral modules. 7. High-speed, High-functional External Interface The MN10200 series supports external interface functions including chip select (CS) signal generation, handshake function and bus arbitration. 8. C-Language Development Environment The MN10200 series contains highly efficient C compiler and simple hardware optimized for C-language programming. With this advantage, this series improves development environment for C-language embedded applications without expanding the program size. The PanaXSeries development tools support the MN10200 series devices. 9. Outstanding Power Savings The MN10200 series contains separate buses which distribute and reduce load capacitance. This reduces overall power consumption. The MN10200 series also supports three modes of SLOW, HALT and STOP for power savings. 4 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description 1-1-3 Overview This section describes the basic configuration and function of this series. s Address Space The memory contains up to 16-Mbyte linear address space. The instruction area and data area are not separated so that internal RAM, special function registers for internal peripheral functions are allocated into the first 64 kbytes in memory as the basic configuration. Three memory modes shown in Table 1-1-1 are available depending on models and sizes of user programs. x'000000' External Memory x'008000' Internal RAM x'00FC00' I/O Control Registers x'010000' Program start address x'080000' Interrupt handlerstart address x'080008' x'080000' External Memory 16 Mbytes 1 Kbyte Max of 31 Kbytes This is a general example of the memory expansion mode. Both start address and end address of internal RAM are changed within x'008000' to x'00FBFF' depending on models. Internal ROM Max of 496 Kbytes x'0FC000' External Memory x'FFFFFF' The start address of internal ROM is fixed at x'008000' while the end address of internal ROM depending on sizes of internal ROM. (The end address in this example is 496 kbytes.) Figure 1-1-1 Address Space Table 1-1-1 Memory Modes Mode Single-chip Mode Memory Expansion Mode Processor Mode Up to 24 bits Address Bit Width Internal ROM Capacity 16 kbytes or more None MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 5 Chapter 1 General Description s Internal Registers, Memory and Special Function Registers Program Counter 23 PC Address Registers 23 A0 A1 A2 A3 Data Registers 23 D0 D1 D2 D3 0 The data registers perform all arithmetic and logic operations. When the byte (8-bit) data or the word (16-bit) data is transferred to memory or another register, the instruction adds a zero or sign extension. 0 The program counter specifies the address (24 bits) of the program during the execution. 0 The address registers specify the data location on the memory. Of four registers, A3 is assigned as the stack pointer. Multiplication/Division Register 15 MDR 0 The multiplication/division register stores the upper 16 bits of the 32-bit product of the multiplication operations. In division operations, this register stores the upper 16 bits of the 32-bit dividend before the execution and the 16-bit remainder of the quotient after the execution. Processor Status Word 15 PSW 0 The processor status word indicates the CPU status. This register stores the operation result flags and interrupt mask levels. Memory, Special Registers, I/O Ports ROM RAM CPUM, MEMCTR, IAGR GnICR SCnCTR, SCnTRB, SCnSTR ANCTR, ANBUF TMnMD, TMnBC, TMnBR... MEMMDn, EXMCTR ATCBC, ATCCTR PnOUT, PnIN, PnDIR Internal ControlRegisters Interrupt Control Registers Serial Interface A/D Converter Timers/Counters Memory Control ATC Controller I/O Ports Memory (ROM and RAM), special registers for controlling peripheral functions and I/O ports are assigned to the same address space. 6 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description s Interrupt Controller The interrupt controller (group 0 to group 7) allocated to the outside of the CPU controls all nonmaskable interrupts and maskable interrupts except reset. Each group contains up to four interrupt vectors and specifies any of seven priority levels. CPU Core Maskable Interrupt Receive Interrupt Enable Nonmaskable Interrupt Receive Reset Receive Reset Interrupt Controller Nonmaskable Interrupts Nonmaskable Interrupt Controller Group 0 (G0CIR) 0 3 Maskable Interrupt Controller Group 1 (G1CIR) Maskable Interrupts 26 Vectors 3 Maskable Interrupt Controller Group 7 (G7CIR) 3 Watchdog Timers Undefined Instruction External Pin NMI Interrupt Mask 6 5 4 3 2 1 External Pin Interrupts Peripheral Interrupts, etc. Figure 1-1-2 Interrupt Controller Configuration The CPU checks the processor status word status to determine whether an interrupt request is accepted or not. When an interrupt is accepted, automatic servicing by hardware starts and the program counter and PSW are pushed to the stack. Next, the program moves to the interrupt, searches to the interrupt vector and branches to the entry address of the interrupt service for that interrupt. Interrupt preprocessing Push registers, branch to entry address, etc. Main Program x'080008' Interrupt service routine Reset interrupt vectors at the beginning JMP, etc. Hardware processing Push PC, PSW Interrupt Max. of 4 mashine cycles 7 machine cycles Figure 1-1-3 Interrupt Servicing Sequence MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 7 Chapter 1 General Description 1-2 Basic Specifications This section describes the basic specification of this series. Please refer to Product Standards for details. Table 1-2-1 Basic Specifications (1/2) CPU Structure Load/store architecture Eight registers: Four 24-bit data registers Four 24-bit address registers Others: 24-bit program counter 16-bit processor status word 16-bit multiplication/division register Instruction 36 instructions 6 addressing modes One-byte basic instruction length Code assignment: 1 to 2 bytes (Basic) + 0 to 3 bytes (Extension) Basic Performance 10 MHz internal operating frequency with a 20-MHz oscillator Clock cycles: For instruction execution, minimum 1 cycle (100 ns) For register-to-register operations, minimum 1 cycle For load/store operations, minimum 1 cycle For branch operations, 1 to 3 cycles Pipeline Address Space External Bus 3-stage: Instruction fetch, decode, execute 16-Mbyte linear address space 24-bit address bus Four chip select (CS) signals (fixed addresses) 8- or 16- bit data bus Minimum 1 bus cycle (100 ns with a 20-MHz oscillator) Set bus width for each 4 Mbytes Set wait control (Handshake setting and fixed wait setting are possible.) Support ROM burst mode Select address/data separate pins or address/data shared pins Low-power Mode Frequency Circuit SLOW mode, STOP mode, HALT mode High-speed: Up to 20 MHz Low-speed: Up to 32 kHz 8 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-2-1 Basic Specifications (2/2) Interrupt 26 vectors 3 nonmaskable interrupts 23 maskable interrupts (7 interrupt priority level settings) 6 external interrupts 5 external interrupts (individual IRQ, edge specification) 1 external nonmaskable interrupt 20 internal interrupts 12 timer interrupts, 4 serial interrupts, 1 ATC interrupt, 1 A/D interrupt, 1 watchdog timer interrupt, 1 undefined instruction interrupt Timer/Counter Six 8-bit timers (down counters) Reload timer Cascading function (form as 16-bit or 40-bit timer) Timer output (duty of 1:1) Internal clock source or external clock source Serial interface clock generation Start timing generation for A/D converter Two 16-bit timers (up/down counters) Two channels of compare/capture registers Internal clock source or external clock source Timer output (duty of 1:1) (Max. of four channels) PWM/one-shot pulse output (Max. of two channels) Two-phase encoder input (4x or 1x method) 17-bit watchdog timer ATC * 1 Channel (fixed between serial channel 0 and internal RAM) Serial (ch0) transmit/receive interrupt request 600 ns of 1-byte data transfer speed with a 20-MHz oscillator Serial Interface Analog Interface Two UART/Synchronous (shared) serial interfaces A/D converter Eight 8-bit inputs Auto scanning (1 to 8 channel settings) Byte-swap Register I/O Port 2-byte byte-swap, 3-byte byte-swap, or 4-byte byte-swap 80 I/O ports (All shared pins except ROM less) 48 I/O ports (all shared pins, with ROM less) Package 100-pin LQFP MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 9 Chapter 1 General Description 1-3 Block Diagram Figure 1-3-1 shows the block diagram including the CPU core and the table 1-3-1 describes the block functions. Address Registers Data Registers A0 A1 A2 A3 A B Program Counter Increment ALU D0 D1 D2 D3 Multiplication/Division Register T1 T2 MDR Clock Generator Clock Source Instruction Execution Controller Instruction Decoder PSW Instruction Queue Program Address Operand Address Interrupt Controller Interrupt Bus Bus Controller ROM Bus RAM Bus Peripheral Extension Bus External Interface Internal ROM Internal RAM External Expansion Bus BREQ BRACK Internal Peripheral Function Figure 1-3-1 Block Diagram 10 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-3-1 Block Functions Block Clock Generator Function The clock generator contains the clock oscillation circuit connected to an external crystal and supplies the clock to all CPU blocks. The program counter generates addresses for instruction queues. Normally, it increments based on the sequencer indication, but for branch instructions and interrupt acceptance, it sets the branch address or ALU operation results. The instruction queue saves up to 4 bytes of prefetched instructions. The instruction decoder decodes the instruction queue content, generates control signals needed for the instruction execution, and executes the instruction by controlling each block in the CPU. The instruction execution controller controls the operations of each CPU function based on results from the instruction decoder and interrupt requests. The ALU calculates the operand addresses for arithmetic operations, logic operations, shift operations, register relative indirect addressing, indexed addressing and register indirect addressing. Internal ROM and internal RAM are allocated as the program, data and stack areas. The address registers (An) store the addresses of memory accessed during data transfer. They also store the base addresses in the register relative indirect, indexed addressing and register indirect addressing modes. The data registers (Dn) store the operation results and transfer the data to memory. They also store the operand addresses in indexed addressing and register indirect addressing mode. The multiplication/division register (MDR) stores the data for multiplication/division operations. Program Counter Instruction Queue Instruction Decoder Instruction Execution Controller ALU Internal ROM, Internal RAM Address Registers (An) Operation Registers (Dn, MDR) PSW The processor status word (PSW) stores the flags that indicate the status of the CPU interrupt controller and operation results. The interrupt controller detects the interrupt requests from the peripheral functions, and requests the CPU to move to the interrupt service routine. The bus controller controls the connection between the CPU internal bus and the CPU external bus. It also contains the bus arbitration function. This series contains the peripheral functions including timers, serial interface and A/D converter. Interrupt Controller Bus Controller Internal Peripheral Function MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 11 Chapter 1 General Description 1-4 Pin Description TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 53 52 TM6IC,P90 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 * * SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 PA5,ADSEP RST VDD P00,D00,AD00 P01,D01,AD01 P02,D02,AD02 P03,D03,AD03 P04,D04,AD04 P05,D05,AD05 P06,D06,AD06 P07,D07,AD07 VSS P10,D08,AD08 P11,D09,AD09 P12,D10,AD10 P13,D11,AD11 P14,D12,AD12 P15,D13,AD13 P16,D14,AD14 P17,D15,AD15 51 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 41 MN102L(P,F)25x Series (TOP VIEW) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 TM2IO,P82 TM1IO,P81 TM0IO,P80 A23,WDOUT,AN7,P47 A22,STOP,AN6,P46 A21,AN5,P45 A20,AN4,P44 VSS A19,P43 A18,P42 A17,P41 A16,P40 A15,P37 A14,P36 A13,P35 A12,P34 VDD A11,P33 A10,P32 A09,P31 A08,P30 A07,P27 A06,P26 A05,P25 A04,P24 P60,WAIT P56,ALE,ALE,BSTRE P57,WORD P20,A00 P21,A01 P22,A02 P23,A03 VDD SYSCLK VSS P63,WEH P50,CS0 P61,RE P51,CS1 P52,CS2 P53,CS3 P54,BREQ P55,BRACK P62,WEL Figure 1-4-1 Pin Configuration The unused input pins are connected to VDD/VSS, the unused output pins are opened and the unused I/O pins are connected to VDD/VSS by setting the direction in ports. 12 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G OSCI OSCO MODE XI XO VDD * : Use 33 k to 50 k. Chapter 1 General Description 1-4-1 List of Pin Functions Refer to "9-2-3 List of Pin Functions" for each pin's input level, Schmidt and pull-up resistor availability. TTL in the input level column means that the input is determined at TTL level. CMOS in the input level column means that the input is determined at CMOS level. The column with "yes" sign shows Schmidt, while the column with no mark shows no Schmidt. Pull-up can be programmable with the pull-up control registers. Please see "Chapter 8 Ports" for details. Table 1-4-1 List of Pin Functions (1/9) Pin Name VDD Input/Output Shared Pin Power Function Description There are six VDD pins. Connect these six pins to a power supply of 4.5 V to 5.5 V. VSS Power (Ground) There are four VSS pins. Connect these four pins to a power supply of 0 V. OSCI OSCO Input Output High-speed Oscillator Input (4 MHz to 20 MHz) High-speed Oscillator Output (4 MHz to 20 MHz) For a self-excited oscillator configuration, connect crystal or ceramic oscillator across these two pins. They have a built-in feedback resistor between them. For stability, insert capacitor of 20 pF to 33 pF between the OSCI or OSCO pin and VSS pin. (For the exact capacitance, consult the oscillator manufacturer.) For an external oscillator configuration, connect the OSCI pin to an oscillator with an amplitude of 4 MHz to 20 MHz and the width between VDD and VSS. Leave the OSCO open. See "Figure 1-4-2". Connecting the OSCO pin with the external circuit is not allowed. Select the SYSCLK pin as a synchronous signal. XI XO Input Output Low-speed Oscillator Input (32 kHz to 200 kHz) Low-speed Oscillator Output (32 kHz to 200 kHz) For a self-excited oscillator configuration, connect crystal or ceramic oscillator across these two pins. They have a built-in feedback resistor between them. For stability, insert capacitor of 100 pF to 200 pF between the XI or XO pin and VSS pin. (For the exact capacitance, consult the oscillator manufacturer.) See "Figure 1-4-3". For an external oscillator configuration, connect the XI pin to an oscillator with an amplitude of 32 kHz to 200 kHz and the width between VDD and VSS. Leave the XO open. See "Figure 1-4-3". If these pins are not used, fix XI to VDD or VSS and leave XO open. Connecting the XO pin with the external circuit is not allowed. Select the SYSCLK pin as a synchronous signal. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 13 Chapter 1 General Description Table 1-4-1 List of Pin Functions (2/9) Pin Name RST Input/Output Input Shared Pin Function Reset Input Description This pin resets the chip. With a 20-MHz oscillator, reset starts when the low level is input to this pin for more than 400 ns. Reset starts even when the noise is input to this pin for less than 400 ns. Reset is released when the high level is input to the pin. The oscillation waits of the high-speed oscillation pin (OSCI) are performed (approximately 6 ms to 7 ms with a 20-MHz oscillator). After that, the chip starts executing the instruction from x'08000'. See "Figure 1-4-4". SYSCLK Output System Clock Output This pin provides the system clock. After reset release, the oscillation waits of OSCI are always performed and this pin outputs the clock of 10 MHz. This pin hold the high level until the oscillation waits are released after the RST pin became the low level. MODE Input Memory Mode Setup Input This pin sets either processor mode or single-chip mode (memory expansion mode). Pulling the pin low sets the processor mode and internal ROM area becomes the external memory area. Pulling the pin high sets the single-chip mode (memory expansion mode). See "2-1-1, 2-2-3 Memory Expansion Mode". Do not change the mode setting in this pin during operation. When the setting is changed, proper operation cannot be guaranteed. In the MN102L2503 (ROM less), this pin is fixed the low level. P57 I/O WORD General-purpose Port 5 Data Bus Width Setup Input This pin can be used as a general-purpose input/output port only in the single-chip mode. See "Chapter 8 Ports". In processor mode or memory expansion mode, this pin sets either 8-bit data bus width or 16-bit data bus width in block 0 (the address of x'010000' to x'3FFFFF') of 4 blocks (Block 0 to Block 3) divided in the 16-MB space. The data bus widths for internal ROM, RAM and special registers are 16-bit width regardless of this pin setting. Pulling the pin low sets the 16-bit data bus width while pulling the pin high sets the 8-bit data bus width. In processor mode or memory expansion mode, always use this pin as an input pin for specifying the data bus width. Do not change the data bus width in this pin during operation. When the setting is changed, proper operation cannot be guaranteed. 14 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-4-1 List of Pin Functions (3/9) Pin Name P54 P55 Input/Output I/O Input I/O Output BREQ BRACK Shared Pin Function General-purpose Port 5 Bus Request General-purpose Port 5 Bus Request Enable Output Description This pin can be used as a general-purpose input/output port. See "Chapter 8 Ports". The BREQ and BRACK pins operate bus arbitration. Pulling the BREQ pin low suspends the execution of the current instruction. After that, the CPU releases bus and pulls the BRACK pin low. While the CPU is accessing bus, the CPU releases the bus after the bus access is completed and then pulls the BRACK pin low. Pulling the BREQ pin high restores the bus master to the CPU. See "2-2-2 External Memory Connection Example". P62 I/O Output WEL General-purpose Port 6 Lower Byte Write Enable Output General-purpose Port 6 Upper Byte Write Enable Output General-purpose Port 6 RE Read Enable Output This pin can be used as a general-purpose input/output port. See "Chapter 8 Ports". These pins provide control signals for the memory read/write. When connecting SRAM and ROM, connect RE to OE in memory. RE outputs low level during read operation and the CPU read out the content of the memory. When connecting SRAM, connect WEL and WEH to WE pins in memory. WEL and WEH output low level during write operation and the CPU writes the data to the memory. WEH controls writing of D15 to D08 while WEL controls writing of D00 to D07. WEL is invalid and used as a generalpurpose port 6 when 8-bit bus width for the external memory space is selected in the memory expansion mode. These pins become WEL, WEH and RE pins in the processor mode. (It means these cannot be used as general-purpose ports.) During bus request, STOP mode or HALT mode, these pins become in a high impedance state. (When using as ports, these are not in a high impedance state.) See "2-2-, 2-2-4 External Memory Connection Example". P63 I/O Output I/O Output WEH P61 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 15 Chapter 1 General Description Table 1-4-1 List of Pin Functions (4/9) Pin Name P43 to P40 Input/Output I/O Output A19 to A16 Shared Pin Function General-purpose Port 4 Address Output Description When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". Those pins output addresses (A19 to A16) of memory in processor mode or memory expansion mode. Connect them to address pins of memory or address decode circuit. When they are not accessing the memory, they output undefined addresses. (They output the some fixed values.) During the processor mode, these pins function as A19 to A16, and cannot be used as general-purpose I/O ports. During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports.) P45 to P44 I/O Input Output AN5 to AN4 A19 to A16 General-purpose Port 4 A/D Converter Input Address Output When using as general-purpose input/output ports, the I/O direction is controlled in bit units. These pins are used as A/D conversion input pins. See "Chapter 6 A/D Converter". These pins output addresses (A21 to A20) of memory in processor mode or memory expansion mode. Connect them to address pins of memory or address decode circuit. When they are not accessing the memory, they output undefined addresses. (They output the some fixed values.) During the processor mode, these pins function as A21 to A20, and cannot be used as general-purpose I/O ports. During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports or analog input pins.) 16 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-4-1 List of Pin Functions (5/9) Pin Name P46 Input/Output I/O Input Output Output AN6 STOP A22 Shared Pin Function General-purpose Port 4 A/D Conversion Input STOP Status Signal Address Output Description When using as a general-purpose input/output port, the I/O direction is controlled in bit units. This pin is used as an A/D conversion input pin. See "Chapter 6 A/D Converter". This pin becomes high level during STOP or HALT mode. This pin outputs the address (A22) of memory in processor mode or memory expansion mode. Connect it to address pin of memory or address decode circuit. When it is not accessing the memory, it outputs undefined address. (It outputs the any fixed value.) During a bus request (BREQ is low level), STOP mode or HALT mode, this pin will be in a high impedance state. (However, it will not be in a high impedance state when they are using as a general-purpose I/O port, an analog input or STOP pin.) P47 I/O Input Output Output AN7 WDOUT A23 General-purpose Port 4 A/D Converter Input Watchdog Timer Overflow Signal Address Output When using as a general-purpose input/output port, the I/O direction is controlled in bit units. This pin is used as an A/D conversion input pin. See "Chapter 6 A/D Converter". This pin outputs a pulse when the watchdog timer overflows. This pin outputs the address (A23) of memory in processor mode or memory expansion mode. Connect it to address pin of memory or address decode circuit. When it is not accessing the memory, it outputs undefined address. (It outputs the any fixed value.) During a bus request (BREQ is low level), STOP mode or HALT mode, this pin will be in a high impedance state. (However, it will not be in a high impedance state when they are using as a general-purpose I/O port, an analog input or WDOUT pin.) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 17 Chapter 1 General Description Table 1-4-1 List of Pin Functions (6/9) Pin Name P37 to P30 Input/Output I/O Output A15 to A08 Shared Pin Function General-purpose Port 3 Address Output Description When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". These pins output addresses (A15 to A08) of memory in processor mode or memory expansion mode. Connect them to address pins of memory or address decode circuit. When they are not accessing the memory, they output undefined addresses. (They output the some fixed values.) During the processor mode, these pins function as A15 to A08, and cannot be used as general-purpose I/O ports. During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports.) P27 to P20 I/O Output A07 to A00 General-purpose Port 2 Address Output When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". These pins output addresses (A07 to A00) of memory in processor mode or memory expansion mode. Connect them to address pins of memory or address decode circuit. When they are not accessing the memory, they output undefined addresses. (They output the some fixed values.) During the processor mode, these pins function as A07 to A00, and cannot be used as general-purpose I/O ports. During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports.) 18 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-4-1 List of Pin Functions (7/9) Pin Name P17 to P10 P07 to P00 Input/Output I/O Shared Pin Function General-purpose Port 1 General-purpose Port 0 I/O D15 to D00 (AD15 to AD00) Data (Address/Data) I/O pin Description When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". In processor mode or memory expansion mode, these pins function as data input/output during address/ data separate mode, and these pins time-divide the address (the lower 16-bit) output of memory and data input.output during address/data shared mode. When they are not accessing the memory, they become input. When the 8-bit data bus width is selected in memory expansion mode or address/data separate mode, P07 to P00 can function as I/O ports. See "2-2-2, 2-2-4 External Memory Connection" During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports.) P53 to P50 I/O Output CS3 to CS0 General-purpose Port 5 Chip Select Output When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". Connect CS3 to CS0 to each corresponding CS pin of the memory when accessing SRAM and ROM. See "Chapter 2 Bus Interface" for address allocation for CS3 to CS0. CS0 cannot be output when accesssing internal ROM. During a bus request (BREQ is low level), STOP mode or HALT mode, these pins will be in a high impedance state. (However, these pins will not be in a high impedance state when they are using as general-purpose I/O ports.) PA5 I/O Input ADSEP General-purpose Port A Addree/Data Separate/ Shared Mode Setup This pin can be used as a general-purpose input/output port only during single-chip mode. See "Chapter 8 Ports". This pin sets either address/data separate mode or address/data shared mode in processor mode or memory expansion mode. Pulling the pin high sets the address/data separate mode while pulling the pin low sets the address/data shared mode. Always use as ADSEP in processor mode or memory expansion mode. Do not change this pin's setting during the operation. When the setting is changed, proper operation cannot be guaranteed. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 19 Chapter 1 General Description Table 1-4-1 List of Pin Functions (8/9) Pin Name P56 Input/Output I/O Output BSTRE (ALE/ALE) Shared Pin Function General-purpose Port 5 Read Enable for Burst ROM (Address Latch Enable Output) Description This pin can be used as a general-purpose input/output port. See "Chapter 8 Ports". This pin becomes a RE signal for burst ROM during the address/data separate mode in processor mode. (However, this pin is not used as BSTRE because connecting the RE pin to burst ROM is possible with the penalty for burst ROM.) See "2-1-3 ROM Burst Mode Timing" This pin provides a timing signal of latching the address which outputs to A15 to A00 during the address/data shred mode. ALE outputs at positive logic at reset release, but the register switches to negative logic. Because of this, ALE cannot be used at negative logic in ROM less or processor mode. ALE can be output even during cycles when ALE is not accessing the external device. During a bus request (BREQ is low level), STOP mode or HALT mode, this pin will be in a high impedance state. (However, this pin will not be in a high impedance state when it is using as a generalpurpose I/O port.) P60 I/O Input WAIT General-purpose Port 6 Bus Cycle Wiat Input This pin can be used as a general-purpose input/output port. See "Chapter 8 Ports". This pin extends the cycle of accessing to the external memory when the external memory wait is set to handshake mode. Pulling this pin low ends access to the external memory. See "Figure 1-4-5" P74, P71 I/O Input SBI1 to SBI0 General-purpose Port 7 Serial Interface Data Input These pins can be used as general-purpose input/output ports. See "Chapter 8 Ports". These pins can be used as data input/output for serial interface. When these are unused, the input pins are fixed as high level while the output pins are opened. See "Chapter 5 Serial Interface". These pins can be used as general-purpose input/output ports. See "Chapter 8 Ports". These pins can be used as synchronous transfer clock signals for serial interface. When these are unused, the input pins are fixed as high level while the output pins are opened. See "Chapter 5 Serial Interface". P75, P72 I/O Output SBO1 to SBO0 General-purpose Port 7 Serial Interface Data Output P70 I/O I/O SBT0 General-purpose Port 7 Serial Interface 0 Clock Input/Output P73 I/O I/O SBT1 General-purpose Port 7 Serial Interface 1 Clock Input/Output 20 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description Table 1-4-1 List of Pin Functions (9/9) Pin Name P85 to P80 Input/Output I/O Shared Pin Function General-purpose Port 8 Description When using as general-purpose input/output ports, the I/O direction is controlled in bit units. See "Chapter 8 Ports". I/O TM5IO to TM0IO Timer 5 to Timer 0 Input/Output These pins can be used as timer 5 to timer 0 input/ output pins. This pin can be used as a general-purpose input/output port. TM6IOA Timer 6A Input/Output This pin can be used as a timer input capture input/ output compare output pin. This pin can be used as a general-purpose input/outTM6IOB Timer 6B Input/Output put port. This pin can be used as a timer input capture input/ output compare output pin. P90 I/O Input TM6IC Timer 6 Counter Clear This pin can be used as a general-purpose input/output port. This pin can be used as a timer 6 counter clear pin. See "Chapter 4 Timers" P91 I/O I/O TM7IOA Timer 7A Input/Output This pin can be used as a general-purpose input/output port. This pin can be used as a timer input capture input/ output compare output pin. This pin can be used as a general-purpose input/output port. This pin can be used as a timer input capture input/ output compare output pin. This pin can be used as a general-purpose input/outTM7IC Timer 7 Counter Clear put port. This pin can be used as a timer 7 counter clear pin. See "Chapter 4 Timers" P97 to P94 I/O Input AN3 to AN0 General-purpose Port 9 A/D Conversion Input When using as a general-purpose input/output port, the I/O direction is controlled in bit units. This pin is used as an A/D conversion input pin. See "Chapter 6 A/D Converter". NMI A NMI interrupt occurs on the falling edge to low level at negative logic. (When reading the Port A, monitor the pin value at bit 6.) PA4 to PA0 I/O Input IRQ4 to IRQ0 General-purpose Port A External Interrupt When using as a general-purpose input/output port, the I/O direction is controlled in bit units. See "Chapter 8 Ports". P86 I/O I/O P87 I/O I/O P92 I/O I/O TM7IOB General-purpose Port 8 Timer 7B Input/Output P93 I/O Input NMI Input MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 21 Chapter 1 General Description OSCI OSCO 4 MHz to 20 MHz OSCI OSCO 20 pF to 33 pF 20 pF to 33 pF 4 MHz to 20 MHz Oscillation Circuit Figure 1-4-2 OSCI and OSCO Connection Example XI XO XI XO 32 kHz to 200 kHz 100 pF to 200 pF 100 pF to 200 pF 32 kHz to 200 kHz Oscillation Circuit Figure 1-4-3 XI and XO Connection Example 10 k to 50 k RST Di 10 F to 100F + - SW Figure 1-4-4 Reset Connection Example RE WEH WEL RESET Delay Circuit WAIT Figure 1-4-5 WAIT Signal Control Circuit Example 22 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 1 General Description 1-5 External Dimensions Package Code: LQFP100-P-1414 Body Material: Epoxy Resin, Lead Material: FeNi42 Alloy, Lead Finish Method: Solder Plating Figure 1-5-1 External Dimensions: 100-pin LQFP External Dimensions are subject to change. Before using, please contact your nearest sales office for the latest product specifications. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 23 Chapter 1 General Description 24 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 Chapter 2 Bus Interface 2 3 4 5 6 7 8 9 Chapter 2 Bus Interface 2-1 Bus Interface 2-1-1 Overview The MN102L2503 has only processor mode. This series contains three memory modes of single-chip mode, memory expansion mode and processor mode. The chip of this series connects to the external memory or I/O consisted of gate array in the expansion mode or processor mode. The address space is divided into four fixed areas (Block 0 to Block 3). Each block has approximately 4 MB area and generates four chip-select signals to its corresponding external space. (The address space is optionally divided when the chip-select signals are generated externally.) 16-bit bus width or 8-bit bus width is selected for each block. The WORD pin sets the 16bit bus width or 8-bit bus width for Block 0 where the reset handler exists. On the other hand, the MEMMDn register sets the bus width for Block 1 to Block 3. See "1-4 Pin Functions for pin setting. x'00EC00' or x'00F400' * Accessing the virtual area using the program means accessing the real area in this series. x'080000' or x'088000' or x'090000' or x'0A0000' 26 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G ;; ;; ; ; ;; ;; ;; x'000000' Virtual Image External Memory Internal RAM (5 KB or 3 KB) (56 KB) x'00E000' Access Prohibited Area (2 KB or 4 KB) (1 KB) x'00FC00' x'010000' Special Registers External Memory (448 KB) Block 0 x'080000' Internal ROM (128 KB or 64 KB or 32 KB or 0KB) External Memory Burst ROM Support Area (384 KB or 448 KB or 480 KB or 512 KB) x'100000' External Memory (3952 KB) (4 MB) CS0 Area x'400000' External Memory CS1 Area Block 1 x'800000' Actual Image External Memory (56 KB) CS2 Area Block 2 External Memory (4 MB) x'C00000' External Memory (4 MB) CS3 Area Block 3 x'FFFFFF' Figure 2-1-1 Address Space ;;;;; ;;; Single-chip Mode Memory Expansion Mode External Memory Internal RAM Chapter 2 Bus Interface Processor Mode x'000000' Access Prohibited Area Internal RAM External Memory Internal RAM x'00E000' Figure 2-1-2 shows the bus controller of the MN102L25G. x'00F3FF' x'00FC00' Access Prohibited Area Special Registers Access Prohibited Area Special Registers Access Prohibited Area Special Registers x'00FFFF' x'080000' Access Prohibited Area External Memory External Memory Internal ROM Reset Handler Interrupt Handler Internal ROM Reset Handler Interrupt Handler Reset Handler Interrupt Handler External Memory x'09FFFF' Access Prohibited Area External Memory x'FFFFFF' Pin Mode = 'H' Pin Mode = 'H' After reset, set ports 0,1,2,3,4,5,6 to A23 -A00, D15 - D00 and Bus interface signals using software. Pin Mode = 'L' Figure 2-1-2 Bus Controller In this series, the addresses of x'000000' to x'00DFFF' replaces the addresses of x'800000' to x'80DFFF'. Beacuse of this, the CS2 signal is generated even though the program accesses the address of x'000000' to x'00DFFF' shown in Figure 2-1-1. The CS1 pin, CS2 pin and CS3 pin are allocated into Block1, Block2 and Block 3 respectively, and these pins become low level. CS0 x'010000' to x'3FFFFF' (The CS0 signal is not generated in the internal ROM area.) x'400000' to x'7FFFFF' x'000000' to x'00DFFF' x'800000' to x'BFFFFF' x'C00000' to x'FFFFFF' The CS0 signal is generated even in the internal ROM area during processor mode. CS1 CS2 CS3 Accessing the logical addresses of x'000000' to x'00DFFF' means accessing the addresses of x'800000' to x'80DFFF'. Table 2-1-1 CS Signal Generation This series has two modes of address/data shared mode and address/data separated mode. The ADSEP pin selects each mode. Figure 2-1-3 to Figure 2-1-7 show the pin configuration in each mode. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 27 Chapter 2 Bus Interface TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 53 52 TM6IC,P90 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 RST VDD AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 VSS AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 91 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102L25x (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 A23,WDOUT,AN7,P47 A22,STOP,AN6,P46 A21,AN5,P45 A20,AN4,P44 VSS A19,P43 A18,P42 A17,P41 A16,P40 P37 P36 P35 P34 VDD P33 P32 P31 P30 P27 P26 P25 P24 10 11 12 13 14 15 16 17 18 19 20 21 22 23 53 SYSCLK VSS P60,WAIT P54,BREQ P55,BRACK ALE,ALE WORD P20 P21 P22 P23 VDD Figure 2-1-3 Memory Expansion Mode (Address/Data Shared Pin Configuration) TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 52 P62,WEL WEH P50,CS0 P51,CS1 P52,CS2 P53,CS3 TM6IC,P90 OSCI OSCO 91 XI XO VDD RE 24 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 RST VDD P00,D00 P01,D01 P02,D02 P03,D03 P04,D04 P05,D05 P06,D06 P07,D07 VSS D08 D09 D10 D11 D12 D13 D14 D15 56 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI 25 1 2 3 4 5 6 7 8 9 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102L25x (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 A23,WDOUT,AN7,P47 A22,STOP,AN6,P46 A21,AN5,P45 A20,AN4,P44 VSS A19,P43 A18,P42 A17,P41 A16,P40 A15,P37 A14,P36 A13,P35 A12,P34 VDD A11,P33 A10,P32 A09,P31 A08,P30 A07,P27 A06,P26 A05,P25 A04,P24 SYSCLK VSS P60,WAIT P56,BSTRE WORD P20,A00 P21,A01 P22,A02 P23,A03 VDD WEH P50,CS0 P51,CS1 Figure 2-1-4 Memory Expansion Mode (Address/Data Separated Pin Configuration) 28 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G P52,CS2 P53,CS3 P54,BREQ P55,BRACK P62,WEL OSCI OSCO XI XO VDD RE Chapter 2 Bus Interface TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 53 52 TM6IC,P90 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 RST VDD AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 VSS AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 91 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102L25x (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 A23,WDOUT,AN7,P47 A22,STOP,AN6,P46 A21 A20 VSS A19 A18 A17 A16 P37 P36 P35 P34 VDD P33 P32 P31 P30 P27 P26 P25 P24 ALE is not generated during processor mode. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 P60,WAIT SYSCLK VSS WEH CS0 CS1 CS2 CS3 P54,BREQ P55,BRACK ALE WORD P20 P21 P22 P23 VDD Figure 2-1-5 Processor Mode (Address/Data Shared Pin Configuration) TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 53 52 TM6IC,P90 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 RST VDD P00,D00 P01,D01 P02,D02 P03,D03 P04,D04 P05,D05 P06,D06 P07,D07 VSS D08 D09 D10 D11 D12 D13 D14 D15 91 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI OSCI OSCO WEL XI XO VDD RE 24 25 1 2 3 4 5 6 7 8 9 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102L25x (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 A23,WDOUT,AN7,P47 A22,STOP,AN6,P46 A21 A20 VSS A19 A18 A17 A16 A15 A14 A13 A12 VDD A11 A10 A09 A08 A07 A06 A05 A04 SYSCLK VSS P60,WAIT WEH CS0 CS1 CS2 CS3 P54,BREQ P55,BRACK BSTRE WORD A00 A01 A02 A03 VDD Figure 2-1-6 Processor Mode (Address/Data Separated Pin Configuration) OSCI OSCO WEL XI XO VDD RE MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 29 Chapter 2 Bus Interface TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 55 54 53 52 TM6IC,P90 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBO1,P75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 PA5 RST VDD P00 P01 P02 P03 P04 P05 P06 P07 VSS P10 P11 P12 P13 P14 P15 P16 P17 91 TM3IO,P83 SBT0,P70 VDD (Vpp) AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS NMI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102L25x (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 WDOUT,AN7,P47 STOP,AN6,P46 AN5,P45 AN4,P44 VSS P43 P42 P41 P40 P37 P36 P35 P34 VDD P33 P32 P31 P30 P27 P26 P25 P24 10 11 12 13 14 15 16 17 18 19 20 21 22 23 P56 P57 P20 P21 P22 P23 VDD SYSCLK Figure 2-1-7 Single-chip Mode 30 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G OSCI OSCO VSS P60 P61 P63 P50 P51 P52 P53 P54 P55 P62 XI XO VDD 24 25 1 2 3 4 5 6 7 8 9 Chapter 2 Bus Interface MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 31 Chapter 2 Bus Interface 2-1-2 Control Registers These registers control the bus interface: the memory control register (MEMCTR), the memory moode control register (MEMMDn) and the external memory control register (EXMCTR). Table 2-1-2 List of Bus Interface Control Registers Register MEMCTR MEMMD0 MEMMD1 MEMMD2 MEMMD3 EXMCTR Address x'00FC02' x'00FC30' x'00FC32' x'00FC34' x'00FC36' x'00FD00' R/W R/W R/W R/W R/W R/W R/W Function Memory Control Register Memory Mode Control Register 0 Memory Mode Control Register 1 Memory Mode Control Register 2 Memory Mode Control Register 3 External Memory Control Register The MEMCTR register and the MEMMDn register need to set the conditions matched the system configuration during the initialization program. [See "9-4 Initialization Program"] The MEMCTR register sets x'04n0' (n = 0 to 3, the wait cycle of special registers is normally 1) during the initialization program. The MEMMD0 register sets the wait cycle for the device connected to Block 0. The bits for selecting bus mode do noe exist in the MEMMD0 register like other MEMMDn registers because the bus width for Block 0 is selected using the pin. Setting the WAIT[1:0] is ignored in the burst ROM support area when using burst ROM. MEMMD0: x'00FC30' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT WAIT 1 0 Wait Cycle Setting for Block 0 00: None 01: 1 cycle 10: 2 cycles 11: Handshake 32 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface The MEMMD1 register sets the wait cycles and bus mode for Block 1. MEMMD1: x'00FC32' 15 14 13 12 11 10 9 8 BSMOD 7 6 5 4 3 2 1 0 WAIT WAIT 1 0 Wait Cycle Setting for Block 1 00: None 01: 1 cycle 10: 2 cycles 11: Handshake Bus Width Setting for Block 1 0: 16-bit Bus Width 1: 8-bit Bus Width The MEMMD2 register sets the wait cycles and bus mode for Block 2. When using the address converted area (x'000000' to x'00DFFF'), set the bus width for block 2 as the same as the bus width for block 0. MEMMD2: x'00FC34' 15 14 13 12 11 10 9 8 BSMOD 7 6 5 4 3 2 1 0 WAIT WAIT 1 0 Wait Cycle Setting for Block 2 00: None 01: 1 cycle 10: 2 cycles 11: Handshake Bus Width Setting for Block 2 0: 16-bit Bus Width 1: 8-bit Bus Width The MEMMD3 register sets the wait cycles and bus mode for Block 3. MEMMD3: x'00FC36' 15 14 13 12 11 10 9 8 BSMOD 7 6 5 4 3 2 1 0 WAIT WAIT 1 0 Wait Cycle Setting for Block 3 00: None 01: 1 cycle 10: 2 cycles 11: Handshake Bus Width Setting for Block 3 0: 16-bit Bus Width 1: 8-bit Bus Width MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 33 Chapter 2 Bus Interface The EXMCTR register sets the burst mode for ROM, the polarity of ALE signal during the address/data shared mode, and the pulse width of WEH signal and WEL signal. EXMCTR: x'00FD00' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WE SHT NALE EN BRPG BRPG 0 1 BREN BREN 1 0 *3 See "2-1-3 ROM Burst Mode Timing" for the penalty availability of burst mode. ROM burst mode without penalty is not allowed during processor mode or in the MN102L2503. (*3) ROM Burst Mode 00: Disable 01: Reserved 10: Enable (Without penalty) 11: Enable (With penalty) Page Size of ROM Burst Mode 00: 4 bytes 01: 8 bytes 10: 16 bytes 11: Reserved ALE Siganl Polarity 0: Pogitive logic 1: Negative logic (*2) *2 Setting the NALEEN bit is invalid during the address/data separated mode. *1 Setting the WESHT bit to 1 makes the rising edge of WEH and WEL 1/4 cycle (25 ns with a 20MHz oscillator) forward and the hold time of address/data longer. WEH, WEL Pulse Width Shortening 0: Disable 1: Enable (*1) 34 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 35 Chapter 2 Bus Interface 2-1-3 ROM Burst Mode Timing This LSI series supports interface for ROM corresponding to burst mode accesses. The burst mode is a mode which reads the data of consecutive few bytes (only few lower bits are changed) at high-speed (access twice faster than normal access). Use burst mode only during the address/data separated mode. (Do not use burst mode during the address/ data shared mode.) Access area for burst mode is x'080000' to x'0FFFFF'. The access cycle in x'080000' to x'0FFFFF' is 1 wait cycle outside the page and no wait cycle in the page. (Bits[1:0] of the MEMMD0 register are ignored.) This series supports the lower 2 bits (4 bytes for page size), the lower 3 bits (8 bytes for page size), and the lower 4 bits (16 bytes for page size). An - A02 CE OE A01 - 00 D07 - 00 Figure 2-1-8 ROM Timing for Burst Mode (4 bytes for Page Size) 36 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface This series has the access cycle with penalty and without penalty when the chip accesses to devices except ROM after it accesses to ROM during the burst mode. Figure 2-1-9 shows their timings and Figure 2-1-10 shows the connection example. The ROM burst mode is used only during the address/data separated mode and the WAIT pin is ignored even though handshake mode us selected. (Figure 2-1-9 shows the timing of 8 bytes/page during the 16-bit bus mode.) With Penalty OSCI SYSCLK A23-00 D15-00 CS0 CSn RE WEH WEL (A2-0=000) (A2-0=010)(A2-0=100)(A2-0=110) (A2-0=000) ;; ;; (Not ROM) (Penarty)(Not ROM) Without Penalty OSCI SYSCLK (A2-0=000) (A2-0=010)(A2-0=100)(A2-0=110) (A2-0=000) (A2-0=010) A23-00 D15-00 CS0 CSn BRE RE WEH WEL When the access without penalty is selected, accessing x'010000' to x'07FFFF' and x'100000' to x'3FFFFF' is not allowed. Figure 2-1-9 ROM Burst Mode Access Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 37 Chapter 2 Bus Interface MN102L25x A23-00 D15-00 MN102L25x A23-00 D15-00 OE *Note A D A D A D A D ROM OE CE RAM OE WR CE ROM OE CE RAM OE WR CE RE WEH (WEL) CS0 CSn BSTRE RE WEH (WEL) CS0 CSn *Note: When using ROM with longer output data hold time, you may need to equip the 3-state buffer (for example, 74ALS541) in the broken line. Figure 2-1-10 Access Timing Memory Connection Example During ROM Burst Mode As Figure 2-1-10 shows, the access is fast but RE signal (BSTRE) for burst ROM is required when access without penalty cycle is selected. In addition, the external 3-state buffer (for example, 74ALS541) may be required when the ROM data hold time is long. 38 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 39 Chapter 2 Bus Interface 2-2 External Memory Connection Examples 2-2-1 Memory Expansion Mode (Address/Data Separated Mode) In this LSI series, the control registers for address or data setting need to be set as follows during address/data separated mode. [See Chapter 8 Ports.] No. 1 Up to 16 bytes (A03 to A00) 8 bit (D15 to D08) P0DIR= P1DIR= P2DIR= P3DIR= P4DIR= - - - - - - - * P0MD= P1MD= P2MD= P3MD= P4MD= P0MD= - - - - - - - * Use D07 to D00 as general-purpose ports. - - - - - - - 0 - - - - - - - 1 - - - * - - - 0 - - - 0 - - - 1 Use A23 to A04 as general-purpose ports. * * * * * * * * 0 0 0 0 0 0 0 0 * * * * * * * * 0 0 0 0 0 0 0 0 16 bit (D15 to D00) P0DIR= - - - - - - - 0 - - - - - - - 1 Use A23 to A04 as general-purpose ports. P1DIR to P4DIR and P1MD to P4MD are same as those in the above 8-bit bus width of No. 1. No. 2 Up to 256 bytes (A07 to A00) 8 bit (D15 to D08) P0DIR= P1DIR= P2DIR= - - - - - - - * P0MD= P1MD= P2MD= - - - - - - - * Use D07 to D00 as general-purpose ports. Use A23 to A08 as general-purpose ports. - - - - - - - 0 - - - - - - - 1 - - - 0 - - - 0 - - - 1 - - - 1 P3DIR to P4DIR and P1MD to P4MD are same as those in the above 8-bit bus width of No. 1. 16 bit (D15 to D00) P0DIR= - - - - - - - 0 P0MD= - - - - - - - 1 Use A23 to A08 as general-purpose ports. No.3 Up to 512 bytes (A08 to A00) 8 bit (D15 to D08) P1DIR to P4DIR and P1MD to P4MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * * * * * * 0 Use D07 to D00 as general-purpose ports. 0 1 P3MD= 0 0 0 0 0 0 Use A23 to A09 as general-purpose ports. 16 bit (D15 to D00) No.4 Up to 1k bytes (A09 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * * * * * 0 0 Use A23 to A09 as general-purpose ports. Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 0 0 0 0 0 Use A23 to A10 as general-purpose ports. 16bit (D15 to D00) No.5 Up to 2k bytes (A10 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * * * * 0 0 0 Use A23 to A10 as general-purpose ports. Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 0 0 0 0 1 Use A23 to A11 as general-purpose ports. 16bit (D15 to D00) No.6 Up to 4k bytes (A11 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * * * 0 0 0 0 Use A23 to A11 as general-purpose ports. Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 0 0 0 1 1 Use A23 to A12 as general-purpose ports. 16bit (D15 to D00) No.7 Up to 8k bytes (A12 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * * 0 0 0 0 0 Use A23 to A12 as general-purpose ports. Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 0 0 1 1 1 Use A23 to A13 as general-purpose ports. 16bit (D15 to D00) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. Use A23 to A13 as general-purpose ports. 40 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface No.8 Up to 16k bytes (A13 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * * 0 0 0 0 0 0 Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 0 1 1 1 1 Use A23 to A14 as general-purpose ports. 16bit (D15 to D00) No.9 Up to 32k bytes (A14 to A00) 8bit (D15 to D08) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= * 0 0 0 0 0 0 0 Use A23 to A14 as general-purpose ports. Use D07 to D00 as general-purpose ports. 1 1 P3MD= 0 1 1 1 1 1 Use A23 to A15 as general-purpose ports. 16bit (D15 to D00) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 8-bit bus width of No. 1. P3DIR= 0 0 0 0 0 0 0 0 Use A23 to A15 as general-purpose ports. No.10 Up to 64k bytes (A15 to A00) 8bit (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 P3MD= 1 1 1 1 1 1 Use A23 to A16 as general-purpose ports. 16bit (D15 to D00) P0DIR to P2DIR, P4DIR and P0MD to P2MD, P4MD are same as those in the above 16-bit bus width of No. 1. P3DIR and P3MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * * * * * * 0 Use A23 to A16 as general-purpose ports. No.11 Up to 128k bytes (A16 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 0 0 1 P4MD= 0 0 0 0 0 Use A23 to A17 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * * * * * 0 0 Use A23 to A17 as general-purpose ports. No.12 Up to 256k bytes (A17 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 0 1 1 P4MD= 0 0 0 0 0 Use A23 to A18 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * * * * 0 0 0 Use A23 to A18 as general-purpose ports. No.13 Up to 512k bytes (A18 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 1 P4MD= 0 0 0 0 0 Use A23 to A19 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * * * 0 0 0 0 Use A23 to A19 as general-purpose ports. No.14 Up to 1M bytes (A18 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 1 P4MD= 0 0 0 0 1 Use A23 to A20 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * * 0 0 0 0 0 Use A23 to A20 as general-purpose ports. No.15 Up to 2M bytes (A19 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 1 P4MD= 0 0 0 1 1 Use A23 to A21 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * * 0 0 0 0 0 0 Use A23 to A21 as general-purpose ports. No.16 Up to 4M bytes (A20 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 1 P4MD= 0 0 1 1 1 Use A23 to A22 as general-purpose ports. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= * 0 0 0 0 0 0 0 Use A23 to A22 as general-purpose ports. No.17 Up to 8M bytes (A21 to A00) Or (/CS2 to /CS0, A21 to A00) 8bit (All Spaces) (D15 to D08) Use D07 to D00 as general-purpose ports. 1 1 1 P4MD= P6MD= 0 1 1 1 1 * 0 - - * * * - In addition, use A22 as a general-purpose port when the address is determined by /CS2 to /CS0. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. P0DIR to P3DIR and P0MD to P3MD are same as those in the above 8-bit bus width of No. 10. P4DIR= 0 0 0 0 0 0 0 0 Use A23 as a general-purpose port. In addition, use A22 as a general-purpose port when the address is determined by /CS2 to /CS0. Use D07 to D00 as general-purpose ports. 1 1 1 No.18 Up to 16M bytes (A23 to A00) Or (/CS3 to /CS0, A23 to A00) 8bit (All Spaces) (D15 to D08) P4MD= P6MD= 1 1 1 1 1 0 0 - - * * * - In addition, use A23 to A22 as generalpurpose ports when the address is determined by /CS3 to CS0. 16bit (D15 to D00) P0DIR to P3DIR and P0MD to P3MD are same as those in the above 16-bit bus width of No. 10. P4DIR and P4MD are same as those in the above 8-bit bus width. Use /CS3 to /CS0 as general-purpose ports. In addition, use A23 to A22 as generalpurpose ports when the address is determined by /CS3 to CS0. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 41 Chapter 2 Bus Interface 2-2-2 External Memory Connection Examples (Address/Data Separeted Mode) This section describes the external memory connection examples. s Memory System with 16-bit Bus Width The following is the example of connecting the 4-Mbit ROM (256 kilowords x 16 bits), the 1-Mbit SRAM (128 kilo words x 8 bits) and the ASIC with 16-bit bus width to the CS0 area (1 wait cycle fixed), the CS1 area (no wait cycle fixed) and the CS3 area (handshake), respectively. A18-A00 D15-D00 A23-A19 Port 18:1 15:0 D15-D00 A17-A00 15:8 I/O7-0 A16-A00 16:0 15:0 D A ROM CS0 CS1 ADSEP WORD WAIT CS3 CS OE CS OE WE WAIT CS OE WEH WEL SRAM ASIC RE WEH WEL Figure 2-2-1 Memory Connection Example with 16-bit Bus Width (Address/Data Separated Mode) MEMMD0: x'00FC30' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 1 MEMMD1: x'00FC32' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 1 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 0 MEMMD3: x'00FC36' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 1 0 42 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface s Memory System with 8-bit Bus Width in All Areas The following is the example of connecting the 4-Mbit ROM (512 kilowords x 8 bits), the 1-Mbit SRAM (128 kilowords x 8 bits) and the ASIC with 8-bit bus width to the CS0 area (2 wait cycles fixed), the CS1 area (1 wait cycle fixed) and the CS3 area (handshake), respectively. A18-A00 D15-D08 A23-A19 D07-D00 Port 18:0 15:8 D15-D00 A18-A00 15:8 16:0 15:8 I/O7-0 A16-A00 D A ROM CS0 CS1 CS OE CS OE WE WAIT CS OE WE SRAM ASIC ADSEP WAIT CS3 WORD RE WEH Figure 2-2-2 Memory Connection Example with 8-bit Bus Width (Address/Data Separated Mode) MEMMD0: x'00FC30' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 0 In the MN10200 series, the data is input to the upper pins of D15 to D08. MEMMD1: x'00FC32' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 1 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 1 MEMMD3: x'00FC36' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 1 1 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 43 Chapter 2 Bus Interface s ROM, RAM Access Timing with 16-bit Bus Width OSCI SYSCLK A23-00 (A00=H) (A00=L)) D15-08 D07-00 CS RE WEH WEL Read 16-bit Write 8-bit Write High Side 8-bit Write Low side Figure 2-2-3 No Wait Access Timing with 16-bit Bus Width OSCI SYSCLK A23-00 D15-08 D07-00 CS RE WEH WEL Read 16-bit Write 8-bit Write Low Side Figure 2-2-4 1 Wait Access Timing with 16-bit Bus Width 44 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface s ROM, RAM Access Timing with 16-bit Bus Width OSCI SYSCLK A23-00 D15-08 D07-00 CS RE WEH WEL WAIT 16-bit Read 16-bit Write Figure 2-2-5 Handshake Access Timing with 16-bit Bus Width s ROM, RAM Access Timing with 8-bit Bus Width OSCI SYSCLK A23-00 (A00=0) (A00=1) D15-08 CS RE WEH 16-bit Read 8-bit Write Figure 2-2-6 No Wait Access Timing with 8-bit Bus Width MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 45 Chapter 2 Bus Interface s ROM, RAM Access Timing with 8-bit Bus Width OSCI SYSCLK A23-00 (A00=0) (A00=1) D15-08 CS RE WEH 16-bit Read 8-bit Write Figure 2-2-7 1 Wait Access Timing with 8-bit Bus Width OSCI SYSCLK A23-00 D15-08 CS WE WAIT 16-bit Write Figure 2-2-8 Handshake Access Timing with 8-bit Bus Width 46 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface s Access Timing during Bus Request (Address/Data Separated Mode) OSCO SYSCLK A23-16 D15-00 CSn BRE RE WEH,WEL WAIT BREQ BRACK Bus Master CPU External Device CPU D FLOATING FLOATING FLOATING FLOATING FLOATING FLOATING A D Figure 2-2-9 Access Timing during Bus Request (Address/Data Separated Mode) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 47 Chapter 2 Bus Interface 2-2-3 Memory Expansion Mode (Address/Data Shared Mode) In this LSI series, the control registers for address or data setting need to be set as follows during address/data shared mode. [See Chapter 8 Ports.] No.1 Up to 64 Kbytes 8/16bit P0DIR= P1DIR= P4DIR= - - - - - - - 0 P0MD= P1MD= P4MD= - - - - - - - 1 Use A23 to A16 as general-purpose ports. - - - - - - - 0 - - - - - - - 1 * * * * * * * 0 0 0 0 0 0 0 0 0 No.2 Up to 128 Kbytes 8/16bit P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 0 0 0 0 P4DIR= * * * * * * * 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 0 0 0 0 P4DIR= * * * * * * 1 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 0 0 0 1 P4DIR= * * * * * 1 1 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 0 0 1 1 P4DIR= * * * * 1 1 1 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 0 1 1 1 P4DIR= * * * 1 1 1 1 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 0 1 1 1 1 P4DIR= * * 1 1 1 1 1 1 P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 0 1 1 1 1 1 P4DIR= * 1 1 1 1 1 1 1 P6MD= * 0 * * Use A23 to A17 as general-purpose ports. 0 1 No.3 Up to 256 Kbytes 8/16bit Use A23 to A18 as general-purpose ports. 1 1 No.4 Up to 512 Kbytes 8/16bit Use A23 to A19 as general-purpose ports. 1 1 No.5 Up to 1 Mbyte 8/16bit Use A23 to A20 as general-purpose ports. 1 1 No.6 Up to 2 Mbytes 8/16bit Use A23 to A21 as general-purpose ports. 1 1 No.7 Up to 4 Mbytes 8/16bit Use A23 to A22 as general-purpose ports. 1 1 No.8 Up to 8 Mbytes 8/16bit Use A23 as a general-purpose port. 1 1 * - No.9 Up to 16 Mbytes 8/16bit P0DIR to P1DIR and P0MD and P1MD are set as same as those in the above. P4MD= 1 1 1 1 1 1 P4DIR= 1 1 1 1 1 1 1 1 P6MD= 0 0 * * 1 1 * - 48 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 49 Chapter 2 Bus Interface 2-2-4 External Memory Connection Examples (Address/Data Shared Mode) This section describes the external memory connection examples. s Memory System with 16-bit Bus Width The following is the example of connecting the 4-Mbit ROM (256 kilo words x 16 bits), the 1-Mbit SRAM (128 kilo words x 8 bits) and the ASIC with 16-bit bus width to the CS0 area (1 wait cycle fixed), the CS1 area (1 wait cycle fixed) and the CS3 area (handshake), respectively. 15:8 7:0 18:16 DQ E 15:8 DQ E 7:0 15:0 18:1 D15-D00 A17-A00 I/O7-0 15:8 16:0 A16-A00 15:0 A18-A16 AD15-AD08 Port A23-A19 AD07-A00 ALE CS0 CS1 ADSEP WAIT WORD CS3 D A ROM SRAM CS OE CS OE WE WAIT CS OE WEH WEL ASIC RE WEH WEL Figure 2-2-10 Memory Connection Example with 16-bit Bus Width (Address/Data Shared Mode) MEMMD0: x'00FC30' During the address/data shared mode, this LSI series operates in 1 wait cycle even though WAIT[1:0] are set to `00'. 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 1 MEMMD1: x'00FC32' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 1 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 1 MEMMD3: x'00FC36' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 1 0 50 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface s Memory System with 8-bit Bus Width in All Areas The following is the example of connecting the 4-Mbit ROM (512 kilo words x 8 bits), the 1-Mbit SRAM (128 kilo words x 8 bits) and the ASIC with 8-bit bus width to the CS0 area (2 wait cycles fixed), the CS1 area (1 wait cycle fixed) and the CS3 area (handshake), respectively. A18-A16 AD15-AD08 AD07-AD00 D E Q 18:16 18:0 15:8 7:0 I/O7-0 A18-A00 I/O7-0 A16-A00 D A ROM SRAM CS OE CS OE WE WAIT CS OE WE ALE CS0 CS1 ASIC WAIT CS3 RE WEH Figure 2-2-11 Memory Connection Example with 8-bit Bus Width (Address/Data Shared Mode) MEMMD0: x'00FC30' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 0 In the MN10200 series, the data is input to the upper pins of D15 to D08. MEMMD1: x'00FC32' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 1 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 0 1 MEMMD3: x'00FC36' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 BMOD 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 WAIT1 WAIT0 1 1 1 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 51 Chapter 2 Bus Interface s ROM, RAM Access Timing with 16-bit Bus Width OSCI SYSCLK A23-A16 (Address) (Data) (Data) (Address)(Data) (Address)(Data) (AD00=0) (Address)(Data) (Address) (AD00=1) (Address) (Address)(Data) (AD00=0) AD15-AD08 (Address) AD07-AD00 (AD00=0) ALE CS RE WEH WEL Read 16-bit Write 8-bit Write High Side 8-bit Write Low Side Figure 2-2-12 Fixed Wait Access Timing with 16-bit Bus Width OSCI SYSCLK A23-A16 (Address) (Data) (Address) (Data) AD15-AD08 (Address) (Data) (Address) (Data) AD07-AD00 ALE CS RE WEH WEL WAIT Read Write Figure 2-2-13 Handshake Access Timing with 16-bit Bus Width 52 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 2 Bus Interface s ROM, RAM Access Timing with 8-bit Bus Width OSCI SYSCLK A23-A16 (Address) (Data) (Address) (Address) (AD00=1) (Data) (Address)(Data) (Address) (AD00=1) (Address)(Data) (Address) (AD00=0) AD15-AD08 (Address) AD07-AD00 (AD00=0) ALE CS RE WEH WEL Lower 8-bit Access Upper 8-bit Access 8-bit Write High Side 8-bit Write Low Side 16-bit Read Figure 2-2-14 Fixed Wait Access Timing with 8-bit Bus Width OSCI SYSCLK A23-A16 (Address) (Data) (Address) (Address) (AD00=1) (Data) AD15-AD08 (Address) AD07-AD00 (AD00=0) ALE CS RE WEH WEL WAIT Lower 8-bit Access 16-bit Write Upper 8-bit Access Figure 2-2-15 Handshake Access Timing with 8-bit Bus Width MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 53 Chapter 2 Bus Interface s Access Timing during Bus Request (Address/Data Shared Mode) OSCO SYSCLK A23-A16 D15-D00 ALE CSn RE WEH,L WAIT BREQ BRACK Bus Master CPU External Device CPU A D FLOATING FLOATING FLOATING FLOATING FLOATING FLOATING A D Figure 2-2-16 Access Timing during Bus Request (Address/Data Shared Mode) 54 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 Chapter 3 Interrupts 3 4 5 6 7 8 9 Chapter 3 Interrupts 3-1 Interrupts 3-1-1 Overview The interrupt Controller contains eight groups. Each group has some interrupt vectors . When an interrupt occurs, the CPU receives an interrupt request. [See the MN10200 Series LSI User's Manual Linear Addressing Version.] Table 3-1-1 List of Interrupt Control Registers Interrupt Group Interrupt Vector (Number is IDTn bit position) 2 Undefined Instruction Interrupt 1 Watchdog Timer Interrupt 0 NMI Interrupt 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Reserved Timer/Counter 5 Underflow Timer/Counter 0 Underflow External Interrupt IRQ0 Reserved A/D Conversion End Timer/Counter 1 Underflow External Interrupt IRQ1 Serial Ch0 Reception End Serial Ch0 Transmission End Timer/Counter 2 Underflow External Interrupt IRQ2 Serial Ch1 Reception End Serial Ch1 Transmission End Timer/Counter 3 Underflow External Interrupt IRQ3 Control Register Nonmaskable Interrupt Control Register 0 G0ICR: x'00FC40' Maskable Interrupt Control Register 1 G1ICR: x'00FC42' Group 0 Group 1 Group 2 Maskable Interrupt Control Register 2 G2ICR: x'00FC44' Group 3 Maskable Interrupt Control Register 3 G3ICR: x'00FC46' Group 4 Maskable Interrupt Control Register 4 G4ICR: x'00FC48' Group 5 3 Reserved (Set the corresponding enable flag to 0.) 2 Reserved (Set the corresponding enable flag to 0.) 1 Timer/Counter 4 Underflow 0 External Interrupt IRQ4 3 2 1 0 3 2 1 0 ATC End Timer/Counter 6 Compare/Capture B Timer/Counter 6 Compare/Capture A Timer/Counter 6 Underflow Reserved Timer/Counter 7 Compare/Capture B Timer/Counter 7 Compare/Capture A Timer/Counter 7 Underflow Maskable Interrupt Control Register 5 G5ICR: x'00FC4A' Group 6 Maskable Interrupt Control Register 6 G6ICR: x'00FC4C' Group 7 Maskable Interrupt Control Register 7 G7ICR: x'00FC4E' 56 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 3 Interrupts The control register is assigned to its corresponding interrupt group except Group 0 and controls the assigned interrupt vectors. For example, in the MN102L(F, P) 25x, when timer 0 underflows, the interrupt request flag (IRF1=TM0IR) of the maskable interrupt control register (G1ICR) becomes 1. At this point, the CPU receives an interrupt request if the corresponding interrupt enable flag (IEN1=TM0IE) is 1. Comparing the interrupt mask level (IM2 - 0 ) of the processor status word (PSW) and the group interrupt level (ILVn=G1LV[2:0]) of the G1ICR register determines whether the CPU receives the interrupt or not. G1ICR: x'00FC42' 15 14 G1 LV2 13 G1 LV1 12 G1 LV0 11 10 TM5 IE 9 TM0 IE 8 IRQ0 IE 7 6 TM5 IR 5 TM0 IR 4 IRQ0 IR 3 2 TM5 ID 1 TM0 ID 0 IRQ0 ID Group Interrupt Level ILVn Interrupt Level Setup Interrupt Enable Flag IENn Interrupt Enable Setup Interrupt Request Flag IRFn Interrupt Vector Generation Interrupt Detect Flag IDTn Interrupt Request Detect See "2-5 Interrupt Controller" in the MN10200 Series LSI User's Manual Linear Addressing Version for detail operations. See the MN10200 Series Instruction Manual Linear Addressing Version for interrupt service flow and handler programming. Set the interrupt enable flags IEN[3:2] (bits [11:10]) of the G5ICR to 0. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 57 Chapter 3 Interrupts 3-2 External Interrupts 3-2-1 External Pin Interrupts Group 5 to Group 1 control external pin interrupts. The EXTMD register sets the interrupt conditions. The EXTMD register sets the interrupt levels and timing of external interrupts. The EXTMD register specifies each pins's level or edge. EXTMD: x'00FC50' 15 14 13 12 11 10 9 IRQ4 TG1 8 IRQ4 TG0 7 IRQ3 TG1 6 IRQ3 TG0 5 IRQ2 TG1 4 IRQ2 TG0 3 IRQ1 TG1 2 IRQ0 TG0 1 IRQ0 TG1 0 IRQ0 TG0 EIRQ4 EIRQ3 EIRQ2 EIRQ1 EIRQ0 00: An Interrupt occurs at low level 01: An interrupt occurs at high level 10: An interrupt occurs at negative edge 11: An interrupt occurs at pogitive edge 3-2-2 NMI Interrupts This series supports a NMI interrupt. The NMI interrupt occurs on the negative edge of NMI pin. An NMI interrupt occurs when the CPU is in the bus release state or the handshake access is in wait state. 58 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 3 Interrupts MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 59 Chapter 3 Interrupts 3-3 Interrupt Setup Examples 3-3-1 External Pin Interrupt Setup An interrupt occurs on the negative edge from the external interrupt pin IRQ0 (PA0). The external interrupt edge specification register (EXTMD) sets the interrupt request at low level after reset release, and the IRQ0IR bit of the maskable interrupt control register 1 (G1ICR) becomes 0. s Interrupt Enable Setup (1) Set the interrupt conditions of the interrupt pin IRQ0 (PA0). Set the IRQ0TG of the EXTMD register to 2. (Bit Setting: 10) EXTMD: x'00FC50' 15 -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 8 7 6 5 4 3 2 1 0 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 0 0 0 0 0 0 0 0 1 0 In this example, the interrupt level is 4. (2) Enable interrupts. At this point, clear all prior interrupt requests. To do this, set G1LV[2:0], IRQ0IR and IRQ0IE of the G1ICR register to an interrupt level, 0 and 1, respectively. G1ICR: x'00FC42' 15 -- -- 14 G1 LV2 1 13 G1 LV1 0 12 G1 LV0 0 11 -- -- 10 9 8 7 -- -- 6 5 4 3 -- -- 2 1 0 TM5 TM0 IRQ0 IE IE IE 0 0 1 TM5 TM0 IRQ0 IR IR IR 0 0 0 TM5 TM0 IRQ0 ID ID ID 0 0 0 (3) Enable interrupts by setting the interrupt enable flag (IE) of the processor status Word (PSW) to 1 and the interrupt mask level (IMn) to 7 (bit setting:111). 60 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 3 Interrupts Thereafter, an interrupt occurs on the negative edge of the interrupt pin IRQ0 (PA0). The program branches to x'080008' when the interrupt accepted. Normally, the program generates the interrupt start address and branches to that address. s Interrupt Service Routine (4) Specify the interrupt group by reading the interrupt accept group register (IAGR) during interrupt preprocessing. (5) Specify the interrupt vector in the group by reading the G1ICR register. Check the IRQ0ID with the bit test instruction (BTST). If IRQ0ID is 1, execute the interrupt service routine. (6) Clear the IRQ0IR bit of the G1ICR register. (7) Return to the main program with the interrupt return instruction (RTI) after the interrupt service routine ends. During interrupt service routine, the IM and IE of PSW become the interrupt level and 0 respectively. The multiple interrupts are not allowed. It means that other interrupts except the nonmaskable interrupt are not accepted during interrupt service routine unless the PSW is set. PA0(IRQ0) EXTMD IRQ0IE IRQ0IR Interrupt Service Routine Registers [R/W] Procedure EXTMD(W) G1ICR(R) (1) (2) G1ICR(R/W) (3)(4)(5)(6)(7) G1ICR(R/W) (4)(5)(6)(7) Low Level Negative Edge Figure 3-3-1 External Pin Interrupt Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 61 Chapter 3 Interrupts 3-3-2 Watchdog Timer Interrupt An interrupt occurs by using the watchdog timer. Set the WDRST flag of the CPU mode control register (CPUM) to enable (`0') after reset. This starts the watchdog timer. A nonmaskable interrupt occurs when the watchdog counter overflows. Because of this, the watchdog timer needs to be cleared during the main program. s Interrupt Enable Setup (1) Enable interrupts by setting the interrupt enable flag (IE) of the processor status Word (PSW) to 1 and the interrupt mask level (IMn) to 7 (bit setting:111). (2) Clear the WDRST flag of the CPUM register. This starts the watchdog timer. When the watchdog timer counts 65536 cycles of SYSCLK (6.5536 ms with a 20-MHz oscillator), a watchdog interrupt occurs. CPUM: x'00FC00' 15 WD RST 0 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 3 2 1 0 OSC STOP HALT OSC1 OSC0 ID 0 0 0 0 0 s Watchdog Timer Clear Normally, clear the watchdog timer before an interrypt occurs. (3) Set the WDRST flag of the CPUM register to 1 and then immediately clear to 0. The watchdog timer clears to 0 when the WDRST flag is 1. Normally, the program generates the interrupt start address and branches to that address. s Interrupt Service Routine The program branches to x'080008' when an interrupt is generated and accepted. (4) Specify the interrupt group by reading the interrupt accept group register (IAGR) during interrupt preprocessing. (5) Verify a watchdog interrupt by reading the nonmaskable interrupt control register (G0ICR). Check the WDIF with the bit test instruction (BTST). If WDIF is 1, execute the interrupt service routine. The IM of PSW becomes the highest level during interrupt service routine and other interrupts are not accepted. 62 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 3 Interrupts (6) Clear the WDIR flag of the G0ICR register. (7) Return to the main program with the interrupt return instruction (RTI) after the interrupt service routine ends. The watchdog timer and the oscillation stabilization wait counter are shared. The watchdog timer functions as the oscillation stabilization wait counter when the CPU returns from the STOP mode. Because of this, the WDIF flag is cleared to 0 when the CPU move to the STOP mode. The WDIF flag cleared to 0 again after the CPU moves to the normal mode. [See "2-6 Standby Function" in the MN10200 Series LSI User's Manual Linear Addressing Version.] Overflow RST Pin Clear WD Count WDRST(CPUM) WDIF(G0ICR) Interrupt Service Routine Registers [R/W] Procedure (1) CPUM(W) (2) CPUM(W) (3) CPUM(W) (3) G0ICR(R/W) (4)(5)(6)(7) Figure 3-3-2 Watchdog Interrupt Timing The watchdog interrupt does not occur when the chip is in bus release. The watchdog interrupt occurs when the chip waits for the handshake access. When a watchdog interrupt is accepted during wait for the handshake access, the watchdog interrupt occurs by suspending the bus cycle during the wait state. Therefore, the bus cycle operation is not guaranteed when the watchdog interrupt occurs during the wait. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 63 Chapter 3 Interrupts 64 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 Chapter 4 Timers 4 5 6 7 8 9 Chapter 4 Timers 4-1 Timers 4-1-1 Overview This LSI series contains six 8-bit timers (timer 0 to timer 5) and two 16-bit timers (timer 6 and timer 7). Table 4-1-1 Timer Function (1/2) Timer Function Interrupt Request Destination Timer 0 Group 1 (G1ICR) * TM0IR Timer 1 Group 2 (G2ICR) * TM1IR 8-bit Timer Timer 2 Group 3 (G3ICR) * TM2IR Timer 3 Group 4 (G4ICR) * TM3IR Interrupt Source Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Clock Source * TM0IO pin * /128(*1) * (*2) * fxi/4(*3) * TM1IO pin * fxi/4 * Timer 0 * * TM2IO pin * Timer 1 * Timer 0 * * TM3IO pin * Timer 2 * Timer 0 * Counting Method Interval Timer Event Counter Timer Output PWM Two-phase Timer Output One-shot Pulse Output One-phase Capture Input Two-phase Capture Input Two-phase Encoder External Count Direction Control External Count Reset Control Serial Interface Transfer Clock Generation A/D Conversion Timing Generation Down counting -- -- -- -- -- -- -- -- -- -- Down counting -- -- -- -- -- -- -- -- -- Down counting -- -- -- -- -- -- -- -- -- Down counting -- -- -- -- -- -- -- -- -- 66 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers Table 4-1-1 Timer Function (2/2) Timer Function Interrupt Request Destination Timer 4 Group 5 (G5ICR) * TM4IR Timer 5 Group 1 (G1ICR) * TM5IR 8-bit Timer Timer 6 Group 6 (G6ICR) * TM6UIR * TM6AIR * TM6BIR Timer 6 underflow Timer 6 compare A or capture A match Timer 6 compare B or capture B match * SYSCLK * Timer 4 * Timer 5 * TM6IOB pin * Two-phase encoder Up/Down counting Arbitrary duty 4x, 1x -- -- Timer 7 Group 7 (G7ICR) * TM7UIR * TM7AIR * TM7BIR Timer 7 underflow Timer 7 compare A or capture A match Timer 7 compare B or capture B match * SYSCLK * Timer 4 * Timer 5 * TM7IOB pin * Two-phase encoder Up/Down counting Arbitrary duty 4x, 1x -- -- Interrupt Source Timer 4 underflow Timer 5 underflow Clock Source * TM4IO pin * Timer 3 * Timer 0 * fxi/4 * TM5IO pin * Timer 4 * Timer 0 * fxi/4 Counting Method Interval Timer Event Counter Timer Output PWM Two-phase Timer Output One-shot Pulse Output One-phase Capture Input Two-phase Capture Input Two-phase Encoder External Count Direction Control External Count Reset Control Serial Interface Transfer Clock Generation A/D Conversion Timing Generation Down counting -- -- -- -- -- -- -- -- -- -- Down counting -- -- -- -- -- -- -- -- -- -- *1 System Clock (10 MHz with a 20-MHz ocillator)/128 *2 System Clock (10 MHz with a 20-MHz ocillator) *3 Low-speed Clock (32 kHz)/4 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 67 Chapter 4 Timers TMnBC Value TMnBR Value Time TMnIO (Input) Figure 4-1-1 Event Counter Timing (Timer 0 to Timer 5) TMnBC Value TMnBR Value Time Interrupts TMnIO (Output) Figure 4-1-2 Timer Output, Interval Timer Timing (Timer 0 to Timer 5) TMnBC Value TMnCA TMnCB Time TMnIOA (Output) Figure 4-1-3 PWM Output Timing (Timer 6 and Timer 7) 68 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers TMnBC Value TMnCA TMnCB Rewrite the TMnCB value Keep in the current cycle Reflect the result from the next cycle Time TMnIOA (Output) Figure 4-1-4 PWM Output Timing (Data Write) (Timer 6 and Timer 7) TMnBC Value TMnCA TMnCB Time TMnOA (Output) TMnOB (Output) Figure 4-1-5 Two-phase Timer Output Timing (Timer 6 and Timer 7) TMnBC Value TMnCA Time TMnIB (Input) TMnOA (Output) Figure 4-1-6 One-shot Pulse Output Timing (Timer6 and Timer 7) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 69 Chapter 4 Timers TMnBC Value FFFF Time TMnIB (Input) TMnIA (Input) TMnCA (Register value) 0033 (Example) 5A87(Example) TMnCB (Register value) Figure 4-1-7 One-phase Capture Input Timing (Timer6 and Timer 7) TMnBC Value FFFF Time TMnIB (Input) TMnIA (Input) TMnCA TMnCB 0033(Example) 5A87(Example) Figure 4-1-8 Two-phase Capture Input Timing (Timer 6 and Timer 7) TMnBC Value Time TMnIA (Input) TMnIB (Input) Figure 4-1-9 Two-phase Encoder (4x) Timing 70 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers TMnBC Value Time TMnIA (Input) TMnIB (Input) Figure 4-1-10 Two-phase Encoder (1x) Timing (Timer 6 and Timer 7) TMnBC Value Time TMnIB (Input) TMnIA (Input) Figure 4-1-11 External Count Direction Control Timing (Timer 6 and Timer 7) TMnBC Value TMnCA Time TMnIA TMnIB (Input) TMnIC (Input) Figure 4-1-12 External Count Reset Control (Two-phase Encoder) Timing (Timer 6 and Timer 7) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 71 Chapter 4 Timers Timer 1 to timer 5 can cascade. For example, cascading timer 1 and timer 2 can form as a 16-bit timer. cascading timer 3, timer 4 and timer 5 can form as a 24-bit timer. Cascading these timers can form a 40bit timer at most. s Timer 0 to Timer 5 Timer 0 to Timer 5 are 8-bit timers. They are down counting and are divided by the 8-bit value set in the base register (TMnBR) plus one. (Do not set 0 to TMnBR). An interrupt occurs when each timer underflows (the binary counter changes from x'00' to the 8-bit value). They can function as interval timers, event counters, clock output, base clock for serial interface and A/D conversion start timing. s Timer 6 and Timer 7 Timer 6 and Timer 7 are 16-bit timers. They are up/down counting. Each timer has two compare/capture registers (TMnCA and TMnCB). These registers capture and compare the up/down counter value, generate PWM and interrupts. The PWM contains the double buffer mode that changes the cycle and transition from the next cycle. This prevents the PWM waveform losses and distorts during timing changes. These timers can function as interval timers, event counters (at clock oscillation), one-phase PWM, two-phase PWM, two capture input, dual two-phase encoders, one-shot pulse generators and external count direction controllers. An underflow interrupt occurs only when these timers are down counting. 72 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers Figure 4-1-13 shows the timer configuration. Combining timers serves as various interval timers. 8-bit Timer Timer 2 (Divided by 2 to 256) 8-bit Timer Timer 0 (Divided by 2 to 256) 8-bit Timer Timer 1 (Divided by 2 to 256) 16-bit Timer Timer 3 Timer 4 (Divided by 2 to 65536) Clock Synchronous Serial SYSCLK (10 MHz) Timer Output Long-term Interval Timer fxi/4 (8 kHz) 8-bit Timer Timer 5 (Divided by 2 to 256) Clock Figure 4-1-13 Timer Configuration Each timer n (n=2 to 5) cascade inputs cascade output of timer n-1. Therefore, timer does not function as a 8-bit counter but it functions as a 16-bit counter. SYSCLK is a signal of dividing the clock from OSCI pin by 2 (10 MHz with a 20-MHz oscillator) during normal mode or HALT0 mode. SYSCLK becomes a signal of dividing the clock from XI pin by 2 (16 kHz with a 32-kHz oscillator) during SLOW mode or HALT1 mode. SYSCLK stops during STOP0 mode or STOP1 mode. SYSCLK outputs to the external SYSCLK pin. The fxi/4 means a signal of dividing the clock from XI pin by 4 (18 kHz with a 32kHz oscillator) during modes except STOP0 and STOP1 modes. The fxi/4 stops during STOP0 or STOP1 mode. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 73 Chapter 4 Timers 4-1-2 Control Registers The following table shows timer control registers. Table 4-1-2 List of Timer Control Registers Register Timer 0 TM0MD TM0BC TM0BR TM1MD TM1BC TM1BR TM2MD TM2BC TM2BR TM3MD TM3BC TM3BR TM4MD TM4BC TM4BR TM5MD TM5BC TM5BR TM6MD TM6BC TM6CA TM6CAX TM6CB TM6CBX TM7MD TM7BC TM7CA TM7CAX TM7CB TM7CBX Address x'00FE20' x'00FE00' x'00FE10' x'00FE21' x'00FE01' x'00FE11' x'00FE22' x'00FE02' x'00FE12' x'00FE23' x'00FE03' x'00FE13' x'00FE24' x'00FE04' x'00FE14' x'00FE25' x'00FE05' x'00FE15' x'00FE30' x'00FE32' x'00FE34' x'00FE36' x'00FE38' x'00FE3A' x'00FE40' x'00FE42' x'00FE44' x'00FE46' x'00FE48' x'00FE4A' R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R R/W R/W Function Timer 0 Mode Register Timer 0 Binary Counter Timer 0 Base Register Timer 1 Mode Register Timer 1 Binary Counter Timer 1 Base Register Timer 2 Mode Register Timer 2 Binary Counter Timer 2 Base Register Timer 3 Mode Register Timer 3 Binary Counter Timer 3 Base Register Timer 4 Mode Register Timer 4 Binary Counter Timer 4 Base Register Timer 5 Mode Register Timer 5 Binary Counter Timer 5 Base Register Timer 6 Mode Register Timer 6 Binary Counter Timer 6 Compare/Capture Register A Timer 6 Compare/Capture Register Set A Timer 6 Compare/Capture Register B Timer 6 Compare/Capture Register Set B Timer 7 Mode Register Timer 7 Binary Counter Timer 7 Compare/Capture Register A Timer 7 Compare/Capture Register Set A Timer 7 Compare/Capture Register B Timer 7 Compare/Capture Register Set B Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 T h e T M 6 C A X r e g i s t e r, t h e TM6CBX register, the TM7CAX register and the TM7CBX register are dummy registers to specify the double buffer mode when the PWM is output. Timer 6 Timer 7 74 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers 4-1-3 Timer Block Diagram This section describes block diagrams of timer 0 to timer 7. Data Bus 8 8 (x'00FE10') 8 Timer 0 Base Register TM0BR Load (x'00FE20') Reload 8 (x'00FE00') TM0IO pin SYSCLK/128 SYSCLK Low-speed clock/4 Low-speed Clock/4 Timer 0 SYSCLK TM0EN TM0LD TM0S1 TM0S0 Timer 0 Binary Counter TM0BC Count Underflow Interrupt Controller TM0MD Clock Source for Timer1 to Timer 5 Reset 0 1 2 3 Selector 1/2 TM0IO pin Figure 4-1-14 Timer 0 Block Diagram Data Bus 8 8 (x'00FE11') 8 Timer 1 Base Register TM1BR Load (x'00FE21') Reload 8 (x'00FE01') A/D Conversion Controller Interrupt Controller TM1EN TM1IO pin TM1LD TM1S1 TM1S0 Timer 1 Binary Counter TM1BC Underflow Count TM1MD Timer 1 cascade signal Reset 0 1 2 3 Selector 1/2 TM1IO pin Figure 4-1-15 Timer 1 Block Diagram MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 75 Chapter 4 Timers Data Bus 8 8 (x'00FE12') 8 Timer 2 Base Register TM2BR Load (x'00FE22') Reload 8 (x'00FE02') Serial I/F Controller Interrupt Controller TM3IO pin Timer 2 cascade Timer 0 SYSCLK TM2EN TM2IO pin Timer 1 cascade Timer 0 SYSCLK TM2LD TM2S0 TM2S1 Timer 2 Binary Counter TM2BC Underflow Count TM2MD Timer 2 cascade signal Reset 0 1 2 3 Selector 1/2 TM2IO pin Figure 4-1-16 Timer 2 Block Diagram Data Bus 8 8 (x'00FE13') 8 Timer 3 Base Register TM3BR Load (x'00FE23') Reload 8 (x'00FE03') Serial I/F Controller Interrupt Controller TM3EN TM3S1 TM3S0 TM3LD Timer 3 Binary Counter TM3BC Count Underflow TM3MD Timer 3 cascade signal Reset 0 1 2 3 Selector 1/2 TM3IO pin Figure 4-1-17 Timer 3 Block Diagram 76 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers Data Bus 8 8 (x'00FE14') 8 Timer 4 Base Register TM4BR Load (x'00FE24') TM4S0 TM4EN TM4LD TM4S1 Reload (x'00FE04') Timer 4 Binary Counter TM4BC Count Underflow Interrupt Controller TM4MD Timer 4 cascade signal Reset TM4IO pin Timer 3 cascade Timer 0 Low-speed Clock/4 1/2 TM4IO pin 0 1 2 3 Selector Figure 4-1-18 Timer 4 Block Diagram Data Bus 8 8 (x'00FE15') 8 Timer 5 Base Register TM5BR Load (x'00FE25') TM5EN TM5LD TM5S1 TM5S0 Reload 8 (x'00FE05') Timer 5 Binary Counter TM5BC Count Underflow Interrupt Controller TM5MD Reset TM5IO pin (P30) Timer 4 cascade Timer 0 Low-speed Clock/4 1/2 TM5IO pin (P30) 0 1 2 3 Selector Figure 4-1-19 Timer 5 Block Diagram MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 77 Chapter 4 Timers TM6IC Timer 4 Timer 5 SYSCLK Clear [ECLR] [S] Selector [EN] U/D Control [UD] TM6BC(x'00FE32') Load (When TM6BC=0) [LP] [ASEL] TM6CA(x'00FE34') TM6IOB TM6IOA Capture Control T R Q Selector TM6CAX (x'00FE36') TM6IOA R Q SR Q R Capture TM6CB(x'00FE38') Match TM6CBX (x'00FE3A') T TM6IOB [MD] [NLD] [ONE] [TGE] TM6MD(x'00FE30') Figure 4-1-20 Timer 6 Block Diagram TM7IC Timer 4 Timer 5 SYSCLK Clear [ECLR] Selector [EN] U/D Control [UD] TM7BC(x'00FE42') Load (When TM7BC=0) [LP] [ASEL] [S] TM7CA(x'00FE44') TM7IOB TM7IOA Capture Control T R Q Selector TM7CAX (x'00FE46') TM7IOA Q R SR Match Capture TM7CB(x'00FE48') TM7CBX (x'00FE4A') T R Q TM7IOB [MD] [NLD] [ONE] [TGE] TM7MD (x'00FE40') Figure 4-1-21 Timer 7 Block Diagram 78 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 79 Chapter 4 Timers 4-2 8-bit Timer Setup Examples 4-2-1 Event Counter Using 8-bit Timer The event counter setup procedures for Timer 0 to Timer 5 are the same. In this example, timer 2 counts the rising edge of the TM2IO pin input four times and generates an interrupt at underflow. (1) Set the interrupt enable flag (IE) of the processor status word (PSW) to 1. This verification is unnecessary immediately after a reset. (2) Verify that counting is stopped using the timer 2 mode register (TM2MD). TM2MD: x'00FE22' 7 6 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 TM2 TM2 EN LD 0 0 TM2 TM2 S1 S0 0 0 (3) Enable interrupts. At the same time, clear all prior interrupt requests. Set G3LV[2:0] bits of the maskable interrupt control register 3 (G3ICR) to the interrupt level of 6 to 0, TM2IR and TM2IE to 0 and 1, respectively. For example, write x'4200' to the G3ICR register. Thereafter, an interrupt occurs when timer 2 underflows. G3ICR: x'00FC46' 15 -- 14 G3 LV2 1 13 G3 LV1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 1 0 0 0 0 0 0 0 0 0 -- 80 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (4) Set the timer divisor. Since timer 2 divides the TM2IO pin by 4, set the timer 2 base register (TM2BR) to 3. (The valid range for TM2BR is 1 to 255.) TM2BR: x'00FE12' 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BR7 0 BR6 0 BR5 0 BR4 0 BR3 0 BR2 0 BR1 1 BR0 1 (5) Load the TM2BR value to the TM2BC register. To do this, set TM2LD and TM2EN of the TM2MD register to 1 and 0 respectively. At the same time, select the clock source. Set TM2S[1:0] to 00. (6) Set both TM2LD and TM2EN of the TM2MD register to 0. If this setting is omitted, the timer 2 binary counter may not start at the first cycle. (7) Set both TM2LD and TM2EN to 0. This starts timer 2. Counting starts at the beginning of the next cycle. Changing the clock source while controlling count operation will corrupt the binary counter value. When the timer 2 binary counter value reaches 0 and loads the value of 3 from the timer 2 base register (TM2BR), a timer 2 underflow interrupt request occurs. Interrupt Enable TM2BR TM2BC Timer 2 Underflow Interrupt 00 00 03 03 02 01 00 03 TM2IO TM2MD(W) G3ICR(W) TM2BR(W) TM2MD(W) TM2MD(W) TM2MD(W) Procedure (2) (3) (4) (5) (6) (7) Figure 4-2-1 Event Counter Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 81 Chapter 4 Timers 4-2-2 Clock Output Using 8-bit Timer Timer 0 to timer 5 contain clock output functions. The setup procedures for timer 0 to timer 5 are same. In this example, timer 0 and timer 1 output 12 clock cycles (SYSCLK/6). 8-bit Timer SYSCLK (10 MHz) Timer 0 (Divided by 2) 8-bit Timer Timer 1 (Divided by 3) Clock Output Figure 4-2-2 Clock Output Configuration (1) This verification is unnecessary immediately after a reset. s Timer 0 Setup (1) Verify that timer 0 counting is stopped using the timer 0 mode register (TM0MD). TM0MD: x'00FE20' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 TM0 TM0 EN LD 0 1 TM0 TM0 S1 S0 1 0 (2) Set the timer 0 divisor. Since timer 0 divides SYSCLK by 2, set the timer 0 base register (TM0BR) to 1. (The valid range for TM0BR is 1 to 255.) If setting 1 of divisor, write the dummy value (for example, x'0F') once. TM0BR: x'00FE10' 7 6 5 4 3 2 1 0 TM0 TM0 TM0 TM0 TM0 TM0 TM0 TM0 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 0 0 0 0 0 0 1 (3) Load the TM0BR value to TM0BC. To do this, set TM0LD and TM0EN to 1 and 0 resepctively. TM0MD: x'00FE20' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 TM0 TM0 EN LD 0 1 TM0 TM0 S1 S0 1 0 82 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (4) Set both TM0LD and TM0EN of the TM0MD register to 0. If this setting is omitted, the timer 0 binary counter may not start at the first cycle. (5) Set TM0LD and TM0EN to 0 and 1 respectively. This starts timer 0. Counting starts at the beginning of the next cycle. When the timer 0 binary counter value reaches 0 and loads the value of 1 from the timer 0 base register (TM0BR), a timer 0 underflow interrupt request occurs. s Pin Setup (6) Select the TM1IO pin to output using the port 8 I/O control register (P8DIR) and the port 8 output mode register (P8MD). (The set value is 2.) P8DIR: x'00FFE8' 7 6 5 4 3 2 1 0 If selecting 1 of divisor, set 0 to the timer 0 base register (TM0BR) once again after step (5). The first count is the value set in step (2), but the second count becomes 1. For example, if 0 is set to TM0BR in step (2), the first count is 257 and the second count becomes 1. P8MD: x'00FFF8' 7 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 0 0 0 0 0 0 1 0 P8 P8 P8 P8 P8 P8 P8 P8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 0 0 0 0 0 0 1 0 s Timer 1 Setup (7) Verify that timer 1 counting is stopped using the timer 1 mode register (TM1MD). This verification is unnecessary immediately after a reset. TM1MD: x'00FE21' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 TM1 TM1 EN LD 0 0 TM1 TM1 S1 S0 1 0 (8) Set the timer 1 divisor. Since timer 1 divides timer 0 output by 3, set the timer 1 base register (TM1BR) to 2. (The valid range for TM0BR is 1 to 255.) TM1BR: x'00FE11' 7 6 5 4 3 2 1 0 TM1 TM1 TM1 TM1 TM1 TM1 TM1 TM1 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 0 0 0 0 0 1 0 (9) Load the TM1BR value to TM1BC. To do this, set TM1LD and TM1EN to 1 and 0 resepctively. At the same time, select the clock source. Changing the clock source while controlling count operation will corrupt the binary counter value. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 83 Chapter 4 Timers (10) Set both TM1LD and TM1EN of the TM1MD register to 0. If this setting is omitted, the timer 0 binary counter may not start at the first cycle. (11) Set TM1LD and TM1EN to 0 and 1 respectively. This starts timer 1. Counting starts at the beginning of the next cycle. When the TM1BC value reaches 0, TM1IO output is inverted as soon as the value of 2 from the timer 1 base register (TM1BR) is loaded. Immediately after TM1BC starts counting, the TM1IO output pin outputs 0. The TM1IO output pin outputs 1 at the beginning of the next cycle when TM1BC becomes 0. Then the TM1IO output pin outputs 0 again at the beginning of the next cycle. This repeated operation results in 12 clock cycles. SYSCLK TM0BR TM0BC TM0 Output TM1BR TM1BC TM1IO Output Procedure (1) (2) (3) (4) (5)(6)(7)(8) (9) (10)(11) 00 00 02 01 00 02 02 01 00 02 00 00 01 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 Figure 4-2-3 Clock Output Timing 84 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers 4-2-3 Interval Timer Using 8-bit Timer The interval timer setup procedures for timer 0 to timer 5 are same. In this example, timer 0, timer 2 and timer 3 generate an interrupt at regular intervals (1 second). (To divide SYSCLK by 10,000,000, timer 0 divides SYSCLK by 250 and timer 2 and timer 3 divide SYSCLK by 40,000.) 8-bit Timer SYSCLK (10 MHz) Timer 0 16-bit Timer Timer 2 Timer 3 (Divided by 40000) Interrupt Request (Divided by 250) Figure 4-2-4 Clock Output Configuration (2) (1) Set the interrupt enable flag (IE) of the processor status word (PSW) to 1. (2) Enable interrupts. At the same time, clear all prior interrupt requests. Set G4LV[2:0] bits of the maskable interrupt control register 4 (G4ICR) to the interrupt level of 6 to 0, TM3IR and TM3IE to 0 and 1, respectively. For example, write x'4200' to the G4ICR register. Thereafter, an interrupt occurs when timer 3 underflows. G4ICR: x'00FC48' 15 -- 14 G4 LV2 1 13 G4 LV1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 G4 SC1R SC1T TM3 IRQ3 SC1R SC1T TM3 IRQ3 SC1R SC1T TM3 IRQ3 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 1 0 0 0 0 0 0 0 0 0 -- s Timer 0 Setup (3) Verify that timer 0 counting is stopped using the timer 0 mode register (TM0MD). TM0MD: x'00FE20' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 This verification is unnecessary immediately after a reset. TM0 TM0 EN LD 0 0 TM0 TM0 S1 S0 1 0 (2) Set the timer 0 divisor. Since timer 0 divides SYSCLK by 250, set the timer 0 base register (TM0BR) to 249. (The valid range for TM0BR is 1 to 255.) TM0BR: x'00FE10' 7 6 5 4 3 2 1 0 If setting 1 of divisor, write the dummy value (for example, x'0F') once. TM0 TM0 TM0 TM0 TM0 TM0 TM0 TM0 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 1 1 1 1 1 0 0 1 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 85 Chapter 4 Timers (5) Load the TM0BR value to TM0BC. To do this, set TM0LD and TM0EN to 1 and 0 resepctively. TM0MD: x'00FE20' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 TM0 TM0 EN LD 0 0 TM0 TM0 S1 1 S0 0 (6) Set both TM0LD and TM0EN of the TM0MD register to 0. If this setting is omitted, the timer 0 binary counter may not start at the first cycle. If selecting 1 of divisor, set 0 to the timer 0 base register (TM0BR) once again after step (7). The first count is the value set in step (4), but the second count becomes 1. For example, if 0 is set to TM0BR in step (4), the first count is 257 and the second count becomes 1. (7) Set TM0LD and TM0EN to 0 and 1 respectively. This starts timer 0. Counting starts at the beginning of the next cycle. When the timer 0 binary counter (TM0BC) reaches 0 and loads the value of 1 from the timer 0 base register (TM0BR), a timer 0 underflow interrupt request occurs. This verification is unnecessary immediately after a reset. s Timer 2 and Timer 3 Setup (8) Verify that counting is stopped using the timer 2 mode register (TM2MD) and the timer 3 mode register (TM3MD). TM2MD: x'00FE22' 7 6 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 TM3MD: x'00FE23' 7 6 5 -- 4 -- 3 -- 2 -- 1 0 TM2 TM2 EN LD 0 0 TM2 TM2 S1 S0 0 0 TM3 TM3 EN LD 0 0 TM3 TM3 S1 S0 0 1 (9) Set the timer divisor. Since the divisor is 40000 (x'9C40'), set the timer 2 base register (TM2BR) and the timer 3 base register (TM3BR) to x'3F' and x'9C'. (The valid range is 1 to 255.) TM2BR: x'00FE12' 7 6 5 4 3 2 1 0 TM3BR: x'00FE13' 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 0 1 1 1 1 1 1 TM3 TM3 TM3 TM3 TM3 TM3 TM3 TM3 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 1 0 0 1 1 1 0 0 Changing the clock source while controlling count operation will corrupt the binary counter value. (10) Load the TM2BR value to TM2BC and the TM3BR to TM3BC. To do this, set both TM2LD and TM3LD to 1, and both TM2EN and TM3EN to 0. At the same time, select the clock sources. (Select timer 0 for the timer 2 clock source and timer 2 cascade for the timer 3 clock source.) 86 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (11) Set both TM2LD and TM3LD to 0, and both TM2EN and TM3EN to 0. If this setting is omitted, the binary counter may not start at the first cycle. (12) Set TM2LD and TM3LD to 0, and TM2EN and TM3EN to 1. This starts the timer. Counting starts at the beginning of the next cycle. When the TM2BC value and the TM3BC value reache 0, a timer 3 underflow interrupt request occurs as soon as the TM2BR value x'3F' and the TM3BR value x'9C' are loaded. SYSCLK TM0BR TM0BC TM0 Output TM2BR TM2BC Timer 2 Cascade Signal TM3BR TM3BC 00 00 9C 9C 9C 9B 01 00 00 9C 00 00 3F 00 FF 3F 00 FF 00 3F 02 00 00 F9 F9 F8 F7 F6 F5 F4 F3 00 F9 F8 F7 00 F9 F8 00 F9 F8 F7 Procedure (1)(2)(3)(4) (5) (6) (7) (8) (9)(10)(11) (12) Figure 4-2-5 Interval Timer Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 87 Chapter 4 Timers 4-3 16-bit Timer Setup Examples 4-3-1 Event Counter Using 16-bit Timer The event counter setup procedures for Timer 6 and Timer 7 are same except the up/down counting selection. In this example, timer 6 counts TM6IOB pin input (SYSCLK/2 or less, 5 MHz or less with a 20-MHz oscillaor) and generates an interrupt on the second cycle and fifth cycle. s Interrupt Enable Setup (1) Enable interrupts. At the same time, clear all prior interrupt requests. Set G6LV[2:0] bits of the G6ICR to the interrupt level of 6 to 0, TM6AIR and TM6BIR to 0, and TM6AIE and TM6BIE to 1. For example, write x'4600' to the G6ICR register. Thereafter, an interrupt occurs when the timer 6 capture A and the timer 6 capture B occur. s Timer 6 Setup (2) Set the operating mode to the timer 6 mode register (TM6MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Select TM6IOB as the timer 6 clock source. TM6MD: x'00FE30' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 Use the MOV instruction to set the data and always use 16-bit write operations. Stop TM6BC counting and initialize (clear) TM6BC and RS.F.F. TM6 TM6 EN NLD 0 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 (3) Set the timer 6 divisor. Since timer 6 divides TM6IOB pin input by 5, set 4 to the timer 6 compare/capture register A (TM6CA). (The valid range for TM6CA is 1 to x'FFFE'.) TM6CA: x'00FE34' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 In the single buffer mode, both TM6CA and TM6CB are compared to TM6BC. The TM6CB value is set to `-1' by writing x'FFFF' to TM6CB. When TM6CB is not compared to TM6BC, the TM6CB value is set to `-1'. (4) Set the phase difference for timer 6. Since the phase difference is 2 cycles, set 1 to the timer 6 compare/capture register B (TM6CB). (The valid range for TM6CB is -1 TM6CB < TM6CA.) TM6CB: x'00FE38' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 88 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (5) Set TM6NLD and TM6EN of the timer 6 mode register (TM6MD) to 1 and 0 respectively. This enables TM6BC, T.F.F and RS.F.F. TM6MD: x'00FE30' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 EN NLD 0 1 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 (6) Set both TM6NLD and TM6EN to 1. This starts the timer 6. Counting starts at the beginning of the next cycle. When SYSCLK operates (in normal and halt modes), the external TM6IOB input is sampled on SYSCLK. When SYSCLK stops (in STOP mode), TM6BC counts on the TM6IOB input. Select the oscillation clock/4 (5 MHz with a 20-MHz oscillator) or less as the event counter clock. Figure 4-3-1 shows the example of generating an interrupt during up counting. If this step is omitted, TM6BC may not count during the first cycle. Do not change other bits in the TM6MD register at the same time. TM6CA TM6CB TM6BC TM6IOB B Interrupts 0000 0004 0001 0001 0002 0003 0004 0000 0001 0002 0003 0004 A B A Figure 4-3-1 Event Counter Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 89 Chapter 4 Timers 4-3-2 PWM Output Using 16-bit Timer The PWM output setup procedures for Timer 6 and Timer 7 are same except the up/down counting selection. In this example, timer 6 divides SYSCLK by 5 and outputs PWM signal on the fifth cycle. The duty is 2:3. Therefore, set the divisor of 5 (the set value is `4') to the timer 6 compare/capture register A and the cycle of 2 (the set value is `1') to the timer 6 compare/ capture B. s Pin Setup (1) Set the TM6IOA pin to output using the port 8 I/O control register (P8DIR) and the port 8 output mode register (P8MD). P8DIR: x'00FFE8' 7 6 5 4 3 2 1 0 P8MD: x'00FFF8' 7 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 0 1 0 0 0 0 0 0 P8 P8 P8 P8 P8 P8 P8 P8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 0 1 0 0 0 0 0 0 Use the MOV instruction to set the data and always use 16-bit write operations. Stop TM6BC counting and initialize (clear) TM6BC and RS.F.F. s Timer 6 Setup (2) Set the operating mode to the timer 6 mode register (TM6MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Select SYSCLK as the timer 6 clock source. Select the double buffer operating mode. TM6MD: x'00FE30' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 EN NLD 0 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 1 (3) Set the timer 6 divisor. Since timer 6 divides SYSCLK by 5, set 4 to the timer 6 compare/capture register A (TM6CA). (The valid range for TM6CA is 1 to x'FFFE'.) TM6CA: x'00FE34' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 90 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (4) Set the timer 6 duty. Since the duty is 2/5 of SYSCLK, set 1 to the timer 6 compare/capture register B (TM6CB). (The valid range for TM6CB is -1 TM6CB < TM6CA.) TM6CB: x'00FE38' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The TM6CB value is set to `-1' by writing x'FFFF' to TM6CB. When TM6CB is not compared to TM6BC, the TM6CB value is set to `-1'. TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (5) In the double buffer mode, compare TM6BC to TM6CAX. The TM6CAX is updated when TM6CAX = TM6BC, so that TM6CAX remains x'0000' before TM6BC starts counting. Therefore, to load the TM6CA value to TM6CAX, write the dummy data to TM6CAX. (The dummy data can be any values.) TM6CAX: x'00FE36' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6CAX and TM6CBX are valid only when the timer 6 compare/capture register is set to double buffer mode. TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CAX15 CAX14 CAX13 CAX12 CAX11 CAX10 CAX9 CAX8 CAX7 CAX6 CAX5 CAX4 CAX3 CAX2 CAX1 CAX0 (6) In the double buffer mode, compare TM6BC to TM6CBX. The TM6CBX is updated when TM6CBX = TM6BC, so that TM6CBX remains x'0000' before TM6BC starts counting. Therefore, to load the TM6CA value to TM6CBX, write the dummy data to TM6CBX. (The dummy data can be any values.) TM6CBX: x'00FE3A' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CBX15 CBX14 CBX13 CBX12 CBX11 CBX10 CBX9 CBX8 CBX7 CBX6 CBX5 CBX4 CBX3 CBX2 CBX1 CBX0 The setup steps after step (6) are the same as steps (5) and (6) in "4-3-1 Event Counter Using 16-bit Timer". MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 91 Chapter 4 Timers TM6EN TM6BC SYSCLK TM6CA TM6CB TM6IOA B Interrupts A B A B 0004 0001 0 0 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 Figure 4-3-2 PWM Timing When timer n changes the duty of PWM output waveforms dynamically, the PWM output waveforms and interrupts may corrupt at the timing of changing the TMnCB value in the single buffer mode. In the double buffer mode, the corrupt of PWM output waveforms and interrupts does not occur at any timing of changing the TMnCB value. This corrupt does not occur even when the output waveforms consist of 1s and 0s. TMnEN TMnCB Write TMnBC SYSCLK CLRBC 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 TMnCB TMnCBX S R TMnIOA 3 3 1 1 B Interrupts A B A B A B Figure 4-3-3 PWM Timing in Double Buffer Mode 92 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers 4-3-3 Two-phase PWM Output Using 16-bit Timer The two-phase PWM output setup procedures for Timer 6 and Timer 7 are same except the up/down counting selection. In this example, timer 6 divides SYSCLK by 5 and outputs two-phase PWM signal on the fifth cycle. The phase difference is 2 cycles. Therefore, set the divisor of 5 (the set value is `4') to the timer 6 compare/capture register A and the cycle of 2 (the set value is `1') to the timer 6 compare/capture B. s Pin Setup (1) Set the TM6IOA pin to output using the port 8 I/O control register (P8DIR) and the port 8 output mode register (P8MD). P8DIR: x'00FFE8' 7 6 5 4 3 2 1 0 This verification is unnecessary immediately after a reset. P8MD: x'00FFF8' 7 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 1 1 0 0 0 0 0 0 P8 P8 P8 P8 P8 P8 P8 P8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 1 1 0 0 0 0 0 0 s Timer 6 Setup (2) Set the operating mode to the timer 6 mode register (TM6MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Select TM6IOB as the timer 6 clock source. TM6MD: x'00FE30' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 Use the MOV instruction to set the data and always use 16-bit write operations. Stop TM6BC counting and initialize (clear) TM6BC and RS.F.F. TM6 TM6 EN NLD 0 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 0 (3) Set the timer 6 divisor. Since timer 6 divides TM6IOB pin input by 5, set 4 to the timer 6 compare/capture register A (TM6CA). (The valid range for TM6CA is 1 to x'FFFE'.) TM6CA: x'00FE34' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 93 Chapter 4 Timers (4) Set the phase difference of timer 6. Since the phase difference is two cycles of prescaler 0, set 1 to the timer 6 compare/capture register B (TM6CB). (The valid range for TM6CB is -1 < TM6CB < TM6CA.) TM6CB: x'00FE38' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 TM6CAX and TM6CBX are valid only when the timer 6 compare/capture register is set to double buffer mode. (5) In the double buffer mode, compare TM6BC to TM6CAX. The TM6CAX is updated when TM6CAX = TM6BC, so that TM6CAX remains x'0000' before TM6BC starts counting. Therefore, to load the TM6CA value to TM6CAX, write the dummy data to TM6CAX. (The dummy data can be any values.) TM6CAX: x'00FE36' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CAX15 CAX14 CAX13 CAX12 CAX11 CAX10 CAX9 CAX8 CAX7 CAX6 CAX5 CAX4 CAX3 CAX2 CAX1 CAX0 (6) In the double buffer mode, compare TM6BC to TM6CBX. The TM6CBX is updated when TM6CBX = TM6BC, so that TM6CBX remains x'0000' before TM6BC starts counting. Therefore, to load the TM6CA value to TM6CBX, write the dummy data to TM6CBX. (The dummy data can be any values.) TM6CBX: x'00FE3A' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 CBX15 CBX14 CBX13 CBX12 CBX11 CBX10 CBX9 CBX8 CBX7 CBX6 CBX5 CBX4 CBX3 CBX2 CBX1 CBX0 The setup steps after step (6) are the same as steps (5) and (6) in "4-3-1 Event Counter Using 16-bit Timer". TM6EN TM6BC SYSCLK TM6CA TM6CB TM6IOA TM6IOB B Interrupts Figure 4-3-4 Two-phase PWM Timing 0 0 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 0004 0001 A B A B 94 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers When timer n changes the duty of PWM output waveforms dynamically, the PWM output waveforms and interrupts may corrupt at the timing of changing the TMnCB value in the single buffer mode. In the double buffer mode, the corrupt of PWM output waveforms and interrupts does not occur at any timing of changing the TMnCB value. This corrupt does not occur even when the output waveforms consist of 1s and 0s. TMnEN TMnCB Write TMnBC Clock Output CLRBC 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 TMnCB TMnCBX S R TMnIOA TMnIOB Interrupts 3 3 1 1 B A B A B A B Figure 4-3-5 Two-phase PWM Timing in Double Buffer Mode MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 95 Chapter 4 Timers 4-3-4 One-phase Capture Input Using 16-bit Timer The one-phase capture input setup procedures for timer 6 and timer 7 are same except the up/down counting selection. In this example, timer 7 divides SYSCLK by 65536 and measures how long the TM7IOA input is high. An interrupt occurs on the capture B and the width where the TM7IOA input is high is calculated by the instruction (TMnCB - TMnCA). Use the MOV instruction to set the data and always use 16-bit write operations. s Interrupt Enable Setup (1) Enable interrupts. At the same time, clear all prior interrupt requests. Set G7LV[2:0] bits of the G7ICR to the interrupt level of 6 to 0, TM7BIR 7 and TM7BIE to 0 and 1 respectively. For example, write x'4400' to the G7ICR register. Thereafter, an interrupt occurs when the timer 7 capture B occurs. Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. s Timer 7 Setup (2) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Set TM7LP to 0 to count the loop of 0 to x'FFFF'. Select SYSCLK as the timer 7 clock source. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 1 0 0 0 0 0 1 1 If this step is omitted, TM7BC may not count during the first cycle. (3) Set TM7NLD and TM7EN of the TM7MD register to 1 and 0 respectively. This enables TM7BC, T.F.F and RS.F.F. (4) Set both TM7NLD and TM7EN to 1. This starts the timer 7. Counting starts at the beginning of the next cycle. 96 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers s Compare/Capture Register Setup (5) When TM7MD[1:0] = `10' (the capture is selected), TM7CA and TM7CB are reserved for read operations. When setting TM7CA and TM7CB is required, first set TM7MD[1:0] to `00'. TM7CA: x'00FE44' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 TM7CB: x'00FE48' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 TM7CA is captured on the rising edge of TM7IOA and TM7CB is captured on the falling edge of TM7IOA. s Interrupt Processing and Width Calculation (6) Execute interrupt processing. The interrupt processing specifies the interrupt group and vector, and clears IRFn. (7) Calculate the width. Store the TM7CA value and TM7CB value to the data register and subtract TM7CA from TM7CB. Ignore C and V flags. The width is calculated correctly even though the TM7CA value is greater than the TM7CB value by setting TM7LP to 0. The following figure shows 000A - 0007 = 0003 or 3 cycles. Load the TM7CA value and TM7CB value during interrupt processing. The width is calculated by ignoring flags even though the TM7CA value is greater than the TM7CB value. TM7EN TM7BC SYSCLK TM7CA TM7CB TM7IOA B Interrupts 3 Cycles 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 0 0 A-7=3 7 A Figure 4-3-6 One-phase Capture Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 97 Chapter 4 Timers 4-3-5 Two-phase Capture Input Using 16-bit Timer The two-phase capture input setup procedures for timer 6 and timer 7 are same except the up/down counting selection. In this example, timer 7 divides SYSCLK by 65536 and measures the width from positive edge of the TM7IOA input to the positive edge of TM7IOB input. An interrupt occurs on the capture B and the width is calculated by the instruction (TMnCB TMnCA). s Interrupt Enable Setup (1) Enable interrupts. At the same time, clear all prior interrupt requests. Set G7LV[2:0] bits of the G7ICR to the interrupt level of 6 to 0, TM7BIR and TM7BIE to 0 and 1 respectively. For example, write x'4400' to the G7ICR register. Thereafter, an interrupt occurs when the timer 7 capture B occurs. Use the MOV instruction to set the data and always use 16-bit write operations. Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. s Timer 7 Setup (2) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Set TM7LP to 0 to count the loop of 0 to x'FFFF'. Select SYSCLK as the timer 7 clock source. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 1 1 0 0 0 0 1 1 TM7CA is captured on the rising edge of TM7IOA and TM7CB is captured on the rising edge of TM7IOB. The setup steps after step (2) are the same as steps (3) to (7) in "4-3-4 One-phase Capture Input Using 16-bit Timer". The Figure 4-3-7 shows 000A - 0007 = 0003 or 3 cycles. 98 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers TM7EN TM7BC SYSCLK TM7CA TM7CB TM7IOA TM7IOB Interrrupts A-7=3 B 0 0 7 A 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 3 Cycles Figure 4-3-7 Two-phase Capture Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 99 Chapter 4 Timers 4-3-6 Two-phase Encoder Input Using 16-bit Timer (4x) The two-phase encoder input setup procedures for timer 6 and timer 7 are same. In this example, timer 7 inputs the two-phase encoder (4x) and counts up/down. An interrupt occurs when the TM7BC reaches the set value. Use the MOV instruction to set the data and always use 16-bit write operations. s Interrupt Enable Setup (1) Enable interrupts. At the same time, clear all prior interrupt requests. Set G7LV[2:0] bits of the G7ICR to the interrupt level of 6 to 0, TM7BIR and TM7BIE to 0 and 1 respectively. For example, write x'4400' to the G7ICR register. Thereafter, an interrupt occurs when the timer 7 capture B occurs. Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. s Timer 7 Setup (2) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. Select up counting or down counting. Set TM7LP to 1 when TM7BC starts loop counting from the TM7CA value. Set TM7LP to 0 when TM7BC counts the loop of 0 to x'FFFF'. Select two-phase encoder (4x) as the timer 7 clock source. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 0 0 0 0 1 0 1 0 0 (3) Set the timer 7 looping value (the valid range is 1 to x'FFFF'). When writing x'1FFF' to TM7CA, The TM7BC counts from 0 to x'1FFF'. TM7CA: x'00FE44' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Whenever the up or down counter reaches the TM7CA value, a compare/capture A interrupt occurs at the beginning of the next cycle. 100 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (4) Set the value for a timer 7 interrupt when the interrupt occurs at the TM7CB value. (The valid range is 0 to TM7CA.) When the up or down counter reaches this value, a compare/capture B interrupt occurs at the beginning of the next cycle. Set the value for timer 7 interrupt when the TM7BC counts from 0 to x'FFFF'. (The valid range is 0 to x'FFFF'.) (5) Set TM7NLD and TM7EN to 1 and 0 respectively. This enables TM7BC, T.F.F and RS.F.F. Do not change other bits of the TM7MD register. (6) Set both TM7NLD and TM7EN to 1. This starts timer 7. Counting starts at the beginning of the next cycle. If this step is omitted, TM7BC may not count during the first cycle. s Interrupt Processing (6) Execute interrupt processing. The interrupt processing specifies the interrupt group and vector, and clears IRFn. The following figure shows the count direction. TM7IOA TM7IOB 0 Up Counting Down Counting 1 0 0 1 1 1 0 TM7CA TM7CB TM7BC TM7IOA TM7IOB 0000 1FFF 1FFE 1FFD 1FFF 1000 1FFE 1FFF 0000 0001 0FFF 1000 1001 B Interrupts Figure 4-3-8 Two-phase Encoder Input Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 101 Chapter 4 Timers 4-3-7 One-shot Pulse Output Using 16-bit Timer The one-shot pulse setup procedures for timer 6 and timer 7 are same. In this example, timer 7 generates a one-shot pulse. The pulse width is 2 cycles of SYSCLK. Use the MOV instruction to set the data and always use 16-bit write operations. s Timer 7 Setup (1) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. Select up counting. Select SYSCLK as the timer 7 clock source. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 10 9 8 7 6 5 4 3 2 1 0 Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 UD1 UD0 TGE ONE MD1 MD0 ECLR LP ASEL S2 S1 S0 0 0 0 1 0 0 0 1 0 0 1 1 (2) Set the timer 7 pulse width to TM7CA. (The valid range is 1 to x'FFFF'.) Since the timer 7 pulse width is 2 cycles of SYSCLK, write `3' to TM7CA. TM7BC counts from 0 to 3, and TM7IOA outputs high while TM7BC counts from 2 to 3. TM7CA: x'00FE44' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 (3) Write `1' to TM7CB. TM7CB: x'00FE48' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Do not output athe first one-shot pulse when TM7CB is set to `0'. TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 If this step is omitted, TM7BC may not count during the first cycle. (4) Set TM7NLD and TM7EN to 1 and 0 respectively. This enables TM7BC, T.F.F and RS.F.F. (5) Set TM7EN to 1 when TM7IOB rises. Counting starts at the beginning of the next cycle after TM7IOB rises. TM7EN is substitute for the BUSY flag for one-shot pulse. 102 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers Figure 4-3-9 shows the one-shot pulse output timing. Set TM7EN on the falling edge of TM7IOB and start counting from the next cycle. Before counting starts, TM7BC is 0, the initial value of TM7IOA is 0, and a reset (R) signal and a set (S) signal cannot be output. When counting starts, TM7BC changes from 0 to 1 and the S signal is output. TM7IOA becomes 1 and the pulse is output. TM7BC reaches 3, TM7BC resets and changes from 3 to 0. At the same time, the R signal is output and TM7IOA outputs 0. Because TM7ONE is set to 1, the TM7EN flag is also reset and counting stops. When TM7IOB rises again, TM7EN is set and the same operation is repeated. As a result, the one-shot pulse is output. TM7CA TM7CB TM7BC SYSCLK TM7EN TM7IOB Input S R TM7IOA Output 0000 0003 0001 0001 0002 0003 0000 0001 0002 0003 0000 Figure 4-3-9 One-shot Pulse Output Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 103 Chapter 4 Timers 4-3-8 External Count Direction Control Using 16-bit Timer The external count direction control setup procedures for timer 6 and timer 7 are same. In this example, timer 7 counts SYSCLK and controls the counting direction using TM7IOA. An interrupt occurs when TM7BC reaches the set value. Use the MOV instruction to set the data and always use 16-bit write operations. s Interrupt Enable Setup (1) Enable interrupts. At the same time, clear all prior interrupt requests. Set G7LV[2:0] bits of the G7ICR to the interrupt level of 6 to 0, TM7BIR and TM7BIE to 0 and 1 respectively. For example, write x'4400' to the G7ICR register. Thereafter, an interrupt occurs when the timer 7 capture B occurs. Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. s Timer 7 Setup (2) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. The count direction is up when TM7IOA pin is 1 while the count direction is down when TM7IOA is 0. Select SYSCLK as the timer 7 clock source. (3) Set the timer 7 looping value (the valid range is 1 to x'FFFF'). When writing x'1FFF' to TM7CA, The TM7BC counts from 0 to x'1FFF'. The up or down counter reaches the TM7CA value, a compare/capture A interrupt occurs at the beginning of the next cycle. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 TM7 UD1 1 10 TM7 UD0 0 9 TM7 TGE 0 8 7 6 5 4 3 2 1 TM7 S1 1 0 TM7 S0 1 TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 ONE MD1 MD0 ECLR LP ASEL S2 0 0 0 0 1 0 0 (4) Set the value for a timer 7 interrupt when the interrupt occurs at the TM7CB value. (The valid range is 0 to TM7CA.) When the up or down counter reaches this value, a compare/capture B interrupt occurs at the beginning of the next cycle. Set the value for timer 7 interrupt when the TM7BC counts from 0 to x'FFFF'. (The valid range is 0 to x'FFFF'.) TM7CA: x'00FE44' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 104 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers (5) Set TM7NLD and TM7EN to 1 and 0 respectively. This enables TM7BC, T.F.F and RS.F.F. Do not change other bits of the TM7MD register. (6) Set both TM7NLD and TM7EN to 1. This starts timer 7. Counting starts at the beginning of the next cycle. If this step is omitted, TM7BC may not count during the first cycle. s Interrupt Processing (6) Execute interrupt processing. The interrupt processing specifies the interrupt group and vector, and clears IRFn. The following figure shows the count direction. Timer 7 controls the count direction using TM7IOA or TM7IOB. The count direction becomes the opposite edge of the count edge (shown as in Figure 4-3-10). Figure 4-310 shows the external count direction control timing and the example of becoming down counting from up counting and generating an interrupt. TM7CA TM7CB TM7BC SYSCLK TM7IOA Interrupts Count Direction Down Down Up Up 1FFF 1000 0000 1FFF 1FFE 1FFD 1FFE 1FFF 0000 0001 0002 0003 1000 1001 B Up Up Up Up Up Up Up Figure 4-3-10 External Count Direction Control Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 105 Chapter 4 Timers 4-3-9 External Reset Control Using 16-bit Timer The external reset control setup procedures for timer 6 and timer 7 are same. In this example, timer 7 is reset by an external signal while counting up. Use the MOV instruction to set the data and always use 16-bit write operations. s Timer 7 Setup (1) Set the operating mode to the timer 7 mode register (TM7MD). Verify that counting is stopped and an interrupt is disabled. Select up counting. Set TM7ECLR to 1 becuase TM7BC is reset by TM7IC pin asynchronously. Select SYSCLK as the timer 7 clock source. TM7MD: x'00FE40' 15 14 13 -- -- 12 -- -- 11 TM7 UD1 0 10 TM7 UD0 0 9 TM7 TGE 0 8 7 6 5 4 3 2 1 TM7 S1 1 0 TM7 S0 1 Stop TM7BC counting and initialize (clear) TM7BC and RS.F.F. TM7 TM7N EN LD 0 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 ONE MD1 MD0 ECLR LP ASEL S2 0 0 0 1 1 0 0 (2) Set the timer 7 looping value (the valid range is 1 to x'FFFF'). When writing x'1FFF' to TM7CA, The TM7BC counts from 0 to x'1FFF'. TM7CA: x'00FE44' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 If this step is omitted, TM7BC may not count during the first cycle. (3) Set TM7NLD and TM7EN to 1 and 0 respectively. This enables TM7BC, T.F.F and RS.F.F. Do not change other bits of the TM7MD register. (4) Set both TM7NLD and TM7EN to 1. This starts timer 7. Counting starts at the beginning of the next cycle. 106 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 4 Timers Thereafter, timer 7 is reset asynchronously when TM7IC is high. This allows external synchronization easily. It can be used to adjust the motor or to initialize the timer by hardware. TM7BC SYSCLK TM7IC 0000 0001 0002 0003 0004 0000 0001 0002 0003 Figure 4-3-11 External Reset Control Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 107 Chapter 4 Timers 108 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 4 Chapter 5 Serial Interface 5 6 7 8 9 Chapter 5 Serial Interface 5-1 Serial Interface 5-1-1 Overview This LSI series contains two serial interfaces. Each serial interface transmits and receives the data in the synchronous mode, asynchronous mode and I2C mode. The maximum baud speed in synchronous mode is SYSCLK/ 4. The maximum baud speed in asynchronous mode is 312,500 bps with a 20-MHz oscillator. (The baud speed can be set to 312,500 bps or more by changing the oscillation frequency.) Timer 2 Underflow Timer 3 Underflow Transmission End Interrupt 0 Transmitter TXD TXC SBO0 SBT0 Reception End Interrupt 0 Receiver RXC RXD SBI0 Transmission End Interrupt 0 Transmitter TXD TXC SBO1 SBT1 Reception End Interrupt 0 receiver RXC RXD SBI1 Figure 5-1-1 Serial Interface Configuration Table 5-1-1 Serial Interface Features Synchronous Serial Interface Parity Character Length Bit Order Clock Source LSB first, MSB first Timer 2/16 or Timer 3/16 External Clock Timer 2/2 (Ch0) Timer 3/2 (Ch1) Max. Transfer Speed 2,500,000 bps (with a 20-MHz Oscillator) Error Detect Parity Error Overrun Error Asynchronous Serial Interface I 2C -- 8-bit MSB Timer 2/16 or Timer 3/16 None, 0, 1, Even, Odd 7-bit, 8-bit LSB Timer 2/16 or Timer 3/16 312,500 bps (with a 20-MHz Oscillator) Parity Error Overrun Error Framing Error 100,000 bps Slave Response Buffer Interrupt Independent Transmit/Receive buffer (Single Transmit Buffer, Double Receive Transmission End Interrupt, Reception End Interrupt 110 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface 5-1-2 Control Registers Three registers control the serial interface: serial control register (SCnCTR), serial transmit/receive register (SCnTRB) and serial status register (SCnSTR). Table 5-1-2 List of Serial Interface Control registers Serial Interface 0 Serial Control Register Serial Transmit/Receive Register Serial Status Register Serial 0 Control Register (SC0CTR), x'00FD80' Serial 0 Transmit/Receive Register (SC0TRB), x'00FD82' Serial 0 Status Register (SC0STR), x'00FD83' Serial Interface 1 Serial 1 Control Register (SC1CTR), x'00FD90' Serial 1 Transmit/Receive Register (SC1TRB), x'00FD92' Serial 1 Status Register (SC1STR), x'00FD93' The serial control register (SCnCTR) sets the operating conditions for serial interface. This register controls clock source selection, parity bit selection, protocol selection and transmit/receive enable. The transmit data is written to the serial transmit/receive register (SCnTRB), while the receive data is written to the SCnTRB register. The transmission starts at the end of the first cycle or second cycle of the transfer clock (timer 2 underflow or timer 3 udnerflow) after the data is written to SCnTRB. The serial transmission is operated in double buffer mode. After the reception is completed, the data is set to the SCnTRB register. The receive data is loaded when an interrupt occurs or the SCnRXA flag of the SCnSTR register is 1. The serial status register (SCnSTR) reads the status of error detection of serial interface. An overrun error occurs when the next data is received before the received data is loaded by SCnTRB. An error does not occur on the next cycle by reading the SCnTRB register. The overrun error data is updated when the last bit (the 7th bit or the 8th bit) of the data is received. A parity error occurs when the parity bit is 1 although it is supposed to 0, when the parity bit is 0 although it is supposed to 1, when the parity bit is odd although it is even and when the parity bit is even although it is supposed to set odd. The parity error data is updated when the parity bit is received. A framing error occurs when the stop bit is 0. The framing error data is updated when the stop bit is received. Figure 5-1-2 shows the timing when each bit of the serial status register (SCnSTR). Igonore MSB (bit 7) in the 7-bit transmission. Write the data to the serial transmit/ receive register after verifying the data is not in transmission by checking the SCnTBSY of the SCnSTR register or a transmission end interrupt. The serial transmission may not occur if writing to the serial transmit/receive register during the transmission is operated. The MSB (bit 7) becomes 0 in the 7-bit reception. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 111 Chapter 5 Serial Interface s Asynchronous/Synchronous Timing Transmission SBO Write Data to SCnTRB SCnTBSY Transmission Interrupt b0 b1 b2 b3 b4 b5 b6 PTY ST Reset even when transmission is disabled. Reception SBI SCnRBSY Reception Interrupt RXA Read Data of SCnTRB SCnOE (Overrun Error) SCnPE (Parity Error) SCnFE (Framing Error) b0 b1 b2 b3 b4 b5 b6 PTY ST Reset even when reception is disabled. Reset even when reception is disabled. Update Update Update s I2C Timing SBO SBT SCnSTS Start Detect SCnTRB Write SCnSPS After reset, the signal is low during the first I 2 C transmission. The signal is high during other transmission. Figure 5-1-2 SCnSTR Change Timing 112 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface 5-1-3 Serial Interface Connection There are six serial interface connecting methods. s Asynchronous Mode The serial interface can connect using either simplex transfer or duplex transfer mode. Transmit/Receive SBO SBI Transmit SBO SBI Receive SBO SBI SBO SBI Simplex Connection Duplex Connection Figure 5-1-3 Asynchronous Connection s Synchronous Mode The serial interface can connect using either simplex transfer, duplex transfer or halfduplex transfer mode. SBO SBI SBT Transmit SBO SBI SBT Receive SBO SBI SBT SBO SBI SBT Transmit/Receive Transmit/Receive Transmit/Receive See "Chapter 7" for SBT port setup. Simplex Connection Duplex Connection Transmit/Receive When the data cannot be transmitted in half-duplex mode, both SBT pins become input so that they need pull-up resistors. The SBT pins connect a pull-up resistor externally or a built-in pull-up resistor by the PPLU register. Transmit/Receive SBO SBI SBT SBO SBI SBT Half-duplex Connection Figure 5-1-4 Synchronous Connection MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 113 Chapter 5 Serial Interface The I2C mode is used only as the master transmission/reception in the single master system. Because I2C mode do not control the protocol, setting the transfer baud rate and controlling the transfer start are required to function the slave transmission/reception. s I2C Mode The serial interface can connect to the devices which can slave transmit and receive. The SBO pin and SBT pin connect pull-up resistors (externally or internally). This LSI Series Slave Transmit/Receive Slave Transmit/Receive The acknowledge (ACK) bit is substituted for a parity bit. In the system requiring the ACK, fix the parity bit to 1 (SCnPTY[2:0] = 101) when this LSI master transmits the data. In that case, a parity error occurs when the ACK (low level) returns from the slave. Therefore, the parity bit of the SCnSTR register becomes 1 when the transmission is completed normally. On the other hand, when this LSI master receives the data, fix the parity bit to 0 (SCnPTY[2:0] = 100) if the ACK returns from the slave and set the parity bit to 1 (SCnPTY[2:0] = 101) if the ACK does not return. During I2C transmission/reception, the transmit state flag of the SCnSTR register shows the transmission/reception in progress. s Asynchronous Serial Transfer Speed In asynchronous mode, set the serial transfer clock to 16 times of transfer baud rate. The following is the baud rate calculation. Baud Rate (bps) = OSCI, OSCO x 1/32 x 1/timer divisor The transmission is possible if the baud rate error is within 2 %. Table 5-1-3 to Table 5-110 show the baud rates with frequently used oscillators. Master Transmition/Reception SBO SBT Figure 5-1-5 I2C Mode Connection 114 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface Table 5-1-3 Baud Rate Setup Example in Asynchronous Mode Table 5-1-4 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 20 MHz Baud Rate Divisor Real Time Error 1200 520 * 1201.92 0.16 2400 260 * 2403.85 0.16 4800 130 4807.69 0.16 9600 65 9615.38 0.16 19200 33 18939.39 -1.36 28800 22 28409.09 -1.36 31250 20 31250.00 0.00 38400 16 39062.50 1.73 48000 13 48076.92 0.16 57600 11 56818.18 -1.36 76800 8 78125.00 1.73 153600 4 156250.00 1.73 307200 2 312500.00 1.73 312500 2 312500.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-5 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 19.6608 MHz Baud Rate Divisor Real Time Error 1200 520 * 1181.54 -1.54 2400 260 * 2363.08 -1.54 4800 130 4726.15 -1.54 9600 65 9452.31 -1.54 19200 32 19200.00 0.00 28800 21 29257.14 1.59 31250 20 30720.00 -1.70 38400 16 38400.00 0.00 48000 13 47261.54 -1.54 57600 11 55854.55 -3.03 76800 8 76800.00 0.00 153600 4 153600.00 0.00 307200 2 307200.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-6 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 17.2032 MHz Baud Rate Divisor Real Time Error 1200 448 * 1200.00 0.00 2400 224 2400.00 0.00 4800 112 4800.00 0.00 9600 56 9600.00 0.00 19200 28 19200.00 0.00 28800 19 28294.74 -1.75 31250 17 31623.53 1.20 38400 14 38400.00 0.00 48000 11 48872.73 1.82 57600 9 59733.33 3.70 76800 7 76800.00 0.00 153600 3 179200.00 16.67 268800 2 268800.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-7 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 16 MHz Baud Rate Divisor Real Time Error 1200 417 * 1199.04 -0.08 2400 208 2403.85 0.16 4800 104 4807.69 0.16 9600 52 9615.38 0.16 19200 26 19230.77 0.16 28800 17 29411.76 2.12 31250 16 31250.00 0.00 38400 13 38461.54 0.16 48000 10 50000.00 4.17 57600 9 55555.56 -3.55 76800 7 71428.57 -6.99 153600 3 166666.67 8.51 250000 2 250000.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-8 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 14 MHz Baud Rate Divisor Real Time Error 1200 368 * 1188.86 -0.93 2400 184 2377.72 -0.93 4800 92 4755.43 -0.93 9600 46 9510.87 -0.93 19200 23 19021.74 -0.93 28800 15 29166.67 1.27 31250 14 31250.00 0.00 38400 11 39772.73 3.57 48000 9 48611.11 1.27 57600 8 54687.50 -5.06 76800 6 72916.67 -5.06 153600 3 145833.33 -5.06 218750 2 218750.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-9 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 12 MHz Baud Rate Divisor Real Time Error 1200 312 * 1201.92 0.16 2400 156 2403.85 0.16 4800 78 4807.69 0.16 9600 39 9615.38 0.16 19200 20 18750.00 -2.34 28800 13 28846.15 0.16 31250 12 31250.00 0.00 38400 10 37500.00 -2.34 48000 8 46875.00 -2.34 57600 7 53571.43 -6.99 76800 5 75000.00 -2.34 153600 3 125000.00 -18.62 187500 2 187500.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. Table 5-1-10 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 10 MHz Baud Rate Divisor Real Time Error 1200 260 * 1201.92 0.16 2400 130 2403.85 0.16 4800 65 4807.69 0.16 9600 33 9469.70 -1.36 19200 16 19531.25 1.73 28800 11 28409.09 -1.36 31250 10 31250.00 0.00 38400 8 39062.50 1.73 48000 7 44642.86 -6.99 57600 5 62500.00 8.51 76800 4 78125.00 1.73 153600 2 156250.00 1.73 156250 2 156250.00 0.00 (Max) * : Available with Timer 0 in case of the divisor of 256 or greater. External Oscillator at 8 MHz Baud Rate Divisor Real Time 1200 208 1201.92 2400 104 2403.85 4800 52 4807.69 9600 26 9615.38 19200 13 19230.77 28800 9 27777.78 31250 8 31250.00 38400 7 35714.29 48000 5 50000.00 57600 4 62500.00 76800 3 83333.33 125000 2 125000.00 Error 0.16 0.16 0.16 0.16 0.16 -3.55 0.00 -6.99 4.17 8.51 8.51 0.00 (Max) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 115 Chapter 5 Serial Interface 5-2 Serial Interface Setup Examples 5-2-1 Serial Transmission in Asynchronous Mode Using Timer 2 This section describes the example of serial interface 0 transmission in asynchronous mode with the following settings: * 20 MHz oscillation * Baud Rate = 9600 bps (SYSCLK/65 by timer 2) * Bit Order: LSB * 8-bit data transfer * Two stop bits * Odd parity The next data is transmitted when a transmission end interrupt occurs. Serial Interface SYSCLK (10 MHz) 8-bit Timer Timer 2 (Divided by 65) Divider (Divided by 16) Serial I/F Transfer Clock Figure 5-2-1 Aynchronous Transmission Configuration The transmission starts when the data is written to the SC0TRB register. The transmission starts synchronizing with timer 2 underflow. An interrupt occurs after the transmission is completed and the new data is written to the SC0TRB register during the interrupt service routine. The SC0TBSY flag of the SC0STR register polls if an interrupt does not occur. Setting timer is required during serial reception in asynchronous mode. The serial interface generates the serial transfer baud rate with timer 2 or timer 3 divided by 16. With a 20-MHz oscillator (SYSCLK is 10 MHz) and 9600 bps, 10 MHz/16/9600 = 65.10 Therefore, set the timer 2 or timer 3 underflow to 65. s Pin Setup Set P72 pin to data output of serial interface 0. [See Chapter 8 Ports] 116 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface s Timer 2 Setup (1) Verify that counting is stopped with the timer 2 mode register (TM2MD). TM2MD: x'00FE22' 7 6 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 This verification is unnecessary immediately after a reset. TM2 TM2 EN LD 0 0 TM2 TM2 S1 1 S0 1 (2) Set the timer 2 divisor. Since the timer 2 divisor is SYSCLK/65, set the timer 2 base register (TM2BR) to 64. (The valid range is 1 to 255.) TM2BR: x'00FE12' 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BR7 0 BR6 1 BR5 0 BR4 0 BR3 0 BR2 0 BR1 0 BR0 0 (3) Load the TM2BR value to TM2BC. To do this, set TM2LD and TM2EN to 1 and 0 respectively. At the same time, select the clock source. (4) Set both TM2LD and TM2EN to 0. (5) Set TM2LD and TM2EN to 0 and 1 respectively. This starts timer 2. Do not change the clock source once you have selected it. Changing the clock source while controlling count operation will corrupt the binary counter value. If this step is omitted, TM2BC may not count during the first cycle. s Serial Interface 0 Setup (6) Enable interrupts. At this point, clear all prior interrupt requests. Set the G3ICR register to the interrupt level (level 6 to 0), SC0TIR and SC0TIE to 0 and 1 respectively. For example, write the G3ICR register to x'4400'. Thereafter, a serial transmission end interrupt occurs when the data written to the serial transmit/receive register is transferred. G3ICR: x'00FC46' 15 -- 14 G3 LV2 1 13 G3 LV1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 0 1 0 0 0 0 0 0 0 0 0 0 0 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 117 Chapter 5 Serial Interface (7) Set the operating control conditions to the serial 0 control register (SC0CTR). Set asynchronous mode, LSB for bit order, timer 2/16, 8-bit data transfer, 2 stop bits and odd parity. SC0CTR: x'00FD80' 15 14 13 12 11 10 -- -- 9 8 7 6 5 4 3 2 1 0 SC0 S0 1 SC0 SC0 SC0 SC0 SC0 TEN REN BRE I2CS PTL SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB POD S1 0 0 1 1 1 1 1 0 0 1 1 0 0 0 (8) Set the first data to be transferred to the serial 0 transmit/receive register (SC0TRB). When the data to be transferred is set to the SC0TRB register, the transmission starts synchronizing with timer 2. Execute the interrupt service routine and transfer the next data when an interrupt occurs. Timer 2 underflow/16 SC0TRB Write SBO0 Interrupt Request Interrupt Service Routine SC0TBSY ST b0 b1 b2 b3 b4 b5 b6 b7 PT SP SP ST b0 b1 b2 b3 b4 Figure 5-2-2 Bit Transmission Timing in Asynchronous Mode 118 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 119 Chapter 5 Serial Interface 5-2-2 Serial Reception in Synchronous Mode Using Timer 2 This section describes the example of serial interface 0 reception in synchronous mode with the following settings: * Bit Order: MSB * 8-bit data transfer * Even parity The next data is read when a reception end interrupt occurs. s Pin Setup Set P70 pin and P71 pin to serial clock input and data input of serial interface 0 respectively. [See Chapter 8 Ports] s Serial Interface 0 Setup (1) Set the operating control conditions to the serial 0 control register (SC0CTR). Set synchronous mode, MSB for bit order, the external clock source, 8-bit data transfer and even parity. SC0CTR: x'00FD80' 15 14 13 12 11 10 -- -- 9 8 7 6 5 4 3 2 1 0 SC0 S0 0 SC0 SC0 SC0 SC0 SC0 TEN REN BRE I2CS PTL SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB POD S1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 (2) Enable interrupts. At this point, clear all prior interrupt requests. Set the G3ICR register to the interrupt level (level 6 to 0), SC0RIR and SC0RIE to 0 and 1 respectively. For example, write the G3ICR register to x'4800'. Thereafter, a serial reception end interrupt occurs when the data is transferred to the serial transmit/ receive register. G3ICR: x'00FC46' 15 -- 14 G3 LV2 1 13 G3 LV1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 After specifying the interrupt group and vector, and clearing IRFn, program the interrupt service routine. G3 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Thereafter, an interrupt occurs when the serial data is received. 120 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 5 Serial Interface 5-2-3 Serial Transmission/Reception in I2C Mode Using Timer 3 This section describes the example of serial interface 0 transmission/reception in I2C mode explaining I2C start sequence transmission, data transmission, data reception and I2C stop sequence transmission in order. s Pin Setup Set P70 pin and P72 pin to serial clock input and port input respectively. If P70 pin and P72 pin do not equip a pull-up resistor externally, set the pull-up resistor by the pull-up control register. [See Chapter 8 Ports] When selecting P70 and P72 to I2C mode by the serial 0 control register, these pins becomes output mode. Therefore, they should be set to input when they are used as ports. s Serial Interface 0 Setup SC0CTR: x'00FD80' 15 14 13 12 11 10 -- -- 9 8 7 6 5 4 3 2 1 0 SC0 S0 1 In this example, select the slave response. SC0 SC0 SC0 SC0 SC0 TEN REN BRE I2CS PTL SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB POD S1 1 1 1 1 0 1 0 1 1 Set both the transmission enable flag and the reception enable flag to 1. 1 1 0 0 1 SC0CTR: x'00FD80' 15 14 13 12 11 10 -- -- 9 8 7 6 5 4 3 2 1 0 SC0 S0 1 SC0 SC0 SC0 SC0 SC0 TEN REN BRE I2CS PTL SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB POD S1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 (3) Load the data to the serial 0 transmit/receive register. This allows the data to output. The SBO pin output changes with 1/8 cycles delay of the falling edge of the SBT pin output. After transmission, both SBO pin output and SBT pin output stay low. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 121 Chapter 5 Serial Interface (4) After transmission ends, read the dummy data of the serial 0 transmit/receive register (SC0TRB). An interrupt (a serial 0 transmission end interrupt or a serial 0 reception end interrupt) or polling the serial status register identifies the transmission end. (Polling the reception state flag during I2C mode is prohibited.) (5) Read the serial 0 status register and verify the parity error. If a parity error occurs, the response is obtained from the slave correctly. If a parity error does not occur, the response is not obtained from the slave. (This step is not required in the system without ACK.) When the data is transmitted continuously, repeat the steps (3) to (5). (6) Load the dummy data x'FF' to the serial 0 transmit/receive register (SC0TRB). This allows the SBO pin to output resistive high (because the SBO pin is an opendrain pin) and input low when the slave outputs low. An interrupt (a serial 0 transmission end interrupt or a serial 0 reception end interrupt) or polling the serial status register identifies the reception end. (Polling the reception state flag during I2C mode is prohibited.) (7) After reception ends, retrieve the received data by reading the serial 0 transmit/ receive register (SC0TRB). When the data is received continuously, repeat the steps (6) and (7). SC0CTR: x'00FD80' 15 14 13 12 11 10 -- -- 9 8 7 6 5 4 3 2 1 0 SC0 S0 1 SC0 SC0 SC0 SC0 SC0 TEN REN BRE I2CS PTL SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB POD S1 1 1 1 1 0 1 0 1 0 1 1 0 0 1 (9) Disable the reception enable flag once immediately after the stop sequence is generated. I C Sequence Output Bit Write to SC0TRB Register SBO Pin Output b7 b6 b5 b4 b3 b2 b1 b0 ACK 2 Transmitting the dummy data for reception b7 b6 b4 b5 b3 b2 b1 b0 ACK Transmit Interrupt Request Transmit Interrupt Request SBT Pin Output START Detect Bit = 1 (2) STOP Detect Bit = 1 (8) (3) (6) Figure 5-2-3 Transmission/Reception in I2C Mode 122 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 4 5 Chapter 6 Analog Interface 6 7 8 9 Chapter 6 Analog Interface 6-1 Analog Interface 6-1-1 Overview This LSI series contains a 8-bit charge redistribution A/D converter. The A/ D converter supports digital signal processing in the voice and audio frequency ranges with a 8-bit resolution, a maximum conversion frequency of 208 kHz (4.8 s per channel with a 20-MHz oscillator) and a low current. VDD A/Dn Conversion Data Buffer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VSS AN0BUF AN1BUF AN2BUF AN3BUF AN4BUF AN5BUF AN6BUF AN7BUF M U X S/H 8-bit Successive Approximation ADC Figure 6-1-1 Analog Interface Configuration s Notices When Using A/D Converter (1) Set the impedance of the analog signal for A/D conversion to 8 k or less. (2) Connect the A/D input pin to the condenser of 2000 pF or more to control the voltage change of the A/D input pin if the impedance of the analog signal cannot be set to 8 k or less. (3) To prevent the power potential fluctuation, do not change the chip output level from high level to low level or vice verse, or do not switch the peripheral load circuit on/off during A/D conversion. Equivalent Circuit Block Outputs Analog Signal R A/D Input Pin MN102L25x Series C (AVss) R < 8 k Or C 2000 pF Connect to Vss in the chip model which has no AVss. 124 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 6 Analog Interface Table 6-1-2 A/D Converter Functions Feature S/H Conversion Resolution Description Built-in 8-bit 3 LSB (AN3 to AN0) 8-bit 4 LSB (AN7 to AN4) The A/D converter converts the voltage between VDD and Vss divided into 256 and this converted result is tored in AN7BUF to AN0BUF. 4.8 s or more per channel (sample time of 400 ns with a 20-MHz oscillator) Internal System Clock SYSCLK divided by 1, 2, 4, 8 30 operating modes: Single conversion of single channel (channel 0 to channel 7) Single conversion of multiple channels (channel 0 to channel 1, channel o to channel 2, channel 0 to channel 3, channel 0 to channel 4, channel 0 to channel 5, channel 0 to channel 6, channel 0 to channel 7) Continuous conversion of single channel (channel 0 to channel 7) Continuous conversion of multiple channels (channel 0 to channel 1, channel o to channel 2, channel 0 to channel 3, channel 0 to channel 4, channel 0 to channel 5, channel 0 to channel 6, channel 0 to channel 7) Timer 1 underflow or register setting An interrupt occurs each time the conversion sequence ends. "Ch" stands for channel. ANn pin corresponds to the channel number. For example, the AN3 pin corresponds to channel 3. Conversion Time Clock Source Operating Mode Conversion Start Interrupt s Selecting the A/D Converter Clock Source The A/D converter clock source is selected to SYSCLK, SYSCLK/2, SYSCLK/4 or SYSCLK/8 as the conversion time is 4.8 s or more. Select the A/D converter clock source as follows: SYSCLK frequency/divisor 5 MHz For example, select the A/D converter clock source as SYSCLK/4 (the conversion speed of 4.8 s) or SYSCLK/8 (the conversion time of 9.6 s) with a 20-MHz oscillator. Select SYSCLK/2, SYSCLK/4 or SYSCLK/8 with a 10-MHz oscillator. Select SYSCLK. SYSCLK/2, SYSCLK/4, SYSCLK/8 with a 5-MHz oscillator or less. The conversion time is 12 cycles of the A/D converter clock source as Figure 6-1-2 shows. For example, the conversion time is calculated as follows when SYSCLK/4 is selected. [SYSCLK cycle (s) x 4 (divisor) x 12 (cycle)] State A/D Conversion Clock Start S/H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 transfer The input current is run to the standard voltage only during conversion. Therefore, the on/off control of input current to the voltage is not required. Figure 6-1-2 A/D Conversion Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 125 Chapter 6 Analog Interface s One Channel/Single Conversion The A/D converter converts one A/D input signal of 1 channel once. An interrupt occurs as soon as the conversion ends. Set the channel to be converted to AN1CH[2:0] bits. Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag. The ANEN flag becomes 1 during the conversion and 0 when the conversion ends. Interrupt State ANEN Figure 6-1-3 One Channel/Single Conversion Timing Ch n Conversion s Multiple Channels/Single Conversion The A/D converter converts A/D input signals of continuous channels from channel 0 once. An interrupt occurs as soon as the conversion for all channels ends. Set AN1CH[2:0] bits to channel 0 and the ANNCH flag to the last channel to be converted. Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag. The ANEN flag becomes 1 during the conversion and 0 when the conversion sequence ends. In addition, the AN1CH[2:0] bits are set to the channel number during the conversion and channel 0 after the conversion sequence ends. Interrupt State ANEN Ch5 Ch4 Ch0 Ch1 Ch2 Ch3 Conversion Conversion Conversion Conversion Conversion Conversion Figure 6-1-4 Multiple Channels/Single Conversion Timing 126 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 6 Analog Interface s One Channel/Continuous Conversion The A/D converter converts one A/D input signal continuously. An interrupt occurs each time the conversion ends. Set AN1CH[2:0] bits to the channel number to be converted. Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag. Setting the ANEN flag to 0 ends the conversion forcibly. Interrupt State ANEN Ch n Ch n Ch n Conversion Conversion Conversion Figure 6-1-5 One Channel/Continuous Conversion Timing s Multiple Channels/Continuous Conversion The A/D converter converts A/D input signals of continuous channels from channel 0 continuously. An interrupt occurs each time the continuous conversion ends. Set AN1CH[2:0] bits to channel 0 and the ANNCH flag to the last channel to be converted. (The conversion starts from channel 0.) Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag. The ANEN flag becomes 1 during the conversion and 0 when the conversion sequence ends. Setting the ANEN flag to 0 ends the conversion forcibly. The AN1CH[2:0] bits are set to the channel number during the conversion and channel 0 after the conversion sequence ends. Interrupts State ANEN Ch0 Ch0 Ch1 Ch2 Ch0 Ch1 Ch2 Conversion Conversion Conversion Conversion Conversion Conversion Conversion Figure 6-1-5 Multiple Channels/Continuous Conversion Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 127 Chapter 6 Analog Interface AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 128 64 32 16 8 4 2 1 1 M U X VDD VSS Storage for Data Conversion Shift Registers for State Information VDD ANCTR Data Bus ANNCH AN1CH VSS AN7BUF-AN0BUF SYSCLK Divider comp INC Eight 8-bit Registers Figure 6-1-7 Analog Interface Block Diagram 128 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 6 Analog Interface 6-1-2 Control Registers The A/D converter contains the A/D conversion control register (ANCTR) and the A/D conversion data buffers (ANnBUF) corresponding to channel 7 to channel 0 (AN7 pin to AN0 pin). Table 6-1-2 List of A/D Conversion Control Registers Control Register Data Buffers A/D Conversion Control Register (ANCTR), x'00FDA0' A/D0 Conversion Data Buffer (AN0BUF), x'00FDA8' A/D1 Conversion Data Buffer (AN1BUF), x'00FDA9' A/D2 Conversion Data Buffer (AN2BUF), x'00FDAA' A/D3 Conversion Data Buffer (AN3BUF), x'00FDAB' A/D4 Conversion Data Buffer (AN4BUF), x'00FDAC8' A/D5 Conversion Data Buffer (AN5BUF), x'00FDAD' A/D6 Conversion Data Buffer (AN6BUF), x'00FDAE' A/D7 Conversion Data Buffer (AN7BUF), x'00FDAF' The A/D conversion control register (ANCTR) sets the A/D conversion operating conditions. The A/D conversion results for channel 7 to channel 0 are input to the A/D conversion data buffers (ANnBUF). MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 129 Chapter 6 Analog Interface 6-2 Analog Interface Setup Examples 6-2-1 One Channel A/D Conversion Using AN2 Pin This section describes the one channel A/D conversion setup by software. The AN2 pin inputs the analog voltage (0 V to 5 V) and obtains the A/D conversion result. MN102L25x Series 5V P96/AN2 1000 pF 0V Figure 6-2-1 One Channel A/D Conversion s Pin Setup (1) Set AN2 pin (P96) of the port 9 to input (P9DIR6 = `0'). s A/D Conversion Control Register Setup (2) Set the operating conditions to the A/D conversion control register (ANCTR). Set ANMD to 1ch/single conversion and select the clock source to SYSCLK/4 (10 MHz/4 with a 20-MHz oscillator). Set ANEN to `0' and AN1CH[2:0] to the channel number to be converted. ANCTR: x'00FDA0' 15 -- -- 14 13 12 11 -- -- 10 9 8 7 6 AN TM1 0 5 -- -- 4 -- -- 3 2 1 0 ANNCH[2:0] are ignored. AN AN AN NCH2 NCH1 NCH0 0 0 0 AN AN AN AN 1CH2 1CH1 1CH0 EN 0 1 0 0 AN AN AN AN CK1 CK0 MD1 MD0 1 0 0 0 130 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 6 Analog Interface (3) Set the ANEN flag to `1' to start the conversion. Conversion starts on the falling edge of the A/D conversion clock source after ANEN is set to 1. The conversion time is 12 cycles of the A/D conversion clock source (4.8 s, 4.8 s to 5.2 s after ANEN is set). (4) Wait for the conversion to end. Set the ANEN flag to 1 during the conversion and 0 after the conversion ends. The program waits until the ANEN flag is cleared to 0. (5) Read the A/D 2 conversion data buffer (AN2BUF). The converter divides 0 V to 5 V into 256 and the conversion result is the value from 0 to 255. Set the ANEN flag to 1 when starting the conversion by software. The CPU can read the conversion result by generating an interrupt. In this case, the CPU does not need to wait until the ANEN flag is set because an interrupt occurs after the conversion result is stored in AN2BUF. AN2BUF: x'00FDAA' 7 6 5 4 3 2 1 0 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 131 Chapter 6 Analog Interface 6-2-2 Multiple Channels A/D Conversion Using AN2 to AN0 pins The AN2, AN1 and AN0 pins input the analog voltage of 0 V to 5 V and obtains the A/D conversion results. The converter performs periodically using timer 1. Volume 1 10 5 0 Volume 2 10 Volume 3 10 5 0 5 0 MN102L(P, F) 25x Series ch0 ch1 ch2 A/D Conversion Data Buffers Underflow CPU Timer 1 Figure 6-2-2 Multiple Channel A/D Conversion s A/D Conversion Control Register Setup (2) Set the operating conditions to the A/D conversion control register (ANCTR). Set ANMD to multiple channel/single conversion and select the ANCK[1:0] bits to SYSCLK/4 (10 MHz/4 with a 20-MHz oscillator). Set ANEN and ANTM1 to `0' and `1' respectively. Set AN1CH[2:0] to the first channel number to be converted (channel 0) and ANNCH[2:0] to the last channel number to be converted (channel 2). ANCTR: x'00FDA0' 15 -- -- 14 13 12 11 -- -- 10 9 8 7 6 AN TM1 1 5 -- -- 4 -- -- 3 2 1 0 AN AN AN NCH2 NCH1 NCH0 0 1 0 AN AN AN AN 1CH2 1CH1 1CH0 EN 0 0 0 0 AN AN AN AN CK1 CK0 MD1 MD0 1 0 0 1 132 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 6 Analog Interface s Timer 1 Setup (2) Set the timer 1 divisor. Since timer 1 divides SYSCLK by 256, set the timer 1 base register (TM1BR) to 255. (The valid range for TM1BR is 1 to 255.) TM1BR: x'00FE11' 7 6 5 4 3 2 1 0 TM1 TM1 TM1 TM1 TM1 TM1 TM1 TM1 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 1 1 1 1 1 1 1 1 (3) Load the TM1BR value to TM1BC. To do this, set TM1LD and TM1EN to 1 and 0 resepctively. At the same time, select the clock source. TM1MD: x'00FE21' 7 6 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 0 Do not change the clock source after this step. Changing the clock source while controlling count operation will corrupt the binary counter value. TM1 TM1 EN LD 0 1 TM1 TM1 S1 1 S0 0 (4) Set both TM1LD and TM1EN of the TM1MD register to 0. (5) Set TM1LD and TM1EN to 0 and 1 respectively. This starts timer 1. Counting starts at the beginning of the next cycle. When the timer 1 binary counter (TM1BC) reaches 0 and loads the value of 255 from the timer 1 base register (TM1BR), a timer 1 underflow interrupt request occurs. The A/D converter converts each AN2, AN1, and AN0 once when timer 1 underflows. If this setting is omitted, the timer 1 binary counter may not start at the first cycle. The periodical conversion saves the power consumption compared to the continuous conversion. Timer 1 Underflow Conversion Interrupt Ch0 Ch1 Ch2 Ch0 Ch1 Ch2 Figure 6-2-3 A/D Conversion Timing (Single Conversion of Channel 2 to Channel 0) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 133 Chapter 6 Analog Interface 134 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 4 5 6 Chapter 7 ATC 7 8 9 Chapter 7 ATC 7-1 ATC 7-1-1 Overview This series contains an Auto Transfer Control (ATC) which activates by an interrupt request. This series can transfer the data of serial interface 0 and internal RAM speedily without using the CPU. Table 7-1-1 ATC Functions Start Transfer Direction Transfer Mode Transfer End Transfer Unit Transfer Speed Transfer Addressing A serial 0 transmission end interrupt or serial 0 reception end interrupt Internal RAM Serial 0 Transmit/Receive Buffer (SC0TRB) Internal RAM The address for Internal RAM is x'00E000' to x'00E3FF' (1 kbyte) * One-word Transfer Internal RAM Address Setting Byte 600 ns / byte (with a 20-MHz Oscillator) Increment The following is four serial interface 0 modes that the ATC can operate. 1. Synchronous Transmission Internal Clock Master (when this LSI series generates the synchronous clock) 2. Synchronous Reception External Clock Master (when this LSI series receives the synchronous clock externally) 3. Asynchronous Transmission 4. Asynchronous Reception * Setting bi-direction of transmission and reception does not allow. 136 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 7 ATC Serial Interrupt Main Program ATC Transfer (A) Interrupt Service Routine When a Serial Interrupt is Enabled Serial Interrupt Main Program ATC Transfer Interrupt Service Routine (A) Serial Interrupt Service Routine When Overrun Error Occurs Serial Interrupt Serial Interrupt Main Program ATC Transfer Interrupt Service Routine (C) ATC Transfer End Interrupt Service Routine ; ;; ; Serial Interrupt (B) Serial Interrupt (B) ATC Transfer End Interrupt When a Serial Interrupt is Disabled. ATC Transfer End Interrupt Normal Operations Internal RAM SC0TRB A ATC Transfer End Interrupt Service Routine ATC Transfer End Interrupt End Address (ATCEND) B Identify that both a serial interrupt and an ATC transfer end interrupt occur. Internal RAM SC0TRB C ATCBC Value End Address (ATCEND) The value of C is invalid. Figure 7-1-1 ATC Operations MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 137 Chapter 7 ATC 7-1-2 Control Registers The ATC contains the ATC control register (ATCCTR) and the ATC binary counter (ATCBC). Table 7-1-2 List of ATC Control Registers Control Register ATC Control Register (ATCCTR), x'00FD10' Counter ATC Binary Counter (ATCBC), x'00FD12' Set the value of the internal RAM address for ATC end greater than the value of the ATCBC counter. The ATC control register (ATCCTR) sets the transfer direction, the internal RAM address for the ATC end and ATC enable. In addition, the ATC monitors the overrun error (*) generation. Overrun Error * An overrun error occurs when a next serial 0 reception end interrupt occurs before the ATC operation is completed after the serial 0 reception end interrupt occurred during the serial 0 reception (ATCDIR = `0'). When this error occurs, setting bit 14 (OVREF) of the ATCCTR register to 1 as well as negating bit 15 (ATCEN) ends the ATC operation forcibly. At this point, the data stored in the address which subtracted by 1 from the internal RAM address the ATCBC counter shows is invalid. (No data is stored in the address the ATCBC counter shows.) First, the ATC binary counter (ATCBC) sets the start address of internal RAM. Next the ATCBC counter shows the RAM address to write (or read) during ATC operation. The internal RAM area where the ATC can transfer the data is 1 k byte of x'00E000' to x'00E3FF'. The upper 14 bits are fixed at `00000000111000'. Therefore, the lower 10 bits are read when the ATCBC counter is read. The address in the ATCCTR register or the ATCBC counter is set to only lower 10 bits. 138 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 7 ATC 7-2 ATC Setup Examples 7-2-1 Serial Reception The ATC transfers the serial transmit/receive buffer contents to internal RAM automatically after the serial reception is completed. The ATC generates an ATC transfer end interrupt after the ATC transfers 5 times, and starts software processing. The start address of the ATC destination is x'00E0A0'. s Serial Interface 0 Setup (1) Enable an ATC transfer end interrupt. G6ICR: x'00FC40' 15 -- 14 G6 LV2 0 13 G6 LV1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 G6 ATC TM6B TM6A TM6U ATC TM6B TM6A TM6U ATC TM6B TM6A TM6U LV0 IE IE IE IE IR IR IR IR ID ID ID ID 0 1 0 0 0 0 0 0 0 0 0 0 0 When a serial reception end interrupt is enabled, a serial reception end interrupt occurs each time the 1word transfer ends. -- s ATC Setup (2) Set the lower 10 bits of the internal RAM start address for ATC destination to the ATC binary counter (ATCBC). ATCBC: x'00FD12' 15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 8 7 6 5 4 3 2 1 0 ATCBC ATCBC ATCBC ATCBC ATCBC ATCBC ATCBC ATCBC ATCBC ATCBC 9 8 7 6 8 4 3 2 1 0 0 0 1 0 1 0 0 0 0 0 (3) Set the internal RAM end address (x'00E0A4') and the transfer direction (serial internal RAM) and clear the overrun error flag. ATCCTR: x'00FD10' 15 14 13 -- 12 ATC DIR 0 11 -- 10 -- 9 8 7 6 5 4 3 2 1 0 ATC OVR EN EF 0 0 ATC ATC ATC ATC ATC ATC ATC ATC ATC ATC END9 END8 END7 END6 END5 END4 END3 END2 END1 END0 0 0 1 0 1 0 0 1 0 0 (4) Set ATCEN to enable. Keep the same setting as step (3). ATCCTR: x'00FD10' 15 14 13 -- 12 ATC DIR 0 11 -- 10 -- 9 8 7 6 5 4 3 2 1 0 ATC OVR EN EF 1 0 ATC ATC ATC ATC ATC ATC ATC ATC ATC ATC END9 END8 END7 END6 END5 END4 END3 END2 END1 END0 0 0 1 0 1 0 0 1 0 0 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 139 Chapter 7 ATC (5) Set the mode of serial interface 0. See "5-2 Serial Interface Setup Examples" for detail. With the above setting, when the serial reception is completed, the ATC transfer the received data to memory automatically. When the ATC transfers repeatedly until the set number of operation is reached, an ATC transfer end interrupt occurs and the ATC transfer end interrupt service routine is executed. Serial Reception ATC Transfer Destination Memory x'00E0A0' A Transfer B Transfer C Transfer D Transfer E Transfer ATC Tranfer End Interrupt Processing A A B A B C A B C D A B C D E A, B, C, D and E means 1-byte data. x'00E0A1' x'00E0A2' x'00E0A3' x'00E0A4' Figure 7-2-1 Serial Reception Data Transfer OSCI SYSCLK Serial Reception Serial End Interrupt Address Data CPU CPU x'00FDA8' E x'00E0A4' E CPU CPU Serial Reception Bus Authority ATC Transfer Content CPU Start ATC Serial Reception Buffer Internal RAM Write End CPU Figure 7-2-2 Last Data Transfer Timing 140 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 4 5 6 7 Chapter 8 Ports 8 9 Chapter 8 Ports 8-1 Ports 8-1-1 Overview This LSI series contains ten I/O ports. Of ports 0 to 5, port 8 and port 9 are 8 bits. Port 7 and port A are 6 bits. Port 6 is 4 bits. All ports are bidirectional. Port 0 and Port 1 control the I/O direction in 8-bit unit. Port 2 controls the I/O direction in 4-bit unit while ports 3 to A control the I/O direction in bit unit. Table 8-1-1 Port Functions (1 of 8) Port Pin (Shared Pin) Port 0 P07 to P00 (D07 to D00) (AD07 to AD00) Port 0 is used as the port 0 general-purpose port, data (address/data separated) input/output, or address/data (address/data shared) input/output. At reset, this port operates as a general-purpose port input during other modes except processor mode and as D07 to D00 (AD07 to AD00) pins during processor mode. However, this port operates as a general-purpose port during processor mode when 8-bit bus width is selected for all spaces in address/data separated mode. The mode for port 0 is selected in 8-bit unit. During processor mode (without 8-bit bus width setting for all spaces), P0MD is invalid. During memory expansion mode, set P0MD and P0DIR to 1 and 0 respectively. Function DLP Address/Data Output Control (Bus Controller) P0DIR0 P0MD0 P0OUT7 to 0 Address/Data Output (Bus Controller) P0IN7 to 0 Data Input (Bus Controller) 0 MUX 1 P07 to 00 (D07 to 00) (AD07 to 00) 142 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports Table 8-1-1 Port Functions (2 of 8) Port Pin (Shared Pin) P17 to P10 (D15 to D08) (AD15 to AD08) Function Port 1 Port 1 is used as the port 1 general-purpose port, data (address/data separated) input/output, or address/data (address/data shared) input/output. At reset, this port operates as a general-purpose port input during other modes except processor mode and as D15 to D08 (AD15 to AD08) pins during processor mode. The mode for port 1 (either port, data or address/data mode) is selected in 8-bit unit. During processor mode (without 8-bit bus width setting for all spaces), P1MD is invalid. During memory expansion mode, set P1MD and P1DIR to 1 and 0 respectively. DHP Address/Data Output Control (Bus Controller) P1DIR0 P1MD0 P1OUT7 to 0 Address/Data (Bus Controller) P1IN7 to 0 Data Input (Bus Controller) 0 MUX 1 P17 to 10 (AD15 to 08) Port 2 P27 to P20 (A07 to A00) Port 2 is used as the port 2 general-purpose port or address output. At reset, this port operates as a general-purpose port input during other modes except processor mode and as A07 to A00 pins during processor mode. During processor mode, P2MD is invalid. See "2-2-1 Memory Expansion Mode (Address/Data Separated Mode)" and "2-2-3 Memory Expansion Mode (Address/Data Shared Mode)" for port setting during memory expansion mode. ALP Address/Data Output Control (Bus Controller) P2DIR4,P2DIR0 P2MD4,P2MD0 P2OUT7 to 0 Address/Data Output Control (Bus Controller) P2IN7 to 0 0 MUX 1 P27 to 24 (A07 to04) P23 to 20 (A03 to 00) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 143 Chapter 8 Ports Table 8-1-1 Port Functions (3 of 8) Port Pin (Shared Pin) P37 to P30 (A15 to A08) Function Port 3 Port 3 is used as the port 3 general-purpose port or address output. At reset, this port operates as a general-purpose port input during other modes except processor mode and as A15 to A08 pins during processor mode. During processor mode, P3MD is invalid. See "2-2-1 Memory Expansion Mode (Address/Data Separated Mode)" and "2-2-3 Memory Expansion Mode (Address/Data Shared Mode)" for port setting during memory expansion mode. AMP Address/Data Output Control (Bus Controller) P3DIR7 to 0 P3MD7 to 0 P3OUT7 to 0 Address/Data (Bus Controller) P3IN7 to 0 0 MUX 1 P37 to 30 (A15 to 08) Port 4 P43 to P40 (A19 to A16) P45 to P44 (A21 to A20, AN5 to AN4) P46 (A22, AN6, STOP) P47 (A23, AN7, WDOUT) Port 4 is used as the port 4 general-purpose port, address output, A/D converter input pin or CPU status signal pin. At reset, this port operates as a general-purpose port input during other modes except processor mode and as A21 to A16 pins (P47 and P46 operate as general-purpose input) during processor mode. During processor mode, P4MD of P45 to P40 is invalid. See "2-2-1 Memory Expansion Mode (Address/Data Separated Mode)" and "2-2-3 Memory Expansion Mode (Address/Data Shared Mode)" for port setting during memory expansion mode. AMP Address/Data Output Control (Bus Controller) P4DIR3 to 0 P4MD3 to 0 P4OUT3 to 0 Address/Data (Bus Controller) P4IN3 to 0 0 MUX 1 P43 to 40 (A19 to 16) 144 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports Table 8-1-1 Port Functions (4 of 8) Port Pin (Shared Pin) Function Port 4 AHP Address/Data Output Control (Bus Controller) P4DIR5 to 4 P4MD5 to 4 P4OUT5 to 4 Address P4IN5 to 4 0 MUX 1 P45 to 44 (A21 to 20) (AN5 to 4) To A/D Converter AHP Address/Data Output Control (Bus Controller) P4DIR7 to 6 P6MD7 to 6 P4MD7 to 6 A B P4OUT7 to 6 Address Watchdog overflow,STOP P4IN7 to 6 To A/D Converter (A , B) 0* 10 11 P47 to 46 (A23 to 22) (AN7 to 6) (WDOUT,STOP) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 145 Chapter 8 Ports Table 8-1-1 Port Functions (5 of 8) Port Pin (Shared Pin) P57 to P50 (/WORD, /BSTRE, ALE, /ALE, /BRACK, /BREQ, /CS3 to /CS0) BIFP1 to 0 External memory Interface Signal Output Control (Bus Controller) P5DIR7 to 0 P57,P55,P54do not contain pull-up resistors. Function Port 5 Port 5 is used as the port 5 general-purpose port or external memory interface signals pins (/ WORD, /BSTRE, ALE, /ALE, /BRACK, /BREQ, /CS3 to /CS0). At reset, this port operates as a general-purpose port input during other modes except processor mode while P56, P53 to P50 pins operate as /BSTRE, ALE, /ALE, /BRACK, /BREQ, /CS3 to /CS0 pins during processor mode. During processor mode, P5MD6, P5MD3 to P5MD0 are invalid. P5MD6 to 0 P5OUT7 to 0 External Memory Interface Signal (Bus Controller) P5IN7 to 0 (WORD,BREQ) (Bus Controller) 0 MUX 1 P57 does not have MUX. P57 to 50 (WORD,CS3 to 0 BSTRE/ALE/ALE) Port 6 P63 to P60 (/WEL, /WEH, /RE, WAIT) Port 6 is used as the port 6 general-purpose port or external memory interface signals pins (WAIT, /RE, /WEH, /WEL). At reset, this port operates as a general-purpose port input during other modes except processor mode while P63 to P61 pins operate as /WEH, /WEL and /RE pins during processor mode. During processor mode, P6MD3 to P6MD1 are invalid. BIFP0,WAITP External memory Interface Signal Output Control (Bus Controller) P6DIR3 to 0 P6MD3 to 0 P6OUT3 to 0 External memory Interface Signal (Bus Controller) P6IN3 to 0 WAIT (Bus Controller) 0 MUX 1 P60 does not have MUX. P63 to 60 (WEH,WEL, RE,WAIT) 146 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports Table 8-1-1 Port Functions (6 of 8) Port Pin (Shared Pin) P75 (SBO1) P74 (SBI1) P73 (SBT1) P72 (SBO0) P71 (SBI0) P70 (SBT0) Function Port 7 Port 7 is used as the port 7 general-purpose port or serial interface signal pins. At reset, this port operates as a general-purpose port input. SB1P,SB0P Serial I/F Data Enable P7DIR5,P7DIR2 P7MD5,P7MD2 P7OUT5,P7OUT2 Serial I/F Data Output P7IN5,P7IN2 0 1 MUX P75 (SBO1) P72 (SBO0) SB1P,SB0P P7DIR4,P7DIR1 P7OUT4,P7OUT1 P74 (SBI1) P71 (SBI0) P7IN4,P7IN1 Serial I/F Data Input SB1P,SB0P Serial I/F Clock Enable P7DIR3,P7DIR0 A P7MD3,P7MD0 B Decoder(note) (Note) C=A*B C P7OUT3,P7OUT0 Serial I/F Clock Output P7IN3,P7IN0 Serial I/F Clock Input 0 1 A MUX P73 (SBT1) P70 (SBT0)) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 147 Chapter 8 Ports Table 8-1-1 Port Functions (7 of 8) Port Pin (Shared Pin) P87 (TM6IOB) P86 (TM6IOA) P85 to P80 (TM5IO to TM0IO) Function Port 8 Port 8 is used as the port 8 general-purpose port or timer input/output pins (TM0IO to TM5IO, TM6IOA, TM6IOB). At reset, this port operates as a general-purpose port input. P8DIR7 to 0 P8MD7 to 0 P8OUT7 to 0 Timer Output P8IN7 to 0 Timer Input 0 MUX 1 P87 (TM6IOB) P86 (TM6IOA) P85 to 80(TM5IO to TM0IO) Port 9 P97 to P94 (AN3 to AN0) P93 (TM7IC) P92 (TM7IOB) P91 (TM7IOA) P90 (TM6IC) Port 9 is used as the port 9 general-purpose port, timer input/output pins or A/D converter input pins (AN3 to AN0, TM7IC, TM7IOB, TM7IOA, TM6IC). At reset, this port operates as a general-purpose port input. P9DIR3 to 0 P9MD2,P9MD1 P9OUT3 to 0 Timer Output P9IN3 to 0 Timer Input 0 MUX 1 P93 and P90do not have MUX. P93 (TM7IC) P92 (TM7IOB) P91 (TM7IOA) P90 (TM6IC) P9DIR7 to 4 P9OUT7 to 4 P97 (AN3) P96 (AN2) P95 (AN1) P94 (AN0) P9IN7 to 4 To A/D Converter 148 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports Table 8-1-1 Port Functions (8 of 8) Port Pin (Shared Pin) PA5 (ADSEP) PA4 to PA0 (IRQ4 to IRQ0) Function Port A Port A is used as the port A general-purpose port or interrupt related signal pins (ADSEP, IRQ4 to IRQ0). At reset, this port operates as a general-purpose port input. This port can read the level of /NMI pin by operating as the port input pin (PAIN6), and verify an error due to chattering using software. PA4P,PA3P,PA2P, PA1P,PA0P PA4 does not have a pull-up resistor. PADIR5 to 0 PAOUT5 to 0 PA5 (ADSEP) PA4 to 0 (IRQ4 to 0) PAIN5 to 0 (IRQ4 to 0) ADSEP PAIN6 NMI NMI MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 149 Chapter 8 Ports 8-1-2 Control Registers This section describes the port control registers. Table 8-1-2 List of Port Control Registers Port 0 Port 0 Output Register Port 0 Input Register Port 0 Input/Output Control Register Port 0 Output Mode Register Port 1 Output Register Port 1 Input Register Port 1 Input/Output Control Register Port 1 Output Mode Register Port 2 Output Register Port 2 Input Register Port 2 Input/Output Control Register Port 2 Output Mode Register Port 3 Output Register Port 3 Input Register Port 3 Input/Output Control Register Port 3 Output Mode Register Port 4 Output Register Port 4 Input Register Port 4 Input/Output Control Register Port 4 Output Mode Register Port 5 Output Register Port 5 Input Register Port 5 Input/Output Control Register Port 5 Output Mode Register Port 6 Output Register Port 6 Input Register Port 6 Input/Output Control Register Port 6 Output Mode Register Port 7 Output Register Port 7 Input Register Port 7 Input/Output Control Register Port 7 Output Mode Register P0OUT P0IN P0DIR P0MD P1OUT P1IN P1DIR P1MD P2OUT P2IN P2DIR P2MD P3OUT P3IN P3DIR P3MD P4OUT P4IN P4DIR P4MD P5OUT P5IN P5DIR P5MD P6OUT P6IN P6DIR P6MD P7OUT P7IN P7DIR P7MD x'00FFC0' x'00FFD0' x'00FFE0' x'00FFF0' x'00FFC1' x'00FFD1' x'00FFE1' x'00FFF1' x'00FFC2' x'00FFD2' x'00FFE2' x'00FFF2' x'00FFC3' x'00FFD3' x'00FFE3' x'00FFF3' x'00FFC4' x'00FFD4' x'00FFE4' x'00FFF4' x'00FFC5' x'00FFD5' x'00FFE5' x'00FFF5' x'00FFC6' x'00FFD6' x'00FFE6' x'00FFF6' x'00FFC7' x'00FFD7' x'00FFE7' x'00FFF7' Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 150 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports Port 8 Port 8 Output Register Port 8 Input Register Port 8 Input/Output Control Register Port 8 Output Mode Register Port 9 Output Register Port 9 Input Register Port 9 Input/Output Control Register Port 9 Output Mode Register Port A Output Register Port A Input Register Port A Input/Output Control Register Port Pull-up Control Register Word Data Byte Swap Register Pointer Data Byte Swap Register L Pointer Data Byte Swap Register H Long-word data Byte Swap Register L Long-word data Byte Swap Register H P8OUT P8IN P8DIR P8MD P9OUT P9IN P9DIR P9MD PAOUT PAIN PADIR PPLU WBSWP PBSWPL PBSWPH LBSWPL LBSWPH x'00FFC8' x'00FFD8' x'00FFE8' x'00FFF8' x'00FFC9' x'00FFD9' x'00FFE9' x'00FFF9' x'00FFCA' x'00FFDA' x'00FFEA' x'00FFB0' x'00FFA0' x'00FFA2' x'00FFA4' x'00FFA6' x'00FFA8' Port 9 Port A Other MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 151 Chapter 8 Ports The pullup resistor is approximately 30 k. See the product specifications for the exact value. The port output register (PnOUT) sets the data to be output. The port input register (PnIN) reads the pin values. The port input/output control register (PnDIR) sets the input or output of all bits or each bit. The output mode register (PnMD) selects the port output. The port pull-up control register (PPLU) selects on/off of each pin. s P07 to P00 Pins Selection Port Input Port Output D07 to D00/ AD07 to AD00 Reserved P0DIR0 0 1 0 1 P0MD0 0 0 1 1 Description Select the port input or the port output only when 8-bit bus width for all spaces is selected during single-chip mode or address/data separated mode (the word pin is high and all 8th bits of the MEMMD3 to MEMMD1 registers are high). Select D07 to D00 during address/data separated mode, AD07 to AD00 during address/data shared mode. Note: Set only in 8-bit unit. s P17 to P10 Pins Selection Port Input Port Output D15 to D08/ AD15 to AD08 Reserved P1DIR0 0 1 0 1 P1MD0 0 0 1 1 Select D15 to D08 during address/data separated mode, AD15 to AD08 during address/data shared mode. Description Select the port input or the port output only when single-chip mode is selected. Note: Set only in 8-bit unit. s P23 to P20 Pins Selection Port Input Port Output A03 to A00 Reserved P2DIR0 0 1 0 1 P2MD0 0 0 1 1 Description Do not select the port input or the port output in address/data separated mode during processor mode. Note: Set only in 4-bit unit. s P27 to P24 Pins Selection Port Input Port Output A07 to A04 Reserved P2DIR4 0 1 0 1 P2MD4 0 0 1 1 Description Do not select the port input or the port output in address/data separated mode during processor mode. Note: Set only in 4-bit unit. 152 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports s P37 to P30 Pins Selection Port Input Port Output A15 to A08 Reserved P3DIRn P3MDn (n=7 to 0) (n=7 to 0) 0 1 0 1 0 0 1 1 Description Do not select the port input or the port output in address/data separated mode during processor mode. s P43 to P40 Pins Selection Port Input Port Output A19 to A16 Reserved P4DIRn P4MDn (n=3 to 0) (n=3 to 0) 0 1 0 1 0 0 1 1 Description Do not select the port input or the port output during processor mode. s P45 to P44 Pins Selection Port Input AN5, 4 Input Port Output A21, A20 Reserved 0 1 0 1 0 0 1 1 P4DIRn (n=5, 4) P4MDn (n=5, 4) Description Do not select the port input or the port output during processor mode. s P46 Pin Selection Port Input AN6 Input Port Output A22 Output STOP Output Reserved 1 0 1 1 0 1 1 1 * 0 1 0 P4DIR6 0 P4MD6 0 P6MD6 * MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 153 Chapter 8 Ports s P47 Pin Selection Port Input AN7 Input Port Output A23 Output WDOUT Output Reserved 1 0 1 1 0 1 1 1 * 0 1 0 P4DIR7 0 P4MD7 0 P6MD7 * s P53 to P50 Pins Selection Port Input Port Output /CS Output Reserved P5DIRn P5MDn (n=3 to 0) (n=3 to 0) 0 1 0 1 0 0 1 1 Description Do not select the port input or the port output during processor mode. s P54 Pin Selection Port Input Port Output /BREQ Output Reserved P5DIR4 0 1 0 1 P5MD4 0 0 1 1 s P55 Pin Selection Port Input Port Output /BREQ Output Reserved P5DIR5 0 1 1 0 P5MD5 0 0 1 1 s P56 Pin Selection Port Input Port Output /BSTRE, ALE, /ALE Reserved P5DIR6 0 1 0 1 P5MD6 0 0 1 1 Select /BSTRE during address/data separated mode, ALE (/ALE) during address/ data shared mode. Description Do not select the port input or the port output during processor mode. s P57 Pin Selection Port Input 0 /WORD Input Port Output 1 P5DIR7 Description Select the port input during single-chip mode. Otherwise, select /WORD input. 154 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports s P60 Pin Selection Port Input 0 WAIT Input Port Output 1 P6DIR0 Description Select WAIT input when the clock is set to handshake mode. Otherwise, select the port input. s P63 to P61 Pins Selection Port Input Port Output /WEH, /WEL. /RE Output Reserved P6DIRn P6MDn (n=3 to 1) (n=3 to 1) 0 1 0 1 0 0 1 1 Description Do not select the port input or the port output during processor mode. s P73 and P70 Pins Selection Port Input Serial Clock Input Serial Clock I/O (Half-duplex) Port Output Serial Clock Output P7DIRn (n=3,0) 0 0 1 1 P7MDn (n=3,0) 0 1 0 1 Description Operate as a serial clock input pin when setting the serial clock source to the SBT pin (including I2C mode). Become output only when this LSI series output during bidirectional synchronous transfer. s P74 and P71 Pins Selection Port Input Serial Input Port Output P7DIRn (n=4, 1) 0 1 Description Operate as a serial data input pin when the serial reception is enabled. s P75 and P72 Pins Selection Port Input Port Output Serial Output P7DIRn (n=5, 2) 0 1 1 P7MDn (n=5, 2) * 0 1 Select the port input during I2C mode. Description MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 155 Chapter 8 Ports s P87 to P80 Pins Selection Port Input 0 Timer Input Port Output Timer Output 1 1 0 1 * P8DIRn P8MDn (n=7 to 0) (n=7 to 0) Description Operate as a timer input pin when selecting the timer closk source to the pin. s P93 and P90 Pins Selection Port Input Serial Input Port Output 1 P9DIRn (n=3, 0) 0 Description Operate as a serial data input pin when selecting the 16-bit timer binary counter clear condition 2 (5th bit of TMnMD). s P92 and P91 Pins Selection Port Input 0 Timer Input Port Output Timer Output 1 1 0 1 * P9DIRn (n=2, 1) P9MDn (n=2, 1) Description Operate as a timer input pin when setting the timer closk source, capture, trigger and encoder. s P97 to P94 Pins Selection Port Input 0 AN3 to 0 Input Port Output 1 P9DIRn (n=7 to 4) s PA4 to PA0 Pins Selection Port Input 0 Interrupt Input Port Output 1 PADIRn (n=4 to 0) 156 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports s PA5 Pin Selection Port Input 0 ADSEP Input Port Output 1 Operate as the port output only during single-chip mode. This operation is not guaranteed with other modes. PADIR5 Description Operate as the port input only during single-chip mode. Otherwise, operate as the ADSEP input. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 157 Chapter 8 Ports 8-2 Byte Swap Registers 8-2-1 Overview This LSI series contains a word byte swap register, point byte swap registers and long word swap registers. The data is swapped and read as Figure 8-2-1 shows. Word Byte Swap Register WBSWP(x'00FFA0') (All initial values are 0.) bp15 A 87 B 0 bp23 Point Byte Swap Register PBSWPH(x'00FFA4') PBSWPL(x'00FFA2') (All initial values are 0.) 16 15 A B 87 C 0 WRITE WRITE B A READ C B A READ Long-word Byte Swap Register LBSWPH(x'00FFA8') LBSWPL(x'00FFA6') (All initial values are 0.) bp31 A 24 23 B 16 15 C 87 D 0 WRITE D C B A READ Figure 8-2-1 Byte Swap Register 158 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 8 Ports 8-3 Pull-up Control Register 8-3-1 Overview This LSI series contains a pin which sets a pull-up resistor using the program. See "9-2-3 List of Pin Functions". Table 8-3-1 Pull-up Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Corresponded Pin Number 84 to 91 93 to 100 13 to 16, 26 to 29 30 to 33, 35 to 38 39 to 42, 44 to 47 1 2 to 4, 11 5 to 8 76 77 78 79 80 67 to 69 70 to 72 Reserved Description D07 to D00, AD07 to AD00, P07 to P00 D15 to D08, AD15 to AD08, P17 to P11 A07 to A00, P27 to P20 A15 to A08, P37 to P30 A23 to A16, P47 to P40 WAIT, P60 /RE, /WEH, /WEL, /BSTRE, P63 to P61, P56 /CS3 to /CS0, P53 to P50 /IRQ0, PA0 /IRQ1, PA1 /IRQ2, PA2 /IRQ3, PA3 /IRQ4, PA4 SBT0, SBI0, SBO0, P72 to P70 SBT1, SBI1, SBO1, P75 to P73 Always set to 0. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 159 Chapter 8 Ports 160 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 0 1 2 3 4 5 6 7 8 Chapter 9 Appendix 9 Chapter 9 Appendix 9-1 Electrical Characteristics 9-1-1 Electrical Characteristics 5 V Structure Application Function Pin Configuration External Dimensions CMOS integrated circuit General purpose 16-bit microcontroller Figure 1-4-1 Figure 1-5-1 A. Absolute Maximum Ratings VSS = 0 V Parameter A1 A2 A3 A4 A5 A6 Power supply voltage Input pin voltage Output pin voltage Input/output pin voltage Operating ambient temperature Storage temperature Symbol VDD VI VO VIO Topr Tstg Rating - 0.3 to + 7.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 40 to + 85 -55 to + 125 Unit V V V V C C Note: 1. Absolute Maximum Ratings are stress ratings not to cause damage to the device. Operation at these ratings is not guaranteed. 2. All of the VDD and Vss pins are external pins. Connect them directly to the power source and ground. 3. To prevent latch-up tolerance, connect more than one by-pass condenser between power supply pins and ground. Use at least 0.2 F condenser. 162 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix B. Operating Conditions VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min B1 Power supply voltage Crystal Oscillator 1 (OSCI) B2 Oscillator frequency Crystal Oscillator 2 (XI) B3 Oscillator frequency Fosc2 32 200 Unit Typ 5 Max 5.5 VDD 4.5 V Fosc1 4 20 MHz kHz MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 163 Chapter 9 Appendix VDD = 5.0 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min C1 Power supply current during operation Power supply current during slow mode Power supply current in STOP mode Power supply current in HALT0 mode Power supply current in HALT1 mode Unit Typ Max 75 IDD1 VI = VDD or VSS Fosc1 = 20 MHz Output pins open VI = VDD or VSS Fosc2 = 32 kHz Output pins open Oscillator stop All functions stop Fosc1 = 20 MHz Fosc2 = 32 kHz Fosc1 = Oscillator stop Fosc2 = 32 kHz mA C2 IDD2 10 mA C3 IDD3 50 A C4 IDD4 30 mA C5 IDD5 1 mA 164 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 1 < Output pushpull/Input CMOS level schmidt trigger > TMnIO(n=0 to 5), TMnIOA(n=6, 7), TMnIOB(n=6, 7), TMnIC(n=6, 7), ADSEP C6 Input high voltage VIH1 VIL1 Only ADSEP pin Other pins VDD = 5.0 V IOH = -4.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD-0.6 0.4 +/- 10 VDD 0.8 VDD 0.1 VDD 0.2 V V V V V A Symbol Conditions Min Typ Max Unit C7 Input low voltage VIL2 C8 C9 Output high voltage Output low voltage VOH1 VOL1 ILO1 C10 Output leakage current Input/Output Pins 2 < Output pushpull/Input CMOS level schmidt trigger/Programmable pullup > SBO1, SBI1, SBT1, SBO0, SBI0, SBT0 C11 Input high voltage C12 Input low voltage C13 Output high voltage C14 Output low voltage C15 Output leakage current C16 Pullup resistance VIH2 VIL3 VOH2 VOL2 ILO2 PPU1 VDD = 5.0 V IOH = -4.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD = 5.0 V VI = 1.5 V 10 30 VDD-0.6 0.4 +/- 10 50 VDD 0.8 VDD 0.2 V V V V A k MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 165 Chapter 9 Appendix VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 3 < Output pushpull/Input TTL level schmidt trigger/Programmable pullup > WAIT, /RE, /WEL, /WEH, /CS3 to /CS0, ALE, A19 to A0, /IRQ4 to /IRQ0 C17 Input high voltage C18 Input low voltage C19 Output high voltage C20 Output low voltage C21 Output leakage current C22 Pullup resistance Input/Output Pins 4 < Output pushpull/Input TTL level schmidt trigger > /BREQ, /BRACK, /WORD C23 Input high voltage C24 Input low voltage C25 Output high voltage C26 Output low voltage C27 Output leakage current VIH4 VIL5 VOH4 VOL4 ILO4 VDD = 5.0 V IOH = -2.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD-0.6 0.4 +/- 10 2.4 0.8 V V V V A VIH3 VIL4 VOH3 VOL3 ILO3 PPU2 VDD = 5.0 V IOH = -2.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD = 5.0 V VI = 1.5 V 10 30 VDD-0.6 0.4 +/- 10 50 2.4 0.8 V V V V A k Symbol Conditions Min Typ Max Unit 166 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 5 < Output pushpull/Input TTL level schmidt trigger/Programmable pullup > D15 to D0 C28 Input high voltage C29 Input low voltage C30 Output high voltage C31 Output low voltage C32 Output leakage current C33 Pullup resistance Input/Output Pins 6 < Output pushpull/Analog Input > AN3 to AN0 C34 Input high voltage C35 Input low voltage C36 Output high voltage C37 Output low voltage C38 Output leakage current VIH6 VIL7 VOH6 VOL6 ILO6 VDD = 5.0 V IOH = -4.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD-0.6 0.4 +/- 10 VDD 0.8 VDD 0.2 V V V V A VIH5 VIL6 VOH5 VOL5 ILO5 PPU3 VDD = 5.0 V IOH = -2.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD = 5.0 V VI = 1.5 V 10 30 VDD-0.6 0.4 +/- 10 50 2.4 0.8 V V V V A k Symbol Conditions Min Typ Max Unit MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 167 Chapter 9 Appendix VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 7 < Output pushpull/Analog Input/Programmable pullup > A23 to A20 C39 Input high voltage C40 Input low voltage C41 Output high voltage C42 Output low voltage C43 Output leakage current C44 Pullup resistance Input/Output Pins 8 < Input CMOS level schmidt trigger/Output open-drain/Pullup > /RST C45 Input high voltage C46 Input low voltage C47 Pullup resistance VIH8 VIL9 PPU5 VDD = 5.0 V VI = 1.5 V 10 30 VDD 0.9 VDD 0.1 50 V V k VIH7 VIL8 VOH7 VOL7 ILO7 PPU4 VDD = 5.0 V IOH = -4.0 mA VDD = 5.0 V IOL = 4.0 mA Vo = Hi-z VDD = 5.0 V VI = 1.5 V 10 30 VDD-0.6 0.4 +/- 10 50 VDD 0.8 VDD 0.2 V V V V A k Symbol Conditions Min Typ Max Unit 168 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Output Pin < Output pushpull > SYSCLK C48 Output high voltage C49 Output low voltage Input Pins < Input CMOS level schmidt trigger > /NMI, MODE C50 Input high voltage C51 Input low voltage C52 Input leakage current VIH9 VIL10 VLO9 VDD = 5.5 V VI = VSS to VDD VDD 0.9 VDD 0.1 +/- 10 VOH8 VOL8 VDD = 5.0 V IOH = -4.0 mA VDD = 5.0 V IOL = 4.0 mA VDD-0.6 0.4 Symbol Conditions Min Typ Max Unit V V V V A OSCI pin, XI pin (at external clock input) : crystal, ceramic self-excited oscillation See Figure 1-4-2 to Figure 1-4-3 C53 Input high voltage C54 Input low voltage Pin Capacitance C55 Input pin C56 Output pin C57 Input/output pin CIN COUT CI/O VIN = 0 V Ta=25 C 7 7 7 15 15 15 VIH10 VIL11 VDD 0.8 VSS VDD VDD 0.2 V V pF pF pF MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 169 Chapter 9 Appendix D. A/D Converter Characteristics VDD = 5.0 V VSS = 0 V Ta = 25 C Capacitance Parameter Symbol Conditions Min D1 Resolution VDD = 5 V AN3-0 AN7-4 4.8 4.8 VSS VDD Unit Typ Max 8 +/- 3 +/- 3 Bits LSB LSB s s V D2 A/D conversion relative precision A/D conversion time A/D conversion cycle Analog input voltage VIA VSS = 0 V D3 D4 D5 Fosc = 20 MHz Fosc = 20 MHz 170 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix E. AC Characteristics Input Timing Conditions VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min External Clock Input Timing (Fosc1 = 20 MHz) E1 E2 E3 E4 E5 External clock input cycle time external clock input high pulse width External clock input low pulse width External clock input rise time External clock input fall time Typ Max Unit tEXCcyc tEXCH tEXCL tEXCR tEXCF Fig 9-1 2 50 ns ns ns 5 5 tEXCcy -5 tEXCcy -5 2 ns ns Reset Input Timing E6 Reset signal pulse width (/RST) tRSTW Fig 9-2 4 tEXCcyc MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 171 Chapter 9 Appendix Input Timing Conditions VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Input Timing E7 E8 Data acknowledge signal setup time (WAIT) Data acknowledge signal hold time (WAIT) tWAITS tWAITH 20 Fig 9-4 Fig 9-6 ns ns 0 Data Transfer Signal Input Timing E9 Read data setup time (D15-00) tRDS tRDH E10 Read data hold time (D15-00) Bus Authority Request Input Timing E11 E12 Bus authority request signal setup time (/BREQ) Bus authority request signal hold time (/BREQ) Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 20 0 ns ns tBREQS tBREQH 0 Fig 9-8 0 ns ns Interrupt Signal Input Timing E13 E14 Nonmaskable interrupt signal pulse width (NMI) External interrupt signal pulse width (/IRQ4-0) tNMIW tIRQW Fig 9-9 5 (Note) 2 (Note) tcyc tcyc Note : An interrupt may occur when the noise of the specified time or less is input. 172 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Input Timing Conditions VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Capacitance Symbol Conditions Min Typ Max Unit Parameter Serial Interface Related Signal Timing (Synchronous Serial Reception) E15 Data reception setup time (SBI1-0) E16 Data reception hold time (SBI1-0) E17 E18 Serial clock input high pulse width (SBT1-0) Serial clock input low pulse width (SBT1-0) tRXDS tRXDH tSCH tSCL Fig 9-13 25 25 ns ns ns ns tcyc+100 tcyc+100 Timer/Counter Signal Input Timing Timer external input clock low pulse E19 width (TMnIO: n=5-0) (TMnIOA, TMnIOB, TMnIC: n=6,7) Timer external input clock high pulse E20 width (TMnIO: n=5-0) (TMnIOA, TMnIOB, TMnIC: n=6,7) tTCCLKL Fig 9-14 tcyc ns tTCCLKH tcyc ns MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 173 Chapter 9 Appendix F. AC Characteristics (Output) Output Signal Characteristics VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Parameter Symbol Conditions Min System Clock Output Timing F1 F2 F3 F4 F5 System clock output cycle time (SYSCLK) System clock output low pulse width (SYSCLK) System clock output high pulse width (SYSCLK) System clock output rise time (SYSCLK) System clock output fall time (SYSCLK) Typ Max Unit tcyc tCL tCH tCR tCF Fig 9-1 100 45 35 10 10 ns ns ns ns ns 174 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Output Signal Characteristics VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 1 F6 Address delay time 1 (A23-0), (A23-16) Address delay time 2 (AD15-0) Address hold time 1 (A23-0), (A23-16) Address hold time 2 (A23-0), (A23-16) Address hold time 3 (AD15-0) Address/Data hold time 1 (AD15-0) Address/Data hold time 2 (AD15-0) Data delay time 1 (D15-0) Data delay time 2 (AD15-0) Data delay time 3 (D15-0) Data hold time 1 (D15-0) Data hold time 2 (D15-0) tAD1 tAD2 tAH1 tAH2 tAH3 tADH1 tADH2 tDD1 tDD2 tDD3 tDH1 Fig 9-3 to Fig 9-6 Fig 9-4 Fig 9-6 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 30 ns F7 tcy 4 5 tcy +15 4 ns F8 ns F9 tcyc 4 ns F10 tcy -10 4 ns F11 Fig 9-5 Fig 9-6 5 ns F12 tcyc 4 ns F13 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 Fig 9-7 15 ns F14 tcyc 2 ns F15 tcyc 4 5 ns F16 ns Fig 9-3 Fig 9-4 F17 tDH2 tcyc 4 ns MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 175 Chapter 9 Appendix Output Signal Characteristics VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 2 F18 Chip-select signal fall delay time 1 (/CS3-0), (/CS3-1) Chip-select signal rise delay time 1 (/CS3-0), (/CS3-1) Chip-select signal fall delay time 2 (/CS0) Chip-select signal rise delay time 2 (/CS0) Chip-select signal hold time 1 (/CS3-0) Chip-select signal hold time 2 (/CS3-0) Address latch signal fall delay time (ALE) Address latch signal pulse width (ALE) Address latch signal hold time 1 (ALE) Address latch signal hold time 2 (ALE) tCSDF1 Fig 9-3 to Fig 9-7 20 ns F19 tCSDR1 tCSDF2 Fig 9-7 20 ns F20 tcyc +10 4 ns F21 tCSDR2 tCSH1 tCSH2 tALEDF tALEPW Fig 9-5 Fig 9-6 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 5 tcyc +10 4 ns F22 ns F23 tcyc 4 ns F24 tcyc -10 4 ns F25 tcyc -10 2 5 ns F26 tALEH1 tALEH2 ns F27 tcyc 4 ns 176 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Output Signal Characteristics VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 3 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 Read enable signal fall delay time 1 (/RE) Read enable signal fall delay time 2 (/RE) Read enable signal fall delay time 3 (/RE) Read enable signal rise delay time 1 (/RE) Read enable signal rise delay time 2 (/RE) Read enable signal hold time (/RE) Burst ROM read enable signal fall delay time (/BSTRE) Burst ROM read enable signal rise delay time (/BSTRE) Write enable signal fall delay time 1 (/WEH, WEL) Write enable signal fall delay time 2 (/WEH, WEL) Write enable signal fall delay time 3 (/WEH, WEL) Write enable pulse width time 1 (/WEH, WEL) Write enable pulse width time 2 (/WEH, WEL) Write enable pulse width time 3 (/WEH, WEL) Write enable pulse width time 4 (/WEH, WEL) tREDF1 tREDF2 tREDF3 tREDR1 tREDR2 tREH tBREDF tBREDR tWEDF1 tWEDF2 tWEDF3 tWEPW1 tWEPW2 tWEPW3 tWEPW4 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 Fig 9-7 Fig 9-3 to Fig 9-6 10 15 20 15 ns ns ns ns ns ns tcyc+10 4 tcyc Fig 9-7 4 20 ns ns ns ns ns ns ns ns ns tcyc+10 4 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 Fig 9-7 15 20 tcyc 4 Fig 9-3 Fig 9-4 tcyc -20 2 tcyc -10 4 Fig 9-5 Fig 9-6 tcyc -10 3 4 tcyc -10 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 177 Chapter 9 Appendix Output Signal Characteristics VDD = 4.5 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Serial Interface Signal Output Timing (Synchronous Serial Transmission) Transfer data delay time F43 (SBO1-0) Fig 9-10 Fig 9-11 Fig 9-12 Normal I2C 10 tcyc 2 ns ns ns tTXDD tcyc 2 F44 Transfer data hold time (transfer in progress) (SBO1-0) tTXDH1 tTXDH2 Fig 9-10 Transfer data hold time F45 (Transfer end timing at SBT input) (SBO1-0) Transfer data hold time F46 (Transfer end timing at SBT output) (SBO1-0) Fig 9-11 tcyc 2 ns tTXDH3 Fig 9-12 tSCH+tSCL 2 ns 178 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-1-2 Electrical Characteristics 3 V Structure Application Function Pin Configuration External Dimensions CMOS integrated circuit General purpose 16-bit microcontroller Figure 1-4-1 Figure 1-5-1 A. Absolute Maximum Ratings VSS = 0 V Parameter A1 A2 A3 A4 A5 A6 Power supply voltage Input pin voltage Output pin voltage Input/output pin voltage Operating ambient temperature Storage temperature Symbol VDD VI VO VIO Topr Tstg Rating - 0.3 to + 7.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 40 to + 85 -55 to + 125 Unit V V V V C C Note: 1. Absolute Maximum Ratings are stress ratings not to cause damage to the device. Operation at these ratings is not guaranteed. 2. All of the VDD and Vss pins are external pins. Connect them directly to the power source and ground. 3. To prevent latch-up tolerance, connect more than one by-pass condenser between power supply pins and ground. Use at least 0.2 F condenser. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 179 Chapter 9 Appendix B. Operating Conditions VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min B1 Power supply voltage Crystal Oscillator 1 (OSCI) B2 Oscillator frequency Crystal Oscillator 2 (XI) B3 Oscillator frequency Fosc2 32 200 Unit Typ 3 Max 3.6 VDD 2.7 V Fosc1 4 10 MHz kHz 180 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix C. Electrical Characteristics 1. DC Characteristics VDD = 3.0 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min C1 Power supply current during operation Power supply current during slow mode Power supply current in STOP mode Power supply current in HALT0 mode Power supply current in HALT1 mode Unit Typ Max 20 IDD1 VI = VDD or VSS Fosc1 = 10 MHz Output pins open VI = VDD or VSS Fosc2 = 32 kHz Output pins open Oscillator stop All functions stop Fosc1 = 10 MHz Fosc2 = 32 kHz Fosc1 = Oscillator stop Fosc2 = 32 kHz mA C2 IDD2 5 mA C3 IDD3 50 A C4 IDD4 8 mA C5 IDD5 100 A MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 181 Chapter 9 Appendix VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 1 < Output pushpull/Input CMOS level schmidt trigger > TMnIO(n=0 to 5), TMnIOA(n=6, 7), TMnIOB(n=6, 7), TMnIC(n=6, 7), ADSEP C6 Input high voltage VIH1 VIL1 Only ADSEP pin Other pins IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VDD-0.6 0.3 +/- 10 VDD 0.8 VDD 0.1 VDD 0.2 V V V V V A Symbol Conditions Min Typ Max Unit C7 Input low voltage VIL2 C8 C9 Output high voltage Output low voltage VOH1 VOL1 ILO1 C10 Output leakage current Input/Output Pins 2 < Output pushpull/Input CMOS level schmidt trigger/Programmable pullup > SBO1, SBI1, SBT1, SBO0, SBI0, SBT0 C11 Input high voltage C12 Input low voltage C13 Output high voltage C14 Output low voltage C15 Output leakage current C16 Pullup resistance VIH2 VIL3 VOH2 VOL2 ILO2 PPU1 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VI = VSS 20 60 VDD-0.6 0.3 +/- 10 180 VDD 0.8 VDD 0.2 V V V V A k 182 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 3 < Output pushpull/Input TTL level schmidt trigger/Programmable pullup > WAIT, /RE, /WEL. /WEH, /CS3 to /CS0, ALE, A19 to A0, /IRQ4 to /IRQ0 C17 Input high voltage C18 Input low voltage C19 Output high voltage C20 Output low voltage C21 Output leakage current C22 Pullup resistance Input/Output Pins 4 < Output pushpull/Input TTL level schmidt trigger > /BREQ, /BRACK, /WORD C23 Input high voltage C24 Input low voltage C25 Output high voltage C26 Output low voltage C27 Output leakage current VIH4 VIL5 VOH4 VOL4 ILO4 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VDD-0.6 0.3 +/- 10 2.1 0.4 V V V V A VIH3 VIL4 VOH3 VOL3 ILO3 PPU2 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VI = VSS 20 60 VDD-0.6 0.3 +/- 10 180 2.1 0.4 V V V V A k Symbol Conditions Min Typ Max Unit MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 183 Chapter 9 Appendix VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 5 < Output pushpull/Input TTL level schmidt trigger/Programmable pullup > D15 to D0 C28 Input high voltage C29 Input low voltage C30 Output high voltage C31 Output low voltage C32 Output leakage current C33 Pullup resistance Input/Output Pins 6 < Output pushpull/Analog Input > AN3 to AN0 C34 Input high voltage C35 Input low voltage C36 Output high voltage C37 Output low voltage C38 Output leakage current VIH6 VIL7 VOH6 VOL6 ILO6 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VDD-0.6 0.3 +/- 10 VDD 0.8 VDD 0.2 V V V V A VIH5 VIL6 VOH5 VOL5 ILO5 PPU3 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VI = VSS 20 60 VDD-0.6 0.3 +/- 10 180 2.1 0.4 V V V V A k Symbol Conditions Min Typ Max Unit 184 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Input/Output Pins 7 < Output pushpull/Analog Input/Programmable pullup > A23 to A20 C39 Input high voltage C40 Input low voltage C41 Output high voltage C42 Output low voltage C43 Output leakage current C44 Pullup resistance Input/Output Pins 8 < Input CMOS level schmidt trigger/Output open-drain/Pullup > /RST C45 Input high voltage C46 Input low voltage C47 Pullup resistance VIH8 VIL9 PPU5 VI = VSS 20 60 VDD 0.9 VDD 0.1 180 V V k VIH7 VIL8 VOH7 VOL7 ILO7 PPU4 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VI = VSS 20 60 VDD-0.6 0.3 +/- 10 180 VDD 0.8 VDD 0.2 V V V V A k Symbol Conditions Min Typ Max Unit MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 185 Chapter 9 Appendix VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Output Pin < Output pushpull > SYSCLK C48 Output high voltage C49 Output low voltage C50 Output leakage current Input Pins < Input CMOS level schmidt trigger > /NMI, MODE C51 Input high voltage C52 Input low voltage C53 Input leakage current VIH9 VIL10 VLO9 VDD = 3.3 V VI = VSS to VDD VDD 0.9 VDD 0.1 +/- 10 VOH8 VOL8 ILO8 IOH = -2.0 mA IOL = 2.0 mA Vo = Hi-z VDD-0.6 0.3 +/- 10 Symbol Conditions Min Typ Max Unit V V V V V A OSCI pin, XI pin (at external clock input) : crystal, ceramic self-excited oscillation See Figure 1-4-2 to Figure 1-4-3 C54 Input high voltage C55 Input low voltage Pin Capacitance C56 Input pin C57 Output pin C58 Input/output pin CIN COUT CI/O VIN = 0 V Ta=25 C 7 7 7 15 15 15 VIH10 VIL11 VDD 0.8 VSS VDD VDD 0.2 V V pF pF pF 186 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix D. A/D Converter Characteristics VDD = 3.0 V VSS = 0 V Ta = 25 C Capacitance Parameter Symbol Conditions Min D1 Resolution VDD = 3.0 V AN3-0 AN7-4 9.6 9.6 VSS VDD Unit Typ Max 8 +/- 3 +/- 4 Bits LSB LSB s s V D2 A/D conversion relative precision VSS = 0 V D3 D4 D5 A/D conversion time A/D conversion cycle Analog input voltage VIA Fosc = 10 MHz Fosc = 10 MHz MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 187 Chapter 9 Appendix E. AC Characteristics Input Timing Conditions VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Parameter Symbol Conditions Min External Clock Input Timing (Fosc1 = 10 MHz) E1 E2 E3 E4 E5 External clock input cycle time external clock input high pulse width External clock input low pulse width External clock input rise time External clock input fall time Typ Max Unit tEXCcyc tEXCH tEXCL tEXCR tEXCF Fig 9-1 100 ns -5 -5 5 5 tEXCcyc 2 ns ns ns ns tEXCcyc 2 Reset Input Timing E6 Reset signal pulse width (/RST) tRSTW Fig 9-2 4 tEXCcyc 188 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Input Timing Conditions VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Input Timing E7 E8 Data acknowledge signal setup time (WAIT) Data acknowledge signal hold time (WAIT) tWAITS tWAITH 20 Fig 9-4 Fig 9-6 ns ns 0 Data Transfer Signal Input Timing E9 Read data setup time (D15-00) tRDS tRDH E10 Read data hold time (D15-00) Bus Authority Request Input Timing E11 E12 Bus authority request signal setup time (/BREQ) Bus authority request signal hold time (/BREQ) Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 40 0 ns ns tBREQS tBREQH 0 Fig 9-8 0 ns ns Interrupt Signal Input Timing E13 E14 Nonmaskable interrupt signal pulse width (NMI) External interrupt signal pulse width (/IRQ4-0) tNMIW tIRQW Fig 9-9 5 (Note) 2 (Note) tcyc tcyc Note : An interrupt may occur when the noise of the specified time or less is input. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 189 Chapter 9 Appendix Input Timing Conditions VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C Capacitance Symbol Conditions Min Typ Max Unit Parameter Serial Interface Related Signal Timing (Synchronous Serial Reception) E15 Data reception setup time (SBI1-0) E16 Data reception hold time (SBI1-0) E17 E18 Serial clock input high pulse width (SBT1-0) Serial clock input low pulse width (SBT1-0) tRXDS tRXDH tSCH tSCL Fig 9-13 25 25 ns ns ns ns tcyc+100 tcyc+100 Timer/Counter Signal Input Timing Timer external input clock low pulse E19 width (TMnIO: n=5-0) (TMnIOA, TMnIOB, TMnIC: n=6,7) Timer external input clock high pulse E20 width (TMnIO: n=5-0) (TMnIOA, TMnIOB, TMnIC: n=6,7) tTCCLKL Fig 9-14 tcyc ns tTCCLKH tcyc ns 190 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix F. AC Characteristics (Output) Output Signal Characteristics VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Parameter Symbol Conditions Min System Clock Output Timing F1 F2 F3 F4 F5 System clock output cycle time (SYSCLK) System clock output low pulse width (SYSCLK) System clock output high pulse width (SYSCLK) System clock output rise time (SYSCLK) System clock output fall time (SYSCLK) Typ Max Unit tcyc tCL tCH tCR tCF Fig 9-1 200 90 90 20 20 ns ns ns ns ns MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 191 Chapter 9 Appendix Output Signal Characteristics VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 1 F6 Address delay time 1 (A23-0), (A23-16) Address delay time 2 (AD15-0) Address hold time 1 (A23-0), (A23-16) Address hold time 2 (A23-0), (A23-16) Address hold time 3 (AD15-0) Address/Data hold time 1 (AD15-0) Address/Data hold time 2 (AD15-0) Data delay time 1 (D15-0) Data delay time 2 (AD15-0) Data delay time 3 (D15-0) Data hold time 1 (D15-0) Data hold time 2 (D15-0) tAD1 tAD2 tAH1 tAH2 tAH3 tADH1 tADH2 tDD1 tDD2 tDD3 tDH1 Fig 9-3 to Fig 9-6 Fig 9-5 9-6 Fig 9-3 Fig 9-4 Fig 9-5 9-6 Fig Fig 50 ns F7 tcy 4 5 tcy +40 4 ns F8 ns F9 tcyc 4 ns F10 tcy -30 4 ns F11 Fig 9-5 9-6 Fig 5 ns F12 tcy 4 ns F13 Fig 9-3 9-4 Fig 9-5 9-6 Fig 9-7 Fig 40 ns F14 Fig tcy 2 ns F15 tcy 4 5 ns F16 ns Fig 9-3 Fig 9-4 F17 tDH2 tcy 4 ns 192 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Output Signal Characteristics VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 2 F18 Chip-select signal fall delay time 1 (/CS3-0), (/CS3-1) Chip-select signal rise delay time 1 (/CS3-0), (/CS3-1) Chip-select signal fall delay time 2 (/CS0) Chip-select signal rise delay time 2 (/CS0) Chip-select signal hold time 1 (/CS3-0) Chip-select signal hold time 2 (/CS3-0) Address latch signal fall delay time (ALE) Address latch signal pulse width (ALE) Address latch signal hold time 1 (ALE) Address latch signal hold time 2 (ALE) tCSDF1 Fig 9-3 to Fig 9-7 40 ns F19 tCSDR1 tCSDF2 Fig 9-7 40 ns F20 tcyc +30 4 ns F21 tCSDR2 tCSH1 tCSH2 tALEDF tALEPW Fig 9-5 Fig 9-6 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 5 tcy 4 +30 ns F22 ns F23 tcyc 4 ns F24 tcyc -10 4 ns F25 tcyc -30 2 5 ns F26 tALEH1 tALEH2 ns F27 tcyc 4 ns MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 193 Chapter 9 Appendix Output Signal Characteristics VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Data Transfer Signal Output Timing 3 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 Read enable signal fall delay time 1 (/RE) Read enable signal fall delay time 2 (/RE) Read enable signal fall delay time 3 (/RE) Read enable signal rise delay time 1 (/RE) Read enable signal rise delay time 2 (/RE) Read enable signal hold time (/RE) Burst ROM read enable signal fall delay time (/BSTRE) Burst ROM read enable signal rise delay time (/BSTRE) Write enable signal fall delay time 1 (/WEH, WEL) Write enable signal fall delay time 2 (/WEH, WEL) Write enable signal fall delay time 3 (/WEH, WEL) Write enable pulse width time 1 (/WEH, WEL) Write enable pulse width time 2 (/WEH, WEL) Write enable pulse width time 3 (/WEH, WEL) Write enable pulse width time 4 (/WEH, WEL) tREDF1 tREDF2 tREDF3 tREDR1 tREDR2 tREH tBREDF tBREDR tWEDF1 tWEDF2 tWEDF3 tWEPW1 tWEPW2 tWEPW3 tWEPW4 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 Fig 9-7 Fig 9-3 to Fig 9-6 20 30 40 30 ns ns ns ns ns ns tcy +20 4 tcy Fig 9-7 4 40 ns ns ns ns ns ns ns ns ns tcy +20 4 Fig 9-3 Fig 9-4 Fig 9-5 Fig 9-6 Fig 9-7 30 40 tcy 4 Fig 9-3 Fig 9-4 tcyc -20 2 tcy -10 4 Fig 9-5 Fig 9-6 tcyc -10 3 4 tcyc -10 194 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Output Signal Characteristics VDD = 2.7 V to 3.6 V VSS = 0 V Ta = -40 C to +85 C CL = 70 pF Capacitance Symbol Conditions Min Typ Max Unit Parameter Serial Interface Signal Output Timing (Synchronous Serial Transmission) Transfer data delay time F43 (SBO1-0) Fig 9-10 Fig 9-11 Fig 9-12 Normal I2C 10 tcyc 2 ns ns ns tTXDD tcyc 2 F44 Transfer data hold time (transfer in progress) (SBO1-0) tTXDH1 tTXDH2 Fig 9-10 Transfer data hold time F45 (Transfer end timing at SBT input) (SBO1-0) Transfer data hold time F46 (Transfer end timing at SBT output) (SBO1-0) Fig 9-11 tcy 2 ns tTXDH3 Fig 9-12 tSCH+tSCL 2 ns MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 195 Chapter 9 Appendix AC Timing Voltage Level Cycle Time Input Signal VDD x 0.1 VDD x 0.9 Pulse Width High VDD x 0.9 VDD x 0.1 VDD x 0.1 VDD x 0.9 Pulse Width Low Fall Time Rise Time Cycle Time Output Signal VDD x 0.1 VDD x 0.9 Pulse Width High VDD x 0.9 VDD x 0.1 VDD x 0.1 VDD x 0.9 Pulse Width Low Fall Time Rise Time VDD x 0.5 Output Signal Delay Time VDD x 0.5 (Both setup time and hold time are VDD x 0.5) 196 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix tEXCcyc FOSC 1 tEXCH tEXCF tEXCL t EXCR tcyc SYSCLK tCH tCF tCL tCR Fig. 9-1 System Clock Timing RST tRSTW Fig. 9-2 Reset Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 197 Chapter 9 Appendix tcyc SYSCLK tCL tCH A23-00 tAD1 tAD1 tAH1 tAH2 /CS3-0 tCSDF1 tCSDR1 tCSH1 tCSH2 tRDS tRDH /RE (Normal) tREDF1 tREDR1 tREPW1 tDD1 Data tDH1 tDH2 /WEL,/WEH (Normal) tWEPW1 /WEL,/WEH (WE short mode) tWEDF1 tWEPW2 Fig. 9-3 Data Transfer Signal Timing (Address/Data Separated Mode, Without Wait) 198 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix *: N is the number of waits (N1) tcyc tcyc x (N-1)* tcyc SYSCLK tCL tCH tCL tCH A23-00 tAD1 tAD1 tAH1 tAH2 CS3-0 tCSDF1 tCSDR1 tCSH1 tCSH2 WAIT tWAITS tWAITH tWAITS tWAITH tWAITS tWAITH tRDS tRDH RE tREDF1 tREDR1 tDD1 Data tDH1 tDH2 WEL,WEH (Normal) WEL,WEH (WE Short Mode) tWEDF1 tWEPW2 tWEPW1 Fig. 9-4 Data Transfer Signal Timing (Address/Data Separated Mode, With Wait) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 199 Chapter 9 Appendix tcyc tcyc SYSCLK tCL tCH tCL tCH A23-16 tAD1 tAD1 tAH1 tAH2 CS3-0 tCSDF1 tCSDR1 tCSH1 tCSH2 * Note 1 ALEH1 tALEPW ALE tALEDF t ALEH2 AD07-00 (8-bit bus mode) Address tAD2 tAH3 tADH1 tADH2 Address tAD2 Data tRDS tRDH tAH3 t REDF2 tREDR1 Address tAD2 tDD2 Data tADH1 tADH2 tWEPW3 WEL,WEH (WE short mode) tWEDF2 tWEPW4 Fig. 9-5 Data Transfer Signal Timing (Address/Data Shared Mode, Without Wait) 200 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix *: N is the number of waits (N1) tcyc t cyc x (N-1)* tcyc SYSCLK tCL tCH tCL tCH A23-16 tAD1 tAD1 tAH1 tAH2 CS3-0 tCSDF1 tCSDR1 tCSH1 tCSH2 WAIT tWAITS tWAITH tWAITS tWAITH * Note 1 ALE tALEPW tALEDF tALEH1 tALEH2 AD07-00 (8-bit bus mode) Address tAD2 tAH3 tADH1 tADH2 Address tAD2 Data tRDS tRDH tAH3 tREDF2 tREDR1 Address tAD2 tDD2 Data tADH1 tADH2 tWEPW3 tWEPW4 tWEDF2 Fig. 9-6 Data Transfer Signal Timing (Address/Data Shared Mode, With Wait) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 201 Chapter 9 Appendix tcyc tcyc tcyc x N tcyc tcyc tcyc SYSCLK tCL tCH tCL tCH tCL tCH tCL tCH tCL tCH tCL tCH (ROM-read) (ROM-read) (ROM-read) (Penarty-cyc.)(NotROM-read) CS0 tCSDF2 tCSDR2 CS3-1 tCSDF1 tCSDR1 RE tREDF3 tREDR2 tREDF1 tREDR1 (ROM-read) (ROM-read) (ROM-read) (ROM-read) (NotROM-access) CS0 tCSDF2 tCSDR2 CS3-1 tCSDF1 tCSDR1 BSTRE (read) RE (write) D15-00 tDD3 tREH tBREDF tBREDR WEL,WEH tWEDF3 Fig. 9-7 Data Transfer Signal Timing (Burst ROM Interface) 202 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix BRACK BREQ tBREQS tBREQH Fig. 9-8 Bus Authority Request Signal Timing IRQ3-0 tIRQW NMI tNMIW Fig. 9-9 Interrupt Signal Timing SBT1-0 SBO1-0 tTXDD tTXDH 1 Fig. 9-10 Serial Interface Signal Timing 1 (Synchronous Serial Transmission: Transfer in Progress) SBT1-0 SBO1-0 tTXDD tTXDH 2 Fig. 9-11 Serial Interface Signal Timing 2 (Synchronous Serial Transmission: Transfer End Timing at SBT Input) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 203 Chapter 9 Appendix SBT1-0 SBO1-0 tTXDD tTXDH 3 Fig. 9-12 Serial Interface Signal Timing 3 (Synchronous Serial Transmission: Transfer End Timing at SBT Output) SBT1-0 tSCL tSCH SBI1-0 tRXDS tRXDH Fig. 9-13 Serial Interface Signal Timing 4 (Synchronous Serial Reception) TMnIO(n=5-0) TMnIOA(n=6,7) TMnIOB(n=6,7) TMnIC(n=6,7) tTCCLKL tTCCLKH Fig. 9-14 Timer/Counter Signal Timing 204 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 9-2 9-2-1 Data Appendix List of Special Registers MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 205 Chapter 9 Appendix About This Section s Description of Each Page Each page of this chapter describes one or more registers. Each page lists the register name, address, register access, bit map, flag explanation of each bit number and supplementary explanation. The following is the layout and definition of this section. Register Name Bit Map Bit Number Flag Name Access R: Read only W: Write only R/W: Read/Write 15 AT3 EN R/W 0 0/1 14 13 12 AT3 BW R/W 0 0/1 11 AT3 DB8 R/W 0 0/1 10 AT3 DI R/W 0 0/1 9 AT3 SB8 R/W 0 0/1 8 AT3 SI R/W 0 0/1 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 AT3 IQ3 R/W 0 0/1 2 AT3 IQ2 R/W 0 0/1 1 AT3 IQ1 R/W 0 0/1 0 AT3 IQ0 R/W 0 0/1 Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Supplemental Explanation Register Access Address AT3CTR : x'00FD30' ATC 3 Control Register 16-bit access register AT3 AT3 MD1 MD0 R/W 0 0/1 R/W 0 0/1 Value at reset 15 Transfer Busy/Start Flag 0: Disable 1: Transfer start/transfer in progress 14,13 Transfer Mode 00: One byte/word transfer 01: Burst transfer 10: Two bytes/words transfer 11: Reserved 12 Transfer Units 0: Byte 1: Word 11 Destination Bus Width 0: 16-bit 1: 8-bit 10 Destination Pointer Increment 9 Source Bus Width 0: Fixed 1: Increment 0: 16-bit 1: 8-bit 8 Source Pointer Increment 0: Fixed 1: Increment 3-0 ATC Activation Factor Setup 0000: Software Initialization 0001: /DMAREQ1 pin input 0010: External interrupt 2 0011: External interrupt 3 0100: Timer 2 underflow interrupt 0101: Timer 6 underflow interrupt 0110: Timer 8 capture B interrupt 0111: Timer 10 underflow interrupt 1000: Timer 11 capture A interrupt 1001: Timer 12 capture B interrupt 1010: Serial 2 transmission end interrupt 1011: Serial 2 reception end interrupt 1100: Serial 3 transmission end interrupt 1101: Serial 3 reception end interrupt 1110: A/D conversion end interrupt 1111: Key interrupt Read value 0: Always 0 1: Always 1 Sets the ATC3 operating control conditions. Selecting the two bytes/words transfer mode is valid only in byte access. The LSB of the address in the first word forcibly becomes 0, and the LSB of the address in the second word forcibly becomes 1. Selecting word as the unit is not allowed when 8-bit bus width is allowed in the external memory space. Selecting 8-bit desitination bus width or 8-bit source bus width is allowed only when 8-bit bus width is selected in the external memory space. When destination pointer increment or source pointer increment is selected, the pointer increments by 1 in byte access and by 2 in word access. The AT3IQ0 ~ 3 bits are cleared to 0 by the ATC3 transfer end interrupt. Bit Number Flag Description MN102H55D/55G/F55G 9-69 206 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 WD RST R/W 1 0/1 14 WD lng1 R/W 0 0/1 13 WD lng0 R/W 0 0/1 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 ID 3 2 1 0 CPUM : x'00FC00' CPU Mode Control Register 16-bit access register OSC STOP HALT OSC1 OSC0 R 0 0 R 0 0 R 1 0 R 1 0 R 1 0 R 0 0 R 0 0 R 1 0 R 1 0/1 R/W 0 0/1 R/W 1 0/1 R/W 1 0/1 R/W 1 0/1 15 Watchdog Timer Enable 0: Enable 00: 2 16 1: Disable and clear Setting WDRST to '0' after setting it to '1' clears the watchdog timer counting value and starts counting. The watchdog timer consists of a 17-bit binary counter counting on the oscillation clock. Therefore, clear the watchdog timer counting value within 2 16 (65,536) machine cycles. Changing the set value reduces the wait time for oscillation stabilization when returning from STOP mode. (At reset release, the wait time for oscillation stabliation is 216 (65,536) machine cycles. 14:13 Watchdog Timer Count * 01: 24 10: 28 11: Reserved 4 System Clock Monitor 0: High-speed 1: Low-speed 3 CPU Operating Control (STOP tranfer request) 2 CPU Operating Control (HALT tranfer request) 1:0 Oscillator Control 0000: NORMAL mode 0001: IDLE mode 0011: SLOW mode 0100: HALT0 mode 0111: HALT1 mode 1000: STOP0 mode 1011: STOP1 mode The following describes programming rules and precautions in the STOP/HALT mode. Points for Programming (1) Setting the CPUM address in the address register in advance, set the CPUM register using the MOV instruction with the register indirect addressing mode. (2) Immediately after the MOV instruction, locate three NOPs consecutively. (3) Immediately before the MOV instruction, locate the JMP instruction and align to the even address. This avoids the effects by the differences of the bus widths in the memory mode or expansion mode and provides the same result when operating in any conditions. Programming Coding Example in Assembler (as 102Ver.1.0, Ver.2.0) MOV MOV OR JMP ALIGN STP_HLT MOV NOP NOP NOP CPUM, A0 (A0), D0 x'000*', D0 STP_HLT 2 D0, (A0) ; Set A0 to the CPUM address. ; Transfer the contents of CPUM to D0. ; Generate the data to set the STOP/HALT mode. ; Branch unconditionally to the even address to ; eliminate the difference of operating conditions. ; Set the STOP/HALT mode to CPUM. ; Dummy ; Dummy ; Dummy Precautions (1) * of OR instruction varies depending on the STOP or HALT mode. (2) Set the ALIGN value to '2' or more in the above file when the ALIGN value is set using SECTION dummy instruction before this programming coding is described. (3) Code the above programming in another file of the assembler source file when the program is developed with C complier cc 102. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 207 Chapter 9 Appendix 15 - 14 - 13 - 12 - 11 - 10 IOE 9 IOE R/W 1 0/1 8 SET R/W 1 0/1 7 SZ R/W 0 0/1 6 - 5 IO1 4 IO0 R/W 1 0/1 3 - 2 2 1 1 R/W 1 0/1 0 0 R/W 1 0/1 MEMCTR : x'00FC02' Memory Control Register 16-bit access register HSWT NWAIT WAIT ARB WAIT WAIT WAIT WAIT WAIT R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R/W 1 0/1 R 0 0 R/W 1 0 R 0 0 R/W 1 0/1 10 Peripheral Fixed Wait Cycle Enable Flag During Handshake Mode 0: No Wait 1: Peripheral Fixed Wait Cycle (Always set '1' in this series.) 9 Peripheral Fixed Wait Cycle Enable Flag 0: Enable 1: Disable (Always set '0' in this series.) In this series, set MEMCTR to x'0410' or x'0490'. 8 Fixed Wait Mode/ Handhsake Mode Switch 0: Handshake Mode 1: Fixed Wait Mode (Always set '0' in this series.) 7 Bus Width Setup Flag for Fixed Area (x'040000' to x'07FFFF') 0: Based on /WORD pin 1: 8-bit Bus Access regardless of /WORD pin 00: No wait 01: 1 wait cycle 10: 2 wait cycles 11: 3 wait cycles (Always set '01' in this series.) 5:4 Peripheral Fixed Wait Cycle 2:0 Fixed Wait Cycle 000: No wait cycle 001: 1 wait cycle 010: 2 wait cycles 011: 3 wait cycles 100: 4 wait cycles 101: 5 wait cycles 110: 6 wait cycles 111: 7 wait cycles (Don't care in this series.) 208 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 R 0 0 7 R 0 0 6 R 0 0 5 GN4 R 0 0/1 4 GN3 R 0 0/1 3 GN2 R 0 0/1 2 GN1 R 0 0/1 1 GN0 R 0 0/1 0 R 0 0 IAGR : x'00FC0E' Interrupt Accept Group Register 8/16-bit access register 5:1 Group Number of Accepted Interrupt IAGR is a read-only register. 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 R 0 0 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 0 MEMMD0 : x'00FC30' Memory Mode Control Register 0 16-bit access register WAIT WAIT 1 0 R/W 0 0/1 R/W 0 0/1 1:0 Wait Cycle for Block 0 00: No Wait 01: 1 Wait Cycle 10: 2 Wait Cycles 11: Handshake Set any values when block 0 is unused. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 209 Chapter 9 Appendix 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 BMOD R/W 0 0/1 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 0 MEMMD1 : x'00FC32' Memory Mode Control Register 1 16-bit access register WAIT WAIT 1 0 R/W 0 0/1 R/W 0 0/1 8 Bus Mode for Block 1 0: 16-bit Bus Mode 1: 8-bit Bus Mode Set any values when block 1 is unused. 1:0 Wait Cycle for Block 1 00: No Wait 01: 1 Wait Cycle 10: 2 Wait Cycles 11: Handshake 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 BMOD R/W 0 0/1 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 0 MEMMD2 : x'00FC34' Memory Mode Control Register 2 16-bit access register WAIT WAIT 1 0 R/W 0 0/1 R/W 0 0/1 8 Bus Mode for Block 2 0: 16-bit Bus Mode 1: 8-bit Bus Mode (Select the same bus width as the bus width set by /WORD pin.) Set any values when block 2 is unused. 1:0 Wait Cycle for Block 2 00: No Wait 01: 1 Wait Cycle 10: 2 Wait Cycles 11: Handshake 210 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 BMOD R/W 0 0/1 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 0 MEMMD3 : x'00FC36' Memory Mode Control Register 3 16-bit access register WAIT WAIT 1 0 R/W 0 0/1 R/W 0 0/1 8 Bus Mode for Block 3 0: 16-bit Bus Mode 1: 8-bit Bus Mode Set any values when block 3 is unused. 1:0 Wait Cycle for Block 3 00: No Wait 01: 1 Wait Cycle 10: 2 Wait Cycles 11: Handshake 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 R 0 0 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 1 0 G0ICR : x'00FC40' Nonmaskable Interrupt Control Register 0 8/16-bit access register UNIF WDIF NMIF R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 2 Nonmaskable Interrupt Request Flag by Executing Undefined Instruction 0: No interrupt requested 1: Interrupt requested 1 Nonmaskable Interrupt Request Flag by Overflowing Watchdog Timer 0: No interrupt requested 1: Interrupt requested 0 Nonmaskable Interrupt Request Flag by /NMI Pin 0: No interrupt requested 1: Interrupt requested MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 211 Chapter 9 Appendix 15 R 0 0 14 G1 LV2 R/W 0 0/1 13 G1 LV1 R/W 0 0/1 12 G1 LV0 R/W 0 0/1 11 R 0 0 10 TM5 IE R/W 0 0/1 9 8 7 R 0 0 6 TM5 IR R/W 0 0/1 5 4 3 R 0 0 2 TM5 ID R/W 0 0/1 1 0 G1ICR : x'00FC42' Maskable Interrupt Control Register 1 8/16-bit access register TM0 IRQ0 IE IE R/W 0 0/1 R/W 0 0/1 TM0 IRQ0 IR IR R/W 0 0/1 R/W 0 0/1 TM0 IRQ0 ID ID R/W 0 0/1 R/W 0 0/1 14:12 Group 1 Interrupt Priority Level 10 Timer 5 Underflow Interrupt Enable Flag Timer 0 Underflow Interrupt Enable Flag IRQ0 Interrupt Enable Flag Timer 5 Underflow Interrupt Request Flag Timer 0 Underflow Interrupt Request Flag IRQ0 Interrupt Request Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 9 0: Disable 1: Enable 8 6 0: Disable 1: Enable 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested Set '1' when timer 5 underflows. Set '1' when timer 0 underflows. Set '1' when an external interrupt occurs from IRQ0 pin. 5 4 2 Timer 5 Underflow Interrupt Detect Flag Timer 0 Underflow Interrupt Detect Flag 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 1 0 IRQ0 Interrupt Detect Flag 212 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 15 R 0 0 14 G2 LV2 R/W 0 0/1 13 G2 LV1 R/W 0 0/1 12 G2 LV0 R/W 0 0/1 11 R 0 0 10 AN IE R/W 0 0/1 9 8 7 R 0 0 6 AN IR R/W 0 0/1 5 4 3 R 0 0 2 AN ID R/W 0 0/1 1 0 G2ICR : x'00FC44' Maskable Interrupt Control Register 2 8/16-bit access register TM1 IRQ1 IE IE R/W 0 0/1 R/W 0 0/1 TM1 IRQ1 IR IR R/W 0 0/1 R/W 0 0/1 TM1 IRQ1 ID ID R/W 0 0/1 R/W 0 0/1 14:12 Group 2 Interrupt Priority Level 10 A/D Conversion End Interrupt Enable Flag Timer 1 Underflow Interrupt Enable Flag IRQ1 Interrupt Enable Flag A/D Conversion End Interrupt Request Flag Timer 1 Underflow Interrupt Request Flag IRQ1 Interrupt Request Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 9 0: Disable 1: Enable 8 6 0: Disable 1: Enable 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested Set '1' when the A/D conversion ends. Set '1' when timer 1 underflows. Set '1' when an external interrupt occurs from IRQ1 pin. L M N O P Q R S T U V W X Y Z 5 4 2 A/D Conversion End Interrupt Detect Flag Timer 1 Underflow Interrupt Detect Flag 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 1 0 IRQ1 Interrupt Detect Flag MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 213 Chapter 9 Appendix 15 R 0 0 14 G3 LV2 R/W 0 0/1 13 G3 LV1 R/W 0 0/1 12 11 10 9 8 7 6 5 4 3 2 1 0 G3ICR : x'00FC46' Maskable Interrupt Control Register 3 8/16-bit access register G3 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 SC0R SC0T TM2 IRQ2 LV0 IE IE IE IE IR IR IR IR ID ID ID ID R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 14:12 Group 3 Interrupt Priority Level 11 Serial 0 Reception End Interrupt Enable Flag 10 Serial 0 Transmission End Interrupt Enable Flag Timer 2 Underflow Interrupt Enable Flag IRQ2 Interrupt Enable Flag Serial 0 Reception End Interrupt Request Flag 6 Serial 0 Transmission End Interrupt Request Flag Timer 2 Underflow Interrupt Request Flag IRQ2 Interrupt Request Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 0: Disable 1: Enable 9 0: Disable 1: Enable 8 7 0: Disable 1: Enable Set '1' when the serial 0 reception ends. Set '1' when the serial 0 transmission ends. Set '1' when timer 2 underflows. Set '1' when an external interrupt occurs from IRQ2 pin. 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 5 4 3 Serial 0 Reception End Interrupt Detect Flag 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 2 Serial 0 Transmission End Interrupt Detect Flag Timer 2 Underflow Interrupt Detect Flag 1 0 IRQ2 Interrupt Detect Flag 214 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L 15 R 0 0 14 G4 LV2 R/W 0 0/1 13 G4 LV1 R/W 0 0/1 12 11 10 9 8 7 6 5 4 3 2 1 0 G4ICR : x'00FC48' Maskable Interrupt Control Register 4 8/16-bit access register G4 SC1R SC1T TM3 IRQ3 SC1R SC1T TM3 IRQ3 SC1R SC1T TM3 IRQ3 LV0 IE IE IE IE IR IR IR IR ID ID ID ID R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 14:12 Group 4 Interrupt Priority Level 11 Serial 1 Reception End Interrupt Enable Flag 10 Serial 1 Transmission End Interrupt Enable Flag Timer 3 Underflow Interrupt Enable Flag IRQ3 Interrupt Enable Flag Serial 1 Reception End Interrupt Request Flag 6 Serial 1 Transmission End Interrupt Request Flag Timer 3 Underflow Interrupt Request Flag IRQ3 Interrupt Request Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 0: Disable 1: Enable 9 0: Disable 1: Enable 8 7 0: Disable 1: Enable Set '1' when the serial 1 reception ends. Set '1' when the serial 1 transmission ends. Set '1' when timer 3 underflows. Set '1' when an external interrupt occurs from IRQ3 pin. 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested M N O P Q R S T U V W X Y Z 5 4 3 Serial 1 Reception End Interrupt Detect Flag 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 2 Serial 1 Transmission End Interrupt Detect Flag Timer 3 Underflow Interrupt Detect Flag 1 0 IRQ3 Interrupt Detect Flag MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 215 Chapter 9 Appendix 15 R 0 0 14 G5 LV2 R/W 0 0/1 13 G5 LV1 R/W 0 0/1 12 11 10 9 8 7 6 5 4 3 R 0 0 2 R 0 0 1 0 G5ICR : x'00FC4A' Maskable Interrupt Control Register 5 8/16-bit access register G5 *Note *Note TM4 IRQ4 *Note *Note TM4 IRQ4 LV0 IE IE IR IR R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 TM4 IRQ4 ID ID R 0 0/1 R 0 0/1 *Note: Always set 0. 14:12 Group 5 Interrupt Priority Level 9 Timer 4 Underflow Interrupt Enable Flag IRQ4 Interrupt Enable Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 8 0: Disable 1: Enable 5 Timer 4 Underflow Interrupt Request Flag IRQ4 Interrupt Request Flag 0: No interrupt requested 1: Interrupt requested Set '1' when timer 4 underflows. 4 0: No interrupt requested 1: Interrupt requested Set '1' when an external interrupt occurs from IRQ4 pin. 1 Timer 4 Underflow Interrupt Detect Flag IRQ4 Interrupt Detect Flag 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0 216 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 15 R 0 0 14 G6 LV2 R/W 0 0/1 13 G6 LV1 R/W 0 0/1 12 G6 LV0 R/W 0 0/1 11 10 9 8 7 6 5 4 3 2 1 0 G6ICR : x'00FC4C' Maskable Interrupt Control Register 6 8/16-bit access register ATC TM6B TM6A TM6U ATC TM6B TM6A TM6U ATC TM6B TM6A TM6U IE IE IE IE IR IR IR IR ID ID ID ID R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 14:12 Group 6 Interrupt Priority Level 11 ATC Transfer End Interrupt Enable Flag 10 Timer 6 Compare/Capture Interrupt B Enable Flag Timer 6 Compare/Capture Interrupt A Enable Flag Timer 6 Underflow Interrupt Enable Flag 7 ATC Transfer End Interrupt Request Flag Timer 6 Compare/Capture Interrupt B Request Flag 5 Timer 6 Compare/Capture Interrupt A Request Flag 4 Timer 6 Underflow Interrupt Request Flag 3 ATC Transfer End Interrupt Detect Flag 2 Timer 6 Compare/Capture Interrupt B Detect Flag Timer 6 Compare/Capture Interrupt A Detect Flag Timer 6 Underflow Interrupt Detect Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 0: Disable 1: Enable 9 0: Disable 1: Enable Set '1' when ATC transfer ends. 8 0: Disable 1: Enable Set '1' when a timer 6 underflow interrupt or compare/capture interrupt occurs. L M N O P Q R S T U V W X Y Z 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 6 1 0 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 217 Chapter 9 Appendix 15 R 0 0 14 G7 LV2 R/W 0 0/1 13 G7 LV1 R/W 0 0/1 12 G7 LV0 R/W 0 0/1 11 R 0 0 10 9 8 7 R 0 0 6 5 4 3 R 0 0 2 1 0 G7ICR : x'00FC4E' Maskable Interrupt Control Register 7 8/16-bit access register TM7B TM7A TM7U IE IE IE R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 TM7B TM7A TM7U IR IR IR R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 TM7B TM7A TM7U ID ID ID R 0 0/1 R 0 0/1 R 0 0/1 14:12 Group 7 Interrupt Priority Level 10 Timer 7 Compare/Capture Interrupt B Enable Flag Timer 7 Compare/Capture Interrupt A Enable Flag Timer 7 Underflow Interrupt Enable Flag 6 Timer 7 Compare/Capture Interrupt B Request Flag Timer 7 Compare/Capture Interrupt A Request Flag 4 Timer 7 Underflow Interrupt Request Flag 2 Timer 7 Compare/Capture Interrupt B Detect Flag 1 Timer 7 Compare/Capture Interrupt A Detect Flag 0 Timer 7 Underflow Interrupt Detect Flag 000 (level 0) to 110 (level 6) 0: Disable 1: Enable 9 0: Disable 1: Enable 8 0: Disable 1: Enable 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt requested 1: Interrupt requested 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected 0: No interrupt detected 1: Interrupt detected Set '1' when a timer 7 underflow interrupt or compare/capture interrupt occurs. 5 218 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 8 7 6 5 4 3 2 1 0 EXTMD : x'00FC50' External Interrupt Edge Setup Register 8/16-bit access register IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 9:8 Set Trigger Conditions for IRQ4 Pin Interrupt 00: Low level 01: High level 10: Negative edge 11: Positive edge IRQTRG sets the trigger conditions for external interrupts. 7:6 Set Trigger Conditions for IRQ3 Pin Interrupt 00: Low level 01: High level 10: Negative edge 11: Positive edge 5:4 Set Trigger Conditions for IRQ2 Pin Interrupt 00: Low level 01: High level 10: Negative edge 11: Positive edge 3:2 Set Trigger Conditions for IRQ1 Pin Interrupt 00: Low level 01: High level 10: Negative edge 11: Positive edge 1:0 Set Trigger Conditions for IRQ0 Pin Interrupt 00: Low level 01: High level 10: Negative edge 11: Positive edge MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 219 Chapter 9 Appendix 15 WE SHT R/W 0 0/1 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 R 0 0 8 NALE EN R/W 0 0/1 7 R 0 0 6 R 0 0 5 4 3 R 0 0 2 R 0 0 1 0 EXMCTR : x'00FD00' External Memory Control Register 8/16-bit access register BRPG BRPG 1 0 R/W 0 0/1 R/W 0 0/1 BREN BREN 1 0 R/W 0 0/1 R/W 0 0/1 15 WEH, WEL Pulse Width Shortening 0: Disbale 1: Enable 8 ALE Signal Polarity 0: Positive logic 1: Negative logic 5:4 Page Size of ROM Burst Mode 00: 4 bytes 01: 8 bytes 10: 16 bytes 11: Reserved Setting a page size of ROM burst mode is invalid when ROM burst mode is disabled. 1:0 ROM Burst Mode 00: Disable 01: Reserved 10: Enable (without penalty) 11: Enable (with penalty) 15 14 13 R 0 0 12 ATC DIR R/W 0 0/1 11 R 0 0 10 R 0 0 9 8 7 6 5 4 3 2 1 0 ATCCTR : x'00FD10' ATC Control Register 8/16-bit access register ATC OVR EN EF R/W 0 0/1 R/W 0 0/1 ATC ATC ATC ATC ATC ATC ATC ATC ATC ATC END9 END8 END7 END6 END5 END4 END3 END2 END1 END0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15 14 13 ATC Enable Overrun Error Flag ATC Transfer Direction 0: Disbale 0: No error 1: Enable 1: Error 0: From serial ch 0 to Internal RAM 1: From Internal RAm to serial ch 0 9:0 ATC End Address Set the ATC end address (the lower 10 bits of the internal RAM area) The upper 14 bits are fixed at '00000000111000' because the internal RAM addresses for TC operation are x'00E000' to x'00E3FF'. Set the larger value than the ATCBC value. 220 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 R 0 0 14 R 0 0 13 R 0 0 12 R 0 0 11 R 0 0 10 R 0 0 9 8 7 6 5 4 ATC BC4 R/W 0 0/1 3 ATC BC3 R/W 0 0/1 2 1 0 ATCBC : x'00FD12' ATC Binary Counter 8/16-bit access register ATC ATC ATC ATC ATC BC9 BC8 BC7 BC6 BC5 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 ATC ATC ATC BC2 BC1 BC0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 9:0 ATC Transfer Address Set the ATC start address (the lower 10 bits of the internal RAM area) (Read the internal RAm address where the chip accesses next during ATC operation.) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 221 Chapter 9 Appendix 15 SC0 TEN R/W 0 0/1 14 SC0 REN R/W 0 0/1 13 SC0 BRE R/W 0 0/1 12 SC0 I2C R/W 0 0/1 11 SC0 PTL R/W 0 0/1 10 R 0 0 9 8 7 6 5 4 3 2 SC0 POD R/W 0 0/1 1 SC0 S1 R/W 0 0/1 0 SC0 S0 R/W 0 0/1 SC0CTR : x'00FD80' Serial 0 Control Register 8/16-bit access register SC0 SC0 SC0 SC0 SC0 SC0 SC0 OD I2CM LN PTY2 PTY1 PTY0 SB R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15 14 13 12 Transmit Enable Receive Enable Break Transmission I2C Start or Stop Sequence 0: Disable 0: Disable 0: Don't break 1: Enable 1: Enable 1: Break (Set SBO to 0) 0: Stop sequence output when changing this bit from 1 to 0. 1: Start sequence output when changing this bit from 0 to 1. 11 Protocol Selection 0: Asynchronous mode 1: Clock synchronous mode, I2C mode 9 Bit Order Selection 0: LSB first 1: MSB first (select only when the character length is 8-bit.) When 7-bit transfer is selected, the bit order is set only to 'LSB first'. 8 7 6:4 I2C mode Selection Character Length Parity Bit Selection 0: I2C mode off 0: 7-bit 000: None 100: 0 (output low) 101: 1 (output high) 1: 8-bit 1: I2C mode on 110: Even (1s are even) 111: Odd (1s are odd) Others: Reserved 3 2 Stop Bit Selection Open-drain Control for I2C pin 1:0 Serial 0 Clock Source Selection 00: SBT0 pin 01: Timer 2 underflow/16 10: Timer 2 underflow/2 11: Timer 3 underflow/16 0: 1-bit 0: Off 1: 2-bit 1: On The stop bit is set only during asynchronous mode. 222 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 7 6 5 4 3 2 1 0 SC0TRB : x'00FD82' Serial 0 Transmit/ Receive Buffer 8-bit access register SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB1 TRB0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Serial Transmit/Receive Data Transmission starts by writing the data into this register. The transmission starts after 1 cycle or 2 cycles of the trasmission clock. In 7-bit transfer, the MSB (bit 7) is ignored. Writing to SC0TRB register must be operated after verifying that the transmission is not in progress. The data is received by reading this register. The data is read when an interrupt occurs or the SC0RXA flag of the SC0STR register is 1. In 7-bit transfer, the MSB (bit 7) becomes 0. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 223 Chapter 9 Appendix 7 6 5 SC0 ISP R 0 0/1 4 SC0 RXA R 0 0/1 3 SC0 IST R 0 0/1 2 SC0 FE R 0 0/1 1 SC0 PE R 0 0/1 0 SC0 OE R 0 0/1 SC0STR : x'00FD83' Serial 0 Status Register 8-bit access register (16-bit access is possible from even address) SC0 SC0 TBY RBY R 0 0/1 R 0 0/1 7 Transmission Busy Flag 0: Ready to transmit 1: Transmission in progress 6 Reception Busy Flag 0: Ready to receive 1: Reception in progress 5 I2C Stop Sequence Detect 0: Undetected 1: Detected 4 Received Data 0: No received data 1: Received data 3 I2C Start Sequence Detect 0: Undetected 1: Detected 2 Framing Error 0: No error 1: Error A framing error occurs when the stop bit is 0. Framing error data is updated whenever the stop bit is received. A parity error occurs when the parity bit is 1 although it is set to 0, when the parity bit is 0 although it is set to 1, when the parity bit is odd although it is set to even, and when the parity bit is even although it is set to odd. Parity error data is updated whenever the parity bit is received. An overrun error occurs when the next data is received completely before the CPU reads the received data (SC3TRB). Overrun error data is updated whenever the last data bit (seventh or eighth bit) is received. Do not use the SC3RBY flag to set polling for the received data wait in clock synchronous mode. Use the interrupt service routine, the serial interrupt flag or the SC3RXA flag. 1 Parity Error 0: No error 1: Error 0 Overrun Error 0: No error 1: Error 224 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L 15 SC1 TEN R/W 0 0/1 14 SC1 REN R/W 0 0/1 13 SC1 BRE R/W 0 0/1 12 SC1 I2C R/W 0 0/1 11 SC1 PTL R/W 0 0/1 10 R 0 0 9 8 7 6 5 4 3 2 SC1 POD R/W 0 0/1 1 SC1 S1 R/W 0 0/1 0 SC1 S0 R/W 0 0/1 SC1CTR : x'00FD90' Serial 1 Control Register 8/16-bit access register SC1 SC1 SC1 SC1 SC1 SC1 SC1 OD I2CM LN PTY2 PTY1 PTY0 SB R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15 14 13 12 Transmit Enable Receive Enable Break Transmission I2C Start or Stop Sequence 0: Disable 0: Disable 0: Don't break 1: Enable 1: Enable 1: Break (Set SBO to 0) 0: Stop sequence output when changing this bit from 1 to 0. 1: Start sequence output when changing this bit from 0 to 1. 11 Protocol Selection 0: Asynchronous mode 1: Clock synchronous mode, I2C mode 9 Bit Order Selection 0: LSB first 1: MSB first (select only when the character length is 8-bit.) When 7-bit transfer is selected, the bit order is set only to 'LSB first'. M N O P Q R S T 8 7 6:4 I2C mode Selection Character Length Parity Bit Selection 0: I2C mode off 0: 7-bit 000: None 100: 0 (output low) 101: 1 (output high) 1: 8-bit 1: I2C mode on 110: Even (1s are even) 111: Odd (1s are odd) Others: Reserved 3 2 Stop Bit Selection Open-drain Control for I2C pin 1:0 Serial 1 Clock Source Selection 00: SBT1 pin 01: Timer 2 underflow/16 10: Timer 2 underflow/2 11: Timer 3 underflow/16 0: 1-bit 0: Off 1: 2-bit 1: On The stop bit is set only during asynchronous mode. U V W X Y Z MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 225 Chapter 9 Appendix 7 6 5 4 3 2 1 0 SC1TRB : x'00FD92' Serial 1 Transmit/ Receive Buffer 8-bit access register SC1 SC1 SC1 SC1 SC1 SC1 SC1 SC1 TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB1 TRB0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Serial Transmit/Receive Data Transmission starts by writing the data into this register. The transmission starts after 1 cycle or 2 cycles of the trasmission clock. In 7-bit transfer, the MSB (bit 7) is ignored. Writing to SC1TRB register must be operated after verifying that the transmission is not in progress. The data is received by reading this register. The data is read when an interrupt occurs or the SC1RXA flag of the SC1STR register is 1. In 7-bit transfer, the MSB (bit 7) becomes 0. 226 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 7 6 5 SC1 ISP R 0 0/1 4 SC1 RXA R 0 0/1 3 SC1 IST R 0 0/1 2 SC1 FE R 0 0/1 1 SC1 PE R 0 0/1 0 SC1 OE R 0 0/1 SC1STR : x'00FD93' Serial 1 Status Register 8-bit access register (16-bit access is possible from even address) SC1 SC1 TBY RBY R 0 0/1 R 0 0/1 7 Transmission Busy Flag 0: Ready to transmit 1: Transmission in progress 6 Reception Busy Flag 0: Ready to receive 1: Reception in progress 5 I2C Stop Sequence Detect 0: Undetected 1: Detected 4 Received Data 0: No received data 1: Received data 3 I2C Start Sequence Detect 0: Undetected 1: Detected 2 Framing Error 0: No error 1: Error A framing error occurs when the stop bit is 0. Framing error data is updated whenever the stop bit is received. A parity error occurs when the parity bit is 1 although it is set to 0, when the parity bit is 0 although it is set to 1, when the parity bit is odd although it is set to even, and when the parity bit is even although it is set to odd. Parity error data is updated whenever the parity bit is received. An overrun error occurs when the next data is received completely before the CPU reads the received data (SC3TRB). Overrun error data is updated whenever the last data bit (seventh or eighth bit) is received. Do not use the SC3RBY flag to set polling for the received data wait in clock synchronous mode. Use the interrupt service routine, the serial interrupt flag or the SC3RXA flag. 1 Parity Error 0: No error 1: Error 0 Overrun Error 0: No error 1: Error MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 227 Chapter 9 Appendix 15 R 0 0 14 13 12 11 R 0 0 10 9 8 7 AN EN R/W 0 0/1 6 AN TM1 R/W 0 0/1 5 R 0 0 4 R 0 0 3 AN CK1 R/W 0 0/1 2 1 0 ANCTR : x'00FF00' A/D Converter Control Register 8/16-bit access register AN AN AN NCH2 NCH1 NCH0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 AN AN AN 1CH2 1CH1 1CH0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 AN AN AN CK0 MD1 MD0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 14:12 Channel Selection for Multiple Channel Conversion 000: Convert AN0 001: Convert from AN0 to AN1 010: Convert from AN0 to AN2 011: Convert from AN0 to AN3 100: Convert from AN0 to AN4 101: Convert from AN0 to AN5 110: Convert from AN0 to AN6 111: Convert from AN0 to AN7 10:8 Channel Selection for Single Channel Conversion 000: Convert AN0 001: Convert AN1 010: Convert AN2 011: Convert AN3 100: Convert AN4 101: Convert AN5 110: Convert AN6 111: Convert AN7 7 Conversion Start/Execution Flag 0: Reserved 1: Conversion start/Conversion in progress 0: Disable 1: Enable 00: SYSCLK 01: SYSCLK/2 10: SYSCLK/4 11: SYSCLK/8 6 Conversion Start at Timer 1 underflow 3:2 Clock Source Selection 1:0 Operating Mode Selection 00: Single channel, single conversion 01: Multiple channels, single conversion 10: Single channel, continuous conversion 11: Multiple channels, continuous conversion 228 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 7 6 5 4 3 2 1 0 AN0BUF : x'00FDA8' A/D 0 Conversion Data Buffer 8/16-bit access register AN0BUF is a read-only buffer. AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note *Note: Undefined 7:0 A/D Conversion Result of Ch 0 (AN0 Pin) 7 6 5 4 3 2 1 0 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note AN1BUF : x'00FDA9' A/D 1 Conversion Data Buffer 8-bit access register (16-bit access is possible from even address) AN1BUF is a read-only buffer. L M N O P Q R S T *Note: Undefined 7:0 A/D Conversion Result of Ch 1 (AN1 Pin) 7 6 5 4 3 2 1 0 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note AN2BUF : x'00FDAA' A/D 2 Conversion Data Buffer 8/16-bit access register AN2BUF is a read-only buffer. U V W X Y Z *Note: Undefined 7:0 A/D Conversion Result of Ch 2 (AN2 Pin) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 229 Chapter 9 Appendix 7 6 5 4 3 2 1 0 AN3BUF : x'00FDAB' A/D 3 Conversion Data Buffer 8-bit access register (16-bit access is possible from even address) AN3BUF is a read-only buffer. AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note *Note: Undefined 7:0 A/D Conversion Result of Ch 3 (AN3 Pin) 7 6 5 4 3 2 1 0 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note AN4BUF : x'00FDAC' A/D 4 Conversion Data Buffer 8/16-bit access register AN4BUF is a read-only buffer. *Note: Undefined 7:0 A/D Conversion Result of Ch 4 (AN4 Pin) 7 6 5 4 3 2 1 0 AN5 AN5 AN5 AN5 AN5 AN5 AN5 AN5 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note AN5BUF : x'00FDAD' A/D 5 Conversion Data Buffer 8-bit access register (16-bit access is possible from even address) AN5BUF is a read-only buffer. *Note: Undefined 7:0 A/D Conversion Result of Ch 5 (AN5 Pin) 230 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 7 6 5 4 3 2 1 0 AN6BUF : x'00FDAE' A/D 6 Conversion Data Buffer 8/16-bit access register AN6BUF is a read-only buffer. AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note *Note: Undefined 7:0 A/D Conversion Result of Ch 6 (AN6 Pin) 7 6 5 4 3 2 1 0 AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 R 0/1 *Note *Note *Note *Note *Note *Note *Note *Note AN7BUF : x'00FDAF' A/D 7 Conversion Data Buffer 8-bit access register (16-bit access is possible from even address) AN7BUF is a read-only buffer. L M N O P Q R S T U V W X Y Z *Note: Undefined 7:0 A/D Conversion Result of Ch 7 (AN7 Pin) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 231 Chapter 9 Appendix 7 TM0 BC7 R 0 0/1 6 TM0 BC6 R 0 0/1 5 TM0 BC5 R 0 0/1 4 TM0 BC4 R 0 0/1 3 TM0 BC3 R 0 0/1 2 TM0 BC2 R 0 0/1 1 TM0 BC1 R 0 0/1 0 TM0 BC0 R 0 0/1 TM0BC : x'00FE00' Timer 0 Binary Counter 8/16-bit access register 7:0 Timer 0 Count Value TM0BC is a read-only register. 7 TM1 BC7 R 0 0/1 6 TM1 BC6 R 0 0/1 5 TM1 BC5 R 0 0/1 4 TM1 BC4 R 0 0/1 3 TM1 BC3 R 0 0/1 2 TM1 BC2 R 0 0/1 1 TM1 BC1 R 0 0/1 0 TM1 BC0 R 0 0/1 TM1BC : x'00FE01' Timer 1 Binary Counter 8-bit access register (16-bit access is possible from even address) TM1BC is a read-only register. 7:0 Timer 1 Count Value 7 TM2 BC7 R 0 0/1 6 TM2 BC6 R 0 0/1 5 TM2 BC5 R 0 0/1 4 TM2 BC4 R 0 0/1 3 TM2 BC3 R 0 0/1 2 TM2 BC2 R 0 0/1 1 TM2 BC1 R 0 0/1 0 TM2 BC0 R 0 0/1 TM2BC : x'00FE02' Timer 2 Binary Counter 8/16-bit access register 7:0 Timer 2 Count Value TM2BC is a read-only register. 232 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 7 TM3 BC7 R 0 0/1 6 TM3 BC6 R 0 0/1 5 TM3 BC5 R 0 0/1 4 TM3 BC4 R 0 0/1 3 TM3 BC3 R 0 0/1 2 TM3 BC2 R 0 0/1 1 TM3 BC1 R 0 0/1 0 TM3 BC0 R 0 0/1 TM3BC : x'00FE03' Timer 3 Binary Counter 8-bit access register (16-bit access is possible from even address) TM3BC is a read-only register. 7:0 Timer 3 Count Value 7 TM4 BC7 R 0 0/1 6 TM4 BC6 R 0 0/1 5 TM4 BC5 R 0 0/1 4 TM4 BC4 R 0 0/1 3 TM4 BC3 R 0 0/1 2 TM4 BC2 R 0 0/1 1 TM4 BC1 R 0 0/1 0 TM4 BC0 R 0 0/1 TM4BC : x'00FE04' Timer 4 Binary Counter 8/16-bit access register L M N O P Q R S T U V W X Y Z 7:0 Timer 4 Count Value TM4BC is a read-only register. 7 TM5 BC7 R 0 0/1 6 TM5 BC6 R 0 0/1 5 TM5 BC5 R 0 0/1 4 TM5 BC4 R 0 0/1 3 TM5 BC3 R 0 0/1 2 TM5 BC2 R 0 0/1 1 TM5 BC1 R 0 0/1 0 TM5 BC0 R 0 0/1 TM5BC : x'00FE05' Timer 5 Binary Counter 8-bit access register (16-bit access is possible from even address) TM5BC is a read-only register. 7:0 Timer 5 Count Value MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 233 Chapter 9 Appendix 7 TM0 BR7 R/W 0 0/1 6 TM0 BR6 R/W 0 0/1 5 TM0 BR5 R/W 0 0/1 4 TM0 BR4 R/W 0 0/1 3 TM0 BR3 R/W 0 0/1 2 TM0 BR2 R/W 0 0/1 1 TM0 BR1 R/W 0 0/1 0 TM0 BR0 R/W 0 0/1 TM0BR : x'00FE10' Timer 0 Base Register 8/16-bit access register 7:0 Timer 0 Count Cycle Set the count cycle (2 to 256). Timer 0 counts the set value plus 1. The valid range for TM0BR is 0 to 255. TM0BR is set to 0 after timer 0 starts. See "4-2 8-bit Timer Setup Examples" for details. 7 TM1 BR7 R/W 0 0/1 6 TM1 BR6 R/W 0 0/1 5 TM1 BR5 R/W 0 0/1 4 TM1 BR4 R/W 0 0/1 3 TM1 BR3 R/W 0 0/1 2 TM1 BR2 R/W 0 0/1 1 TM1 BR1 R/W 0 0/1 0 TM1 BR0 R/W 0 0/1 TM1BR : x'00FE11' Timer 1 Base Register 8-bit access register (16-bit access is possible from even address) TM1BR is set to 0 after timer 1 starts. See "4-2 8-bit Timer Setup Examples" for details. 7:0 Timer 1 Count Cycle Set the count cycle (2 to 256). Timer 1 counts the set value plus 1. The valid range for TM1BR is 0 to 255. 7 TM2 BR7 R/W 0 0/1 6 TM2 BR6 R/W 0 0/1 5 TM2 BR5 R/W 0 0/1 4 TM2 BR4 R/W 0 0/1 3 TM2 BR3 R/W 0 0/1 2 TM2 BR2 R/W 0 0/1 1 TM2 BR1 R/W 0 0/1 0 TM2 BR0 R/W 0 0/1 TM2BR : x'00FE12' Timer 2 Base Register 8/16-bit access register 7:0 Timer 2 Count Cycle Set the count cycle (2 to 256). Timer 2 counts the set value plus 1. The valid range for TM2BR is 0 to 255. TM2BR is set to 0 after timer 2 starts. See "4-2 8-bit Timer Setup Examples" for details. 234 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K 7 TM3 BR7 R/W 0 0/1 6 TM3 BR6 R/W 0 0/1 5 TM3 BR5 R/W 0 0/1 4 TM3 BR4 R/W 0 0/1 3 TM3 BR3 R/W 0 0/1 2 TM3 BR2 R/W 0 0/1 1 TM3 BR1 R/W 0 0/1 0 TM3 BR0 R/W 0 0/1 TM3BR : x'00FE13' Timer 3 Base Register 8-bit access register (16-bit access is possible from even address) TM3BR is set to 0 after timer 3 starts. See "4-2 8-bit Timer Setup Examples" for details. 7:0 Timer 3 Count Cycle Set the count cycle (2 to 256). Timer 3 counts the set value plus 1. The valid range for TM3BR is 0 to 255. 7 TM4 BR7 R/W 0 0/1 6 TM4 BR6 R/W 0 0/1 5 TM4 BR5 R/W 0 0/1 4 TM4 BR4 R/W 0 0/1 3 TM4 BR3 R/W 0 0/1 2 TM4 BR2 R/W 0 0/1 1 TM4 BR1 R/W 0 0/1 0 TM4 BR0 R/W 0 0/1 TM4BR : x'00FE14' Timer 4 Base Register 8/16-bit access register L M N O P Q R S T U V W X Y Z 7:0 Timer 4 Count Cycle Set the count cycle (2 to 256). Timer 4 counts the set value plus 1. The valid range for TM4BR is 0 to 255. TM4BR is set to 0 after timer 4 starts. See "4-2 8-bit Timer Setup Examples" for details. 7 TM5 BR7 R/W 0 0/1 6 TM5 BR6 R/W 0 0/1 5 TM5 BR5 R/W 0 0/1 4 TM5 BR4 R/W 0 0/1 3 TM5 BR3 R/W 0 0/1 2 TM5 BR2 R/W 0 0/1 1 TM5 BR1 R/W 0 0/1 0 TM5 BR0 R/W 0 0/1 TM5BR : x'00FE15' Timer 5 Base Register 8-bit access register (16-bit access is possible from even address) TM5BR is set to 0 after timer 5 starts. See "4-2 8-bit Timer Setup Examples" for details. 7:0 Timer 5 Count Cycle Set the count cycle (2 to 256). Timer 5 counts the set value plus 1. The valid range for TM4BR is 0 to 255. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 235 Chapter 9 Appendix 7 TM0 EN R/W 0 0/1 6 TM0 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM0 S1 R/W 0 0/1 0 TM0 S0 R/W 0 0/1 TM0MD : x'00FE20' Timer 0 Mode Register 8/16-bit access register 7 TM0BC Count 0: Disable 1: Enable 6 TM0BR Setup 0: Disable 1: Load TM0BR to TM0BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM0IO pin clock (Event timer) 01: System clock/128 10: System clock 11: Low-speed clock (32 kHz)/4 7 TM1 EN R/W 0 0/1 6 TM1 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM1 S1 R/W 0 0/1 0 TM1 S0 R/W 0 0/1 TM1MD : x'00FE21' Timer 1 Mode Register 8-bit access register (16-bit access is possible from even address) 7 TM1BC Count 0: Disable 1: Enable 6 TM1BR Setup 0: Disable 1: Load TM1BR to TM1BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM1IO pin clock (Event timer) 01: Low-speed clock (32 kHz)/4 10: Timer 0 output clock 11: System clock 236 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 7 TM2 EN R/W 0 0/1 6 TM2 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM2 S1 R/W 0 0/1 0 TM2 S0 R/W 0 0/1 TM2MD : x'00FE22' Timer 2 Mode Register 8/16-bit access register 7 TM2BC Count 0: Disable 1: Enable 6 TM2BR Setup 0: Disable 1: Load TM2BR to TM2BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM2IO pin clock (Event timer) 01: Timer 1 cascade 10: Timer 0 output clock 11: System clock 7 TM3 EN R/W 0 0/1 6 TM3 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM3 S1 R/W 0 0/1 0 TM3 S0 R/W 0 0/1 TM3MD : x'00FE23' Timer 3 Mode Register 8-bit access register (16-bit access is possible from even address) 7 TM3BC Count 0: Disable 1: Enable 6 TM3BR Setup 0: Disable 1: Load TM3BR to TM3BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM3IO pin clock (Event timer) 01: Timer 2 cascade 10: Timer 0 output clock 11: System clock MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 237 Chapter 9 Appendix 7 TM4 EN R/W 0 0/1 6 TM4 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM4 S1 R/W 0 0/1 0 TM4 S0 R/W 0 0/1 TM4MD : x'00FE24' Timer 4 Mode Register 8/16-bit access register 7 TM4BC Count 0: Disable 1: Enable 6 TM4BR Setup 0: Disable 1: Load TM4BR to TM4BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM4IO pin clock (Event timer) 01: Timer 3 cascade 10: Timer 0 output clock 11: Low-speed clock (32 kHz)/4 7 TM5 EN R/W 0 0/1 6 TM5 LD R/W 0 0/1 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 TM5 S1 R/W 0 0/1 0 TM5 S0 R/W 0 0/1 TM5MD : x'00FE25' Timer 5 Mode Register 8-bit access register (16-bit access is possible from even address) 7 TM5BC Count 0: Disable 1: Enable 6 TM5BR Setup 0: Disable 1: Load TM5BR to TM5BC, Reset the 1/2 divisor circuit, Fix TMIO output to 0. 1:0 Clock Source Selection 00: TM5IO pin clock (Event timer) 01: Timer 4 cascade 10: Timer 0 output clock 11: Low-speed clock (32 kHz)/4 238 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H 15 14 13 R 0 0 12 R 0 0 11 TM6 UD1 R/W 0 0/1 10 TM6 UD0 R/W 0 0/1 9 8 7 6 5 4 3 2 1 TM6 S1 R/W 0 0/1 0 TM6 S0 R/W 0 0/1 TM6MD : x'00FE30' Timer 6 Mode Register 16-bit access register TM6 TM6 EN NLD R/W 0 0/1 R/W 0 0/1 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TGE ONE MD1 MD0 ECLR LP ASEL S2 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15 14 TM6BC Count TM6BC, T.F.F., RS.F.F. Operation 0: Disable 1: Enable 0: Set TM6BC, T.F.F., RS.F.F. to 0 1: Operate TM6BC, T.F.F., RS.F.F. 00: Up counter 01: Down counter 10: Up when TM6IOA pin is high, down when TM6IOA pin is low 11: Up when TM6IOB pin is high, down when TM6IOB pin is low Selecting up/down counting mode is ignored when twophase encoding is slected. 11:10 Up/Down Counter Mode Selection (Ignored when twophase encoding is selected.) I J K 9 Count Start External Trigger Enable 0: Disable 1: Enable Counting starts on the falling edge of TM6IOB pin. Clear TM6EN when TM6BC matches TM6CA. L M N O P Q 8 7:6 Counter Operating Mode Select 0: Repeat TM6CA, TM6CB Operating Mode Selection 1: One-shot counting 00: Compare register (single buffer) 01: Compare register (double buffer) 10: Capture A when TM6IOA pin is high, Capture B when TM6IOA pin is low 11: Capture A when TM6IOA pin is high, Capture B when TM6IOB pin is high During repeat counting, hold the TM6EN flag state. During oneshot counting, set the TM6EN flag to 0 when TM6BC=TM6CA. 5 4 TM6BC Clear When TM6IC is 1 TM6BC Clear/TM6CA Reload 0: Don't clear 1: Clear* * Clear TM6BC synchronizing externally. ** Clear TM6BC when PWM is output. R S T U V W X Y Z When TM6BC=TM6CA while up counting 0: Don't clear TM6BC 0: Don't reload TM6CA 1: Clear TM6BC** When TM6BC=0 while down counting 1: Reload TM6CA*** *** When TM6LP is 1 and upcounting is selected, TM6BC is cleared to 0 on the next cycle if TM6BC counts until TM6BC matches TM6CA or x'FFFF'. When down counting is selected, TM6BC is set to TM6CA on the next cycle regardless of this bit setting if TM6BC becomes 0. 3 TM6IOA Pin Output 0: RS.F.F. output (one-phase PWM) 1: T.F.F. output (two-phase PWM) 2:0 Clock Source Selection 000: Timer 4 output 001: Timer 5 output 010: TM6IOB pin clock 011: SYSCLK 100: Two-phase encoder (4x) of TM6IOA pin, TM6IOB pin 101: Two-phase encoder (1x) of TM6IOA pin, TM6IOB pin 11*: Reserved MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 239 Chapter 9 Appendix 15 14 13 12 11 10 9 8 TM6 BC8 R 0 0/1 7 TM6 BC7 R 0 0/1 6 TM6 BC6 R 0 0/1 5 TM6 BC5 R 0 0/1 4 TM6 BC4 R 0 0/1 3 TM6 BC3 R 0 0/1 2 TM6 BC2 R 0 0/1 1 TM6 BC1 R 0 0/1 0 TM6 BC0 R 0 0/1 TM6BC : x'00FE32' Timer 6 Binary Counter 16-bit access register TM6 TM6 TM6 TM6 TM6 TM6 TM6 BC15 BC14 BC13 BC12 BC11 BC10 BC9 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 15:0 Timer 6 Count Value TM6BC is a read-only register. 15 14 13 12 11 10 9 8 TM6 CA8 R/W 0 0/1 7 TM6 CA7 R/W 0 0/1 6 TM6 CA6 R/W 0 0/1 5 TM6 CA5 R/W 0 0/1 4 TM6 CA4 R/W 0 0/1 3 TM6 CA3 R/W 0 0/1 2 TM6 CA2 R/W 0 0/1 1 TM6 CA1 R/W 0 0/1 0 TM6 CA0 R/W 0 0/1 TM6CA : x'00FE34' Timer 6 Compare/ Capture Register A 16-bit access register TM6 TM6 TM6 TM6 TM6 TM6 TM6 CA15 CA14 CA13 CA12 CA11 CA10 CA9 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15:0 Timer 6 Count Cycle Set the count cycle minus 1. When capture is selected, TM6CA reads the captured values and a timer 6 capture A interrupt is generated when capture occurs. When compare is selected, set the PWM cycle. When this register matches the timer 6 binary counter, a timer 6 capture A interrupt occurs. 15 14 13 12 11 10 9 8 TM6 CB8 R/W 0 0/1 7 TM6 CB7 R/W 0 0/1 6 TM6 CB6 R/W 0 0/1 5 TM6 CB5 R/W 0 0/1 4 TM6 CB4 R/W 0 0/1 3 TM6 CB3 R/W 0 0/1 2 TM6 CB2 R/W 0 0/1 1 TM6 CB1 R/W 0 0/1 0 TM6 CB0 R/W 0 0/1 TM6CB : x'00FE38' Timer 6 Compare/ Capture Register B 16-bit access register TM6 TM6 TM6 TM6 TM6 TM6 TM6 CB15 CB14 CB13 CB12 CB11 CB10 CB9 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15:0 Timer 6 PWM Change or Interrupt Generation When capture is selected, TM6CB reads the captured values and a timer 6 capture B interrupt is generated when capture occurs. When compare is selected, set the PWM cycle. When this register matches the timer 6 binary counter, a timer 6 capture B interrupt occurs. 240 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H 15 14 13 R 0 0 12 R 0 0 11 TM7 UD1 R/W 0 0/1 10 TM7 UD0 R/W 0 0/1 9 8 7 6 5 4 3 2 1 TM7 S1 R/W 0 0/1 0 TM7 S0 R/W 0 0/1 TM7MD : x'00FE40' Timer 7 Mode Register 16-bit access register TM7 TM7 EN NLD R/W 0 0/1 R/W 0 0/1 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TGE ONE MD1 MD0 ECLR LP ASEL S2 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15 14 TM7BC Count TM7BC, T.F.F., RS.F.F. Operation 0: Disable 1: Enable 0: Set TM7BC, T.F.F., RS.F.F. to 0 1: Operate TM7BC, T.F.F., RS.F.F. 00: Up counter 01: Down counter 10: Up when TM7IOA pin is high, down when TM7IOA pin is low 11: Up when TM7IOB pin is high, down when TM7IOB pin is low Selecting up/down counting mode is ignored when twophase encoding is slected. 11:10 Up/Down Counter Mode Selection (Ignored when twophase encoding is selected.) I J K 9 Count Start External Trigger Enable 0: Disable 1: Enable Counting starts on the falling edge of TM7IOB pin. Clear TM7EN when TM7BC matches TM7CA. L M N O P Q 8 7:6 Counter Operating Mode Select 0: Repeat TM7CA, TM7CB Operating Mode Selection 1: One-shot counting 00: Compare register (single buffer) 01: Compare register (double buffer) 10: Capture A when TM7IOA pin is high, Capture B when TM7IOA pin is low 11: Capture A when TM7IOA pin is high, Capture B when TM7IOB pin is high During repeat counting, hold the TM7EN flag state. During oneshot counting, set the TM7EN flag to 0 when TM7BC=TM7CA. 5 4 TM7BC Clear When TM6IC is 1 TM7BC Clear/TM7CA Reload 0: Don't clear 1: Clear* * Clear TM7BC synchronizing externally. ** Clear TM7BC when PWM is output. *** When TM7LP is 1 and upcounting is selected, TM7BC is cleared to 0 on the next cycle if TM7BC counts until TM7BC matches TM7CA or x'FFFF'. When down counting is selected, TM7BC is set to TM7CA on the next cycle regardless of this bit setting if TM7BC becomes 0. R S T U V W X Y Z When TM7BC=TM7CA while up counting 0: Don't clear TM7BC 0: Don't reload TM7CA 1: Clear TM7BC** 1: ReloadTM7CA*** When TM7BC=0 while down counting 3 TM7IOA Pin Output 0: RS.F.F. output (one-phase PWM) 1: T.F.F. output (two-phase PWM) 2:0 Clock Source Selection 000: Timer 4 output 001: Timer 5 output 010: TM7IOB pin clock 011: SYSCLK 100: Two-phase encoder (4x) of TM7IOA pin, TM7IOB pin 101: Two-phase encoder (1x) of TM7IOA pin, TM7IOB pin 11*: Reserved MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 241 Chapter 9 Appendix 15 14 13 12 11 10 9 8 TM7 BC8 R 0 0/1 7 TM7 BC7 R 0 0/1 6 TM7 BC6 R 0 0/1 5 TM7 BC5 R 0 0/1 4 TM7 BC4 R 0 0/1 3 TM7 BC3 R 0 0/1 2 TM7 BC2 R 0 0/1 1 TM7 BC1 R 0 0/1 0 TM7 BC0 R 0 0/1 TM7BC : x'00FE42' Timer 7 Binary Counter 16-bit access register TM7 TM7 TM7 TM7 TM7 TM7 TM7 BC15 BC14 BC13 BC12 BC11 BC10 BC9 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 R 0 0/1 15:0 Timer 7 Count Value TM7BC is a read-only register. 15 14 13 12 11 10 9 8 TM7 CA8 R/W 0 0/1 7 TM7 CA7 R/W 0 0/1 6 TM7 CA6 R/W 0 0/1 5 TM7 CA5 R/W 0 0/1 4 TM7 CA4 R/W 0 0/1 3 TM7 CA3 R/W 0 0/1 2 TM7 CA2 R/W 0 0/1 1 TM7 CA1 R/W 0 0/1 0 TM7 CA0 R/W 0 0/1 TM7CA : x'00FE44' Timer 7 Compare/ Capture Register A 16-bit access register TM7 TM7 TM7 TM7 TM7 TM7 TM7 CA15 CA14 CA13 CA12 CA11 CA10 CA9 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15:0 Timer 7 Count Cycle Set the count cycle minus 1. When capture is selected, TM7CA reads the captured values and a timer 7 capture A interrupt is generated when capture occurs. When compare is selected, set the PWM cycle. When this register matches the timer 7 binary counter, a timer 7 capture A interrupt occurs. 15 14 13 12 11 10 9 8 TM7 CB8 R/W 0 0/1 7 TM7 CB7 R/W 0 0/1 6 TM7 CB6 R/W 0 0/1 5 TM7 CB5 R/W 0 0/1 4 TM7 CB4 R/W 0 0/1 3 TM7 CB3 R/W 0 0/1 2 TM7 CB2 R/W 0 0/1 1 TM7 CB1 R/W 0 0/1 0 TM7 CB0 R/W 0 0/1 TM7CB : x'00FE48' Timer 7 Compare/ Capture Register B 16-bit access register TM7 TM7 TM7 TM7 TM7 TM7 TM7 CB15 CB14 CB13 CB12 CB11 CB10 CB9 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 15:0 Timer 7 PWM Change or Interrupt Generation When capture is selected, TM7CB reads the captured values and a timer 7 capture B interrupt is generated when capture occurs. When compare is selected, set the PWM cycle. When this register matches the timer 7 binary counter, a timer 7 capture B interrupt occurs. 242 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WBSWP : x'00FFA0' Word Data Byte Swap Register 8/16-bit access register WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP- WBSWP WBSWP 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 15:0 Word Data Byte Swap Data During read operations, the upper 8 bits and the lower 8 bits are swapped. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBSWPL : x'00FFA2' Pointer Data Byte Swap Register (Lower) 8/16-bit access register PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I J K L M N O P Q R S T U V W X Y Z R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 15:0 Pointer Data Byte Swap Data During read operations, the upper 8 bits are remain and the lower 8 bits of PBSWPH are read out in the lower 8 bits. 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 PBSWPH : x'00FFA4' Pointer Data Byte Swap Register (Upper) 8/16-bit access register PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 23 22 21 20 19 18 17 16 - - - - - - - - R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 7 6 5 4 3 2 1 0 7:0 Pointer Data Byte Swap Data During read operations, the lower 8 bits of PBSWPL are read out in the upper 8 bits. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBSWPL : x'00FFA6' Long-word Data Byte Swap Register (Lower) 8/16-bit access register LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 15:0 Long-word Data Byte Swap Data During read operations, the lower 8 bits of LBSWPH are read out in the upper 8 bits and the upper 8 bits of LBSWPH are read out in the lower 8 bits. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 243 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBSWPH : x'00FFA8' Long-word Data Byte Swap Register (Upper) 8/16-bit access register LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 15:0 Long-word Data Byte Swap Data During read operations, the lower 8 bits of LBSWPL are read out in the upper 8 bits and the upper 8 bits of LBSWPL are read out in the lower 8 bits. 244 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DHP R/W 0 0/1 0 DLP R/W 0 0/1 PPLU : x'00FFB0' Port Pullup Control Register 16-bit access register Always set bit 15 to 0. *Note SB1P SB0P PA4P PA3P PA2P PA1P PA0P CSP REWEP P60P AHP AMP ALP R 0 0 R/W 0 0/1 R/W 0 0/1 R/w 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 *Note: Always set 0. 14 Pullup Resistors of Serial 1 Related Pins (SBT1, SBI1, SBO1) 0: Off 1: On 13 Pullup Resistors of Serial 0 Related Pins (SBT0, SBI0, SBO0) Pullup Resistor of IRQ4 (PA4) Pullup Resistor of IRQ3 (PA3) Pullup Resistor of IRQ2 (PA2) Pullup Resistor of IRQ1 (PA1) Pullup Resistor of IRQ0 (PA0) Pullup Resistors of /CS3 to /CS0 Pullup Resistors of External Memory Related Pins (/RE, /BSTRE, /WEH, /WEL) 0: Off 1: On 12 11 10 9 8 7 6 0: Off 0: Off 0: Off 0: Off 0: Off 0: Off 0: Off 1: On 1: On 1: On 1: On 1: On 1: On 1: On 5 4 3 2 1 0 Pullup Resistor of WAIT (P60) Pullup Resistors of A23 to A16 Pullup Resistors of A15 to A8 Pullup Resistors of A7 to A0 Pullup Resistors of D15 to D8 Pullup Resistors of D7 to D0 0: Off 0: Off 0: Off 0: Off 0: Off 0: Off 1: On 1: On 1: On 1: On 1: On 1: On MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 245 Chapter 9 Appendix 7 6 5 4 3 2 1 0 P0OUT : x'00FFC0' Port 0 Output Register 8/16-bit access register P0 P0 P0 P0 P0 P0 P0 P0 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 0 Output 7 6 5 4 3 2 1 0 P1OUT : x'00FFC1' Port 1 Output Register 8-bit access register (16-bit access is possible from even address) P1 P1 P1 P1 P1 P1 P1 P1 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 1 Output 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P2OUT : x'00FFC2' Port 2 Output Register 8/16-bit access register 7:0 Port 2 Output 7 6 5 4 3 2 1 0 P3 P3 P3 P3 P3 P3 P3 P3 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P3OUT : x'00FFC3' Port 3 Output Register 8-bit access register (16-bit access is possible from even address) 7:0 Port 3 Output 246 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 7 6 5 4 3 2 1 0 P4OUT : x'00FFC4' Port 4 Output Register 8/16-bit access register P4 P4 P4 P4 P4 P4 P4 P4 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 4 Output 7 6 5 4 3 2 1 0 P5OUT : x'00FFC5' Port 5 Output Register 8-bit access register (16-bit access is possible from even address) P5 P5 P5 P5 P5 P5 P5 P5 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 5 Output 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 2 1 0 P6 P6 P6 P6 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P6OUT : x'00FFC6' Port 6 Output Register 8/16-bit access register 3:0 Port 6 Output MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 247 Chapter 9 Appendix 7 R 0 0 6 R 0 0 5 4 3 2 1 0 P7OUT : x'00FFC7' Port 7 Output Register 8-bit access register (16-bit access is possible from even address) P7 P7 P7 P7 P7 P7 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 5:0 Port 7 Output 7 6 5 4 3 2 1 0 P8OUT : x'00FFC8' Port 8 Output Register 8/16-bit access register P8 P8 P8 P8 P8 P8 P8 P8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 8 Output 7 6 5 4 3 2 1 0 P9OUT : x'00FFC9' Port 9 Output Register 8-bit access register (16-bit access is possible from even address) P9 P9 P9 P9 P9 P9 P9 P9 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Port 9 Output 7 R 0 0 6 R 0 0 5 4 3 2 1 0 PAOUT : x'00FFCA' Port A Output Register 8/16-bit access register PA PA PA PA PA PA OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 5:0 Port A Output 248 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H 7 P0 IN7 R Port 0/1 6 P0 IN6 R Port 0/1 5 P0 IN5 R Port 0/1 4 P0 IN4 R Port 0/1 3 P0 IN3 R Port 0/1 2 P0 IN2 R Port 0/1 1 P0 IN1 R Port 0/1 0 P0 IN0 R Port 0/1 P0IN : x'00FFD0' Port 0 Input Register 8/16-bit access register 7:0 Port 0 Input 7 P1 IN7 R Port 0/1 6 P1 IN6 R Port 0/1 5 P1 IN5 R Port 0/1 4 P1 IN4 R Port 0/1 3 P1 IN3 R Port 0/1 2 P1 IN2 R Port 0/1 1 P1 IN1 R Port 0/1 0 P1 IN0 R Port 0/1 P1IN : x'00FFD1' Port 1 Input Register 8-bit access register (16-bit access is possible from even address) I J K L M N O P Q R S T U V W X Y Z 7:0 Port 1 Input 7 P2 IN7 R Port 0/1 6 P2 IN6 R Port 0/1 5 P2 IN5 R Port 0/1 4 P2 IN4 R Port 0/1 3 P2 IN3 R Port 0/1 2 P2 IN2 R Port 0/1 1 P2 IN1 R Port 0/1 0 P2 IN0 R Port 0/1 P2IN : x'00FFD2' Port 2 Input Register 8/16-bit access register 7:0 Port 2 Input MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 249 Chapter 9 Appendix 7 P3 IN7 R Port 0/1 6 P3 IN6 R Port 0/1 5 P3 IN5 R Port 0/1 4 P3 IN4 R Port 0/1 3 P3 IN3 R Port 0/1 2 P3 IN2 R Port 0/1 1 P3 IN1 R Port 0/1 0 P3 IN0 R Port 0/1 P3IN : x'00FFD3' Port 3 Input Register 8-bit access register (16-bit access is possible from even address) 7:0 Port 3 Input 7 P4 IN7 R Port 0/1 6 P4 IN6 R Port 0/1 5 P4 IN5 R Port 0/1 4 P4 IN4 R Port 0/1 3 P4 IN3 R Port 0/1 2 P4 IN2 R Port 0/1 1 P4 IN1 R Port 0/1 0 P4 IN0 R Port 0/1 P4IN : x'00FFD4' Port 4 Input Register 8/16-bit access register 7:0 Port 4 Input 7 P5 IN7 R Port 0/1 6 P5 IN6 R Port 0/1 5 P5 IN5 R Port 0/1 4 P5 IN4 R Port 0/1 3 P5 IN3 R Port 0/1 2 P5 IN2 R Port 0/1 1 P5 IN1 R Port 0/1 0 P5 IN0 R Port 0/1 P5IN : x'00FFD5' Port 5 Input Register 8-bit access register (16-bit access is possible from even address) 7:0 Port 5 Input 250 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 P6 IN3 R Port 0/1 2 P6 IN2 R Port 0/1 1 P6 IN1 R Port 0/1 0 P6 IN0 R Port 0/1 P6IN : x'00FFD6' Port 6 Input Register 8/16-bit access register 3:0 Port 6 Input 7 R 1 1 6 R 1 1 5 P7 IN5 R Port 0/1 4 P7 IN4 R Port 0/1 3 P7 IN3 R Port 0/1 2 P7 IN2 R Port 0/1 1 P7 IN1 R Port 0/1 0 P7 IN0 R Port 0/1 P7IN : x'00FFD7' Port 7 Input Register 8-bit access register (16-bit access is possible from even address) I J K L M N O P Q R S T U V W X Y Z 5:0 Port 7 Input 7 P8 IN7 R Port 0/1 6 P8 IN6 R Port 0/1 5 P8 IN5 R Port 0/1 4 P8 IN4 R Port 0/1 3 P8 IN3 R Port 0/1 2 P8 IN2 R Port 0/1 1 P8 IN1 R Port 0/1 0 P8 IN0 R Port 0/1 P8IN : x'00FFD8' Port 8 Input Register 8/16-bit access register 7:0 Port 8 Input 7 P9 IN7 R Port 0/1 6 P9 IN6 R Port 0/1 5 P9 IN5 R Port 0/1 4 P9 IN4 R Port 0/1 3 P9 IN3 R Port 0/1 2 P9 IN2 R Port 0/1 1 P9 IN1 R Port 0/1 0 P9 IN0 R Port 0/1 P9IN : x'00FFD9' Port 9 Input Register 8-bit access register (16-bit access is possible from even address) 7:0 Port 9 Input MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 251 Chapter 9 Appendix 7 R 0 0 6 NMI R NMI 0/1 5 PA IN5 R Port 0/1 4 PA IN4 R Port 0/1 3 PA IN3 R Port 0/1 2 PA IN2 R Port 0/1 1 PA IN1 R Port 0/1 0 PA IN0 R Port 0/1 PAIN : x'00FFDA' Port A Input Register 8-bit access register (16-bit access is possible from even address) Bit 6 is the level of /NMI pin. 5:0 Port A Input 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 R 0 0 0 P0 DIR0 R/W 0 0/1 P0DIR : x'00FFE0' Port 0 Input/Output Control Register 8/16-bit access register 0 All Pin Input/Output of Port 0 0: Input 1: Output Setting 1 is allowed only when port 0 is used. 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 R 0 0 0 P1 DIR0 R/W 0 0/1 P1DIR : x'00FFE1' Port 1 Input/Output Control Register 8-bit access register (16-bit access is possible from even address) Setting 1 is allowed only when port 1 is used. 0 All Pin Input/Output of Port 1 0: Input 1: Output 252 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I 7 R 0 0 6 R 0 0 5 R 0 0 4 P2 DIR4 R/W 0 0/1 3 R 0 0 2 R 0 0 1 R 0 0 0 P2 DIR0 R/W 0 0/1 P2DIR : x'00FFE2' Port 2 Input/Output Control Register 8/16-bit access register 4 Bits [7:4] Input/Output of Port 2 0: Input 1: Output Selecting 1 is not allowed in address/data separated mode during processor mode. 0 Bits [3:0] Input/Output of Port 2 0: Input 1: Output 7 6 5 4 3 2 1 0 P3 P3 P3 P3 P3 P3 P3 P3 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P3DIR : x'00FFE3' Port 3 Input/Output Control Register 8-bit access register (16-bit access is possible from even address) Selecting 1 is not allowed in address/data separated mode during processor mode. J K L M N O P Q R S T U V W X Y Z 7:0 Each Pin Input/Output of Port 3 0: Input 1: Output 7 6 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 P4 P4 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P4DIR : x'00FFE4' Port 4 Input/Output Control Register 8/16-bit access register 7:0 Each Pin Input/Output of Port 4 0: Input 1: Output Selecting 1 is not allowed in address/data separated mode during processor mode. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 253 Chapter 9 Appendix 7 6 5 4 3 2 1 0 P5DIR : x'00FFE5' Port 5 Input/Output Control Register 8-bit access register (16-bit access is possible from even address) Setting 1 to bits[7:6] and bits[3:0] of this register is not allowed during processor mode. P5 P5 P5 P5 P5 P5 P5 P5 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Each Pin Input/Output of Port 5 0: Input 1: Output 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 2 1 0 P6 P6 P6 P6 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P6DIR : x'00FFE6' Port 6 Input/Output Control Register 8/16-bit access register 3:0 Each Pin Input/Output of Port 6 0: Input 1: Output Setting 1 to bits[3:1] of this register is not allowed during processor mode. 7 6 5 4 3 2 1 0 *Note *Note R 0 0 R 0 0 P7 P7 P7 P7 P7 P7 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P7DIR : x'00FFE7' Port 7 Input/Output Control Register 8-bit access register (16-bit access is possible from even address) *Note: Always set 0. 5:0 Each Pin Input/Output of Port 7 0: Input 1: Output 254 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I 7 6 5 4 3 2 1 0 P8DIR : x'00FFE8' Port 8 Input/Output Control Register 8/16-bit access register P8 P8 P8 P8 P8 P8 P8 P8 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7:0 Each Pin Input/Output of Port 8 0: Input 1: Output 7 6 5 4 3 2 1 0 P9 P9 P9 P9 P9 P9 P9 P9 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 P9DIR : x'00FFE9' Port 9 Input/Output Control Register 8-bit access register (16-bit access is possible from even address) J K L M N O P Q R S T U V W X Y Z 7:0 Each Pin Input/Output of Port 9 0: Input 1: Output 7 R 0 0 6 R 0 0 5 4 3 2 1 0 PA PA PA PA PA PA DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 PADIR : x'00FFEA' Port A Input/Output Control Register 8/16-bit access register 5:0 Each Pin Input/Output of Port A 0: Input 1: Output MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 255 Chapter 9 Appendix 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 R 0 0 0 P0 MD0 R/W 0 0/1 P0MD : x'00FFF0' Port 0 Output Mode Register 8/16-bit access register 0 Port 0 Output 0: P07 to P00 Output 1: D7 to D0 (AD7 to AD0) I/O P0MD is valid and used as a port when /WORD pin = 'H' and MEMMDn[8] (n=1 to 3) = 'H'. 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 R 0 0 1 R 0 0 0 P1 MD0 R/W 0 0/1 P1MD : x'00FFF1' Port 1 Output Mode Register 8-bit access register (16-bit access is possible from even address) P1MD is invalid during processor mode. 0 Port 1 Output 0: P17 to P10 Output 1: D15 to D8 (AD15 to AD8) I/O 7 R 0 0 6 R 0 0 5 R 0 0 4 P2 MD4 R/W 0 0/1 3 R 0 0 2 R 0 0 1 R 0 0 0 P2 MD0 R/W 0 0/1 P2MD : x'00FFF2' Port 2 Output Mode Register 8/16-bit access register 4 Port 2 Output 0: P27 to P24 Output 1: A07 to A04 Output P2MD is invalid in address/data separated mode during processor mode. 0 Port 2 Output 0: P23 to P20 Output 1: A03 to A00 Output 256 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y 7 6 5 4 3 2 1 0 P3MD : x'00FFF3' Port 3 Output Mode Register 8-bit access register (16-bit access is possible from even address) P3MD is invalid in address/data separated mode during processor mode. P3 P3 P3 P3 P3 P3 P3 P3 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7 6 5 4 3 2 1 0 Port 3 Output Port 3 Output Port 3 Output Port 3 Output Port 3 Output Port 3 Output Port 3 Output Port 3 Output 0: P37 output 0: P36 output 0: P35 output 0: P34 output 0: P33 output 0: P32 output 0: P31 output 0: P30 output 1: A15 output 1: A14 output 1: A13 output 1: A12 output 1: A11 output 1: A10 output 1: A09 output 1: A08 output 7 6 5 4 3 2 1 0 P4MD : x'00FFF4' Port 4 Output Mode Register 8/16-bit access register P4 P4 P4 P4 P4 P4 P4 P4 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7 Port 4 Output 0: P47 output 1: A23 output or WDOUT output* Bits[5:0] of P4MD are invalid during processor mode. * Selection is determined by setting with P6MD. 6 Port 4 Output 0: P46 output 1: A22 output or STOP output* 5 4 3 2 1 0 Port 4 Output Port 4 Output Port 4 Output Port 4 Output Port 4 Output Port 4 Output 0: P45 output 0: P44 output 0: P43 output 0: P42 output 0: P41 output 0: P40 output 1: A21 output 1: A20 output 1: A19 output 1: A18 output 1: A17 output 1: A16 output Z MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 257 Chapter 9 Appendix 7 R 0 0 6 5 4 3 2 1 0 P5MD : x'00FFF5' Port 5 Output Mode Register 8-bit access register (16-bit access is possible from even address) Bits[6, 3:0] of P5MD are invalid during processor mode. P5 P5 P5 P5 P5 P5 P5 MD6 MD5 MD4 MD3 MD2 MD1 MD0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 6 Port 5 Output 0: P56 output 1: /BSTRE output (address/data separated mode) 0: P56 output 1: ALE (/ALE) output (address/data shared mode) 5 4 3 2 1 0 7 Port 5 Output Port 5 Output Port 5 Output Port 5 Output Port 5 Output Port 5 Output 6 5 R 0 0 4 R 0 0 3 2 1 0: P55 output 0: P54 output 0: P53 output 0: P52 output 0: P51 output 0: P50 output 0 R 0 0 1: /BRACK output 1: /BREQ Input 1: /CS3 output 1: /CS2 output 1: /CS1 output 1: /CS0 output P6MD : x'00FFF6' Port 6 Output Mode Register 8/16-bit access register P6 P6 MD7 MD6 R/W 0 0/1 R/W 0 0/1 P6 P6 P6 MD3 MD2 MD1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7 6 3 2 1 Selection When P4MD7 is High Selection When P4MD6 is High Port 6 Output Port 6 Output Port 6 Output 0: A23 output 0: A22 output 0: P63 output 0: P62 output 0: P61 output 1: WDOUT output 1: STOP output 1: /WEH output 1: /WEL output 1: /RE output Bits[3:1] of P6MD are invalid during processor mode. 258 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 7 R 0 0 6 R 0 0 5 P7 MD5 R/W 0 0/1 4 R 0 0 3 2 1 R 0 0 0 P7 MD0 R/W 0 0/1 P7MD : x'00FFF7' Port 7 Output Mode Register 8-bit access register (16-bit access is possible from even address) P7 P7 MD3 MD2 R/W 0 0/1 R/W 0 0/1 5 3 2 0 Port 7 Output Port 7 Output Port 7 Output Port 7 Output 0: P75 output 0: P73 output 0: P72 output 0: P70 output 1: SBO1 output 1: SBT1 output 1: SBO0 output 1: SBT0 output 7 6 5 4 3 2 1 0 P8MD : x'00FFF8' Port 8 Output Mode Register 8/16-bit access register P8 P8 P8 P8 P8 P8 P8 P8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 R/W 0 0/1 7 6 5 4 3 2 1 0 Port 8 Output Port 8 Output Port 8 Output Port 8 Output Port 8 Output Port 8 Output Port 8 Output Port 8 Output 0: P87 output 0: P86 output 0: P85 output 0: P84 output 0: P83 output 0: P82 output 0: P81 output 0: P80 output 1: TM6IOB output 1: TM6IOA output 1: TM5IO output 1: TM4IO output 1: TM3IO output 1: TM2IO output 1: TM1IO output 1: TM0IO output MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 259 Chapter 9 Appendix 7 R 0 0 6 R 0 0 5 R 0 0 4 R 0 0 3 R 0 0 2 1 0 R 0 0 P9MD : x'00FFF9' Port 9 Output Mode Register 8-bit access register (16-bit access is possible from even address) P9 P9 MD2 MD1 R/W 0 0/1 R/W 0 0/1 2 1 Port 9 Output Port 9 Output 0: P92 output 0: P91 output 1: TM7IOB output 1: TM7IOA output 260 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 261 262 9-2-2 Address Map (1/2) B A 9 8 7 6 5 4 3 2 1 0 CPUM MEMMD0 x Lower 4bit Chapter 9 Appendix Upper 20bit F Remarks MEMCTR E MEMMD1 x x G0ICR G1ICR (VCT=2) (VCT=0) D C x'00FC00' IAGR x Internal control reg. Memory register Interrupt control registers x External memory Control register x'00FC30' x G4ICR G5ICR x (VCT=10) (VCT=8) x'00FC40' EXTMD EXMCTR ATCBC x See Note x G6ICR x G7ICR (VCT=14) (VCT=12) MEMMD3 G3ICR x (VCT=6) MEMMD2 x G2ICR (VCT=4) x'00FC50' x'00FD00' x'00FD10' No Access ATCCTR x ATC registers x'00FD70' SC0STR SC0TRB x x x'00FD80' SC0CTR SC1CTR x x MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G x'00FD90' SC1STR SC1TRB Serial interfaces 2 channels x'00FDA0' x x x x AN7BUF AN6BUF AN5BUF AN4BUF AN3BUF AN2BUF AN1BUF AN0BUF ANCTR x A/D converter x x x TM5BC TM4BC TM3BC TM2BC TM1BC TM0BC x x x TM5BR TM4BR TM3BR TM2BR TM1BR TM0BR x x x TM5MD TM4MD TM3MD TM2MD TM1MD TM0MD Timer 8 channels x'00FE00' x'00FE10' x'00FE20' TM6CB TM7CB x'00FE30' TM6CA TM7CA TM6BC TM7BC TM6MD TM7MD x'00FE40' =16-bit access =8-bit access (16-bit access is possible from an even address.) No symbol = 8-bit access x =8/16-bit access Note: x'00FD72' and x'00FD73' are the system reserved area. Accessing those addresses is not allowed. If accessing those areas, the system operation cannot be guaranteed. (2/2) B A 9 8 7 6 5 4 3 2 1 0 x x x x x Lower 4bit Upper 20bit F LBSWPH LBSWPL PPLU x x E PB SWPH PBSWPL WBSWP D C Remarks x'00FFA0' x'00FFB0' PAOUT P9OUT P8OUT P7OUT P6OUT P5OUT P4OUT P3OUT P2OUT P1OUT P0OUT PAIN P3IN P2IN P1IN x x x x x'00FFC0' P9IN P8N P7IN P6IN P5IN P4IN x x x'00FFD0' P0IN x x x I/O port x'00FFE0' P9MD P8MD P7MD P6MD P5MD P4MD P3MD PADIR P9DIR P8DIR P7DIR P6DIR P5DIR P4DIR P3DIR P2DIR P1DIR P0DIR x'00FFF0' P2MD P1MD P0MD x = 8/16-bit access = 16-bit access = 8-bit access (16-bit access is possible from an even address.) No symbol = 8-bit access MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 263 Chapter 9 Appendix 9-2-3 List of Pin Functions EE = External excitation Pin Name P Q R S T U V W X 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P60,WAIT P61,RE P62,WEL P63,WEH P50,CS0 P51,CS1 P52,CS2 P53,CS3 P54,BREQ P55,BRACK P56,ALE,ALE,BSTRE P57,WORD P20,A00 P21,A01 P22,A02 P23,A03 VDD SYSCLK VSS XI XO VDD OSCI OSCO MODE P24,A04 P25,A05 P26,A06 P27,A07 P30,A08 P31,A09 P32,A10 P33,A11 VDD P34,A12 P35,A13 P36,A14 P37,A15 P40,A16 P41,A17 P42,A18 P43,A19 VSS P44,A20,AN4 P45,A21,AN5 P46,A22,STOP,AN6 P47,A23,WDOUT,AN7 P80,TM0IO P81,TM1IO P82,TM2IO Input level TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL CMOS TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog Analog Analog Analog CMOS*6 CMOS*6 CMOS*6 Output level CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Schmitt trigger Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes Pull-up register Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable RESET*1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z High High(EE) High(EE) High(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z RESET*2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z High High(EE) High(EE) Low(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z RESET*3 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z High High(EE) High(EE) Low(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z BREQ="L" * Hi-Z at RE Hi-Z at WEL Hi-Z at WEH Hi-Z at CS0 Hi-Z at CS1 Hi-Z at CS2 Hi-Z at CS3 Low Low Hi-Z except P56 STOP/HALT * Hi-Z at RE Hi-Z at WEL Hi-Z at WEH Hi-Z at CS0 Hi-Z at CS1 Hi-Z at CS2 Hi-Z at CS3 * * Hi-Z except P57 No No Programmable No Programmable Programmable Programmable Programmable * Hi-Z at A00 Hi-Z at A01 Hi-Z at A02 Hi-Z at A03 * * * MODE Hi-Z at A04 Hi-Z at A05 Hi-Z at A06 Hi-Z at A07 Hi-Z at A08 Hi-Z at A09 Hi-Z at A10 Hi-Z at A11 Hi-Z at A12 Hi-Z at A13 Hi-Z at A14 Hi-Z at A15 Hi-Z at A16 Hi-Z at A17 Hi-Z at A18 Hi-Z at A19 Hi-Z at A20 Hi-Z at A21 Hi-Z at A22 Hi-Z at A23 * * * * Hi-Z at A00 Hi-Z at A01 Hi-Z at A02 Hi-Z at A03 *4 *4 *5 MODE Hi-Z at A04 Hi-Z at A05 Hi-Z at A06 Hi-Z at A07 Hi-Z at A08 Hi-Z at A09 Hi-Z at A10 Hi-Z at A11 Hi-Z at A12 Hi-Z at A13 Hi-Z at A14 Hi-Z at A15 Hi-Z at A16 Hi-Z at A17 Hi-Z at A18 Hi-Z at A19 Hi-Z at A20 Hi-Z at A21 Hi-Z at A22 Hi-Z at A23 * * * No No Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No No 264 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P83,TM3IO P84,TM4IO P85,TM5IO VDD P86,TM6IOA P87,TM6IOB P90,TM6IC P91,TM7IOA P92,TM7IOB P93,TM7IC VSS P94,AN0 P95,AN1 P96,AN2 P97,AN3 VDD(VPP) P70,SBT0 P71,SBI0 P72,SBO0 P73,SBT1 P74,SBI1 P75,SBO1 Pull-up Pull-up NMI PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4 PA5,ADSEP RST VDD P00,D00,AD00 P01,D01,AD01 P02,D02,AD02 P03,D03,AD03 P04,D04,AD04 P05,D05,AD05 P06,D06,AD06 P07,D07,AD07 VSS P10,D08,AD08 P11,D09,AD09 P12,D10,AD10 P13,D11,AD11 P14,D12,AD12 P15,D13,AD13 P16,D14,AD14 P17,D15,AD15 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 Analog Analog Analog Analog CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 CMOS*6 TTL TTL TTL TTL TTL CMOS CMOS TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No Programmable Programmable Programmable Programmable Programmable Programmable Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NMI Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NMI Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HighInput) Low(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NMI Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low(Input) Low(Input) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z * * * * * * * * * * * * * * * * * * * NMI * * * * * * High Hi-Z except P00 Hi-Z except P01 Hi-Z except P02 Hi-Z except P03 Hi-Z except P04 Hi-Z except P05 Hi-Z except P06 Hi-Z except P07 * * * * * * * * * * * * * * * * * * * NMI * * * * * * High Hi-Z except P00 Hi-Z except P01 Hi-Z except P02 Hi-Z except P03 Hi-Z except P04 Hi-Z except P05 Hi-Z except P06 Hi-Z except P07 No Programmable Programmable Programmable Programmable Programmable No Always Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Hi-Z except P10 Hi-Z except P11 Hi-Z except P12 Hi-Z except P13 Hi-Z except P14 Hi-Z except P15 Hi-Z except P16 Hi-Z except P17 Hi-Z except P10 Hi-Z except P11 Hi-Z except P12 Hi-Z except P13 Hi-Z except P14 Hi-Z except P15 Hi-Z except P16 Hi-Z except P17 *: Depends on pin setting *1: Single-chip mode *2:Processor mode (Address/Data separated mode) *3: Processor mode (Address/Data shared mode) *4: High during STOP mode *5:High during STOP and HALT 1 mode *6:TTL in the MN102L490A MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 265 Chapter 9 Appendix 9-3 MN10200 Series Linear Addressing Version Instructions MN102L00 SERIES INSTRUCTION SET Instruction MOV Mnemonic MOV Dm,An MOV An,Dm MOV Dn,Dm MOV An,Am MOV PSW,Dn MOV Dn,PSW MOV MDR,Dn MOV Dn,MDR MOV (An),Dm MOV (d8,An),Dm MOV (d16,An),Dm MOV (d24,An),Dm MOV (Di,An),Dm MOV (abs16),Dn MOV (abs24),Dn MOV (An),Am MOV (d8,An),Am MOV (d16,An),Am MOV (d24,An),Am MOV (Di,An),Am MOV (abs16),An MOV (abs24),An MOV Dm,(An) MOV Dm,(d8,An) MOV Dm,(d16,An) MOV Dm,(d24,An) MOV Dm,(Di,An) MOV Dn,(abs16) MOV Dn,(abs24) MOV Am,(An) MOV Am,(d8,An) MOV Am,(d16,An) MOV Am,(d24,An) MOV Am,(Di,An) MOV An,(abs16) MOV An,(abs24) MOV imm8,Dn MOV imm16,Dn MOV imm24,Dn MOV imm16,An MOV imm24,An MOVX MOVX (d8,An),Dm MOVX (d16,An),Dm MOVX (d24,An),Dm MOVX Dm,(d8,An) MOVX Dm,(d16,An) MOVX Dm,(d24,An) MOVB MOVB (An),Dm MOVB (d8,An),Dm MOVB (d16,An),Dm MOVB (d24,An),Dm MOVB (Di,An),Dm MOVB (abs16),Dn MOVB (abs24),Dn MOVB Dm,(An) MOVB Dm,(d8,An) MOVB Dm,(d16,An) MOVB Dm,(d24,An) MOVB Dm,(Di,An) DmAn AnDm DnDm AnAm PSWDn DnPSW MDRDn DnMDR mem16(An)Dm mem16(An+d8)Dm mem16(An+d16)Dm mem16(An+d24)Dm mem16(An+Di)Dm mem16(abs16)Dn mem16(abs24)Dn mem24(An)Am mem24(An+d8)Am mem24(An+d16)Am mem24(An+d24)Am mem24(An+Di)Am mem24(abs16)An mem24(abs24)An Dmmem16(An) Dmmem16(An+d8) Dmmem16(An+d16) Dmmem16(An+d24) Dmmem16(An+Di) Dnmem16(abs16) Dnmem16(abs24) Ammem24(An) Ammem24(An+d8) Ammem24(An+d16) Ammem24(An+d24) Ammem24(An+Di) Anmem24(abs16) Anmem24(abs24) imm8Dn imm16Dn imm24Dn imm16An imm24An mem24(An+d8)Dm mem24(An+d16)Dm mem24(An+d24)Dm Dmmem24(An+d8) Dmmem24(An+d16) Dmmem24(An+d24) mem8(An)Dm mem8(An+d8)Dm mem8(An+d16)Dm mem8(An+d24)Dm mem8(An+Di)Dm mem8(abs16)Dn mem8(abs24)Dns Dmmem8(An) Dmmem8(An+d8) Dmmem8(An+d16) Dmmem8(An+d24) Dmmem8(An+Di) Operation OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code F2:30+Dm<<2+An F2:F0+An<<2+Dm 80+Dn<<2+Dm F2:70+An<<2+Am F3:F0+Dn F3:D0+Dn<<2 F3:E0+Dn F3:C0+Dn<<2 20+An<<2+Dm 60+An<<2+Dm:d8 F7:C0+An<<2+Dm:d16-l:d16-h F4:80+An<<2+Dm:d24-l:d24-m:d24-h F1:40+Di<<4+An<<2+Dm C8+Dn:abs16-l:abs16-h F4:C0+Dn:abs24-l:abs24-m:abs24-h *2 70+An<<2+Am:d8 F7:B0+An<<2+Am:d16-l:d16-h F4:F0+An<<2+Am:d24-l:d24-m:d24-h F1:00+Di<<4+An<<2+Am F7:30+An:abs16-l:abs16-h F4:D0+An:abs24-l:abs24-m:abs24-h 00+An<<2+Dm 40+An<<2+Dm:d8 F7:80+An<<2+Dm:d16-l:d16-h F4:00+An<<2+Dm:d24-l:d24-m:d24-h F1:C0+Di<<4+An<<2+Dm C0+Dn:abs16-l:abs16-h F4:40+Dn:abs24-l:abs24-m:abs24-h *3 50+An<<2+Am:d8 F7:A0+An<<2+Am:d16-l:d16-h F4:10+An<<2+Am:d24-l:d24-m:d24-h F1:80+Di<<4+An<<2+Am F7:20+An:abs16-l:abs16-h F4:50+An:abs24-l:abs24-m:abs24-h 80+Dn<<2+Dn:imm8 F8+Dn:imm16-l:imm16-h F4:70+Dn:imm24-l:imm24-m:imm24-h DC+An:imm16-l:imm16-h F4:74+An:imm24-l:imm24-m:imm24-h F5:70+An<<2+Dm:d8 F7:70+An<<2+Dm:d16-l:d16-h F4:B0+An<<2+Dm:d24-l:d24-m:d24-h F5:50+An<<2+Dm:d8 F7:60+An<<2+Dm:d16-l:d16-h F4:30+An<<2+Dm:d24-l:d24-m:d24-h *4 F5:20+An<<2+Dm:d8 F7:D0+An<<2+Dm:d16-l:d16-h F4:A0+An<<2+Dm:d24-l:d24-m:d24-h F0:40+Di<<4+An<<2+Dm *5 F4:C4+Dn:abs24-l:abs24-m:abs24-h 10+Dm<<2+An F5:10+An<<2+Dm:d8 F7:90+An<<2+Dm:d16-l:d16-h F4:20+An<<2+Dm:d24-l:d24-m:d24-h F0:C0+Di<<4+An<<2+Dm *1 - - - - 0 - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 2 1 2 2 2 2 2 1 2 4 5 2 3 5 2 2 4 5 2 4 5 1 2 4 5 2 3 5 2 2 4 5 2 4 5 2 3 5 3 5 3 4 5 3 4 5 2 3 4 5 2 4 5 1 3 4 5 2 2 2 1 2 2 3 2 2 1 1 2 3 2 1 3 2 2 3 4 3 3 4 1 1 2 3 2 1 3 2 2 3 4 3 3 4 1 1 3 1 3 3 3 4 3 3 4 2 2 2 3 2 2 3 1 2 2 3 2 - 0 - S S S S S S S - - - - - - - - - - - - - - - - - - - - - S S - 0 - - - - - - - S S S S S S S - - - - - Notes: *1 *2 *3 *4 *5 It is not possible to specify that Dn=Dm. This instruction is supported by the assembler. For "MOV (d8,An),Am" the assembler will generate a bit pattern for d8=0. This instruction is supported by the assembler. For "MOV Am,(d8,An)" the assembler will generate a bit pattern for d8=0. This instruction is supported by the assembler. The assembler generates bit patterns for the two instructions "MOVBU (An),Dm" and "EXTXB Dm". This instruction is supported by the assembler. The assembler generates bit patterns for the two instructions "MOVBU (abs16),Dn" and "EXTXB Dn". 266 MN10200 Series Linear Addressing Version Instructions Chapter 9 Appendix Instruction MOVB MOVBU Mnemonic MOVB Dn,(abs16) MOVB Dn,(abs24) MOVBU (An),Dm MOVBU (d8,An),Dm MOVBU (d16,An),Dm MOVBU (d24,An),Dm MOVBU (Di,An),Dm MOVBU (abs16),Dn MOVBU (abs24),Dn EXT EXT Dn Operation Dnmem8(abs16) Dnmem8(abs24) mem8(An)Dm mem8(An+d8)Dm mem8(An+d16)Dm mem8(An+d24)Dm mem8(An+Di)Dm mem8(abs16)Dn mem8(abs24)Dn If Dn.bp15=0, x'0000'MDR If Dn.bp15=1, x'FFFF'MDR EXTX EXTX Dn If Dn.bp15=0, Dn&x'00FFFF'Dn If Dn.bp15=1, Dn|x'FF0000'Dn EXTXU EXTXB EXTXU Dn EXTXB Dn Dn&x'00FFFF'Dn If Dn.bp7=0 Dn&x'0000FF'Dn If Dn.bp7=1 Dn|x'FFFF00'Dn EXTXBU EXTXBU Dn ADD ADD Dn,Dm ADD Dm,An ADD An,Dm ADD An,Am ADD imm8,Dn ADD imm16,Dn ADD imm24,Dn ADD imm8,An ADD imm16,An ADD imm24,An ADDC ADDNF SUB ADDC Dn,Dm ADDNF imm8,An SUB Dn,Dm SUB Dm,An SUB An,Dm SUB An,Am SUB imm16,Dn SUB imm24,Dn SUB imm16,An SUB imm24,An SUBC MUL MULU DIVU SUBC Dn,Dm MUL Dn,Dm MULU Dn,Dm DIVU Dn,Dm Dn&x'0000FF'Dn Dm+DnDm An+DmAn Dm+AnDm Am+AnAm Dn+imm8Dn Dn+imm16Dn Dn+imm24Dn An+imm8An An+imm16An An+imm24An Dm+Dn+CFDm An+imm8An Dm-DnDm An-DmAn Dm-AnDm Am-AnAm Dn-imm16Dn Dn-imm24Dn An-imm16An An-imm24An Dm-Dn-CFDm DmxDnDm (DmxDn)>>16MDR DmxDnDm (DmxDn)>>16MDR (MDR<<16+Dm)/DnDm *** MDR 0 0 S S OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code C4+Dn:abs16-l:abs16-h F4:44+Dn:abs24-l:abs24-m:abs24-h 30+An<<2+Dm F5:30+An<<2+Dm:d8 F7:50+An<<2+Dm:d16-l:d16-h F4:90+An<<2+Dm:d24-l:d24-m:d24-h F0:80+Di<<4+An<<2+Dm CC+Dn:abs16-l:abs16-h F4:C8+Dn:abs24-l:abs24-m:abs24-h F3:C1+Dn<<2 *6 - - 0 0 0 0 0 0 0 S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 5 1 3 4 5 2 3 5 2 1 3 1 2 2 3 2 1 3 3 - - - - - - - - 1 1 B0+Dn *7 - - - - - - - - - - - - - - - - 1 1 1 1 B4+Dn B8+Dn *8 *9 - q q q q q q q q q q q - q q q q q q q q q ? ? ? - q q q q q q q q q q q - q q q q q q q q q ? ? ? - q q q q q q q q q q q - q q q q q q q q q ? ? - q q q q q q q q q q q - q q q q q q q q q ? ? - q q q q q q q q q q q - q q q q q q q q q 0 0 - q q q q q q q q q q q - q q q q q q q q q ? ? ? - q q q q q q q q q q q - q q q q q q q q q q q - q q q q q q q q q q q - q q q q q q q q q q q 1 1 2 2 2 2 4 5 2 4 5 2 3 1 2 2 2 4 5 4 5 2 2 2 2 1 1 2 2 2 1 2 3 1 2 3 2 2 1 2 2 2 2 3 2 3 2 12 12 13 BC+Dn 90+Dn<<2+Dm F2:00+Dm<<2+An F2:C0+An<<2+Dm F2:40+An<<2+Am D4+Dn:imm8 F7:18+Dn:imm16-l:imm16-h *10 - - - - S S - S S F4:60+Dn:imm24-l:imm24-m:imm24-h D0+An:imm8 F7:08+An:imm16-l:imm16-h F4:64+An:imm24-l:imm24-m:imm24-h F2:80+Dn<<2+Dm F5:0C+An:imm8 A0+Dn<<2+Dm F2:10+Dn<<2+An F2:D0+An<<2+Dm F2:50+An<<2+Am F7:1C+Dn:imm16-l:imm16-h F4:68+Dn:imm24-l:imm24-m:imm24-h F7:0C+An:imm16-l:imm16-h F4:6C+An:imm24-l:imm24-m:imm24-h F2:90+Dn<<2+Dm F3:40+Dn<<2+Dm F3:50+Dn<<2+Dm F3:60+Dn<<2+Dm *12 *13 *14 *11 - - S - - - - S - S - - - - - q/? q/? 0/1 q/? q/? Notes: *6 *7 *8 *9 *10 *11 *12 *13 *14 32-bit sign extended word data 24-bit sign extended word data 24-bit zero extended word data 24-bit sign extended byte data 24-bit zero extended byte data Addition without changing flag 16x16 = 32 (signed) 16x16 = 32 (unsigned) 32/16 = 16...16 (unsigned) MN10200 Series Linear Addressing Version Instructions 267 Chapter 9 Appendix Instruction CMP Mnemonic CMP Dn,Dm CMP Dm,An CMP An,Dm CMP An,Am CMP imm8,Dn CMP imm16,Dn CMP imm24,Dn CMP imm16,An CMP imm24,An AND AND Dn,Dm AND imm8,Dn AND imm16,Dn AND imm16,PSW OR OR Dn,Dm OR imm8,Dn OR imm16,Dn OR imm16,PSW XOR NOT ASR XOR Dn,Dm XOR imm16,Dn NOT Dn ASR Dn Dm-Dn An-Dm Dm-An Am-An Dn-imm8 Dn-imm16 Dn-imm24 An-imm16 An-imm24 Dm&(x'FF0000'|Dn)Dm Dn&(x'FF0000'|imm8)Dn Dn&(x'FF0000'|imm16)Dn PSW&imm16PSW Dm|(Dn&x'00FFFF')Dm Dn|imm8Dn Dn|imm16Dn PSW|imm16PSW Dm^(x'00FFFF'&Dn)Dm Dn^imm16Dn Dn^x'00FFFF'Dn Dn.lsbCF Dn.bpDn.bp-1(bp15 Dn.bp15Dn.bp15 LSR LSR Dn Dn.lsbCF Dn.bpDn.bp-1(bp15 0Dn.bp15 ROR ROR Dn Dn.lsbtemp Dn.bpDn.bp-1(bp15 CFDn.bp15 tempCF ROL ROL Dn Dn.bp15temp Dn.bpDn.bp+1(bp14 CFDn.lsb tempCF BTST BSET BCLR Bcc BTST imm8,Dn BTST imm16,Dn BSET Dm,(An) BCLR Dm,(An) BEQ label Dn&imm8 *** PSW Dn&imm16 *** PSW mem8(An)&Dm *** PSW mem8(An)|Dmmem8(An) mem8(An)&Dm *** PSW mem8(An)&(~Dm)mem8(An) If ZF=1, PC+2+d8(label)PC If ZF=0, PC+2PC BNE label If ZF=0, PC+2+d8(label)PC If ZF=1, PC+2PC BLT label If (VF^NF)=1, PC+2+d8(label)PC If (VF^NF)=0, PC+2PC 0 0 0 0 0) 1) 1) 1) Operation OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code F3:90+Dn<<2+Dm F2:20+Dm<<2+An F2:E0+An<<2+Dm F2:60+An<<2+Am D8+Dn:imm8 F7:48+Dn:imm16-l:imm16-h F4:78+Dn:imm24-l:imm24-m:imm24-h EC+An:imm16-l:imm16-h F4:7C+An:imm24-l:imm24-m:imm24-h F3:00+Dn<<2+Dm F5:00+Dn:imm8 F7:00+Dn:imm16-l:imm16-h F7:10:imm16-l:imm16-h F3:10+Dn<<2+Dm F5:08+Dn:imm8 F7:40+Dn:imm16-l:imm16-h F7:14:imm16-l:imm16-h F3:20+Dn<<2+Dm F7:4C+Dn:imm16-l:imm16-h F3:E4+Dn F3:38+Dn *15 *15 *15 *15 *15 *15 *15 *15 *15 *15 *15 *15 - - - - S S q q q q q q q q q - - - q - - - q - - - - q q q q q q q q q - - - q - - - q - - - - q q q q q q q q q - - - q - - - q - - - - q q q q q q q q q - - - q - - - q - - - - q q q q q q q q q 0 0 0 q q q q q q q q q 0 0 0 q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q 2 2 2 2 2 4 5 3 5 2 3 4 4 2 3 4 4 2 4 2 2 2 2 2 2 1 2 3 1 3 2 2 2 3 2 2 2 3 2 2 2 2 - 0 - - 0 - - - 0 q 0 0 0 q 0 0 0 - - - - - - q 0 0 0 0 q 0 0 0 q - - - - - 0 q 0 q 2 2 F3:3C+Dn *15 - - - - - 0 q q q 2 2 F3:34+Dn *15 - - - - - 0 q q q 2 2 F3:30+Dn *15 - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 q q q q - 3 4 2 2 2 2 2 5 5 2/1 F5:04+Dn:imm8 F7:04+Dn:imm16-l:imm16-h F0:20+An<<2+Dm F0:30+An<<2+Dm E8:d8 *16 *16 *17 q 0 0 - - - - - - - - - - - - - 2 2/1 E9:d8 *18 - - - - - - - - - 2 2/1 E0:d8 *19 Notes: *15 *16 *17 *18 *19 16-bit computation Performed under the conditions of bus lock and disabled interrupts. src=dest (lower 16 bits) srcdest (lower 16 bits) src>dest (lower 16 bits, signed) 268 MN10200 Series Linear Addressing Version Instructions Chapter 9 Appendix Instruction Bcc Mnemonic BLE label Operation If ((VF^NF)|ZF)=1, PC+2+d8(label)PC If ((VF^NF)|ZF)=0, PC+2PC BGE label If (VF^NF)=0, PC+2+d8(label)PC If (VF^NF)=1, PC+2PC BGT label If ((VF^NF)|ZF)=0, PC+2+d8(label)PC If ((VF^NF)|ZF)=1, PC+2PC BCS label If CF=1, PC+2+d8(label)PC If CF=0, PC+2PC BLS label If (CF|ZF)=1, PC+2+d8(label)PC If (CF|ZF)=0, PC+2PC BCC label If CF=0, PC+2+d8(label)PC If CF=1, PC+2PC BHI label If (CF|ZF)=0, PC+2+d8(label)PC If (CF|ZF)=1, PC+2PC BVC label If VF=0, PC+3+d8(label)PC If VF=1, PC+3PC BVS label If VF=1, PC+3+d8(label)PC If VF=0, PC+3PC BNC label If NF=0, PC+3+d8(label)PC If NF=1, PC+3PC BNS label If NF=1, PC+3+d8(label)PC If NF=0, PC+3PC BRA label Bccx BEQX label PC+2+d8(label)PC If ZX=1, PC+3+d8(label)PC If ZX=0, PC+3PC BNEX label If ZX=0, PC+3+d8(label)PC If ZX=1, PC+3PC OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code E3:d8 *20 - - - - - - - - - 2 2/1 - - - - - - - - - 2 2/1 E2:d8 *21 - - - - - - - - - 2 2/1 E1:d8 *22 - - - - - - - - - 2 2/1 E4:d8 *23 - - - - - - - - - 2 2/1 E7:d8 *24 - - - - - - - - - 2 2/1 E6:d8 *25 - - - - - - - - - 2 2/1 E5:d8 *26 - - - - - - - - - 3 3/2 F5:FC:d8 *27 - - - - - - - - - 3 3/2 F5:FD:d8 *28 - - - - - - - - - 3 3/2 F5:FE:d8 *29 - - - - - - - - - 3 3/2 F5:FF:d8 *30 - - - - - - - - - - - - - - - - - - 2 3 2 3/2 EA:d8 F5:E8:d8 *31 - - - - - - - - - 3 3/2 F5:E9:d8 *32 Notes: *20 *21 *22 *23 *24 *25 *26 *27 *28 *29 *30 *31 *32 srcdest (lower 16 bits, signed) srcdest (lower 16 bits, signed) src 269 Chapter 9 Appendix Instruction Bccx Mnemonic BLTX label Operation If (VX^NX)=1, PC+3+d8(label)PC If (VX^NX)=0, PC+3PC BLEX label If ((VX^NX)|ZX)=1, PC+3+d8(label)PC If ((VX^NX)|ZX)=0, PC+3PC BGEX label If (VX^NX)=0, PC+3+d8(label)PC If (VX^NX)=1, PC+3PC BGTX label If ((VX^NX)|ZX)=0, PC+3+d8(label)PC If ((VX^NX)|ZX)=1, PC+3PC BCSX label If CX=1, PC+3+d8(label)PC If CX=0, PC+3PC BLSX label If (CX|ZX)=1, PC+3+d8(label)PC If (CX|ZX)=0, PC+3PC BCCX label If CX=0, PC+3+d8(label)PC If CX=1, PC+3PC BHIX label If (CX|ZX)=0, PC+3+d8(label)PC If (CX|ZX)=1, PC+3PC BVCX label If VX=0, PC+3+d8(label)PC If VX=1, PC+3PC BVSX label If VX=1, PC+3+d8(label)PC If VX=0, PC+3PC BNCX label If NX=0, PC+3+d8(label)PC If NX=1, PC+3PC BNSX label If NX=1, PC+3+d8(label)PC If NX=0, PC+3PC JMP JMP label16 JMP label24 JMP (An) PC+3+d16(label16)PC PC+5+d24(label24)PC AnPC OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code F5:E0:d8 *33 - - - - - - - - - 3 3/2 - - - - - - - - - 3 3/2 F5:E3:d8 *34 - - - - - - - - - 3 3/2 F5:E2:d8 *35 - - - - - - - - - 3 3/2 F5:E1:d8 *36 - - - - - - - - - 3 3/2 F5:E4:d8 *37 - - - - - - - - - 3 3/2 F5:E7:d8 *38 - - - - - - - - - 3 3/2 F5:E6:d8 *39 - - - - - - - - - 3 3/2 F5:E5:d8 *40 - - - - - - - - - 3 3/2 F5:EC:d8 *41 - - - - - - - - - 3 3/2 F5:ED:d8 *42 - - - - - - - - - 3 3/2 F5:EE:d8 *43 - - - - - - - - - 3 3/2 F5:EF:d8 *44 - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 5 2 2 4 3 FC:d16-l:d16-h F4:E0:d24-l:d24-m:d24-h F0:An<<2 Notes: *33 *34 *35 *36 *37 *38 *39 *40 *41 *42 *43 *44 src>dest (24 bits, signed) srcdest (24 bits, signed) srcdest (24 bits, signed) src MN10200 Series Linear Addressing Version Instructions Chapter 9 Appendix Instruction JSR Mnemonic JSR label16 A3-4A3 PC+3mem24(A3) PC+3+d16(label16)PC Operation OP EX. VX Flag CX NX ZX VF CF NF Code ZF Size Cycle Machine Code FD:d16-l:d16-h - - - - - - - - - 3 4 JSR label24 A3-4A3 PC+5mem24(A3) PC+5+d24(label24)PC - - - - - - - - - 5 5 F4:E1:d24-l:d24-m:d24-h JSR (An) A3-4A3 PC+2mem24(A3) AnPC - - - - - - - - - 2 5 F0:01+An<<2 NOP RTS RTI NOP RTS RTI PC+1PC mem24(A3)PC A3+4A3 mem16(A3)PSW mem24(A3+2)PC A3+6A3 - - - - - q - - q - - q - - q - - q - - q - - q - - q 1 1 1 1 5 6 F6 FE EB How to Read INSTRUCTION SET s Explanation of symbols used in the chart Dn, Dm, Di An, Am MDR, PSW, PC imm8, imm16, imm16-l, imm16-h imm24, imm24-l, imm24-m, imm24-h d8, d16, d16-l, d16-h d24, d24-l, d24-m, d24-h abs16, abs16-l, abs16-h abs24, abs24-l, abs24-m, abs24-h mem8 (An), mem8 (abs16), mem8 (abs24) mem16 (An), mem16 (abs16), mem16 (abs24) mem24 (Am), mem24 (abs16), mem24 (abs24) .bp,.lsb,.msb &,I,^ ~, << VX, CX, NX, ZX VF, CF, NF, ZF temp , ... Data register Address register Multiplication and division register, program status word, program counter Constant Displacement Absolute address 8-bit memory data referenced at the address enclosed in parenthesis 16-bit memory data referenced at the address enclosed in parenthesis 24-bit memory data referenced at the address enclosed in parenthesis Bit specification Logical AND, logical OR, exclusive OR Bit reversal, bit shift Extended overflow flag, extended carry flag, extended negative flag, extended zero flag Overflow flag, carry flag, negative flag, zero flag Temporary register inside CPU Assignment, reflection of computation results s OP EX. (Operand Extension) O S - zero extension sign extension not applicable s Flag q - 0 1 ? change no change normally 0 normally 1 undefined s Code Size Unit: byte s Cycle The minimum number of cycles are specified. Unit: machine cycle a/b: there are branches in the 'a' cycle there are no branches in the 'b' cycle s Machine Code [:] separates the byte units. [<<2] indicates a 2-bit shift. Dn, Dm, Di, An, Am: register numbers D0 00 A0 00 D1 01 A1 01 D2 10 A2 10 D3 11 A3 11 s Notes * * Instructions that access 16-bit and 24-bit data must use an even memory address. All 8-bit displacements (d8) and 16-bit displacements (d16) are sign extended. MN10200 Series Linear Addressing Version Instructions 271 Chapter 9 Appendix MN102L00 SERIES INSTRUCTION MAP First Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F BLT label MOV Dm, (An) MOVB Dm, (An) MOV (An), Dm MOVBU (An), Dm MOV Dm, (d8, An) MOV Am (d8, An) MOV (d8, An), Dm MOV (d8, An), Am MOV Dn, Dm (When src=dest, MOV imm8, Dn) ADD Dn, Dm SUB Dn, Dm EXTX Dn MOV Dn, (abs16) ADD imm8, An BGT label BGE label BLE label BCS label (5 bytes) EXTXU Dn MOVB Dn, (abs16) ADD imm8, Dn BHI label (3 bytes) EXTXB Dn MOV (abs16),Dn CMP imm8, Dn BLS label Code extended EXTXBU Dn MOVBU (abs16),Dn MOV imm16, An RTI JMP label16 CMP imm16, An JSR label16 RTS BCC label NOP BEQ label BNE label BRA label Code extended (2 bytes) Code extended Code extended (4 bytes) MOV imm16, Dn Two-Byte Instructions (First byte: F0) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 JMP (A0) JSR (A0) JMP (A1) JSR (A1) JMP (A2) JSR (A2) JMP (A3) JSR (A3) BSET Dm, (An) BCLR Dm, (An) MOVB (Di, An), Dm 6 7 8 9 MOVBU (Di, An), Dm A B C D MOVB Dm, (Di, An) E F 272 MN10200 Series Linear Addressing Version Instructions Chapter 9 Appendix Two-Byte Instructions (First byte: F1) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 MOV (Di, An), Am 2 3 4 5 MOV (Di, An), Dm 6 7 8 9 MOV Am, (Di, An) A B C D MOV Dm, (Di, An) E F Two-Byte Instructions (First byte: F2) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F ADD Dm, An SUB Dm, An CMP Dm, An MOV Dm, An ADD An, Am SUB An, Am CMP An, Am MOV An, Am ADDC Dn, Dm SUBC Dn, Dm ADD An, Dm SUB An, Dm CMP An, Dm MOV An, Dm MN10200 Series Linear Addressing Version Instructions 273 Chapter 9 Appendix Two-Byte Instructions (First byte: F3) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F MOV D0, MDR MOV D0, PSW AND Dn, Dm OR Dn, Dm XOR Dn, Dm ROL Dn MUL Dn, Dm MULU Dn, Dm DIVU Dn, Dm ROR Dn ASR Dn LSR Dn CMP Dn, Dm EXT D0 MOV D1, MDR MOV D1, PSW EXT D1 MOV D2, MDR MOV D2, PSW EXT D2 MOV D3, MDR MOV D3, PSW EXT D3 MOV MDR, Dn MOV PSW, Dn NOT Dn Five-Byte Instructions (First byte: F4) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F MOV Dm, (d24, An) MOV Am, (d24, An) MOVB Dm, (d24, An) MOVX Dm, (d24, An) MOV Dn, (abs24) MOV An, (abs24) ADD imm24, Dn MOV imm24, Dn MOV (d24, An), Dm MOVBU (d24, An), Dm MOVB (d24, An), Dm MOVX (d24, An), Dm MOV (abs24), Dn MOV (abs24), An JSR JMP label24 label24 MOV (d24, An), Am MOVB (abs24), Dn MOVBU (abs24), Dn ADD imm24, An MOV imm24, An SUB imm24, Dn CMP imm24, Dn SUB imm24, An CMP imm24, An MOVB Dn, (abs24) 274 MN10200 Series Linear Addressing Version Instructions Chapter 9 Appendix Three-Byte Instructions (First byte: F5) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F BLTX label AND imm8, Dn MOVB Dm, (d8, An) MOVB (d8, An), Dm MOVBU (d8, An), Dm BTST imm8, Dn OR imm8, Dn ADDNF imm8, An MOVX Dm, (d8, An) MOVX (d8, An), Dm BGTX label BGEX label BLEX label BCSX label BHIX label BCCX label BLSX label BEQX label BNEX label BVCX label BVC label BVSX label BVS label BNCX label BNC label BNSX label BNS label Four-Byte Instructions (First byte: F7) Second Byte Upper/Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F AND imm16 PSW AND imm16, Dn OR imm16 PSW BTST imm16, Dn ADD imm16, An ADD imm16, Dn SUB imm16, An SUB imm16, Dn MOV An, (abs16) MOV (abs16), An OR imm16, Dn MOVBU (d16, An), Dm MOVX Dm,(d16, An) MOVX (d16, An), Dm MOV Dm,(d16, An) MOVB Dm,(d16, An) MOV Am,(d16, An) MOV (d16, An), Am MOV (d16, An), Dm MOVB (d16, An), Dm CMP imm16, Dn XOR imm16, Dn MN10200 Series Linear Addressing Version Instructions 275 Chapter 9 Appendix 9-4 Initialization Program After reset, the initialization program must be located in the CS0 area (x'010000' to x'3FFFFF). In the initialization program, set the number of wait cycles for Block 0 to the MEMMD0 register. Next, set the MEMCTR register. Always set bits [8:0] of the MEMCTR register to `100'. The number of wait cycles set in the MEMMD0 register is valid after setting the MEMCTR register. ; Initialization Program init equ * Setting the MEMMD0 register and the MEMCTR register must follow this step. If this step is not followed, writing to the MEMCTR register cannot be guaranteed. ; Memory Mode Setting for Block 0 mov MEM0_INIT,d0 mov d0,(Amemmd0) ; Handshake Mode Setting mov MEMCTR_INIT,d0 mov d0,(Amemctr) ; Pin Setting in Memory Expansion Mode or Processor Mode mov P01M_INIT,d0 mov d0,(Ap01md) mov P01D_INIT,d0 mov d0,(Ap01dir) mov P23M_INIT,d0 mov d0,(Ap23md) mov P23D_INIT,d0 mov d0,(Ap23dir) mov P45M_INIT,d0 mov d0,(Ap45md) mov P45D_INIT,d0 mov d0,(Ap45dir) mov P6M_INIT,d0 movb d0,(Ap6md) mov P6D_INIT,d0 movb d0,(Ap6dir) ; Memory Mode Setting for Block1, Block2, Block 3 mov MEM1_INIT,d0 mov d0,(Amemmd1) mov MEM2_INIT,d0 mov d0,(Amemmd2) mov MEM3_INIT,d0 mov d0,(Amemmd3) ; Burst ROM Setting mov EXMEM_INIT,d0 mov d0,(Aexmctr) Set the number of wait cycles for block 0 to the MEMMD0 register. Set bit 10 (HSWTIOE), bit 9 ( N WA I T I O E ) a n d b i t 8 (WAITSET) of the MEMCTR register to 1, 0 and 0 respectively. Recommend to write x'0410' to MEMCTR_INIT. Set pins. In the program, the following symbols and register addresses are equivalent. (Amemctr) = (x'FC02') (Amemmd0) = (x'FC30') (Amemmd1) = (x'FC32') (Amemmd2) = (x'FC34') (Amemmd3) = (x'FC36') (Aexmctr) = (x'FD00') (Ap01md) = (x'FFF0') (Ap01dir) = (x'FFE0') (Ap23md) = (x'FFF2') (Ap23dir) = (x'FFE2') (Ap45md) = (x'FFF4') (Ap45dir) = (x'FFE4') (Ap6md) = (x'FFF6') (Ap6dir) = (x'FFE6') Set the number of wait cycles for each block to the associated MEMMDn register. (n=1,2,3) Set the EXMCTR register when the burst ROM is used, the ALE signal polarity is changed, the pulse width of write enable signal is shortened. 276 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix ; Register Initialization mov d0,d0 mov d0,d1 mov d0,d2 mov d0,d3 mov d0,a0 mov d0,a1 mov d0,a2 mov STACK_TOP,a3 Clear register to 0. Execute this operation although this step is not always required. Set the initial value of the stack pointer. (Always set the even address.) ; Interrupt Enable mov INIT_PSW,d0 mov d0,psw When using an interrupt, set the interrupt mode and set the interrupt enable flag of PSW to 1 after setting the stack. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 277 Chapter 9 Appendix 9-5 EPROM Version 9-5-1 Overview The MN102LP25x (x: G, Z, A) replaces the MN102L25x (x: G, Z, A) mask ROM with the EPROM which is an electrically erasable/programmable memory. The MN102LP25x is sealed in plastic. Once the data is written to the PROM, the data cannot be erased. Using a dedicated adaptor socket, the program is written with the EPROM writer (EPROM parallel mode). s Features * Memory Capacity * Programming Methods * Pin 128 kbytes (64 k x 16 bits) ... MN102LP25G, MN102LP25Z 32 kbytes (16 k x 16 bits) ... MN102LP25A Word programming, Page programming 40 pins x'00000' x'00000' x'07FFF' EPROM [32 kbytes] MN102LP25A EPROM [128 kbytes] x'1FFFF' MN102LP25G MN102LP25Z Figure 9-5-1 Memory Map During EPROM Parallel Mode 278 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-5-2 Connecting Adaptor Socket When the CPU becomes the EPROM mode, the MN102LP25x stops and writes the program to EPROM. The following figure shows the connection of the dedicated adaptor socket and EPROM. When programming with the EPROM writer, the MN102LP25x must connect to the writer socket correctly. If the MN102LP25x and the writer socket do not connect correctly, the CPU may damage. VPP CE 1 2 40 VDD 39 PGM 38 NC 37 A15 36 A14 35 A13 34 A12 33 A11 32 A10 31 A9 30 Vss 29 A8 28 A7 27 A6 26 A5 25 A4 24 A3 23 A2 22 A1 21 A0 VPP CE 1 2 40 VDD 39 PGM 38 NC 37 NC 36 NC 35 A13 34 A12 33 A11 32 A10 31 A9 30 Vss 29 A8 28 A7 27 A6 26 A5 25 A4 24 A3 23 A2 22 A1 21 A0 I/O15 3 I/O14 4 I/O13 I/O12 I/O11 5 6 7 I/O15 3 I/O14 4 I/O13 I/O12 I/O11 5 6 7 I/O10 8 I/O9 9 I/O8 10 Vss 11 I/O7 12 I/O6 13 I/O5 14 I/O4 15 I/O3 16 I/O2 17 I/O1 18 I/O0 19 OE 20 I/O10 8 I/O9 9 I/O8 10 Vss 11 I/O7 12 I/O6 13 I/O5 14 I/O4 15 I/O3 16 I/O2 17 I/O1 18 I/O0 19 OE 20 Figure 9-5-2 Pin Configuration of Adaptor Socket MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 279 Chapter 9 Appendix I/O00 I/O01 I/O02 I/O03 I/O04 I/O05 I/O06 I/O07 I/O08 I/O09 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 OE PGM CE A0 A1 A2 OPEN VSS VDD * : Connect the MN102LP25A to VSS. Figure 9-5-3 EPROM Pin Configuration 280 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G OPEN OPEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VPP MN102LP25x (TOP VIEW) 100-pin LQFP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 A15* A14* A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 Chapter 9 Appendix I-Mbit EPROM Pin Number 1 2 3 4 5 6 7 8 9 10 11, 30 Pin Name VPP CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 VSS Pin Number 66 4 100 99 98 97 96 95 94 93 1, 5 - 12, 13,17,19 - 20, 23, 25, 40 - 53, 55 - 65, 67 - 75, 80,82,92 91 90 89 88 87 86 85 84 2 14 15 16 26 27 28 29 30 31 32 33 35 36 37 38 39 3 22, 34,54,76 - 79,81,83 Open 18, 21,24 MN102LP25x Pin Name VPP P63 P17 P16 P15 P14 P13 P12 P11 P10 P60,P50 - P57,P20,VDD,VSS,XI,OSCI, MODE,P41 - P43,VSS,P44 - P47, P80 - P85,P86 - P87,P90 - P93, P94 - P97,P70 - P75, NMI, PA4,RST,VSS P07 P06 P05 P04 P03 P02 P01 P00 P61 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P62 VDD,PA0 - PA3,PA5 SYSCLK, XO, OSCO 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 PGM VDD Figure 9-5-4 Adaptor Socket-MN102LP25x Pin Connections MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 281 Chapter 9 Appendix 9-5-3 Programming s Operating Mode The following table describes the operating modes. Table 9-5-1 Operating Mode Selection Read Output Reserved Standby Word Program Page Latch Program Program Verify Reserved /CE /OE /PGM VDD VPP AB0 to AB15 D7 to D0 L L H VDD VDD Address Input Data Output L H H VDD VDD Address Input High Impedance H - VDD VDD High Impedance L H L VDD VPP Address Input Data Input H L H VDD VDD Address Input Data Input H H L VDD VPP High Impedance L L H VDD VPP Address Input Data Output L L L VDD VPP High Impedance L H H VDD VPP High Impedance H L L VDD VPP High Impedance H H H VDD VPP High Impedance 282 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix s Word Programming The word programming is a mode to write 1-word (16-bit) data at a time. To use this programming mode, set VDD = 6 V, VPP = 12.5 V, and address = 0. The data is written by applying 0.2 ms pulses. After each pulse, read is checked. This step is repeated until the read check is OK. Additional pulse is applied when the read check is verified. The width of additional pulses is 0.2 ms times the number of pulses required until the read check is verified. The address increments each time the word data is programmed and then the next word data is programmed. This operation repeats until the last address is programmed. After that, setting VDD = VPP = 5 V and reading all addresses ends programming. DC Characteristics VDD = 6 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25 *C 5 *C Parameter Input Leakage Current Output Voltage Input Voltage VDD Power Supply (Write, Verify) VPP Power Supply (Write) Symbol ILI VOL VOH VIL VIH IDD IPP /CE = VIL Condition ILI = 0 V to VDD IOL = 4 mA IOH = -4 mA Min Typ Max 2 0.45 2.4 0.8 2.4 40.0 40.0 Unit A V V V V mA mA Note: * VPP (12.5 V) must be applied after VDD (6 V) and off before VDD voltage. * Do not allow VPP to exceed 13 V including overshot. * Do not plug or unplug the device while applying VPP (12.5 V). This affaects the reliability of the device. * When /OE = VIL (12.5 V), do not change VPP from VIL to 12.5 V or from 12.5 V to VIL. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 283 Chapter 9 Appendix AC Characteristics VDD = 6 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25 *C 5 *C Parameter Address Setup Time /OE Enable Setup Time Data Setup Time Address Hold Time Data Hold Time VDD Setup Time VPP Setup Time Program Pulse Width Additional Program Pulse Width /OE Setup Time /OE Output Delay Time Symbol Condition Min 2 2 2 0 2 2 2 0.19 0.19 2 0 0.2 0.21 5.25 150 Typ Max Unit s s s s s s s ms ms s ns tAS tOES tDS tAH tDH tVCS tVPS tPW tOPW tCES tOE 284 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Program Program Verify Additional Program tAS Address VIH VIL VIH VIL tDS tDH Data Fixed Valid Data Output Data Fixed tAH Data tDS VPP VDD tVPS tDH VPP VDD 6V GND tVCS CE tPW PGM VIH VIL tOES OE VIH VIL Figure 9-5-5 Word Program Timing tOPW tOE MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 285 Chapter 9 Appendix Start Vpp=12.5 V,VDD=6.0 V Address=0 X=0 X=X+1 Apply 0.2 ms write pulse Verify Address Increment (Address + 2 = Address) OK NG X=25 YES NO Apply 0.2X ms write pulse NO Last Address? YES VDD=Vpp=*5.0 V *4.75 VVDD=Vpp5.25 V NG Read All Addresses OK Write End Fail Figure 9-5-6 Word Program Flow 286 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix s Page Programming The page programming is a mode to write 2-word (32-bit) data. To use this programming mode, first set VDD = 6 V, VPP = 12.5 V. Latch address = 0 and 16-bit data. Then set address = 2 and the next 16-bit data. The data is written by applying 0.2 ms pulses. After each pulse, read is checked. This step is repeated until the read check is OK. Additional pulse is applied when the read check is verified. The width of additional pulses is 0.2 ms times the number of pulses required until the read check is verified. The address increments each time the 2-word data is programmed and then the next 2word data is programmed. This operation repeats until the last address is programmed. After that, setting VDD = VPP = 5 V and reading all addresses ends programming. DC Characteristics VDD = 6 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25 *C 5 *C Parameter Input Leakage Current Output Voltage Input Voltage VDD Power Supply (Write, Verify) VPP Power Supply (Write) Symbol ILI VOL VOH VIL VIH IDD IPP /CE = VIL Condition ILI = 0 V to VDD IOL = 4 mA IOH = -4 mA Min Typ Max 2 0.45 2.4 0.8 2.4 40.0 40.0 Unit A V V V V mA mA Note: * VPP (12.5 V) must be applied after VDD (6 V) and off before VDD voltage. * Do not allow VPP to exceed 13 V including overshot. * Do not plug or unplug the device while applying VPP (12.5 V). This affaects the reliability of the device. * When /OE = VIL (12.5 V), do not change VPP from VIL to 12.5 V or from 12.5 V to VIL. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 287 Chapter 9 Appendix AC Characteristics VDD = 6 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25 *C 5 *C Parameter Address Setup Time NOE Enable Setup Time Data Setup Time Address Hold Time Data Hold Time VPP Setup Time VDD Setup Time NPGM Pulse Width during Initial Programming NPGM Pulse Width during Over Programming NOE Setup Time NOE Output Delay Time NOE Pulse Width during Data Latch NPGM Setup Time NCE Hold Time NOE Hold Time Symbol Condition Min 2 2 2 0 2 2 2 2 0.19 0.19 2 0 1 2 2 2 0.2 0.21 5.25 150 Typ Max Unit s s s s s s s s ms ms s ns s s s s tAS tOES tDS tAH tAHL tDH tVPS tVCS tPW tOPW tCES tOE tLW tPGMS tCEH tOEH 288 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix Page Data Latch Page Program Program Verify Address A2 - A16 VIH VIL tAS tAHL tAH A1 VIH VIL tDS tDH Data Fixed tPGMS tOE Data VIH/VOH VIL/VOL VPP VPP VDD tVPS VDD 6V VDD tVCS tCES VIH tOEH NCE VIL tCEH tPW tOPW NPGM VIH VIL tOES NOE VIH VIL tLW Figure 9-5-7 Page Program Timing MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 289 Chapter 9 Appendix Start Vpp=12.5 V,VDD=6.0 V Address=0 X=0 Latch Address Increment (Address + 2 = Address) Latch X=X+1 Apply 0.2 ms write pulse Verify Address Increment (Address + 2 = Address) ON NG X=25 YES NO Apply 0.2X ms write pulse NO Last Address? YES VDD=Vpp=*5.0 V *4.75 VVDD=Vpp5.25 V NG Read All Addresses OK Write End Fail Figure 9-5-7 Page Program Flow 290 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix s EPROM Version Precautions * Some of the electrical characteristics may differ from the mask ROM version. * The read/write test for all bits cannot be performed due to the nature of the device. Therefore, storing the written data cannot be fully guaranteed. * Recommend to perform a high-temperature test after programming the EPROM and before implementing the device. Program / Verify High Temp. Test 125 C - 48 h Read Implement Figure 9-5-9 High-Temperature Test Flow MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 291 Chapter 9 Appendix 9-6 Flash EEPROM Version 9-6-1 Overview The MN102LF25Z replaces the MN102L25Z mask ROM with the 128kbyte EEPROM which is an electrically erasable/programmable memory. The MN102LF25Z has two modes: PROM programming mode which uses a dedicated writer (a DATA-I/O LabSite writer) and onboard serial programming mode which the CPU controls. The 128-kbyte flash memory is divided into two spaces as follows: 1. Load program area (1 kbyte: x'80000' - x'803FF') This area stores the load program for serial programming. It is used only in PROM programming mode. 2. Firm area (127 kbytes: x'80400' - x'9FFFF') This area stores the user program. It is programmed only in PROM writer mode. The operation is guaranteed with up to 100 programming. x'80000 Block1: 1 K Block2: 15 K Block3: 16 K Block4: 32 K Block5: 6 K Block6: 10 K Block7: 8 K Block8: 8 K Block9: 16 K Block10: 15 K Load Program Area Firm Area x'9FFFF Block11: 1 K Figure 9-6-1 Memory Map for Flash EEPROM Version 292 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-6-2 Flash EEPROM Programming The following figure shows the steps of flash memory programming (erase/write). Write '0' to entire memory Erase Routine Erase (ERASE Process) User Data Program Figure 9-6-2 Flash EEPROM Program Flow As the above figure shows, programming starts after erasing is completed. The whole erase routine consists of two steps: 1. Programming process which writes x'0000' to flash EEPROM before the actual erase process occurs 2. Erase process which operate the actual erasing 9-6-3 PROM Programming Mode In this mode, the MN102LF25Z allows a PROM writer to program the flash EEPROM. The MN102LF25Z uses a dedicated adaptor, which connects to the DATA-I/O's LabSite PROM writer. (Using the dedicated adaptor selects PROM programming mode automatically.) MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 293 Chapter 9 Appendix 9-6-4 Onboard Serial Programming Mode The serial programming mode is used to program the flash ROM in the MN102LF25Z that is installed on the board. The following sections describe the MN102LF25Z hardware, system configuration, protocol for this programming mode. When using YDC dedicated writer, please refer to its user manual. The load program is attached to the serial writer. 9-6-5 Hardware Used in Serial Programming Mode s Interface The MN102LF25Z incorporates the following functions as I/F for serial programming. q One 8-bit Serial Interface o Data transmission/reception synchronizing external clock o Bit order: LSB first o Maximum clock speed: 10 MHz o Positive input/output logic q Two Input/Output Pins o SBT, SBD reserved for serial interface s I/F Block Diagram RXD TXD SBD (74pin) SBT (73pin) 8-bit Serail I/F RXC,TXC Figure 9-6-3 8-bit Serial Interface Block Diagram for Serial Writer 294 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix s Memory Space of Internal Flash EEPROM Address x'80000' - x'803FF' Size 1 KByte Area Serial Writer Load Program Area Reserved Area Branch Instruction to Reset Service Routine Branch Instruction to Interrupt Service Routine x'80400' - x'80407' 8 Bytes x'80408' 8 Bytes x'80410' 8 Bytes x'80418' - x'9FFFF' 127 KBytes User Program Area Figure 9-6-4 Flash EEPROM Memory Space q Serial Writer Load Program Area o The 1-kbyte area from x'80000' stores the load program for serial writer. o In onboard serial programming mode, the erasing/programming in this area is protected. (Programming is possible by using the parallel writer.) q Branch Instruction to Reset Start Service Routine o Normally, the reset start address is x'80000', but the program branches into x'80408' with the soft branch instruction in the serial writer loader. In this area, the JMP instruction to the actual reset service routine is stored. q Branch Instruction to Interrupt Service Routine o Normally, the jump address at interrupt is x'80008', but the program branches into x'80410' with the soft branch instruction in the serial writer loader. In this area, the JMP instruction to the actual interrupt service routine is stored. q User Program Area o This area stores the user program. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 295 Chapter 9 Appendix 9-6-6 Connecting Onboard Serial Programming Mode Use YDC serial writer for flash microcontroller. All input/output pins must be set to input at reset release. SBD (To Writer) SBT (To Writer) Pins 73 and 74 must be connected to pullup resistors even though writer is not used. /RESET (To Writer) Figure 9-6-5 Pin Configuration During Serial Programming Pins 73, 74 and 82 connect to the serial writer. VDD and Vss connect to the external power sources of 5 V and 0 V respectively. In addition, the level is detected by the writer, VDD and Vss must be output to the writer. OSCI and OSCO must be set to the self-excited oscillation or external excited oscillation. The input pins with no specifications in the above figure are 'don't care'. Fix them to VDD or Vss. The output pins with no specifications in the above figure must be open. 296 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G P60 P61 P62 P63 P50 P51 P52 P53 P54 P55 P56 P57 P20 P21 P22 P23 VDD SYSCLK VSS XI XO VDD OSCI OSCO MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PA0,/IRQ0 PA1,/IRQ1 PA2,/IRQ2 PA3,/IRQ3 PA4,/IRQ4 PA5 /RST VDD P00 P01 P02 P03 P04 P05 P06 P07 VSS P10 P11 P12 P13 P14 P15 P16 P17 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 /NMI SBD,P77 SBT,P76 SBO1,P75 SBI1,P74 SBT1,P73 SBO0,P72 SBI0,P71 SBT0,P70 VDD AN3,P97 AN2,P96 AN1,P95 AN0,P94 VSS TM7IC,P93 TM7IOB,P92 TM7IOA,P91 TM6IC,P90 TM6IOB,P87 TM6IOA,P86 VDD TM5IO,P85 TM4IO,P84 TM3IO,P83 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MN102LF25Z (TOP VIEW) 100-pin LQFP TM2IO,P82 TM1IO,P81 TM0IO,P80 WDOUT,P47 STOP,P46 P45 P44 VSS P43 P42 P41 P40 P37 P36 P35 P34 VDD P33 P32 P31 P30 P27 P26 P25 P24 Self-excited or Exertnal-excited (4 MHz-20 MHz) Chapter 9 Appendix 9-6-7 System Configuration for Onboard Serial Programming s System Configuration AC Adaptor Power Source VDD RS232C Serial Writer Target Board Figure 9-6-6 System Configuration for Onboard Serial Writer The PC sends the program data to the serial writer through RS-232C. The serial writer programs the flash memory through serial communication between the serial writer and the MN102L25Z on the target board. The power is required only when the power source is supplied to the target. s Pin Connection for Target Board Target Board Serial Writer VDD = +5 V /RST SBT SBD GND 4.7 k - 10 k /RST SCL1 SDA1 Chip Figure 9-6-7 Target Board-Serial Writer Connection s Pin Description o VDD : 4.5 V - 5.5 V external power supply o VDD (for level detection) :VDD level detection pin for target board o /RST : Reset o SBT : Serial interface clock supply o SBD : Serial interface data supply o GND : Ground * VDD detects the VDD level on the target board using the serial writer. If the VDD level is not satisfied, the serial writer outputs an error message. * /RST outputs microcontroller reset. * Connect pullup resistors to /RST, SBT and SBD on the target board. The pullup resistor value is 4.7 k10 % to 10 k10 %. * /RST, SBT and SBD are output from the serial writer through an open collector. MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 297 Chapter 9 Appendix s MN102LF25Z Clock on the Target Board * Use the existing clock on the target board for the clock supply to the MN102LF25Z on the target board. Because of this, the clock frequency of the MN102LF25Z differs depending on each user purpose. * The following table shows the clock frequency for the MN102LF25Z during serial programming. The clock frequency for the MN102LF25Z is assumed to be 20 MHz if the clock frequency is not specified in the manual. If the clock frequency for the MN102LF25Z is different from the clock frequency on the target board, the value should be calculated proportionately depending on the clock frequency of the MN102LF25Z. Table 9-6-1 Clock Frequency Max. Clock Frequency 20 MHz Min. Clock Frequency 4 MHz 298 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-6-8 Onboard Serial Programming Mode Setup s Programming Mode Setup Timing To set serial programming mode, the microcontroller must be in write mode. This section describes the pin setup for the serial writer. A Normal Timing Waveform B C D VDD /RST SBT SBD Timing Waveform during Serial Programming VDD /RST SBT SBD T1 T2 T3 Figure 9-6-8 Timing for Onboard Serial Programming Mode MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 299 Chapter 9 Appendix s Setup Steps 1. Supply VDD at Timing A. At this point, output /RST = SBD = Low. 2. Through the serial writer, drive /RST for T2 term from Timing B when SBT goes high while the MN102LF25Z is on. The MN102LF25Z initializes. 3. Through the serial writer, drive /RST for T3 term from Timing C when SBD goes high while the MN102LF25Z is on. This informs that the MN102LF25Z is connected to the serial writer. 4. During T3 term, the serial writer makes SBD pin to input low level longer enough than the MN102LF25Z stabilization wait time. s Load Program Reset Start SBT pin ==High && SBD pin ==Low ? No Yes Wait tWAIT1 SBT pin ==High && SBD pin ==Low ? No Yes Has tWAIT2 passed ? Yes No SBT pin ==High && SBD pin ==High ? No Yes Start serial writer load program Execute user program Figure 9-6-9 Load Program Start Flow Conditions 1. 2. 3. 4. When the load program initializes a reset start, SBD = low and SBT = high. The program waits for tWAIT1. SBD must still be low and SBT high. Wait that both SBD and SBT become high during tWAIT2. If any above conditions are not met, the program returns to the user program. 300 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-6-9 Branch to User Program s Branch to Reset Service Routine Reset Start Serial Writer ? No Yes Start serial writer load program Branch to x'80408' Execute User Program Figure 9-6-10 Reset Service Routine Flow When the reset starts, the serial writer load program initializes only if SBD is low. The program branches to the user program at address x'80408'. s Branch to Interrupt Service Routine Interrupt Start Address jmp x'80410' Instruction x'80008' (3 bytes/2 cycles) Branch to x'80410' Write a branch instruction to x'80410' Execute user interrupt service routine (Generate 2-cycle delay) Figure 9-6-11 Interrupt Service Routine Flow Write only the instruction branching to address x'80410' at the interrupt start address (x'80008'). MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 301 Chapter 9 Appendix 9-6-10 Serial Interface for Onboard Serial Programming s Features Fixed-length Serial Interface * Character length 8 bits * Transmission bit order LSB * Clock source External clock * Maximum transfer speed 5 Mbps ( with a 20-MHz oscillator) * Error detection Overrun error * Buffer Transmit/receive shared buffer Single transmit buffer, Double receive buffer s Data Timing SBD LSB MSB SBT Figure 9-6-12 Data Transfer Timing The 8-bit serial data is transfered with LSB first bit order. 302 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G Chapter 9 Appendix 9-6-11 PROM Writer/Onboard Serial Programming START VDD=5.0 V All"0"Program Erase User Data Program END Figure 9-6-13 Programming Flow MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G 303 Chapter 9 Appendix 304 MN102L2503/25A/25D/25Z/25G/F25Z/490A/62D/62F/62G MN102L2503/25A/25D/25Z/25G/ F25Z/490A/62D/62F/62G LSI User's Manual May, 2000 1st Edition Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation (c) Matsushita Electric Industrial Co., Ltd. (c) Matsushita Electronics Corporation Semiconductor Company, Matsushita Electronics Corporation Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.mec.panasonic.co.jp SALES OFFICES s U.S.A. SALES OFFICE Panasonic Industrial Company [PIC] q New Jersey Office: 2 Panasonic Way, Secaucus, New Jersey 07094 Tel: 201-392-6173 Fax: 201-392-4652 q Milpitas Office: 1600 McCandless Drive, Milpitas, California 95035 Tel: 408-945-5630 Fax: 408-946-9063 q Chicago Office: 1707 N. Randall Road, Elgin, Illinois 60123-7847 Tel: 847-468-5829 Fax: 847-468-5725 q Atlanta Office: 1225 Northbrook Parkway, Suite 1-151, Suwanee, Georgia 30174 Tel: 770-338-6940 Fax: 770-338-6849 q San Diego Office: 9444 Balboa Avenue, Suite 185 San Diego, California 92123 Tel: 619-503-2940 Fax: 619-715-5545 s TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co.,Ltd. [PIST] q Head Office: 6th Floor, Tai Ping & First Building No.550. Sec.4, Chung Hsiao E. Rd. Taipei 10516 Tel: 2-2757-1900 Fax: 2-2757-1906 q Kaohsiung Office: 6th Floor, Hsien 1st Road Kaohsiung Tel: 7-223-5815 Fax: 7-224-8362 s SINGAPORE SALES OFFICE Panasonic Semiconductor of South Asia 300 Beach Road # 16-01 The Concourse Singapore 199555 Tel: 390-3688 Fax: 390-3689 [PSSA] s MALAYSIA SALES OFFICE Panasonic Industrial Company (Malaysia) Sdn. Bhd. q Head Office: [PICM] Tingkat 16B Menara PKNS PJ No.17,Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel: 03-7516606 Fax: 03-7516666 q Penang Office: Suite 20-17,MWE PLAZA No.8,Lebuh Farquhar,10200 Penang Malaysia Tel: 04-2625550 Fax: 04-2619989 q Johore Sales Office: 39-01 Jaran Sri Perkasa 2/1,Taman Tampoi Utama,Tampoi 81200 Johor Bahru,Johor Malaysia Tel: 07-241-3822 Fax: 07-241-3996 s CANADA SALES OFFICE Panasonic Canada Inc. [PCI] 5700 Ambler Drive Mississauga, Ontario, L4W 2T3 Tel: 905-624-5010 Fax: 905-624-9880 s GERMANY SALES OFFICE Panasonic Industrial Europe G.m.b.H. q Munich Office: Hans-Pinsel-Strasse 2 85540 Haar Tel: 89-46159-156 Fax: 89-46159-195 [PIEG] s U.K. SALES OFFICE Panasonic Industrial Europe Ltd. [PIEL] q Electric component Group: Willoughby Road, Bracknell, Berkshire RG12 8FP Tel: 1344-85-3773 Fax: 1344-85-3853 s CHINA SALES OFFICE Panasonic SH Industrial Sales (Shenzhen) Co., Ltd. [PSI(SZ)] 7A-107, International Business & Exhibition Centre, Futian Free Trade Zone, Shenzhen 518048 Tel: 755-359-8500 Fax: 755-359-8516 Panasonic Industrial (Shanghai) Co., Ltd. [PICS] 1F, Block A, Development Mansion, 51 Ri Jing Street, Wai Gao Qiao Free Trade Zone, Shanghai 200137 Tel: 21-5866-6114 Fax: 21-5866-8000 s FRANCE SALES OFFICE Panasonic Industrial Europe G.m.b.H. q Paris Office: 270, Avenue de President Wilson 93218 La Plaine Saint-Denis Cedex Tel: 14946-4413 Fax: 14946-0007 [PIEG] s THAILAND SALES OFFICE [PIEG] Panasonic Industrial (Thailand) Ltd. [PICT] 252/133 Muang Thai-Phatra Complex Building,31st Fl.Rachadaphisek Rd.,Huaykwang,Bangkok 10320 Tel: 02-6933407 Fax: 02-6933423 s ITALY SALES OFFICE Panasonic Industrial Europe G.m.b.H. q Milano Office: Via Lucini N19, 20125 Milano Tel: 2678-8266 Fax: 2668-8207 s PHILIPPINES SALES OFFICE National Panasonic Sales Philippines [NPP] 102 Laguna Boulevard Laguna Technopark Sta. Rosa. Laguna 4026 Philippines Tel: 02-520-3150 Fax: 02-843-2778 181199 Printed in JAPAN s HONG KONG SALES OFFICE Panasonic Shun Hing Industrial Sales (Hong Kong) Co., Ltd. [PSI(HK)] 11/F, Great Eagle Centre, 23 Harbour Road, Wanchai, Hong Kong. Tel: 2529-7322 Fax: 2865-3697 (c) Matsushita Electronics Corporation 2000 |
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