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Kawasaki USB device
KL5KUSB201
Datasheet (digest)
rev 1.1E page 1/21
KL5KUSB 201 USB2.0 Compliant Transceiver Chip Datasheet (Digest)
Rev 1. 1E (2002.4.8)
Kawasaki Microelectronics Inc. Kawasaki LSI Inc.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
KL5KUSB201
Datasheet (digest)
rev 1.1E page 2/21
Intellectual Property Disclaimer and Copyright Notice
KAWASAKI MICROELECTRONICS INC. DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETY RIGHTS, RELATING TO USE OF INFORMATION IN THIS DOCUMENT. THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. KAWASAKI MICROELECTRONICS INC. RESERVES THE RIGHT TO MAKE ANY CHANGES, AT ANY TIME, WITHOUT NOTICE, THE DESCRIPTION IN THIS DOCUMENT. NEITHER THE WHOLE NOR ANY PART OF THE INFORMATION CONTAINED IN, OR THE PRODUCT DESCRIBED IN THIS DOCUMENT MAY BE ADAPTED OR REPRODUCED IN ANY MATERIAL FORM EXCEPT WITH THE PRIOR WRITTEN PERMISSION OF KAWASAKI MICRO KAWASAKI PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. ALL PRODUCT NAMES ARE TRADEMARKS, REGISTERED TRADEMARKS, OR SERVICE MARKS OF THEIR RESPECTIVE OWNERS.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
Revision History
revision 0.10J 0.21J 0.30E 1.0E 1.1E date 2001.9.28 2001.10.18 2002.3.15 2002.3.25 2002.4.8
KL5KUSB201
Datasheet (digest)
rev 1.1E page 3/21
Update release first version minor error correction translation from Japanese to English with some minor change Document Review is closed. Table 5-3 pin78, 79 error corrected.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
Table of Contents
1. Overview 1.1 Chip Functionality 1.2 KL5KUSB201 Product Feature 2. Chip Architecture 3. Application Example 4. Pinout Diagram 5. Package Information 5.1 Top View 5.2 Package Size 5.3 Pin Assignment 6. Signal Description 7. SIE Bus Timing 7.1 SIE Bus Output Timing 7.2 SIE Bus Input Timing 8. USB Bus Timing 8.1 Bulk IN Transaction 8.2 Bulk OUT Transaction 9. USB2.0 LSI Family 9.1 T&MT Evaluation Daughter Card (UUT) 9.2 PCI Evaluation Add-in Card 9.3 KL5BUDV002 LSI (U2PCI) 9.4. USB201 and HS_SIE ASIC IP 9.4.1 HS_SIE ASIC IP 9.4.2 USB201 ASIC IP 10. References
KL5KUSB201
Datasheet (digest)
rev 1.1E page 4/21
5 5 6 6 8 8 9 9 10 10 11 13 13 13 14 14 15 15 15 16 17 19 19 20 21
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
1. Overview
KL5KUSB201
Datasheet (digest)
rev 1.1E page 5/21
Kawasaki Microelectronics Inc. and Kawasaki LSI Inc. introduce KL5KUSB201 LSI, which is designed based on USB Specification revision 2.0 and operates as both USB2.0 High Speed and Full Speed transceiver chip. It has two modes - UTMI Specification compatible mode and Kawasaki Original mode. In Kawasaki Original mode, the LSI has several convenient function such as automatic CRC generation and verification, transmit packet abortion and automatic test packet generation for High Speed Signal Quality test. The LSI is recognized as USB2.0 PHY chip and customers are able to build up USB2.0 compliant device system with their logic and PHY control / endpoint buffer function (SIE), which is available by Kawasaki or other IP vendor. Figure 1. KL5KUSB201 Image
1.1 Chip Functionality
KL5KUSB201 Fucntionality is summarized below. 1. HS Chirp Signal Generation and Detection 2. Support for both High Speed (480Mbit/sec) and Full Speed (12Mbit/sec) 3. For received packet, phase lock, buffering, SYNC detection, NRZI decode, bit un-stuffing, CRC error detection (optional), serial to parallel conversion are performed. 16bit data is drived on SIE bus 4.For packet transmission, parallel 16bit data is received, serialized, CRC
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
USB bus with SYNC and EOP attached
KL5KUSB201
Datasheet (digest)
rev 1.1E page 6/21
generation (optional), bit stuffed and NRZI encoded. Packet is transmitted onto 5. USB Bus status is delivered for outside SIE to monitor it 6. Function is controlled by Input Signals 7. Function defined by UTMI Specification is supported 8. Stand-alone Test packet generation for High Speed Signal Quality
1.2 KL5KUSB201 Product Feature
KL5KUSB201 Product Feature is shown below. No 1 2 3 4 5 6 7 8 9 10 11 12 Table 1-2 KL5KUSB201 Product Feature Item Feature Process 0.18um CMOS Package LQFP 80 pin plastic package Input Clock Frequency 48MHz Internal Clock Frequency 480MHz48MHz and other Output Clock Frequency 30MHz (CKOUT) USB port 1 port (USB pin is separated for HS and FS) Parallel Data width (SIE_DAT) 16bit Power voltage 3.30.3V1.80.15V Operation Current in FS typical 50mA Operation Current in HS typical 90mA Operation Current at suspend 1uA Ambient Temperature 070C
Please contact to our sales and marketing person to request samples, datasheet, USB201 IP and / or HS_SIE included ASCP planning.
2. Chip Architecture
Internal Architecture of KL5KUSB201 is shown in figure 2. The LSI consists of 6 major blocks as follows. FrontEnd block transmits and receives USB signals. HS DLL block is used to re-clock High Speed signals with internal 480MHz clock. EBUF block is for buffering High Speed signals. Shared Logic block includes such function as NRZI decode, bit un-stuffing, CRC check, serial to parallel conversion for both High Speed and Full Speed USB signals. SIE_IF block interfaces with SIE bus signals. For Full Speed operation, DPLL block is used to re-clock the Full Speed signals with
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
KL5KUSB201
Datasheet (digest)
rev 1.1E page 7/21
internal 12MHz clock instead of FrontEnd, HSDLL and EBUF blocks. For received signals, the LSI locks them in HS DLL and is buffering them in EBUF. Then signals are transferred to Shared Logic to convert data format, check the CRC, convert from serial to parallel. The data is finally delivered to the SIE bus through SIE_IF. For transmit operation, incoming parallel data is received in SIE_IF and sent to Shared Logic to perform parallel to serial conversion, CRC generation, bit stuffing and NRZI encoding. Finally the data is transmitted onto the USB bus through FrontEnd block. High Speed or Full Speed operation is selected by SIE control signals. USB bus status can be monitored by USB bus status signals.
Figure 2
USB bus HSDP HSDM HS FrontEnd HS DLL EBUF
KL5KUSB201 Internal Architecture
SIE bus CTRL STATUS Shared Logic SIE_IF CKOUT SIE_DAT
RPU_ENA FSDP FSDM
FS FrontEnd
DPLL
External 48MHz clock
CLK GEN
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
3. Application Example
KL5KUSB201
Datasheet (digest)
rev 1.1E page 8/21
Example of system configuration using KL5KUSB201 is shown in figure 3. To realize the USB device application, other than the LSI, SIE PHY control and function logic are needed. Also suitable resistors such as Rpu, Rs and Rext and 48MHz clock oscillator or crystal and related parts are required.
Figure 3 Application Example
Rext
HS_SIE
USB201
Rpu UDP UDM Rs Rs osc 48MHz
USB201 Endpoint Controller Buffer
Function Logic
4. Pinout Diagram
Symbol block of KL5KUSB201 is shown in Figure 4. The LSI has two interfaces - USB bus and SIE bus. USB related bus signals are shown in the left side of the symbol block, while SIE bus signal is in the right side. SIE control signals select LSI operation mode. These signals are FS_HSN, PU_SE0N, MODE, CRCACT, SUSPN and RSTN. USB bus status signals are BSTAT. CRCERR and RXERR are receiving error indicators. SIE_DAT is bi-directional bus. Signal direction and valid timing are controlled by RXACT, RXVLD, TXACT, TXRDY and WDVLD.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
Figure 4
KL5KUSB201
Datasheet (digest)
rev 1.1E page 9/21
KL5KUSB201 Symbol Block
USB bus
SIE bus FS_HSN PU_SE0N
REXT HSDP HSDM
CKOUT RXACT RXVLD CRCERR RXERR
RPU_ENA FSDP FSDM
KL5KUSB201
SIE_DAT[15:0] WDVLD TXACT TXRDY CRCACT RSTN SUSPN MODE[3:0] BSTAT[1:0]
XIN XOUT
5. Package Information 5.1 Top View
TOP VIEW
60 41
61
40
KL5KUSB201
index 80 21
1
20
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
5.2 Package Size
LQFP-80 package size is shown in Table 5.2.
KL5KUSB201
rev 1.1E page 10/21
Datasheet (digest)
Table 5-2. LQFP-80 size information
No 1 2 3
Item body size thickness pin pitch
Size 12.0 max 1.70 0.5
Unit mm mm mm
5.3 Pin Assignment
Package pin number and signal name Table is listed below. Please note that power pins named VDD18 (Pin No 39, 45, 56 and 62) are required to be supplied 1.8V, while other power pins named AVDD and VDD should be supplied 3.3V.
Table 5-3. Pin Assignment
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O ----O 3S --I/O I/O I/O I/O ---I I -I I signal name AVDD GND AVDD GND REXT RPU_ENA AVDD GND FSDP HSDP HSDM FSDM GND AVDD VDD MODE[0] MODE[1] GND MODE[2] MODE[3] Pin No 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I O O I/O --I/O I/O -I/O --I/O --I/O I/O --signal name RSTN SUSPN BSTAT[0] BSTAT[1] SIE_DAT[0] VDD GND SIE_DAT[1] SIE_DAT[2] GND SIE_DAT[3] VDD GND SIE_DAT[4] GND VDD SIE_DAT[5] SIE_DAT[6] VDD18 GND Pin No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O I/O I/O I/O ----I/O I/O -I/O -I/O I/O ----O I/O signal name SIE_DAT[7] SIE_DAT[8] SIE_DAT[9] GND VDD18 GND VDD SIE_DAT[10] SIE_DAT[11] GND SIE_DAT[12] GND SIE_DAT[13] SIE_DAT[14] GND VDD18 GND VDD CKOUT SIE_DAT[15] Pin No 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O --IN IN -IN IN --I/O O O O -O O -I O -signal name GND VDD18 PU_SE0N FS_HSN GND CRCACT TXACT GND VDD WDVLD TXRDY RXERR CRCERR GND RXVLD RXACT VDD XIN XOUT GND
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
6. Signal Description
KL5KUSB201
rev 1.1E page 11/21
Datasheet (digest)
Table 6 describes signal function description and related name in UTMI. Table 6 Signal Description Description
No 1 2 3 4
Signal Name REXT HSDP HSDM RPU_ENA
I/O O I/O I/O O
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
FSDP FSDM XIN XOUT FS_HSN PU_SE0N CKOUT RXACT RXVLD CRCERR RXERR TXACT TXRDY CRCACT SIE_DAT[15:0]
I/O I/O I O I I O O O O O I O I I/O
20 21
WDVLD RSTN
I/O I
UTMI name Reference bias current pin. Connect to GND via -external resistor Rext. High Speed DP pin. Connect to USB Bus D+. DP High Speed DM pin. Connect to USB Bus D-. DM Pull up resister source pin. Connect to external -resistor Rpu, which is tied to USB bus D+. RPU_ENA becomes 3-state in High Speed operation. Full Speed DP pin. Connect to USB Bus D+ via (DP) termination resistor Rs. Full Speed DM pin. Connect to USB Bus D- via (DM) termination resistor Rs. 48MHz clock input pin. Connect to crystal oscillator -or crystal oscillation circuit. 48MHz clock output pin for crystal oscillation circuit. -USB bus speed control pin. XcvrSelect Termination control pin. With FS_HSN and MODE, TermSelect LSI operation mode is selected. SIE bus clock pin. Frequency is 30MHz. CLK USB packet received signal. RXActive SIE bus out data valid signal. Active H. RXValid (RXValidH) CRC error detection signal. Active when CRC logic -is enabled. Receive error detection signal. RX error indicator RXError except for CRC error. USB bus data transmit control signal. SIE bus TXValid switches from output to input when active. (TXValidH) SIE input data ready signal. Valid when TXACT is TXReady active. CRC detection logic enable signal. Also used for -data transmit abortion. 16bit parallel 3-state SIE data bus. Synchronized Data15-8, with CKOUT. Data direction is input when TXACT Data7-0 assertion. Default direction is output. SIE data width indication signal. If last SIE data is a ValidH byte data, WDVLD is asserted. Hardreset signal. Active L. Assertion required when RST power on and USB reset recognition. (assert H)
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
22 SUSPN I
KL5KUSB201
rev 1.1E page 12/21
Datasheet (digest)
23
BSTAT[1:0]
O
24
MODE[3:0]
I
Asynchronous suspend signal. Active L. When asserted, the LSI internal circuit is set to be in stand-by mode. Only BSTAT[1:0] is active for monitoring USB bus status. USB bus monitor signals. In normal operation, the signal is synchronized with CKOUT, while asynchronous during suspend. When UTMI mode is selected, BSTAT is compatible with LineState. Operation mode selection. One of UTMI mode, device test mode, normal operation mode and stand-alone USB2.0 signal quality test mode is selected.
SuspendM
LineState [1:0]
OpMode [1:0]
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
7. SIE Bus Timing 7.1 SIE Bus Output Timing
KL5KUSB201
rev 1.1E page 13/21
Datasheet (digest)
Timing diagram of USB data output to SIE bus is shown in Figure 7-1. SIE bus direction is output in default. The LSI asserts RXACT to notice output of data to the external SIE logic. Valid data is indicated by RXVLD assertion. Odd byte of received USB data is driven to the lower byte of SIE bus. If SIE output data is in odd byte length, the LSI negates WDVLD at the final data valid phase to indicate that the last one is byte data.
Figure 7-1 SIE Bus Output Timing
CKOUT (O) TXACT (I) TXRDY (O) RXACT (O) RXVLD (O) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) WDVLD (IO) B2 B1 B4 B3 B5
7.2 SIE Bus Input Timing
Figure 7-2 shows the receive timing diagram of the LSI from SIE bus. External SIE circuit asserts TXACT to notice the LSI to get data on SIE bus. When TXRDY is asserted, valid data is latched by the LSI. If data from SIE is odd byte length, SIE negates WDVLD at the final data stage like the case in SIE bus output timing. Please note that in Figure 7-2, a case of even byte length data is depicted.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
Figure 7-2 SIE Bus Input Timing
CKOUT (O) TXACT (I) TXRDY (O) RXACT (O) RXVLD (O) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) WDVLD (IO)
KL5KUSB201
rev 1.1E page 14/21
Datasheet (digest)
// // // // // B2 B1 // B4 B3 B6 B5
8. USB Bus Timing 8.1 Bulk IN Transaction
Figure 8-1 shows the data timing of a Bulk IN transaction from USB host. When the LSI receives IN packet from the host PC, it asserts RXACT and drives 3 bytes received data on SIE bus. External SIE logic receives the data, checks the information of address, endpoint and CRC if necessary. If it finds the data valid, the SIE returns the DATA packet to be transmitted. Finally the LSI receives ACK packet and finishes a Bulk IN transaction. Figure 8-1 Bulk IN transaction
USB Bus (IO) RXACT (O) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) AE IN EC AK SE0 SYNC IN AECep SE0 SYNC D 2' 3' 4' .... n' C16ep SE0 SYNC AK ep SE0
TXACT (I) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) 2 DAT 4 3 .... .... n n-1
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
8.2 Bulk OUT Transaction
KL5KUSB201
rev 1.1E page 15/21
Datasheet (digest)
Figure 8-2 shows the data timing of a Bulk OUT transaction from the host PC. When the LSI receives OUT packet from the USB host, the LSI asserts RXACT and drives 3 bytes data received from the host. If the external SIE logic recognizes the OUT packet is valid, it waits for the next DATA packet from USB host. If the SIE logic receives the DATA packet correctly, it returns ACK. Figure 8-2 Bulk OUT transaction
USB Bus (IO) RXACT (O) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) AE OUT EC 24 DAT 3 .... .... n C2 n-1 C1 SE0 SYNC O AECep SE0 SYNC D 2' 3' 4' .... n' C16ep SE0 SYNC AK ep SE0
TXACT (I) SIE_DAT[15:8] (IO) SIE_DAT[7:0] (IO) ACK
9. USB2.0 LSI Family
This section introduces Kawasaki's USB2.0 LSI family.
9.1 T&MT Evaluation Daughter Card (UUT)
The daughter card which is designed based on Transceiver and Macrocell Tester (T&MT) Interface Specification is available for evaluating the KL5KUSB201 chip. All necesary parts including the LSI, USB connector, resistors and crystal oscillator are attached. With using your T&MT compatible controller, the function of the LSI is able to be evaluated such as USB2.0 Test mode function, data transfer in High Speed or Full Speed mode and verification of functionality with the external UTMI compatible SIE.
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
KL5KUSB201
rev 1.1E page 16/21
Datasheet (digest)
Figure 9-1 KL5KUSB201 T&MT Daughter Board
9.2 PCI Evaluation Add-in Card
The USB2.0 to PCI Adapter card is developed for the purpose of evaluating the LSI as a USB device system using PC. The PCI card includes the LSI, USB connector, all necessary parts and U2PCI Chip, which is described later. The PCI card performs the control of the LSI, USB packet buffering, PCI bus transfer operation with high throughput. Evaluation software is available together with the board. Figure 9-2 KL5KUSB201 PCI Evaluation Add-in Card
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
9.3 KL5BUDV002 LSI (U2PCI)
KL5KUSB201
rev 1.1E page 17/21
Datasheet (digest)
The KL5BUDV002 LSI is USB2.0 to PCI adapter chip, which consists of HS_SIE block, PCI Interface block and data buffer RAM. With KL5KUSB201, chipset performs data transfer with high throughput between USB2.0 and PCI bus. The chipset makes it easy to build up a USB2.0 device system. Main feature of KL5BUDV002 LSI is as follows. 1. Directly connected with KL5KUSB201 and realizes USB2.0 data transfer in both High Speed and Full Speed 2. Includes HS_SIE function and support up to 4 endpoints Endpoint 0 Endpoint 1 Endpoint 2 Endpoint 5 Control Transfer Bulk OUT Bulk IN Interrupt IN 64Bytes buffer 512Bytes x2 buffers 512Bytes x2 buffers 8Bytes buffer option
3. Includes 33MHz, 32bit PCI bus interface Target single access for memory mapped register access Master burst access with 2 DMA master controllers for memory access 4. Independent Data buffers for data transmit and receive 5. USB configuration transfer is controlled by the external PCI controller. Figure 9-3-1 KL5BUDV002 Symbol
USB VBDET SIE bus FS_HSN PU_SE0N CKOUT RXACT RXVLD CRCERR RXERR SIE_DAT[15:0] WDVLD TXACT TXRDY CRCACT URSTN SUSPN MODE[3:0] BSTAT[1:0]
PCI bus AD[31:0] CBEN[3:0] PAR IDSEL FRAMEN DEVSELN IRDYN TRDYN STOPN
KL5BUDV002
REQN GNTN INTAN RSTN CLK Misc bus PMODE[2:0] TESTI[3:0] TESTO
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
KL5KUSB201
rev 1.1E page 18/21
Datasheet (digest)
Figure 9-3-2 KL5BUDV002 Application Example
Rext
UDV002 KL5K USB201
SIE16b HS_SIE 30MHz DBUF PCI IF
PCI 32b
Rpu UDP UDM Rs Rs
33MHz
Osc 48MHz
Figure 9-3-3 KL5BUDV002 Package Image
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
9.4 HS_SIE and USB201 ASIC IP 9.4.1 HS_SIE ASIC IP
KL5KUSB201
rev 1.1E page 19/21
Datasheet (digest)
HS_SIE IP is useful for Kawasaki ASIC users to design their LSI, which connects to KL5KUSB201 or includes USB201 IP inside. Together with KL5KUSB201 chip, the IP performs USB2.0 lower level protocol. The main features of HS_SIE are shown below. 1. RTL design makes it easy to implement with various processes 2. Compact design such as 20 k logic gates, 4x512 bytes and 1x64 bytes 1-p RAM 3. Performs HS chirp protocol and Speed detection 4. Processes the basic USB transaction such as token decode, miss-hit judgment, error detection and data toggle bit control 5. Controls transaction flow 6. Supports up to 6 endpoints in total - control, 2 bulk in, 2 bulk out and interrupt. 7. Ease-of-use internal bus interface such as 16bit bus register access or DMA
Figure 9-4-1 HS_SIE IP Symbol
SIE bus FS_HSN PU_SE0N CKOUT RXACT RXVLD CRCERR RXERR SIE_DAT[15:0] WDVLD TXACT TXRDY CRCACT URSTN SUSPN MODE[3:0] BSTAT[1:0]
IHOST bus HIRQ HADR[4:0] HCSN HWRN HRDN HRDY HDAT[15:0]
HS_SIE
HREQ HACK RXLBVLD RXLAST TXLBVLD TXLAST TXNUL
RSTN SYSCK
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
9.4.2 USB201 ASIC IP
KL5KUSB201
rev 1.1E page 20/21
Datasheet (digest)
USB201 macro function is also prepared as ASIC IP in Kawasaki's KS6000 0.18um CMOS technology. Together with synthesizable HS_SIE, a single chip solution of USB device function can be realized. Figure 9-4-2-1 USB device integration concept
USB201 & HS_SIE core ASIC concept ASIC SIE bus IHOST bus
USB bus
USB201 IP
HS_SIE IP
User Logic
User I/O
Figure 9-4-2-2 USB201 IP included ASIC chip image
I/O buffer USB201 IP User Logic HS_SIE IP
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Kawasaki USB device
10. References 10.1 USB2.0 Specification
KL5KUSB201
rev 1.1E page 21/21
Datasheet (digest)
Latest USB Specification, which describes both Full Speed and High Speed operation. The specification is available from USB_IF web site. Following three specifications are piled up to one zip file. a. USB specification (April 27,2000) b. errata to the USB2.0 specification (December 7,2000) c. Mini-B connector Engineering Change Notice to the USB 2.0 specification ( http://www.usb.org/developers/docs.html )
10.2 UTMI Specification
This is the USB2.0 PHY function macro specification proposed by Intel Corp. The interface between PHY and SIE is defined. It is downloadable from Intel site. a. The USB 2.0 Transceiver Macrocell Interface, version 1.05(UTMI) specification ( http://developer.intel.com/technology/usb/spec.htm )
10.3 T&MT Interface Specification
This document is the macrocell test interface proposed by Intel Corp. To test PHY efficiently, card dimensions, connector pin layout and interface signals are defined. It is also downloadable from Intel web site. a. The USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification ( http://developer.intel.com/technology/usb/spec.htm )
10.4 High Speed Board Design Guide
This document depicts the general guideline of High Speed USB device board design. Design tips of handling the high speed signals are available in this document. This document is downloadable from the Intel web site, too. ( http://developer.intel.com/technology/usb/spec.htm )
10.5 Kawasaki's Datasheet
More detailed documents are available by Kawasaki. Please contact our sales person. a. KL5KUSB201 datasheet b. KL5BUDV002 datasheet
Copyright (c) 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

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