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Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
* * * * * * * Fully integrated PLL, no external loop filter requirements Two differential 3.3V LVPECL output Crystal oscillator interface: 10MHz to 25MHz Output frequency range: 41.67MHz to 700MHz VCO range: 250MHz to 700MHz Parallel or I2C interface for programming M and N dividers during power-up Supports Spread Spectrum Clocking (SSC) Center spread: selectable 0.5%, 1.0%, 1.5%, 2% Up/Down spread: selectable 0.5%, 1.0%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4% RMS Period jitter: 9ps (maximum) Cycle-to-cycle jitter: 40ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Industrial temperature information available upon request Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS84330-03 is a general purpose, dual output high frequency synthesizer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the I2C interface. The output can be configured to divide the VCO frequency by 1, 2, 3, 4, and 6.
IC S
Additionally, the device suppor ts spread spectrum clocking (SSC) for minimizing Electromagnetic Interference (EMI). The low cycle-cycle jitter and broad frequency range of the ICS84330-03 make it an ideal clock generator for a variety of demanding applications which require high performance.
* * * * * *
BLOCK DIAGRAM
OE Pullup VCO_SEL Pullup XTAL_IN
PIN ASSIGNMENT
nQ0 nQ1
SCL SDA
1 2 3 4
32 31 30 29 28 27 26 25 24 23
VCC
VCC
VEE
VEE
Q0
Q1
VCO_SEL N1 N0 M8 M7 M6 M5 M4
OSC
1
ADDR_SEL VCCA
ICS84330-03
22 21 20 19 18
XTAL_OUT FREF_EXT
Pulldown
VCCA
0 /16
FREF_EXT XTAL_SEL XTAL_IN
32-Lead LQFP Y package 5 7mm x 7mm x 1.4mm 6 body package 7 Top View
8
XTAL_SEL Pullup
17 9 10 11 12 13 14 15 16
XTAL_OUT OE nP_LOAD M0 M1 M2 M3 nc
PLL
Phase Detector
0
VCO
/M /2 1
/1
1
Q0 nQ0
/2
0
/2 /3 /4 /6
1
Q1 nQ1
0
ADDR_SEL Pulldown SDA SCL nP_LOAD Pullup M0:M8 M0:M7 = Pulldown, M8 = Pullup N0 N1
84330AY-03 Pulldown Pulldown
I2C Parallel Interface
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The programming mode is controlled by the nP_LOAD pin. When this pin is low, The M, N values are set by the logic values on the M, N pins. If nP_LOAD is HIGH, the M, N dividers can be changed using the I2C serial programming interface. The I2C control registers are defined below:
The ICS84330-03 uses either a parallel interface or industry standard I2C interface to control the programming of the internal dividers. The power on defaults are summarized as follows: M 256 Output Q0/nQ0 output at 267MHz (using a 16.667MHz crystal) Q1/nQ1 output at 133MHz (using a 16.667MHz crystal) SSC Mode: Off
Parallel Mode:
Data Byte 0
Control Bit Power-up Default Value N1 0 N0 0 M8 1 M7 0 M6 0 M5 0 M4 0 M3 0
Data Byte 1
Control Bit Power-up Default Value M2 0 M1 0 M0 0 Not Used X Not Used X Not Used X Not Used X Not Used X
Data Byte 2
Control Bit Power-up Default Value Up 0 Down 0 SSC5 0 SSC4 0 SSC3 0 SSC2 0 SSC1 0 SSC0 0
I2C ADDRESSING
The ICS84330-03 can be set to decode one of two addresses to minimize the chance of address conflict on the I2C bus. The
ADDR_SEL (pin 3) = 0 Default Bit 5 Bit 4 Bit 3 Bit 2 0 1 1 0
address that is decoded is controlled by the setting of the ADDR_SEL pin (pin 3).
Bit 7 1
Bit 6 1
Bit 1 0
Bit 0 R/W
Bit 7 1
Bit 6 1
ADDR_SEL (pin 3) = 1 Bit 5 Bit 4 Bit 3 Bit 2 0 1 1 1
Bit 1 0
Bit 0 R/W
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
mum SCL frequency is greater than 10MHz which is more than sufficient for standard I2C clock speeds.
I2C INTERFACE - PROTOCOL
The ICS84330-03 is a slave-only device and uses the standard I2C protocol as shown in the below diagrams. The maxi-
SCL
SDA
START
Valid Data
Acknowledge
STOP
START (ST) - defined as high-to-low transition on SDA while holding SCL HIGH. DATA - Between START and STOP cycles, SDA is synchronous with SCL. Data may change only when SCL is LOW and must be stable when SCL is HIGH. ACKNOWLEDGE (AK) - SDA is driven LOW before the SCL rising edge and held LOW until the SCL falling edge. STOP (SP) - defined as low-to-high transition on SDA while holding SCL HIGH.
I2C INTERFACE - A WRITE EXAMPLE
A serial transfer to the ICS84330-03 always consists of an address cycle followed by 4 data bytes: 1 dummy byte followed by 3 data bytes. Any additional bytes beyond the 4 data bytes will not be acknowledged and the ICS84330-03 will leave the data bus HIGH. These extra bits will not be loaded into the serial control register. Once the 4 Data bytes are loaded
ST 1 Bit
and the master generates a stop condition, the values in the serial control register are latched into the M divider, N divider, and control bits and the device will smoothly slew to the new frequency and any changes to the state of the control bits will take effect.
R/ W 1 Bit AK 1 Bit
Slave Address: 7 Bits Refer to page 2 for address choices based on ADDR_SEL pin setting
Dummy Byte 0: 8 Bits
AK 1 Bit
Data Byte 0: 8 Bits N1 N0 M8 M7 M6 M5 M4 M3
AK 1 Bi t
M2
M1
M0
Data Byte 1: 8 Bits Not Not Used Used
AK Not Used Not Used Not Used 1 Bit
Data Byte 2: 8 Bits Up Down SSC5 SSC4 SSC3 SSC2 SSC1 SSC0
AK 1 Bit
SP 1 Bit
Data Byte values latched into control registers here.
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
has been selected and the M-divider value will toggle between the programmed M value, and M-SS at a 32kHz rate. When both the UP and DN bits are HIGH, then centerspread has been selected and the M-divider will toggle between M+SS and M-SS at a 32kHz rate. The table below shows the desired SS value to achieve 0.5%, 1% and 1.5% spread at selected VCO frequencies. To disable Spread Spectrum operation, program both the UP and DN bits to LOW. Spread Spectrum operation will also be disabled when the nP_LOAD input is LOW.
SPREAD SPECTRUM OPERATION
NOTE: The functional description that follows used a 16.6667MHz crystal with an M divide value of 160. Spread Spectrum operation is controlled by I2C Data Byte 2, Spread Spectrum Control Register. Bits SSC0 - SSC5 (SS) of the register are a subtrahend to the M-divider for down-spread, and they are an addend and a subtrahend to the M-divider for center-spread. When the UP bit is HIGH, then up-spread has been selected and the M-divider value will toggle between the programmed M value, and M+SS at a 32kHz rate. When the DN bit is HIGH, then down-spread
TABLE 1A. SS MODE FUNCTION TABLE
Register Bits SSC7 0 0 1 1 SSC6 0 1 0 1 SS Mode Off Down-Spread Up-Spread Center-Spread
TABLE 1B. UP/DOWN SPREAD CONFIGURATION
Up- or Down-Spread SS Value SSC5 0 0 0 0 0 0 0 0 SSC 4 0 0 0 0 0 0 0 1 SSC3 0 0 0 1 1 1 1 0 SSC2 0 1 1 0 0 1 1 0 SSC1 0 0 1 0 1 0 1 0 SSC0 1 0 0 0 0 0 0 0 Spread % 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
TABLE 1C. CENTER SPREAD CONFIGURATION
Center-Spread SS Value SSC5 0 0 0 0 SSC4 0 0 0 0 SSC3 0 0 0 1 SSC2 0 1 1 0 SSC1 0 0 1 0 SSC0 1 0 0 0 Spread () % 0.50 1.00 1.50 2.00
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The programmable features of the ICS84330-03 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and I2C. Figure 1 shows the timing diagram for parallel mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the LOWto-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until an I2C event occurs. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x 2M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 120 M 336. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N N 16
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16.6667MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 7, NOTE 1. The ICS84330-03 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
Time
FIGURE 1. PARALLEL LOAD OPERATIONS
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input NOTE 1 NOTE 1 Description I2C serial clock input. I2C serial data input. Analog supply pin. Pulldown PLL reference input. LVCMOS / LVTTL interface levels. Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT Pullup when LOW. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is an oscillator input. XTAL_OUT is an oscillator output. Pullup Output enable. LVCMOS / LVTTL interface levels. Parallel load input. Determines when data present at M8:M0 is loaded Pullup into M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup No connect. Determines N output divider value as defined in Table 4B Function Pulldown Table. LVCMOS / LVTTL interface levels. When logic LOW, bypass PLL. When logic HIGH, PLL is active. Pullup LVCMOS/LVTTL interface levels. Negative supply pins. Core supply pins. Differential clock outputs. LVPECL interface levels.
TABLE 2. PIN DESCRIPTIONS
Number 1 2 3 4, 5 6 7 8, 9 10 11 12, 13, 14, 15, 17, 18, 19, 20 21 16 22, 23 24 25, 29 26, 32 27, 28 Name SCL SDA ADDR_SEL VCCA FREF_EXT XTAL_SEL XTAL_IN, XTAL_OUT OE nP_LOAD M0, M1, M2 M3, M4, M5 M6, M7 M8 nc N0, N1 VCO_SEL VEE VCC nQ1, Q1
Pulldown Serial address select pin. LVCMOS / LVTTL interface levels.
Power Input Input Input Input Input
Input Input Unused Input Input Power Power Output
30, 31 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values. NOTE 1: Pullup resistor is only active in parallel mode.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
256 M8 0 0 0 0 * * 1 1 1 128 M7 0 0 0 0 * * 0 0 0 64 M6 1 1 1 1 * * 1 1 1 32 M5 1 1 1 1 * * 0 0 0 16 M4 1 1 1 1 * * 0 0 1 8 M3 1 1 1 1 * * 1 1 0 4 M2 0 0 0 0 * * 1 1 0 2 M1 0 0 1 1 * * 1 1 0 1 M0 0 1 0 1 * * 0 1 0
TABLE 4A. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 250 252 254 256 * * 696 698 700 M Divide 120 121 122 123 * * 334 335 336
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16.6667MHz.
TABLE 4B. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 Q0/nQ0 /2 /1 /2 /1 Outputs Q1/nQ1 /4 /2 /6 /3
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REV. A FEBRUARY 2, 2006
Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, JA 47.9C/W (0 lfpm)
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA ICC ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3. 3 3.3 Maximum 3.465 3.465 180 15 Units V V mA mA
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input ADDR_SEL, SDA, High Current SCL, FREF_EXT, VCO_SEL, M0:M7 M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input ADDR_SEL, SDA, Low Current SCL, FREF_EXT, VCO_SEL, M0:M7 Test Conditions Minimum Typical 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 Maximum VCC + 0.3 0.8 5 150 Units V V A A A A
IIH
IIL
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 10 Typical Maximum 25 50 7 1 Units MHz pF mW
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
Fundamental
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter XTAL; NOTE 1 Input Frequency SCL Test Conditions Minimum 10 Typical Maximum 25 10 Units MH z MHz
FREF_EXT; NOTE 2 10 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 M 511. Using the maximum frequency of 25MHz, valid values of M are 80 M 224. NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for recommendations on optimizing the performance using the FREF_EXT input.
TABLE 8. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol FOUT t jit(per) t jit(cc) t sk(o) tR / tF tS tH FM SSCred tL odc Parameter Output Frequency Period Jitter, RMS; NOTE 1, 2 Cycle-to-Cycle Jitter ; NOTE 1, 2 Output Skew; NOTE 3 Output Rise/Fall Time Setup Time Hold Time SDA to SCL M, N to nP_LOAD SDA to SCL 20% to 80% 200 20 20 20 20 XTAL_IN = 16.6667MHz 30 -7 N /1 48 32 -10 10 52 33.33 3 20 Test Conditions Minimum Typical Maximum 700 9 40 80 900 Units MHz ps ps ps ps ns ns ns ns kH z dB ms % ps
M, N to nP_LOAD SSC Modulation Frequency; NOTE 4 Spectral Reduction; NOTE 4 Output Duty Cycle
PLL Lock Time
tPW Output Pulse Width N = /1 tPERIOD/2 - 275 tPERIOD/2 tPERIOD/2 + 275 See Parameter Measurement Information section. Characterized using a XTAL input. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65 NOTE 2: See Applications section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 4: Spread Spectrum clocking enabled.
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V 2V
VOH
VCC VCCA
Qx
SCOPE
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VREF VOL
LVPECL
nQx
VEE -1.3V 0.165V
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nQ0, nQ1 Q0, Q1 tcycle n
nQx Qx
tcycle n+1
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
nQ0, nQ1 Q0, Q1 80% 80% VSW I N G
t
PERIOD
t PW
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84330AY-03
nQy Qy
tsk(o)
OUTPUT SKEW
Clock Outputs
20% tR tF
20%
x 100%
OUTPUT RISE/FALL TIME
REV. A FEBRUARY 2, 2006
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Integrated Circuit Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84330-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS:
SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
The ICS84330-03 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
50
Cycle-to-Cycle Jitter (ps)
40 30 20 10 0 200
Spec Limit N=1
300
400
500
600
700
Output Frequency (MHz)
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
(instead of 0V to 3.3V). Figure 6B shows amplitude reduction approach for a short trace. The circuit shown in Figure 6C reduces amplitude swing and also slows down the edge rate by increasing the resistor value.
JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the jitter performance can be improved by reducing the amplitude swing and slowing down the edge rate. Figure 6A shows an amplitude reduction approach for a long trace. The swing will be approximately 0.85V for logic low and 2.5V for logic high
VDD VDD Zo = 50 Ohm Td R1 100 VDD
Ro ~ 7 Ohm
RS 43
GND R2 100 TEST_CLK
FREF_EXT
Driver_LVCMOS
FIGURE 6A. AMPLITUDE REDUCTION FOR A LONG TRACE
VDD VDD R1 200 Ro ~ 7 Ohm RS 100 Driver_LVCMOS R2 200 VDD
GND TEST_CLK
FREF_EXT
FIGURE 6B. AMPLITUDE REDUCTION FOR A SHORT TRACE
VDD VDD R1 400 Ro ~ 7 Ohm RS 200 Driver_LVCMOS R2 400 VDD
GND TEST_CLK FREF_EXT
FIGURE 6C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
It is important to note the ICS84330-03 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used from the nominal 333MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 7A below. The ramp profile can be expressed as: * Fnom = Nominal Clock Frequency in Spread OFF mode (333MHz with 16.6667MHz IN) * Fm = Nominal Modulation Frequency (32kHz) * = Modulation Factor (0.25% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < 1 , 2 fm (1 - ) fnom - 2 fm x x fnom x t when 1 < t < 1 2 fm fm
- 10 dBm
Fnom
B
A
0.5/fm 1/fm
FIGURE 7A. TRIANGLE FREQUENCY MODULATION
FIGURE 7B. 333MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
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(1 - ) Fnom
= 0.25%
REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 8A and 8B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 8A. LVPECL OUTPUT TERMINATION
FIGURE 8B. LVPECL OUTPUT TERMINATION
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84330-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 623.7 + 60mW = 683.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.684W * 42.1C/W = 98.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE JA FOR 32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 9.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 10. JAVS. AIR FLOW 32 LEAD LQFP TABLE
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84330-03 is: 9304
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS84330AY03 ICS84330AY03 ICS84330A03L ICS84330A03L Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 12. ORDERING INFORMATION
Part/Order Number ICS84330AY-03 ICS84330AY-03T ICS84330AY-03LF ICS84330AY-03LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84330AY-03
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