View DG211CJZ_872016.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
DG211
Data Sheet December 21, 2005 FN3118.4
SPST 4-Channel Analog Switch
The DG211 is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation, process control and computer peripheral equipment and provides true bidirectional performance in the ON condition and blocks signals to 30VP-P in the OFF condition.
Features
* Switches 15V Analog Signals * TTL Compatibility * Logic Inputs Accept Negative Voltages * rON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 * Pb-Free Plus Anneal Available (RoHS Compliant)
Part Number Information
PART NUMBER DG211CJ PART TEMP. MARKING RANGE (C) DG211CJ 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 16 Ld PDIP 16 Ld PDIP* (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. NO. E16.3 E16.3 M16.15
Functional Block Diagrams
DG211
S1 IN1 D1 S2 IN2
DG211CJZ DG211CJZ (Notes 1, 2) DG211CY (Note 2) DG211CY
DG211CYZ DG211CYZ (Notes 1, 2)
M16.15
D2 S3 IN3 D3 S4 IN4 D4
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "T" suffix for Tape and Reel.
TRUTH TABLE LOGIC 0 1 DG211 ON OFF
Pinout
DG211 (PDIP, SOIC) TOP VIEW
IN1 D1 S1 VGND S4 D4 IN4 1 2 3 4 5 6 7 8 16 IN2 15 D2 14 S2 13 V+ (SUBSTRATE) 12 VL (+5V) 11 S3 10 D3 9 IN3
Logic "0" 0.8V, Logic "1" 2.4V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
DG211 Schematic Diagram
DG211 (1/4 AS SHOWN)
TTL IN -15V
GND
+15V +5V VL -15V V-
-15V +15V IN OUT
2
FN3118.4 December 21, 2005
DG211
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V VIN to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V VS or VD to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to -36V VS or VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 36V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Thermal Information
Thermal Resistance (Typical, Note 3)
JA (C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF1 tOFF2 OFF Isolation, OIRR (Note 7)
V+ = +15V, V- = -15V, VL = +5V, GND, TA = 25C TEST CONDITIONS (NOTE 4) MIN (NOTE 5) TYP MAX UNITS
See Figure 1 VS = 10V, RL = 1k, CL = 35pF
-
460
-
ns
VIN = 5V, RL = 1k, CL = 15pF, VS = 1VRMS , f = 100kHz VD = VS = 0V, VIN = 5V, f = 1MHz -
360 450 70 -90 5 5 16
-
ns ns dB dB pF pF pF
Crosstalk (Channel to Channel), CCRR Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, IIH
VIN = 2.4V VIN = 15V
-1.0 -1.0
-0.0004 0.003 -0.0004
1.0 -
A A A
Input Current with Voltage Low, IIL ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Source OFF Leakage Current, IS(OFF)
VIN = 0V
-15 VD = 10V, IS = 1mA, VIN = 0.8V VIN = 2.4V VS = 14V, VD = -14V VS = -14V, VD = 14V -5.0 -5.0 -5.0
150 0.01 -0.02 0.01 -0.02 0.1 -0.15
15 175 5.0 5.0 5.0 -
V nA nA nA nA nA nA
Drain OFF Leakage Current, ID(OFF)
VS = -14V, VD = 14V VS = 14V, VD = -14V
Drain ON Leakage Current, ID(ON) (Note 6)
VIN = 0.8V
VS = VD = 14V VS = VD = -14V
3
FN3118.4 December 21, 2005
DG211
Electrical Specifications
PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, ILogic Supply Current, IL NOTES: 4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet. 5. For design reference only, not 100% tested. 6. ID(ON) is leakage from driver into ON switch. VS 7. OFF Isolation = 20 log ------- , V S = Input to OFF switch, V D = output . VD VIN = 0V or 2.4V 0.1 0.1 0.1 10 10 10 A A A V+ = +15V, V- = -15V, VL = +5V, GND, TA = 25C (Continued) TEST CONDITIONS (NOTE 4) MIN (NOTE 5) TYP MAX UNITS
Test Circuits and Waveforms
Switch output waveform shown for VS = constant with logic input waveform as shown. Note the VS may be + or - as per switching time test circuit. VO is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
5V VL LOGIC INPUT (IN1) tr < 20ns tf < 20ns SWITCH V INPUT S 90% SWITCH OUTPUT (VO) 0V tOFF1 90% 10% tON tOFF2 GND SWITCH INPUT VS = 10V IN1 S1
15V V+ SWITCH OUTPUT VO RL 1k CL 35pF
50%
D1
LOGIC INPUT
V-15V RL
(REPEAT TEST FOR IN2 , IN3 AND IN4)
Logic shown for DG211.
FIGURE 1. SWITCHING TIME MEASUREMENT POINTS
VO = VS
RL + rDS(ON)
FIGURE 2. SWITCHING TIME TEST CIRCUIT
4
FN3118.4 December 21, 2005
DG211 Die Characteristics
DIE DIMENSIONS: 2159m x 2235m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG211
PIN 1 IN 1 PIN 2 D1
PIN 16 IN 2 PIN 15 D2
PIN 3 S1
PIN 14 S2
PIN 4 V-
PIN 13 V+ (SUBSTRATE)
PIN 5 GND
PIN 12 VL
PIN 6 S4
PIN 11 S3
PIN 7 D4 PIN 8 IN 4 PIN 9 IN 3 PIN 10 D3
5
FN3118.4 December 21, 2005
DG211 Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
6
FN3118.4 December 21, 2005
DG211 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.25 0.40 16 8 0 8 MAX 1.75 0.25 0.51 0.25 10.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 0.2284 0.0099 0.016 16 0
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 0.2440 0.0196 0.050
A1 B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN3118.4 December 21, 2005

▲Up To Search▲

Price & Availability of DG211CJZ

	To Download DG211CJZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .