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KS8620
INTRODUCTION
1 Chip CODEC for Digital Answering phone
The KS8620 consists of on-chip PCM encoders, decoders (PCM CODECs) and PCM line filter. This device provide all the functions required to interface a fullduplex voice telephone circuit, digital answering phone. This device is designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering function in PCM system. Also it is intended to be used at the analog termination of a PCM line / trunk. This device provide the Band pass filtering of the analog signals prior to encoding and after decoding. This combination device performs the encoding and decoding of voice and call progress tones as well as the signaling and supervision information.
16-DIP-300
16-SOP-BD300 - SG
ORDERING INFORMATION
Device KS8620N Package 16-DIP-300 16-SOP- BD300 - SG Operating Temperature 0oC ~ + 70oC
FEATURES
* Complete CODEC and filtering system * Encoding / Decoding : 8 bits -law PCM * On-chip auto zero, sample and hold, and precision voltage references * Low power dissipation : 60mW ( operating ) 3mW ( standby ) * + 5V operation * TTL or CMOS compatible * Automatic power down
KS8620D
PIN CONFIGURATION
V BB GNDA VF RO V CC 1 2 3 4 16 VFI XI+ 15 VFXI14 GSX
KS8620
13 TSX 12 FSX 11 DX 10 BCLK X 9 MCLK X
FS R 5 DR BCLK R/CLKSEL MCLK R/PDN 6 7 8
KS8620
BLOCK DIAGRAM
R2
1 Chip CODEC for Digital Answering phone
14
GSx VFxIR1
Auto-zero logic Switched Capacitor B.P.F
15 Analog In 16
+
VFxI+
RC Active Filter
Sample & Hold DAC
11 Dx
comparator
Voltage Reference
A/D Control Logic
X'it register DE
VFRO
3
Power Amplifier
RC Active Filter
Switched Capacitor L.P.F
Sample & Hold DAC
6
DR
Receive register CLK
Timing and Control
13 /TSx
4
Vcc
1
VBB
2
GNDA
9
MCLKx
8
MCLKR / PDN
10
BCLKx
7
BCLKR / CLKSEL
5
FSR
12
FSx
Fig 1. Block Diagram
KS8620
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 Symbol VBB GNDA VFRO VCC FSR DR BCLKR / CLKSEL
1 Chip CODEC for Digital Answering phone
Description VBB = -5V + 5% Analog ground Analog output of the receiver filter Vcc = +5V + 5% Receive frame sync pulse. 8KHz pulse train. PCM data input Logic input which selects either 1.536MHz / 1.544MHz or 2.048MHz for master clock in normal operation and BCLKx is used for both TX and RX directions. Alternately direct clock input available, vary from 64KHz to 2.048MHz.
8
MCLKR / PDN
When MCLKR is connected continuously high, the device goes powered down . Normally connected continuously low, MCLKx is selected for all DAC timing. Alternately direct 1.536MHz / 1.544MHz or 2.048MHz clock input is available.
9 10
MCLKX BCLKX DX FSX TSX GSX VFXIVFXI+
1.536MHz / 1.544MHz or 2.048MHz clock input is available May be vary from 64KHz 2.048MHz, but BCLKx is externally tied with MCLKx in normal operation.
11 12 13 14
PCM data output. TX frame sync pulse. 8KHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor between pin 14 to pin 15.
15 16
Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal.
ABSOLUTE MAXIMUM RATINGS ( Ta = 25 oC)
Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at any Analog Input or Output Voltage at any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature Range ( soldering , 10 sec ) Symbol Vcc VBB V I (A) V I (D) Ta TSTG TLEAD Value +7 -7 Vcc + 0.3 to VBB - 0.3 Vcc + 0.3 to GNDA - 0.3 0 to 70 -65 to +150 300 Unit V V V V
oC oC oC
KS8620
1 Chip CODEC for Digital Answering phone
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified : Ta = 0oC to 70oC , Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic Power Dissipation Power down Current I CC ( down ) I BB ( down ) Active Current I CC ( A ) I BB ( A ) Digital Interface Input Low Voltage Input High Voltage Input Low Current Input High Current V IL V IH I IL I IH GNDA < VIN < VIL , all digital input VIH < VIN < Vcc DX , IL = 3.2 mA Output Low Voltage V OL SIGR , IL = 1.0 mA /TSX , IL = 3.2 mA , open drain Output High Voltage V OH DX , IH = -3.2 mA SIGR , IH = -1.0 mA Output Current in High impedance state ( Tri - state ) I OH (HZ) DX , GNDA < VO < Vcc 2.4 2.4 -15 15 uA 2.2 -15 -15 15 15 0.4 0.4 0.4 V 0.6 V V uA uA V No Load No Load No Load No Load 0.5 0.05 6.0 6.0 3.0 1.0 10 10 mA mA System Test Conditions Min Typ Max Unit
Analog Interface with Receiver Filter
Output Resistance Load Resistance Load Capacitance Output DC offset voltage RO RL CL V OO(RX) -200 pin VFRO VFRO = + / - 2.5V 600 500 200 1 3 pF mV
Analog Interface with Transmit input Amp
Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain bandwidth Offset Voltage Common - mode Voltage Common mode rejection ratio Power supply rejection ratio I LKG RI RO RL CL V OD(TX) GV BW V IO(TX) V CM(TX) CMRR PSRR CMRRXA > 60dB DC test DC test -2.5V< V<+2.5V , VFXI+ or VFXI-2.5V< V<+2.5V , VFXI+ or VFXIclosed loop , unity gain GSx GSx GSx , RL < 10K VFXI+ to GSx +/-2.8 5,000 1 -20 -2.5 55 55 2 20 2.5 10 50 -200 10 1 3 200 nA M K pF V V/V MHz mV V dB dB
KS8620
1 Chip CODEC for Digital Answering phone
TIMING CHARACTERISTICS
(Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic System Test Conditions Min Typ Depends on the device used Frequency of Master Clock fMCK and the BCLKR /CLKSEL pin. MCLKx and MCLKR Rise time of Bit Clock Fall Time of Bit Clock Hold Time for Bit Clock low to Frame sync Hold Time for Bit Clock High to Frame sync Set-up Time from Frame sync to Bit Clock low Delay time from BCLKx High to data valid Delay time to /TSx low Delay time from BCLKx low to data output disable Delay Time to valid data from FSx or BCLKx. Set-up Time from DR valid to BCLK x/R low Hold time from BCLK x/R low to DR invalid Set-up time from FS x/R to BCLK x/R low Width of master clock High Width of master clock Low Rise Time of Master clock Fall Time of Master clock tW(MCKH) tW(MCKL) tR(MCK) tF(MCK) tSU(FBLS) Short Frame sync pulse ( 1 or 2 bit clock periods long ) : note1 MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR 1st bit clock after the leading edge of FSx 50 160 160 50 50 nS nS nS nS nS 50 nS tH(BLDR) 50 nS tSU(DRBL) tD(VD) CL = 0 pF to 150 pF Whichever comes later. 50 nS 20 165 nS tD(/TSXL) tD(LDD) Load = 150pF + 2 LSTTL loads 50 140 165 nS nS tD(HDV) Load = 150pF + 2 LSTTL loads 0 180 nS tSU(FBCL) Long Frame only 80 nS tH(HFS) Short Frame only 0 nS tR(BCK) tF(BCK) tH(LFS) tPB = 488ns tPB = 488ns Long Frame only 0 1.536 1.544 2.048 50 50 nS nS nS Max Unit MHz
Set-up time from BCLKx High tSU(BHMF) ( FSx in Long Frame Sync mode ) to MCLKx falling edge Period of Bit Clock Width of Bit clock High Width of Bit clock Low Hold time from BCLK x/R to FS x/R low tCK tW(BCKH) tW(BCKL) tH(BLFL)
485 VIH = 2.2V VIL = 0.6V Short Frame sync pulse ( 1 or 2 bit clock periods long ) : note1 160 160 100
488 15,725
nS nS nS nS
KS8620
1 Chip CODEC for Digital Answering phone
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V, f = 1.02KHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting )
Characteristic Amplitude Response Receive Gain, Absolute
System
Test Conditions
Min
Typ
Max
Unit
GV(ARX)
Ta=25oC,VCC = 5V, VBB = -5V Input = Digital code sequence for 0dBm0 signal at 1020Hz
-1.5
1.5
dB
Receive Gain, Relative to Gv(RRX)
GV(RRX)
f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz
-0.6 -0.55 -1.5
0.5 0.5 1.5
dB
Absolute Receive Gain Variations with temperature Receive Gain Variations with level
GV(ARX) / T GV(RXL)
Ta = 0oC to 70oC
+ 0.1
dB
Sinusoidal test method; reference input PCM code correspond to an ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 -0.4 -0.8 -2.5 1.2276 2.501 0.4 0.8 2.5 V Vrms dB
Receive output drive level Absolute level VO(RX) VAL Max overload level VOL(MAX) GV(ATX) GV(RTX)
RL = 600 Norminal 0dBm0 level is same as 4 dBm ( 600 ) Max overload level ( 3.17dBm0)
VPK
Transmit gain, absolute
Ta = 25oC,Vcc =5V, VBB = -5V Input at GSx = 0dBm0 at 1020Hz
-1.5
1.5
dB
Transmit gain, relative to GV(ATX)
f = 16 Hz f = 50 Hz f = 60 Hz f = 200 Hz f = 300 Hz - 3000Hz f = 3300 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz and above, mesaure response from 0 Hz to 4 KHz -2 -0.5 -0.55 -1.5
-35 -25 -21 -0.5 0.5 0.5 -1.5 -10 -25
dB
KS8620
1 Chip CODEC for Digital Answering phone
TRANSMISSION CHARACTERISTICS ( Continued )
Characteristic Absolute trasmit gain variations with temperature Transmit gain variations with level System GV(ATX) / T GV(TXL) Sinusoldal test method ; Reference level = -10dBm0 VFXI + = -40dBm0 to +3dB0 VFXI + = -50dBm0 to -40dB0 Envelope Delay Distortion with Frequency Receive Delay, Absolute Receive Delay, Relative to tD (ARX) tD(ARX) tD(RRX) f = 1600Hz f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz Transmit Delay, Absolute Transmit Delay, Relative to tD(ATX) tD(ATX) tD(RTX) f = 1600Hz f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz Noise Receive Noise, C Message Weighted Transmit Noise, C Message Weighted NTXC NRXC PCM code equals alternating positive and negative zero, KS8620 KS8620 15 dBrnC0 18 dBrnC0 -40 -30 90 125 175 315 220 145 75 40 75 105 155 s s 200 s s -0.4 -0.8 0.4 0.8 dB Test Conditions Ta = 0oC to 70oC Min Typ Max Unit
+ 0.1
dB
KS8620
1 Chip CODEC for Digital Answering phone
TRANSMISSION CHARACTERISTICS ( Continued )
Characteristic Noise, Single Frequency System Test Conditions f = 0KHz to 100KHz, loop around measurement, VFXI+ = 0Vrms Positive Power Supply Rejection, Transmit PSRR(PTX) VFXI+ = 0 Vrms, Vcc = 5.0 VDC + 100mVms f = 0KHz - 50KHz Negative Power Supply Rejection, Transmit PSRR(NTX) VFXI+ = 0 Vrms, VBB = -5.0 VDC + 100mVrms f = 0KHz - 50KHz Positive Power Supply Rejection, Receive PSRR(PRX) PCM code equals positive zero Vcc = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz PCM code equals positive zero Negative Power Supply Rejection, Receive PSRR(NRX) VBB = -5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz Spurious Out-Band Signals at the Channel Output SOS Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR , Measure individual image signals at VFRO 4600Hz -7600Hz 7600Hz - 100,000Hz Distortion Signal to Total Distortion Transmit or Receive Half-Channel THDTX THDRX Sinusoidal test method ; level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV 28 30 25 25 dBC -28 -35 dB 25 25 dBC dB 25 25 dBC dB 25 dBC 25 Min Typ Max Unit
NSF
-53
dBm0 dBC
KS8620
1 Chip CODEC for Digital Answering phone
TRANSMISSION CHARACTERISTICS ( Continued )
Characteristic System Test Conditions Min Typ Max Unit
Single Frequency Disotrtion, THDSF(TX) Transmit Single Frequency Distortion, THDSF(RX) Receive Intermodulation Distortion THDIMD Loop around measurement, VFXI+ = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz Crosstalk Transmit to Receive Crosstalk, 0dBm0 Transmit level Reveive to Transmit Crosstalk, 0dBm0 Receive level CT(RX-TX) f = 300Hz - 3400Hz, VFXI = 0V -90 CT(TX-RX) f = 300Hz - 3400Hz DR = Steady PCM code -90
-41
-dB
-41
-dB
-35
-dB
-75
dB
-70 (note1)
dB
Note 1. CT(RX-TX) is measured with a -40dBm0 activating signal applied at VFXI+
ENCODING FORMAT AT D X OUTPUT -Law
VIN ( at GSX ) = + Full Scale VIN ( at GSx ) = 0V
PCM : KS8620
10000000 11111111 01111111
VIN ( at GSx )
= - Full Scale
00000000

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