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 ADVANCE INFORMATION
CIP 3250A Component Interface Processor
Edition Oct. 9, 1996 6251-403-3AI
MICRONAS
CIP 3250A
Contents Page 4 4 4 7 7 7 7 7 8 8 8 8 9 9 10 10 11 11 13 14 14 14 15 15 15 15 15 16 27 27 27 30 32 33 35 35 35 36 36 36 36 37 37 38 38 39 39 2 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.7.1. 2.7.2. 2.8. 2.9. 2.9.1. 2.10. 2.11. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.13. 2.14. 2.15. 2.16. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 3.6.3.1. 3.6.3.2. 3.6.3.3. 3.6.3.4. 3.6.3.5. 3.6.3.6. 3.6.3.7. 3.6.3.8. 3.6.3.9. Title Introduction Block Diagram System Configurations Functional Description Analog Front End Clamping Matrix YUV Control (on RGB-path only) Delay Adjustment Skew Filter Fast Blank Processing Soft Mixer Fast Blank Monitor FSY Front Sync and AVI Active Video In Digital Input Formats The Chroma Demultiplexers YUVin Interpolator (LPF 4:4:4) YUV Output Low-pass Filter 4:2:2 and 4:1:1 Selectable RGB/YUV Output Formats DIGIT 2000 4:1:1 Output Format DIGIT 2000 4:2:2 Output Format DIGIT 3000 Orthogonal 4:2:2 Output Format Orthogonal 4:1:1 Output Format YUV Output Levels I/O Code Levels AVO Active Video Output PRIO Interface I2C Serial Bus Control Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Characteristics Standby Input Characteristics Test Input Characteristics Reset Input Characteristics Main Clock Input Characteristics Active Video Output Characteristics Active Video Input Characteristics Fsync Input Characteristics I2C Bus Interface Input/Output Characteristics Luma/Chroma Input
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CIP 3250A
Contents, continued Page 40 41 42 42 43 44 Section 3.6.3.10. 3.6.3.11. 3.6.3.12. 3.6.3.13. 4. 5. Title Characteristics Priority Input/Output Characteristics Picture Output Characteristics Analog R, G, B Inputs Characteristics Analog FBL Input Application Circuit Data Sheet History
Micronas
3
CIP 3250A
Component Interface Processor Release Notes: Revision bars indicate significant changes to the previous edition. 1. Introduction The CIP 3250A is a new CMOS IC that contains on a single chip the entire circuitry to interface analog YUV/ RGB/Fast Blank to a digital YUV system. The Fast Blank signal is used to control a soft mixer between the digitized RGB and an external digital YUV source. The CIP supports various output formats such as YUV 4:1:1/4:2:2 or RGB 4:4:4. Together with the DIGIT 3000 (e.g. VPC 32xxA) or DIGIT 2000 (e.g. DTI 2250), an interface to a TV-scanrate conversion circuit and/or multi-media frame buffer can be obtained. 1.1. Block Diagram The CIP 3250A contains the following main functional blocks (see Fig.1-1): - analog input for RGB or YUV and Fast Blank - triple 8 bit analog to digital converters for RGB/YUV with internal programmable clamping - single 6 bit analog to digital converter for Fast Blank signal
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- digital matrix RGB YUV (Y, B-Y, R-Y) - luma contrast and brightness correction for signals from analog input - color saturation and hue correction for signals from analog input - digital input for DIGIT 2000 or DIGIT 3000 formats - digital interpolation to 4:4:4 format - high quality soft mixer controlled by Fast Blank signal - programmable delays to match digital YUVin and analog RGB/YUV - variable low pass filters for YUV output - digital output in DIGIT 2000 and DIGIT 3000 formats, as well as RGB 4:4:4 - I2C bus interface - clock frequency 13.5 ... 20.25 MHz
1.2. System Configurations The following figures, 1-2 and 1-3, show different basic system applications for the CIP 3250A in the DIGIT 3000 environment. Beyond that, a stand alone application (figure 1-4) also shows the flexibility of the CIP 3250A in implementing simple analog video interfaces to digital standards.
FSY
YUV 4:1:1 YUV 4:2:2
FSY interface
Format Conversion 4:4:4 YUV 4:1:1 YUV 4:2:2 RGB 4:4:4
R/V G/Y B/U FBL clock buffer ADC MATRIX (on/off)
CT BR SAT
SOFT MIXER (4:4:4)
Adjustable LPF
Format Conversion
CLK
I2C interface
I2C Bus
Fig. 1-1: Block diagram of the CIP 3250A Component Interface Processor
4
Micronas
ADVANCE INFORMATION
CIP 3250A
H,V-Sync Clock CVBS Y, C RGB/YUV Fast Blank Fig. 1-2: Complete DIGIT 3000 application for 100 Hz and/or PAL+
VPC32xxA
CIP3250A
100 Hz/PAL+ Feature Box
DDP3310B
CRT
H,V-Sync Clock CVBS Y, C RGB/YUV Fast Blank Fig. 1-3: DIGIT 3000 video front-end for ITUR-601 or square pixel data output
VPC32xxA
CIP3250A
YUV Data
CCU 3000
2 I2C Bus Clock HSYNC, VSYNC
CVBS
TV Module
RGB/YUV
CIP3250A
orthogonal YUV pixel
Fig. 1-4: CIP 3250A in a stand alone video application for multimedia or scan rate conversion
Micronas
5
clamp
R/V
ADC 8 bit
clamp
clamp control
G/Y
8
Matrix (on/off)
ADC 8 bit
clamp
B/U
ADC 8 bit
clock buffer
ADC 6 bit
6
FSY AVI 12, 16 YUVin
SKEW FSY AVI HSYNC VSYNC
CIP 3250A
*1)
*2)
RGB-ADC mode
DL1 adjust
(78)
Input Formatter
UV-mux
LPF 4:4:4
Video Control Logic
AVI
AVO
ctrl
8
WR RD
CT BR SAT
Skew Filter *2)
SOFT MIX
Skew Filter *1)
UV-mux
72 Bit
Adjustable LPF
Output Formatter
12 16 R/UV 24 G/Y B 3
DL2 adjust
(48...212)
PRIO coder
PRIO
8
FBL
6
Skew Filter *2) I2C interface
CIP 3250A
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2 CLK I2C Bus
Fig. 2-1: CIP 3250A block diagram Micronas Note: *1) Only used in DIGIT 2000 mode *2) Only used in DIGIT 3000 mode
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CIP 3250A
ue via I2C registers <18> and <19>. A window size of 32 or 64 sample clocks is recommended. Clamping is disabled if start and stop values are equal after reset. Once enabled it can not be switched off. Using a coupling capacitor of 220 nF, a hum of approximately 400 mV at 50 Hz can be compensated. 2.3. Matrix - matrix RGB Y(R-Y)(B-Y): Y = 0.299*R + 0.587*G + 0.114*B (R-Y) = 0.701*R - 0.587*G - 0.114*B (B-Y) = -0.299*R - 0.587*G + 0.886*B - fixed coefficients with a resolution of 8 bits. - matrix enable/disable for analog RGB/YUV input programmable via I2C register The matrix of the CIP 3250A converts the digitized RGB signals to the intermediate signals Y, R-Y, and B-Y. Enable the matrix via I2C register <04>MAON. The intermediate signals at the output of the matrix can be converted to YUV signals of the DIGIT 2000 system or to YCrCb of the DIGIT 3000 system by the YUV control (see section 2.4.). To omit conversion from RGB to Y(R-Y)(B-Y), switch off the matrix and the CTBRST block via I2C register <04>MAON and <04>CBSON. 2.4. YUV Control (on RGB-path only ) - Y contrast (ct) and brightness (br) with rounding or noise shaping and limiting to 8 bit: Y = Y*ct + br ct = 0 ... 63/32 in 64 steps br = -128 ... +127 in 256 steps - UV saturation (sat) with rounding or noise shaping and limiting to 8 bit (controllable by CCU via I2C bus): UEXT = (B-Y) * Usat VEXT = (R-Y) * Vsat Usat,Vsat = 0 ... 63/32 in 64 steps (UINT = [0.5*(B-Y)] * Usat VINT = [0.875*(R-Y)] * Vsat) Within the CTBRST block, switched on via I2C register <04>CBSON, two different options can be used to convert from (R-Y)(B-Y) to UV (PAL standard). In internal mode (UVINT), conversion to PAL standard is done before the multiplication of the contents of the saturation registers. Using the external mode (UVEXT) of <04>SMODE, the user has to implement the conversion factors via the two saturation registers (Usat, Vsat). Since the two saturation registers can be programmed separately, it is also very easy to convert to YCrCb (Studio standard) of the DIGIT 3000 system. Contrast, brightness, and saturation can be adjusted for the video signals of the analog input via I2C registers <00> to <03>. A functional description of this circuit can be found in figures 2-2 and 2-3 respectively. To improve the amplitude resolution of the luma (Y) and chroma (UV) video signals after multiplication with the 7
2. Functional Description This section describes the functionality of the various blocks shown in the block diagram of Fig. 2-1 in detail. The CIP 3250A is controlled via an I2C bus interface. For information regarding how to program the registers of the CIP 3250A, please refer to the register list (see Tables 2-9 and 2-10). The I2C bus interface uses subaddressing to access the register. In the following, I2C registers are referenced by the sub-addresses given in parenthesis; for example, I2C register <9>. To interface correctly, a pin description for the CIP 3250A is given in section 3.3. 2.1. Analog Front End - SCART-level inputs (RGB/YUV and Fast Blank = 1.0 Vpp, Fast Blank must be ext. clipped) - triple 8-bit ADC for RGB/YUV - 6 bit ADC for Fast Blank - sampling rate 13.5 to 20.25 MHz - no sync separation included All analog video input signals and the analog Fast Blank signal must be band limited to 5 MHz before analog to digital conversion. The CIP 3250A can process either analog YUV input signals or analog RGB input signals which are ACcoupled with a nominal input voltage level of 700 mV + 3 dB (1 VPP). There is no circuitry implemented for internal sync separation. Input voltage range of the Fast Blank signal is 0 to 1 V. The Fast Blank input signal is DC-coupled. 2.2. Clamping - internal clamping for RGB and YUV with adjustable start and width - black level reference only during horizontal and vertical blanking interval on RGB/YUV inputs - no proper clamping if sync is on G In RGB mode, clamping takes place on black level (digital 16 or 8) using a clamping window as described below. In YUV mode, clamping is done on black level (digital 16) for Y (luma) and on saturation level zero (digital 128) for UV (chroma) using a clamping window. Select between RGB mode and YUV mode via I2C register <09>YUV. The black level reference value (digital 16 or 8) can be selected via I2C register <09>CLMPOFS. In a standard DIGIT 2000 application without a conversion of Y (luma) to ITUR code levels at the digital inputs (see section 2.9. <10>YLEVEL), convert the black level to digital 32 via I2C register <04>CLSEL. The clamping window is programmable in reference to the H-sync signal (see Fig. 2-13) by a start and stop valMicronas
CIP 3250A
weighting factors (ct) and (sat), the user can select between rounding and two different modes of noise shaping (1 bit error diffusion or 2 bit error diffusion).
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Rounding Y
6
1 bit Err. Diff. 2 bit Err. Diff.
8
255 0
Y 8
<17>PXSKWON. In this mode, the DL2 block serves as a variable delay to match the analog RGB/YUV data with digital YUV data. The first pixel of analog RGB/YUV written into the DL2 block (which works like a FIFO) is selected by <21>DL2. Read of the DL2 block starts synchronously with the AVI input, which in turn marks the first pixel in digital YUV data (see Fig. 2-14). Care must be taken that the number of pixels stored in DL2 block must be within the limits of 48 to 210. In case of SECAM processing in the DIGIT 2000 environment, the digital luma and chroma signals do not match in front of the CIP 3250A. Therefore, the I2C register <10>SECAM must be enabled, and fine adjustment has to be carried out within the ACVP. 2.6. Skew Filter Two interpolation filters perform data orthogonalization (= skew correction) for luma and chroma in case of a non-line-locked system clock. The skew value is serially input via the FSY input. In a system environment where digital YUV data are orthogonal (e.g. DIGIT 3000), the skew correction must be set to DIGIT 3000 mode via I2C register <04>SKWCBS in order to apply skew correction to analog RGB/YUV data only. Additionally, the skew correction must be switched on via I2C register <04>SKWON. This has to be done in order to mix the analog input with the digital YUV input correctly and to output the mixed YUV signal in an orthogonal format. For standard DIGIT 2000 operation, the skew correction should be switched off via I2C register <04>SKWON, in order to output the mixed YUV data with the same skew values as the digital YUV input. Only in special applications (e.g. multi media), where the output connects to a field or frame memory which processes orthogonal data, the skew correction for mixed YUV data has to be switched on and set to DIGIT 2000 mode via I2C register <04>SKWCBS. 2.7. Fast Blank Processing - mixing of RGB-path and YUV-path in YUV 4:4:4 format controlled by the Fast Blank signal - linear or nonlinear mixing technique selectable - programmable polarity of Fast Blank signal - programmable step response of Fast Blank signal - RGB-path or YUV-path can be statically selected - Fast Blank signal monitoring 2.7.1. Soft Mixer In the Fast Blank signal path, special hardware is supplied to improve edge effects, such as blurring because of band limiting in the analog front end. Different step responses are user selectable via I2C register <12>MIXAMP, still obtaining high quality phase resolution. Also, Micronas
2 ct Select br
I 2C Registers
Fig. 2-2: Luma Contrast & Brightness Adjustment
Rounding R-Y B-Y
6
1 bit Err. Diff. 2 bit Err. Diff.
127 -128
V U 8
2 sat Select
I 2C Registers
Fig. 2-3: Chroma Saturation Adjustment
2.5. Delay Adjustment - DL1 to compensate internal processing delay of the CIP 3250A in reference to digital YUVin - DL1 to compensate processing delay of the DIGIT 2000 SPU chroma channel in SECAM mode - DL2 to compensate delay between digital YUVin and analog RGBin or FSY; as for example, produced by ACVP or SPU. To mix the analog RGB/YUV input signals and the digital YUVin input signals at the soft mixer correctly, in reference to the horizontal synchronization pulse, two processing delay adjustments can be made. In many system applications, ICs in front of the CIP 3250A cause a fixed processing delay in the digital YUVin path. Therefore, a delay of up to 210 sample clocks can be programmed via I2C register <21>DL2 to match analog RGB/YUV data with digital YUV data . If the delay is less than 48 sample clocks, the DL1 block can be activated (80 sample clocks) via I2C register <10>DL1ON to get a value for <21>DL2 within the range of 48 to 210. In applications where there will be no fixed delay between digital YUVin and analog RGB/YUV, the pixel skew correction can be switched on via I2C register 8
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CIP 3250A
Table 2-1: Source selection of soft mixer
<11> PASSRGB 0 <06> PASSYUV X 0 1 Fast Blank signal X MIX X Source RGB YUV/RGB YUV
the polarity of the Fast Blank signal can be changed via I2C register <12>MIXAMP. The I2C register <11>FBLOFF influences the phase delay between the RGB path and the Fast Blank signal (see Fig. 2-4). Additionally, a delay of -1 to 2 clocks between the Fast Blank signal and the RGB-path is programmable via I2C register <16>FBLDEL. By selecting a positive delay, shadowing of characters can be obtained, if the background color of the RGB-path is set to black. With the built-in linear mixer, the CIP 3250A is able to support simple AB roll techniques between analog input (A) and digital YUV input (B): VideoOut = A * (1 - FBLMIX/32) + B * FBLMIX/32, controllable via the Fast Blank signal (FBL): FBLMIX = INT[(FBL - FBLOFF)* MIXAMP/2] + 16, with FBL of values from 0 to 63. The mixing coefficient FBLMIX resolves 32 steps within the range from 0 to 32 (dependent on step response chosen via I2C register <12>MIXAMP) (see Fig. 2-4).
1 1 X: don't care
2.7.2. Fast Blank Monitor Bits 0 to 3 of I2C register <27> are monitoring the analog Fast Blank input. Reading I2C register <27> Fig. 2-5 displays the contents depending on the analog FBL input signal.
analog fast blank input reading I2C register <27> <27>FBLSTAT <27>FBLRISE <27>FBLFALL 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 0
When the I2C register bit <16>FBLCLP is enabled, the soft mixer operates independently of the analog Fast Blank input. FBL is clamped to digital 31 (see Fig. 2-4). Mixing between RGB-path and YUV-path is controllable via the I2C register <11>FBLOFF.
<27>FBLHIGH
Fig. 2-5: Fast Blank Monitor
2.8. FSY Front Sync and AVI Active Video In
FBL (0...63) 6 31 16
0 1
- DIGIT 2000 chroma sync detection
1/2
32 0
FBLMIX 6
- DIGIT 2000 throughput of 72-bit data and clock - skew data input for DIGIT 2000 - skew data input for DIGIT 3000
fblclp
fbloff
mixamp
I 2C Registers
Fig. 2-4: Fast Blank Processing
- HSYNC as timing reference for clamping pulse generator - active video input to indicate valid video data and to synchronize chroma multiplex for DIGIT 3000
Select the linear mixer or the nonlinear mixer via I2C register <12>SELLIN. If the nonlinear mixer is selected, a dynamic delay control of the analog RGB/YUV input can be chosen, to avoid edge artefacts of the RGB/YUV signal (e.g. shading), during transition time of Fast Blank signal with the I2C register <12>CTRLDLY. In some applications, it is desired to disable the control by the Fast Blank signal and to pass through the digital YUVin path or the analog RGB/YUV path. This is possible by adequately programming the I2C registers <06>PASSYUV and <11>PASSRGB (Table 2-1). Micronas
The FSY input and the AVI input are used to supply all synchronization information necessary. Three basic modes of operation can be selected via I2C registers <06>D2KIN, <17>D2KSYNC, <17>SYNCSIM, and <17>P72BEN. In a DIGIT 2000 system environment, the CIP 3250A receives the synchronization information at the FSY input via the DIGIT 2000 SKEW-protocol. The AVI Input may be connected to ground GND or VDD (see section 2.14.). 9
CIP 3250A
ADVANCE INFORMATION
input analog video
(not in scale)
skew MSB Bit: 0 1 2 3 skew ig- ig- LSB nored nored 4 5 V: 6
Skew data
V
7
DIGIT 2000, and the YUV 4:2:2 (16 bit) standard from DIGIT 3000. Therefore, the CIP 3250A can be used in either the DIGIT 2000 system environment or the DIGIT 3000 system environment. Refer to I2C registers <06>DELAYU, <10>UVFRM3, and <10>UVFRM1 for a correct setup. Additionally, within the DIGIT 2000 system, a Y (luma) format conversion to ITU-R 601 can be achieved via programming the I2C register <10>YLEVEL. Table 2-2: Digital input selection
<06> DELAYU 0 0 1 1 <11> UVFRM3 0 0 1 0 <11> UVFRM1 0 1 0 0 Digital Input Format DIGIT 2000 4:2:2 DIGIT 2000 4:1:1 DIGIT 3000 4:2:2 MAC
Vert. sync 0 = off 1 = on
Fig. 2-6: DIGIT 2000 skew data In a DIGIT 3000 system environment, the CIP 3250A receives the synchronization information at the FSY input via the DIGIT 3000 FSY-protocol (see Fig. 2-7). The AVI input receives the chroma multiplex information implicitly with the rising edge of the AVI signal.
input analog video
2.9.1. The Chroma Demultiplexers (not in scale)
F0 F1
FSY
F1
skew MSB
skew ig- ig- LSB nored nored
V:
V Parity
Vert. sync 0 = off 1 = on
F0, F2 ... F5: reserved
In DIGIT 2000 mode, via pins 36 to 39, the CIP 3250A receives the V and U signals from the C0 to C3 outputs of the color decoder, time-multiplexed in 4-bit nibbles (Fig. 2-8). For the digital signal processing, the 4-bit V and U chroma nibbles are demultiplexed to 8-bit signals by the V and U demultiplexers. Both demultiplexers are clocked by the main clock. They are synchronized to the V and U transmission during the vertical blanking period.
Fig. 2-7: DIGIT 3000 front sync format a) In a stand alone application, for example, RGB-analogto-digital conversion, a horizontal sync pulse must serve the FSY input, and a vertical sync pulse must serve the AVI input. The polarity of these two sync pulses can be programmed via I2C registers <10>AVIINV and <07>FSYINV. Inside the CIP 3250A, synchronization information is being decoded and used to control clamping, DL2, skew filters, video control logic, input formatter, and output formatter as shown in Fig. 2-1. 2.9. Digital Input Formats - YUV 4:2:2 (16 bit) from DIGIT 2000 and DIGIT 3000 (YUV as well as YCrCb) - YUV 4:1:1 (12 bit) from DIGIT 2000 - input levels according to DIGIT 2000/DIGIT 3000 The CIP 3250A supports the YUV 4:1:1 (12 bit) standard from DIGIT 2000, the YUV 4:2:2 (16 bit) standard from 10
b)
H U MSB L four clock periods V LSB V MSB U LSB U MSB
c)
H L
Fig. 2-8: Timing diagram of the multiplexed color difference signal transfer between decoder and CIP 3250A Notes to Fig. 2-8: a) CLK main clock signal b) Multiplexed color difference signals from PVPU/ ACVP/SPU/VSP/DMA to DTI 2260 c) Sync pulse on C0 output during sync time in vertical blanking interval. Micronas
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CIP 3250A
2.11. YUV Output Low-pass Filter 4:2:2 and 4:1:1 - Y low-pass filter with 7 selectable cutoff frequencies - UV low-pass decimation filter 4:4:4 4:2:2/4:1:1 with 5 selectable cutoff frequencies To meet the bandwidth requirements of different video standards, such as 4:2:2 or 4:1:1 at various sampling frequencies, the luma signal (Y) and the chroma signal (UV) can be lowpass filtered. There are 7 different cutoff frequencies selectable for luma, via I2C register <05>LPFLUM and 5 different cutoff frequencies selectable for chroma, via I2C register <07>LPFCHR. The spectra of the luminance filters are shown in Fig. 2-9, and the spectra of the chrominance filters are shown in Fig. 2-10.
2.10. YUVin Interpolator (LPF 4:4:4) - UV-Interpolation 4:1:1 or 4:2:2 4:4:4 In order to mix the digital input data with the 4:4:4 video standard from the analog RGB/YUV input, correctly, the chroma samples of the digital input have to be interpolated. In case of YUV 4:1:1 input from DIGIT 2000, a two stage interpolation filter is implemented. In the first stage, an interpolation filter is used, which converts the YUV 4:1:1 standard into the YUV 4:2:2 standard. In the second stage, the interpolation is from the YUV 4:2:2 to YUV 4:4:4. In the case of YUV 4:2:2 input, only the second stage is necessary. Refer to I2C registers <06>DELAYU, <10>UVFRM3, and <10>UVFRM1 to choose the correct interpolation filters (see Fig. 2-2).
Micronas
11
CIP 3250A
ADVANCE INFORMATION
Y7 Y6
Y5
Y3 Y4 Y2
Y1
0
0.1*fs
0.2*fs
0.3*fs
0.4*fs
0.5*fs
Fig. 2-9: Spectra of selectable luminance filters
UV5 UV4
UV3 UV2
UV1
0
0.1*fs
0.2*fs
0.3*fs
0.4*fs
0.5*fs
Fig. 2-10: Spectra of selectable chrominance filters
12
Micronas
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CIP 3250A
In a DIGIT 3000 environment, the CIP 3250A can process either RGB or YUV signals from the analog input, mix it with the digital YUV input data - controlled by the Fast Blank input, and generate low pass filtered output data in the YUV 4:2:2 (16 bit) DIGIT 3000 format. Additionally, the signed format of the UV signal is programmable between 2's complement and binary offset. The sampling rate is derived from the VPC 320x and ranges from 13.5 to 20.25 MHz for all of the video standards. The U and V chrominance samples are transmitted in multiplex operation. Depending on the application, the CIP 3250A provides the following different output formats of the YUV signals (selectable via I2C-Bus): - 4:1:1 orthogonal output format for DIGIT 3000 applications - 4:2:2 orthogonal output format for DIGIT 3000 applications - 4:1:1 output format for standard DIGIT 2000 applications - 4:2:2 output format for DIGIT 2000 applications Refer to I2C registers <15> to <16> to select the desired output format. Additionally, the CIP 3250A provides conversion of ITURY (luma) to DIGIT 2000 Y (luma) output black levels, selectable via I2C register <16>ADD16Q. A programmable two-dimensional active video signal (AVO) allows the write control of external video memory directly. The characteristic of the YUV output is selectable between open-drain or push-pull.
2.12. Selectable RGB/YUV Output Formats - RGB, 8-bit pure binary (24 bit) - YUV 4:2:2 (16 bit) for DIGIT 2000, DIGIT 3000, and Philips/Siemens - YUV 4:1:1 (12 bit) for DIGIT 2000 and Philips/Siemens - UV format selectable between 2's complement and binary offset In a first stand alone application, the CIP 3250A can serve as a RGB video analog-to-digital converter to output digital R, G, and B in a pure binary format, 8 bits pure binary per channel, and a sampling rate between 13.5 MHz and 20.25 MHz. In a second stand alone application, the CIP 3250A can serve as a YUV or RGB (with the matrix switched on) video analog-to-digital converter to output digital YUV, supporting various formats such as YUV 4:1:1 (12 bit) from DIGIT 2000 and Philips, YUV 4:2:2 (16 bit) from DIGIT 2000 and DIGIT 3000, or YUV 4:2:2 (16 bit) industry standard. Additionally, the signed format of the UV signal is programmable between 2's complement and binary offset. A sampling rate between 13.5 MHz and 20.25 MHz can be selected, and the YUV output data can be low pass filtered. In a DIGIT 2000 environment, the CIP 3250A can process either RGB or YUV signals from the analog Input, mix it with the digital YUV Input data - controlled by the Fast Blank input, and generate low pass filtered output data in the YUV 4:1:1 (12 bit) DIGIT 2000 format. A sampling rate locked to the color subcarrier frequency (4*fsc) for the NTSC or PAL video standard has to be used.
Table 2-3: Digital output selection <15> YUVO 1 1 1 1 0 <15> MOD411ON 1 1 0 0 0 <15> IND 0 1 0 1 0 <15> UVSW 0 0 1 0 0 <15> DTI 0 0 1 0 0 Digital Output Format DIGIT 2000 4:1:1 orthogonal 4:1:1 DIGIT 2000 4:2:2 DIGIT 3000 4:2:2 4:4:4
Micronas
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CIP 3250A
2.12.1. DIGIT 2000 4:1:1 Output Format The DIGIT 2000 4:1:1 output format is shown in Tables 2-4 and 2-5. A control signal for the chroma multiplex is transmitted during the vertical blanking interval (see Section 2.9.1.). Table 2-4: Bit map of DIGIT 2000 4:1:1 format Luma Chroma C3 , C7 C2 , C6 C1 , C5 C0 , C4 Y1 V23 V22 V21 V20 Y2 V27 V26 V25 V24 Y3 U13 U12 U11 U10 Y4 U17 U16 U15 U14
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Table 2-6: DIGIT 2000 4:2:2 output format Luma Chroma C7 C6 C5 C4 C3 C2 C1 C0 Y1 V27 V26 V25 V24 V23 V22 V21 V20 Y2 U17 U16 U15 U14 U13 U12 U11 U10 Y3 V47 V46 V45 V44 V43 V42 V41 V40 Y4 U37 U36 U35 U34 U33 U32 U31 U30
Note: UxY x = pixel number and y = bit number 2.12.3. DIGIT 3000 Orthogonal 4:2:2 Output Format The DIGIT 3000 orthogonal 4:2:2 output format is compatible to the industry standard. The U and V samples are skew corrected and interpolated to an orthogonal sampling raster, e.g. every line starts with the current U pixel (see Table 2-7). Table 2-7: Orthogonal 4:2:2 output format Luma Chroma C7 C6 C5 C4 C3 C2 C1 C0 Y1 U17 U16 U15 U14 U13 U12 U11 U10 Y2 V17 V16 V15 V14 V13 V12 V11 V10 Y3 U37 U36 U35 U34 U33 U32 U31 U30 Y4 V37 V36 V35 V34 V33 V32 V31 V30
Note: UxY x = pixel number and y = bit number Table 2-5: Sampling raster of DIGIT 2000 4:1:1 format Luma Chroma line 1 line 2 line 3 line 4 line 5 Y1 V2L UXM UXL V1M V2L Y2 V2M V3L UXM UXL V2M Y3 U1L V3M V4L UXM U1L Y4 U1M U2L V4M V5L U1M Y5 V6L U2M U3L V5M V6L
Note: Uxy x = pixel number and y = LSB/MSB nibble pixel no. X indicates an invalid sample at the beginning of the line 2.12.2. DIGIT 2000 4:2:2 Output Format In the DIGIT 2000 4:2:2 output format, the U and V samples are non-orthogonal (calculated from adjacent pixel, e.g. line n starts with a V pixel and line (n+1) starts with a U pixel (see Table 2-6).
Note: UxY x = pixel number and y = bit number
14
Micronas
ADVANCE INFORMATION
CIP 3250A
2.12.4. Orthogonal 4:1:1 Output Format
<23>AVHSTRT <24>AVHLEN
The orthogonal 4:1:1 output format is compatible to the industry standard. The U and V samples are skew corrected and interpolated to an orthogonal sampling raster (see Table 2-8).
AVO
start of field <25>AVVSTRT <26>AVVSTOP
Fig. 2-11: Programmable AVO signal Table 2-8: 4:1:1 orthogonal output format Luma Chroma C3 , C7 C2 , C6 C1 , C5 C0 , C4 Y1 U17 U16 V17 V16 Y2 U15 U14 V15 V14 Y3 U13 U12 V13 V12 Y4 U11 U10 V11 V10 Select the desired mode via I2C register <17>AVINT. If the AVO signal is derived from the AVI signal, the I2C registers <22>AVDLY can be used to compensate internal processing delays of the CIP 3250A. I2C register <22>AVPR can be used to precede the AVO signal in relation to the RGB/YUV data output up to 3 clocks. 2.15. PRIO Interface - real-time bus arbitration for 8 sources in DIGIT 3000 picture bus. Up to eight digital YUV or RGB sources (main decoder, PIP, OSD, Text, etc.) may be selected in real-time by means of a 3 bit priority bus. Thus, a pixelwise bus arbitration and source switching is possible. It is essential that all YUV-sources are synchronous and orthogonal. In general, each source (= master) has its own YUV bus request. This bus request may either be software or hardware controlled, i.e. a fast blank signal. Data collision is avoided by a bus arbiter that provides the individual bus acknowledge, in accordance to a user defined priority. Each master sends a bus request with its individual priority ID onto the PRIO-bus and immediately reads back the bus status. Only in case of positive arbitration (send-PRIO-ID = read-PRIO-ID), the RGB/YUV outputs become active and the data is send. PRIO requests must be enabled by I2C register <14>PRIOEN. The requests asserted by the CIP 3250A may be generated by two different sources, which are selectable by I2C register <09>PRIOSRC. With the first source, the CIP 3250A asserts requests only when the AVO signal is active, else RGB/YUV outputs are tristated. With the second source, the CIP 3250A asserts continuous requests where the YUV data are forced to "clamp/bias level data" (see section 2.13.) during the time that the AVO signal is inactive. If only one source is connected to the YUV bus, the outputs GL, RC, and B may drive the bus during a full clock cycle. This can be selected by I2C register <06>HALFOUT. If more than one source is connected to the YUV bus, the output drivers must be switched to driving only during the first half of clock cycle to avoid bus collision. In the last case, the layout of the PCB must consider that 15
Note: UxY x = pixel number and y = bit number
2.12.5. YUV Output Levels The Y output black level of the CIP 3250A can be converted from ITU-R 601 Standard (digital 16) to DIGIT 2000 Standard (digital 32) via I2C register <16>ADD16Q.
2.13. I/O Code Levels - ITU-R/DIGIT 3000 code levels: Y or RGB = 16 ... 240, clamp level = 16 UV = 112, bias level = 0 - or DIGIT 2000 code levels: Y = 32 ... 127, clamp level = 32 UV = 127, bias level = 0 2.14. AVO Active Video Output In a DIGIT 3000 system environment, the AVO signal is equivalent to the delayed AVI signal. It signalizes valid video data and chroma multiplex at the output of the CIP 3250A. Furthermore, the AVO signal can be used to control the write enable of a frame memory. The polarity of the AVO signal is programmable via I2C register <10>AVOINV. In a DIGIT 2000 system environment, the AVO signal can be programmed via I2C registers <23> to <26> to define a window of valid video data at the output of the CIP 3250A (see Fig. 2-11).
Micronas
CIP 3250A
data on YUV bus must be kept dynamically for a half clock cycle. Thus, capactitvie coupling from other signals to YUV bus must be avoided or reduced to a tolerable minimum. This procedure has many features which have an impact on the appearance of a TV picture: - real-time bus arbitration (PIP, OSD, ...) - priorities are software configurable - different coefficients for different sources 2.16. I2C Serial Bus Control Communication between the CIP 3250A and the external controller is done via I2C bus. The CIP 3250A has an I2C bus slave interface and uses I2C clock synchronization to slow down the interface if required. The I2C bus interface uses one level of subaddressing: one I2C bus address is used to address the IC and a subaddress selects one of the internal registers. The registers of the CIP 3250A have 8 bit data size. All registers are writeable (except subaddress hex27) and readable as well. Register bits of parameter addresses, which are marked with an X in the description field of the register table, must be set to zero. All registers are initialized to zero with reset. Figure 2-12 shows I2C bus protocols for read and write operations of the interface.
ADVANCE INFORMATION
S
1101110
W
Ack
0111 1100
Ack
1 byte Data
Ack
P
I2C write access
1 byte Data Nak P
S
1101110
W
Ack
0111 1100
Ack
S
1101110
R
Ack
I2C read access
SDA S SCL
1 0
P
W R Ack Nak S P
= = = = = =
0 1 0 1 Start Stop
Device Address = 110 1110[R/W]
Fig. 2-12: I2C Bus Protocol 16 Micronas
ADVANCE INFORMATION
CIP 3250A
Table 2-9: The I2C-bus addresses of the CIP 3250A - Device Address: 6E Hex (7 bit, R/W bit omitted, see Sec. 2.16.)
Bit No. Sub. Addr.
MSB 7 NOISSU
6
5
4
3 SATU
2
1
LSB 0
00
noise shaping of U -
saturation multiplier of U 32
NOISSV 01
noise shaping of V -
SATV
saturation multiplier of V 32
NOISSY 02
noise shaping of Y -
SATY
contrast multiplier of Y 32
BRY 03 CBSON 04
CTBRST block enable 1 brightness correction of Y 0
SMODE
saturation mode 0
CLSEL
clamping offset for Y 0
MAON
matrix block enable 1
SKWON
skew correction enable -
SKWCBS
skew filter mode -
ATST
testbits 0
LPFLUM 05 D2KIN
input amplifier of digital YUVin - luma low pass filter selection -
PASSYUV 06
soft mixer control 0
DELAYU
UV format of YUVin -
HALFOUT
output drive duration 0
CYLUM1
Y low pass filter offset correction 1 -
CYLUM2
Y low pass filter offset correction 2 -
CYCHR1
UV low pass filter offset correction 1 -
CYCHR2
UV low pass filter offset correction 2 -
07
FSYINV
polarity FSY -
LPFCHR
chroma low pass filter selection -
TESTLUY 08
test y channel 0
TESTCHU
test u channel 0
TESTCHV
test v channel 0
TESTFBL
test fbl channel 0
ICLPTST
test fbl clamp and IDDQ test 0
TESTCLP 09
test clamping 0
YUV
analog input select 0
SE_4_8Q
analog gain control 0
SELAMP
analog gain control 0
CLMPOFS
RGB clamping offset 0
AVODIS
disable ACVOUT -
PRIOSRC
Source for PRIO request 1
10
AVOINV
polarity AVO -
AVIINV
polarity AVI -
SECAM
delay for SECAM -
DL1ON
delay of YUVin -
UVBINCON
UV sign of YUVin -
UVFRM3
UV format of YUVin -
UVFRM1
UV format of YUVin -
YLEVEL
convert Y format -
FBLTEN 11
Fast Blank test 0
PASSRGB
soft mixer control 1
FBLOFF
Fast Blank offset correction 31
MIXAMP 12
amplification of Fast Blank amplitude 1
SELDLY
adjust delay of RGB/YUV-path 1
SELLIN
select soft mixer 0
CTRLDLY
delay control 0
OVR 13
override value for PRIO-interface -
PRIOEN 14
access to Picture Bus 1
PRIOID
set PRIO priority -
PUDIS
disable pull up of YUV/RBG output -
LOAD
adjust load strength of Picture Bus and PRIO bus -
UVSW 15
UV multiplex of YUV output -
DTI
UV output format -
IND
UV output format -
BINO
UV sign of output format -
YUVO
select RGB/YUV output format -
MOD411ON
UV output format -
CDEL
select UV output sample from 4:4:4 -
FBLCLP 16
static Fast Blank 0
FBLDEL
delay Fast Blank vs. analog RGB/YUV 0
YDEL
adjust Y output delay -
ADD16Q
black level of Y output -
DL422Y
additional Y output delay -
DL422C
additional UV output delay -
SYNCIN 17
UV sync control of YUVin -
SYNCOUT
UV sync control of YUV output -
NEGCLK
select active clockedge -
AVINT
AVO control -
PXSKWON
pixel skew corretion -
P72BEN
72 bit data bypass -
D2KSYNC
sync input at FSY-pin -
SYNCSIM
H-sync, V-sync input -
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CIP 3250A
Table 2-9: The I2C-bus addresses of the CIP 3250A, continued
Bit No. Sub. Addr.
ADVANCE INFORMATION
MSB 7
6
5
4 CLPSTRT
3
2
1
LSB 0
18
start of clamping window -
CLPSTOP 19
stop of clamping window -
SKEWLAT 20
latch time for sub-pixel skew value -
DL2 21
fifo delay adjust for RGB/YUV-path -
AVPR 22
delay between YUV output and AVO -
AVDLY
delay AVI to AVO to compensate CIP 3250 A processing delay -
AVHSTRT 23
horizontal start of AVO -
AVHLEN 24
horizontal length of AVO -
AVVSTRT 25
vertical start of AVO -
AVVSTOP 26
vertical stop of AVO -
FBLSTAT 27
- static FBL read -
FBLRISE
dynamic FBL read rising edge -
FBLFALL
dynamic FBL read falling edge -
FBLHIGH
dynamic FBL read high level -
18
Micronas
ADVANCE INFORMATION
CIP 3250A
Table 2-10: I2C-Bus operation - Device Address: 6E Hex (7 bit, R/W bit omitted, see Sec. 2.16.)
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
I2C registers for ADC and CLAMPING
09 YUV 6 0 analog input select 0 = RGB 1 = YUV start of clamping window (0...255)*2 clocks after H-sync (see Fig. 2-13) stop of clamping window (0...255)*2 clocks after H-sync (see Fig. 2-13) [note: [ 09 CLMPOFS 2 0 - maximum window size: 64 sample clocks] - minimum window size: 6 sample clocks]
18 19
CLPSTRT CLPSTOP
7-0 7-0
30 50
RGB clamping offset 0 = +16 (digital) 1 = +8 (digital) Y (luma) black level adjust at RGB-path 0 =convert Y (luma) black level from digital 16 to 32 (DIGIT 2000) 1 =Y (luma) black level at digital 16 (ITU-R 601 Standard) analog gain control 0 = 1/8 1 = 1/16 2 = 1/32 analog gain control 0 = 1/8 1 = 1/4
04
CLSEL
5
0
09
SELAMP
4-3
0
09
SE_4_8Q
5
0
I2C registers for MATRIX
04 MAON 4 1 matrix block 0 = matrix off (YUV input or RGB bypass) 1 = matrix on (RGB to Y(R-Y)(B-Y))
I2C registers for CONTRAST / BRIGHTNESS / SATURATION
04 CBSON 7 1 CTBRST block 0 = bypassed ( for dig. RGB bypass only (<04>MAON=0)) 1 = on brightness correction of Y (luma) in CTBRST block Y + (-128...127) contrast multiplier of Y (luma) in CTBRST block Y * (0...63)/32 noise shaping of Y (luma) in CTBRST block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion saturation multiplier of U (chroma) in CTBRST block U * (0...63)/32 noise shaping of U (chroma) in CTBRST block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion saturation multiplier of V (chroma) in CTBRST block V * (0...63)/32 noise shaping of V (chroma) in CTBRST block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion saturation mode of UV (chroma) in CTBRST block 0 = internal PAL (U * 0.5, V * 0.875) 1 = external (U * 1, V * 1)
03 02 02
BRY SATY NOISSY
7-0 5-0 7,6
0 32 0
00 00
SATU NOISSU
5-0 7,6
32 0
01 01
SATV NOISSV
5-0 7,6
32 0
04
SMODE
6
0
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CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
ADVANCE INFORMATION
I2C registers for OUTPUT FORMATTER
15 YUVO 3 1 select video component output format 0 = output formater off (i.e. RGB or YUV output with format 4:4:4) 1 = output formater on (i.e. YUV output with format 4:2:2 or 4:1:1) black level of Y (luma) output 0 = Convert Y black level at output from ITU-R 601 Standard to DIGIT 2000 Standard (digital 32) 1 = Y black level at output unchanged UV (chroma) output format 0 = 4:2:2 1 = 4:1:1 UV (chroma) sign of output format 0 = two's complement 1 = binary offset select UV (chroma) output sample from 4:4:4 format (0...3) UV (chroma) output format 0 = DIGIT 2000 1 = DIGIT 3000 / orthogonal UV (chroma) multiplex of output format 0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1 1 = DIGIT 2000 4:2:2 UV (chroma) output format 0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1 1 = DIGIT 2000 4:2:2 adjust Y (luma) output delay in reference to UV (chroma) output (0...3) clocks additional Y (luma) output delay (0...1) clocks (DIGIT 3000 4:2:2 / MAC) additional UV (chroma) output delay (0...1) clocks (DIGIT 3000 4:2:2 / MAC)
16
ADD16Q
2
1
15
MOD411ON
2
0
15
BINO
4
0
15 15
CDEL IND
1-0 5
0 1
15
UVSW
7
0
15
DTI
6
0
16 16 16
YDEL DL422Y DL422C
4-3 1 0
0 0 0
I2C registers for SKEW FILTER
04 SKWON 3 0 skew correction 0 = off 1 = on skew filter active for 0 = DIGIT 2000 pixel orthogonalization 1 = DIGIT 3000 pixel orthogonalization latch time for sub-pixel skew value (from FSY-/SKEW-protocol) to adjust the processing delays of video data to H-sync (see Fig. 2-13) (0...255)*2 clocks
04
SKWCBS
2
1
20
SKEWLAT
7-0
0
I2C registers for PRIO
14 PRIOEN 7 1 access to Picture Bus (GL, RC, B output) 0 = disabled (Picture Bus is tristate) 1 = enabled (access to Picture Bus possible) Source for PRIO request 0 = PRIO request only if AVO is active 1 = PRIO request always independent of AVO set PRIO priority (0...7) override value for PRIO-interface
09
PRIOSRC
0
1
14 13
PRIOID OVR
6-4 7-0
7 0
20
Micronas
ADVANCE INFORMATION
CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
I2C registers for SOFT MIX
11 PASSRGB 6 1 soft mixer control 0 = analog RGB/YUV-path passed only 1 = mixing controlled by Fast Blank (if <11>PASSYUV=0) soft mixer control 0 = mixing controlled by Fast Blank (if <11>PASSRGB=1) 1 = digital YUVin-path passed only (if <11>PASSRGB=1) enable static operation of Fast Blank 0 = Fast Blank derived from analog FBL input 1 = static Fast Blank (FBL = 31) Fast Blank offset correction FBL - (0...63) delay Fast Blank vs. analog RGB/YUV input 3 = -1 clocks 0 = 0 clocks 1 = 1 clocks 2 = 2 clocks amplification of Fast Blank amplitude FBL * (-4...4) [note: value 0 invalid, use <06>PASSYUV or <11>PASSRGB for static operation of soft mixer instead] delay control of analog RGB/YUV data in relation to digital YUV data 0 = statically (by value of <12>SELDLY) 1 = dynamically (by nonlinear mixer) delay value for analog RGB/YUV data in relation to digital YUV data (<12>CTRLDLY=0) 0 = -1 pixel 1 = 0 pixel 2 = +1 pixel select soft mixer type 0 = linear mixer 1 = nonlinear mixer fast blank input : 1 = high, 0 = low (see Fig. 2-5) set with an rising edge at fast blank input reset at read of <27> set with an falling edge at fast blank input reset at read of <27> dynamic FBL read high level
06
PASSYUV
7
0
16
FBLCLP
7
0
11 16
FBLOFF FBLDEL
5-0 6-5
32 0
12
MIXAMP
7-4
1
12
CTRLDLY
0
0
12
SELDLY
3-2
1
12
SELLIN
1
0
27 27 27 27
FBLSTAT FBLRISE FBLFALL FBLHIGH
3 2 1 0
Micronas
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CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
ADVANCE INFORMATION
I2C registers for ACTIVE VIDEO SIGNAL
10 AVIINV 6 0 polarity of AVI signal 0 = active video during AVI is high (if <17>AVINT = 0) 1 = active video during AVI is low (if <17>AVINT = 0) polarity of AVO signal 0 = AVO is high active 1 = AVO is low active delay from AVI (active video in) to AVO to compensate CIP 3250A processing delays (if <17>AVINT = 0) (0...63) + 14 - <22>AVPR clocks (if <10>DL1ON=0) (0...63) + 92 - <22>AVPR clocks (if <10>DL1ON=1) delay between AVO and YUV output AVO preceedes YUV output by AVPR (0...3) clocks AVO (active video out) 0 = derived from AVI (active video in) 1 = generated internally (see <23>AVHSTRT, <24>AVHLEN, <25>AVVSTRT, <26>AVVSTOP) horizontal start of AVO after H-sync if <17>AVINT = 1 (0...255)*8 + 11 - <22>AVPR clocks (see Fig. 2-13) horizontal length of AVO if <17>AVINT = 1 (0...255)*8 clocks vertical start of AVO if <17>AVINT = 1 (0...255)*4 lines vertical stop of AVO if <17>AVINT = 1 (0...255)*4 lines
10
AVOINV
7
0
22
AVDLY
5-0
32
22 17
AVPR AVINT
7-6 4
0 0
23 24 25 26
AVHSTRT AVHLEN AVVSTRT AVVSTOP
7-0 7-0 7-0 7-0
0 0 0 0
22
Micronas
ADVANCE INFORMATION
CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
I2C registers for ADJUSTABLE LOWPASS FILTER
05 LPFLUM 7-0 0 Y luma low pass filter selection 0 = bypass 128 = Y1 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 1) 192 = Y2 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 1) 224 = Y3 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 2) 240 = Y4 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 2) 241 = Y5 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 2) 249 = Y6 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 2) 255 = Y7 (<06>CYLUM1=0, <06>CYLUM2=0, increment <16>YDEL by 2) [note: <16>YDEL has to be incremented to match group delays] Y (luma) low pass filter offset correction 1 0 = off 1 = on Y (luma) low pass filter offset correction 2 0 = off 1 = on UV (chroma) low pass filter selection 0 = bypass 96 = UV1 (<06>CYCHR1=0, <06>CYCHR2=0) 97 = UV2 (<06>CYCHR1=0, <06>CYCHR2=0) 113 = UV3 (<06>CYCHR1=0, <06>CYCHR2=0) 125 = UV4 (<06>CYCHR1=0, <06>CYCHR2=0) 127 = UV5 (<06>CYCHR1=0, <06>CYCHR2=0) UV (chroma) low pass filter offset correction 1 0 = off 1 = on UV (chroma) low pass filter offset correction 2 0 = off 1 = on
06
CYLUM1
3
0
06
CYLUM2
2
0
07
LPFCHR
6-0
0
06
CYCHR1
1
0
06
CYCHR2
0
0
I2C registers for DELAY2 (DL2)
17 PXSKWON 3 1 pixel skew correction (see section 2.5.) 0 = off [note: delay adapted every field, see Fig. 2-15] 1 = on [note: delay adapted every line, see Fig. 2-14] delay adjust for RGB to YUV-path (see section 2.5.) (0...255)*2 + 2 clocks delay to write DL2-FIFO if <17>PXSKWON = 1 (48...212) clocks delay to read DL2-FIFO if <17>PXSKWON = 0
21
DL2
7-0
69
I2C registers for DELAY1 (DL1)
10 SECAM 5 0 delay of digital YUVin (SECAM mode) 0 = see <10>DL1ON 1 = UV: 2 clocks, Y: 76 clocks (set <10>DL1ON = 0) delay of digital YUVin (set <10>SECAM = 0) 0 = 2 clocks 1 = 80 clocks
10
DL1ON
4
1
Micronas
23
CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
ADVANCE INFORMATION
I2C registers for INPUT FORMATTER
06 D2KIN 6 0 input current source of digital YUVin 0 = DIGIT 3000 (current source off) 1 = DIGIT 2000 (current source active, see Fig. 3-8) DIGIT 2000 Y (luma) format conversion to ITU-R 601 Standard 0 = off 1 = on UV (chroma) sign of YUVin 0 = two's complement 1 = binary offset UV (chroma) format of YUVin 0 = DIGIT 2000 4:2:2 / DIGIT 2000 4:1:1 1 = DIGIT 3000 4:2:2 / MAC UV (chroma) format of YUVin 0 = DIGIT 2000 4:1:1 / DIGIT 2000 4:2:2 / MAC 1 = DIGIT 3000 4:2:2 UV (chroma) format of YUVin 0 = DIGIT 2000 4:2:2 / DIGIT 3000 4:2:2 / MAC 1 = DIGIT 2000 4:1:1
10
YLEVEL
0
0
10
UVBINCON
3
0
06
DELAYU
5
1
10
UVFRM3
2
1
10
UVFRM1
1
0
24
Micronas
ADVANCE INFORMATION
CIP 3250A
SubAddress (decimal)
Label
Bit No. (LSB = 0)
Typical Operation Value
Function
I2C registers for OUTPUT CONTROL
06 HALFOUT 4 0 Output drive duration 0 = output active a full clock cycle (only one IC on Picture Bus) 1 = output active half a clock cycle (more than one IC on Picture Bus) disable AVO pin 0 = AVO pin is active 1 = AVO pin is tristate disable pull-up transistors at GL, RC, and B output pins 0 = pull-up on (output is in push-pull mode) 1 = pull-up off (output is in open drain mode) adjust load of AVO, GL, RC, B and PRIO (select lowest possible load to keep electromagnetic radiation and noise at A/D-Converter low) LOAD | GL, RC, B, and AVO outputs | @PVDD = 5 Volt | @PVDD = 3.3 Volt 000 | CLoad v100 pF ILoadv3.4mA| CLoadv50 pF ILoadv3.0mA 001 | CLoad v55 pF ILoadv2.3mA| CLoadv28 pF ILoadv1.5mA 010 | CLoad v37 pF ILoadv1.5mA| CLoadv20 pF ILoadv1.0mA 011 | CLoad v28 pF ILoadv1.2mA| CLoadv16 pF ILoadv0.8mA 100 | CLoad v23 pF ILoadv0.9mA| CLoadv12 pF ILoadv0.6mA 101 | CLoad v18 pF ILoadv0.7mA| CLoadv10 pF ILoadv0.5mA 110 | CLoad v14 pF ILoadv0.6mA| CLoadv8 pF ILoadv0.4mA 111 | pins tristate | pins tristate LOAD | PRIO bus 000 | ISINKv12mA 001 | ISINKv12mA 010 | ISINKv9mA 011 | ISINKv9mA 100 | ISINKv6mA 101 | ISINKv6mA 110 | ISINKv3mA 111 | ISINKv3mA NOTE: Total CLOAD at pins GL, RC, B, AVO, and PRIO must not exceed 2 nF. CLoad = max. load capacitance for AVO CLoad = max. load capacitance for GL, RC, and B at push-pull mode 12C:<14> PUDIS = 0 ILoad = max. sink current for GL, RC, and B at open drain mode 12C:<14> PUDIS = 1
09
AVODIS
1
0
14
PUDIS
3
0
14
LOAD
2-0
0
Micronas
25
CIP 3250A
Table 2-10: I2C-Bus operation, continued
SubAddress (decimal) Label Bit No. (LSB = 0) Typical Operation Value Function
ADVANCE INFORMATION
I2C registers for SYNCHRONIZATION
17 NEGCLK 5 0 select active clockedge for inputs and outputs 0 = all inputs and outputs relate to rising edge at CLK input (DIGIT 3000) 1 = all inputs and outputs relate to falling edge at CLK input (DIGIT 2000) HSYNC, VSYNC input 0 = FSY-/SKEW-protocol (see <17>D2KSYNC) 1 = HSYNC at FSY-pin, VSYNC at AVI-pin (see also <07>FSYINV, <10>AVIINV) sync protocol at FSY-pin 0 = DIGIT 3000 (FSY protocol) AVI-Pin and FSY-Pin with trigger level at 1.2 Volt 1 = DIGIT 2000 (SKEW protocol) AVI-Pin and FSY-Pin with Schmitt-Trigger characteristic polarity of AVI signal 0 = vertical sync at falling edge of AVI (if <17>SYNCSIM = 1 1 = vertical sync at rising edge of AVI (if <17>SYNCSIM = 1) polarity of FSY signal (see also <17>SYNCSIM) 0 = horizontal sync at falling edge of FSY (if <17>SYNCSIM = 1) select always <07>FSYINV = 0 if <17>SYNCSIM = 0 1 = horizontal sync at rising edge of FSY (if <17>SYNCSIM = 1) UV (chroma) multiplex control of digital YUVin 0 = by AVI (active video in) 1 = by 72 bit data (DIGIT 2000) UV (chroma) multiplex control of YUV output 0 = by AVO (active video out) 1 = by 72 bit data (DIGIT 2000) 72 bit data and clock bypass enable 0 = off 1 = on (DIGIT 2000)
17
SYNCSIM
0
1
17
D2KSYNC
1
0
10
AVIINV
6
0
07
FSYINV
7
0
17
SYNCIN
7
0
17
SYNCOUT
6
0
17
P72BEN
2
0
H-sync
(see Fig. 2-13) <21>DL2*2 + 2 clocks
DL2-WR D2KSYNC
<17>
SYNCSIM
<17>
delay
(clocks)
48..212 clocks
X 1 0
1 0 0
4 15 23
AVI DL2-RD
4 clocks <10>DL1ON = 0 82 clocks <10>DL1ON = 1 24 clocks 102 clocks
H-sync delay in respect to falling edge of FSY/ SKEW (H-sync is derived from FSY/SKEW)
Fig. 2-14: DL2-setup
(<17>PXSKWON = 1)
FSY H-sync
(delay/clocks see table)
DL2-WR DL2-RD
program delay see <21>DL2
AVO
<23>AVHSTRT + 11 - <22>AVPR clocks
DL2-reset Fig. 2-13: H-sync reference generation Fig. 2-15: DL2-reset during line 7
(<17>PXSKWON = 0)
26
Micronas
ADVANCE INFORMATION
CIP 3250A
3. Specifications 3.1. Outline Dimensions
2.4 1+0.2 x 45 9 10 2 9 25 +0.25 0.711 24.2 0.1 2 1 61 60 0.457 2.4 1.27 0.1 15 9 24.2 0.1 0.1 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45
26 27 25 +0.25 43
44 1.9 1.5 4.05 4.75 0.15
Fig. 3-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm
3.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No.
PLCC 68-pin
0.2
DVSS = if not used, connect to DVSS AVSS = connect to AVSS
Connection
(if not used)
Pin Name
Type
Short Description
1 2 3 4 5 6 7 8 9 10 11 12
DVSS LV LV LV LV LV LV LV LV LV LV LV
STANDBY B7 B6 B5 B4 B3 B2 B1 B0 GL7 GL6 GL5
IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
Standby connect to ground Blue Output (MSB) Blue Output Blue Output Blue Output Blue Output Blue Output Blue Output Blue Output (LSB) Green/Luma Output (MSB) Green/Luma Output Green/Luma Output
Micronas
16 x 1.27 0.1 = 20.32 0.1
27
CIP 3250A
ADVANCE INFORMATION
Pin No.
PLCC 68-pin
Connection
(if not used)
Pin Name
Type
Short Description
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
LV LV LV LV LV X X LV LV LV LV LV LV LV LV LV Supply +5 V Supply +5 V X X LV LV LV DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
GL4 GL3 GL2 GL1 GL0 PVSS PVDD RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AVO AVI FSY SCL SDA PRIO2 PRIO1 PRIO0 C0 C1 C2 C3 C4 C5 C6 C7
OUT OUT OUT OUT OUT SUPPLY SUPPLY OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN IN IN IN IN IN IN IN
Green/Luma Output Green/Luma Output Green/Luma Output Green/Luma Output Green/Luma Output (LSB) Pad Ground Pad Supply Voltage +5 V/+3.3 V Red/Chroma Output (MSB) Red/Chroma Output Red/Chroma Output Red/Chroma Output Red/Chroma Output Red/Chroma Output Red/Chroma Output Red/Chroma Output (LSB) Active Video Output Active Video Input Front Sync Input I2C Clock Input/Output I2C Data Input/Output Picture Bus Priority (MSB) Picture Bus Priority Picture Bus Priority (LSB) Chroma Input (LSB) Chroma Input Chroma Input Chroma Input Chroma Input Chroma Input Chroma Input Chroma Input (MSB)
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ADVANCE INFORMATION
CIP 3250A
Pin No.
PLCC 68-pin
Connection
(if not used)
Pin Name
Type
Short Description
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS X X X X DVSS X X X X AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS
L0 L1 L2 L3 L4 L5 L6 L7 DVSS DVDD CLK RESQ TMODE AVDD AVSS ADREF SUBSTRATE FB GNDFB BU GNDBU GY GNDGY RV GNDRV
IN IN IN IN IN IN IN IN SUPPLY SUPPLY IN IN IN SUPPLY SUPPLY Reference - IN IN IN IN IN IN IN IN
Luma Input (LSB) Luma Input Luma Input Luma Input Luma Input Luma Input Luma Input Luma Input (MSB) Digital Ground Digital Supply Voltage +5 V Main Clock Input Reset Input Test Mode connect to ground Analog Supply Voltage +5 V Analog Ground External Capacitor Substrate connect to ground Fast Blank Input Ground Fast Blank Blue/U Input Ground Blue/U Green/Luma Input Ground Green/Luma Red/V Input Ground Red/V
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CIP 3250A
3.3. Pin Descriptions Pin 1 - STANDBY Input (Fig. 3-2) Via this input pin, the standby mode of the CIP 3250A is enabled. A high level voltage switches all outputs to tristate mode, and power consumption is significantly reduced. When the IC is returned to active mode, a reset is generated internally. Connect to VSS if not used. Pins 2 to 9 - B7 to B0 Blue Output (Fig.3-3 ) In a stand alone application, where the CIP 3250A serves as an A/D-converter, these are the outputs for the digital Blue signal (pure binary) or the digital U signal (2's complement). Leave vacant if not used. Pins 10 to 17 - GL7 to GL0 Green/Luma Output (Fig.3-3 ) At these outputs, the digital luminance signal is received in pure binary coded format for DIGIT 2000 and DIGIT 3000 applications. In a stand alone application, where the CIP 3250A serves as an A/D-converter, these are the outputs for the digital Green signal (pure binary) or the digital luma signal (pure binary). Leave vacant if not used. Pin 18 - PVSS Output Pin Ground This is the common ground connection of all output stages and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 19 - PVDD Output Pin Supply +5 V / +3.3 V This pin supplies all output stages and must be connected to a positive supply voltage. Note: The layout of the PCB must take into consideration the need for a low-noise supply. A bypass capacitor has to be connected between ground and PVDD (see section 4. Application Circuit. Pins 20 to 27 - RC7 to RC0 Red/Chroma Output (Fig. 3-3 ) These are the outputs for the digital chroma signal in the DIGIT 3000 system, where U and V are multiplexed bytewise. In a DIGIT 2000 system, RC3 to RC0 and RC7 to RC4 carry the halfbyte (nibble) multiplex format. In a stand alone application, where the CIP 3250A serves as an AD-converter, these are the outputs for the digital Red signal (pure binary) or the digital chroma V signal (2's complement). Leave vacant if not used. Pin 28 - AVO Active Video Output (Fig. 3-4) This output provides the Active Video signal, which carries information about the chroma multiplex in a DIGIT 3000 application and indicates valid video data at the Luma/Chroma outputs. This signal is programmable via I2C registers. Leave vacant if not used. 30
ADVANCE INFORMATION
Pin 29 - AVI Active Video Input (Fig. 3-5) In a DIGIT 2000 application, this input can be connected to ground. In a DIGIT 3000 application, this input expects the DIGIT 3000 AVI signal. In a stand alone application, this input expects the VSYNC vertical sync pulse. Connect to ground if not used. Pin 30 - FSY Front Sync Input (Fig. 3-5) In a DIGIT 2000 application, this input pin expects the DIGIT 2000 SKEW protocol. In a DIGIT 3000 application, this input expects the DIGIT 3000 FSY protocol. In a stand alone application, this input expects the HSYNC horizontal sync pulse. Connect to ground if not used. Pins 31 to 32 - SDA and SCL of I2C-Bus (Fig. 3-6) These pins connect to the I2C bus, which takes over the control of the CIP 3250A via the internal registers. The SDA pin is the data input/output, and the SCL pin is the clock input/output of I2C bus control interface. All registers are writeable (except address hex27) and readable. Pins 33 to 35 - PRIO0 to PRIO2 Priority Bus (Fig. 3-7) These pins connect to the Priority Bus of a DIGIT 3000 application. The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the backend processor. Switching for different sources is prioritized and can be on a per pixel basis. In all other applications, they must not be connected. Pins 36 to 43 - C0 to C7 Chroma Input (Fig. 3-8) These are the inputs for the digital chroma signal which can be received in binary offset or 2's complement coded format. In a DIGIT 2000 (4:1:1) system, C3 to C0 take the halfbyte (nibble) multiplex format. C7 to C4 have to be connected to ground. Within the DIGIT 3000 (4:2:2) system, U and V are multiplexed bytewise. Connect to ground if not used. Pins 44 to 51 - L0 to L7 Luma Input (Fig. 3-8) These are the inputs for the digital luma signal which must be in pure binary coded format. Connect to ground if not used. Pin 52 - DVSS Digital Ground This is the common ground connection of all digital stages and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 53 - DVDD Digital Supply +5 V This pin supplies all digital stages and must be connected to a positive supply voltage. Note: The layout of the PCB must take into consideration the need for a low-noise supply. A bypass capacitor has to be connected between ground and DVDD (see section 4. Application Circuit. Pin 54 - CLK Main Clock Input (Fig. 3-9) This is the input for the clock signal. The frequency can vary in the range from 13.5 MHz to 20.25 MHz. Micronas
ADVANCE INFORMATION
CIP 3250A
Pin 63 - BU Analog Blue/U Chroma Input (Fig. 3-13) This input pin takes the AC-coupled analog component signal Blue or U Chroma. The amplitude is 1.0 V maximum at 75 Ohms and a coupling capacitor of 220 nF. Internally, the DC-offset of the input signal is adjusted via the programmable internal clamping circuit. Connect to ground if not used. Pin 64 - GNDBU Analog Ground This is the ground pin for the A/D converter of the Blue or U Chroma signal and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 65 - GY Analog Green/Luma Input (Fig. 3-13) This input pin takes the AC-coupled analog component signal Green or Luma. The amplitude is 1.0 V maximum at 75 Ohms and a coupling capacitor of 220 nF. Internally, the DC-offset of the input signal is adjusted via the programmable internal clamping circuit. Connect to ground if not used. Pin 66 - GNDGY Analog Ground This is the ground pin for the A/D converter of the Green or Luma signal and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 67 - RV Analog Red/V Chroma Input (Fig. 3-13) This input pin takes the AC-coupled analog component signal Red or V Chroma. The amplitude is 1.0 V maximum at 75 Ohms and a coupling capacitor of 220 nF. Internally, the DC-offset of the input signal is adjusted via the programmable internal clamping circuit. Connect to ground if not used. Pin 68 - GNDRV Analog Ground This is the ground pin for the A/D converter of the Red or V Chroma signal and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.
Pin 55 - RESQ Input (Fig. 3-10) A low signal at this input pin generates a reset. The lowto-high transition of this signal should occur when the supply voltage is stable (power-on reset). Pin 56 - TMODE Input (Fig. 3-2) This pin is for test purposes only and must be connected to ground in normal operation. Pin 57 - AVDD Analog Supply +5 V This is the supply voltage pin for the A/D converters and must be connected to a positive supply voltage. Note: The layout of the PCB must take into consideration the need for a low-noise supply. A bypass capacitor has to be connected between ground and AVDD. Pin 58 - AVSS Analog Ground This is the ground pin for the A/D converters and must be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 59 - ADREF Connect External Capacitor (Fig. 3-11) This pin should be connected to ground over a 10 F and a 100 nF capacitor in parallel. Pin 60 - SUBSTRATE This is connected to the platform which carries the "die" and must be connected to the ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground. Pin 61 - FB Analog Fast Blank Input (Fig. 3-12) This input takes the DC-coupled analog Fast Blank signal. The amplitude is 1.0 V maximum at 75 Ohms. Connect to ground if not used. Pin 62 - GNDFB Analog Ground This is the ground pin for the AD converter of the Fast Blank signal and has to be connected to ground. Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.
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CIP 3250A
3.4. Pin Configuration
STANDBY B7 B6 B5 B4 B3 B2 B1 B0 GNDRV RV GNDGY GY GNDBU BU GNDFB FB
ADVANCE INFORMATION
GL7 GL6 GL5 GL4 GL3 GL2 GL1 GL0 PVSS PVDD RC7 RC6 RC5 RC4 RC3 RC2 RC1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60 59
SUBSTRATE ADREF AVSS AVDD TMODE RESQ CLK DVDD DVSS L7 L6 L5 L4 L3 L2 L1 L0
CIP 3250A
58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
RC0 AVO AVI FSY SCL SDA PRIO2 PRIO1 PRIO0 C0 C1 C2 C3 C4 C5 C6
C7
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ADVANCE INFORMATION
CIP 3250A
I2C:D2KSYNC
3.5. Pin Circuits The following figures schematically show the circuitry at the various pins. The integrated protection structures are not shown.
-
Comp.
+ 1.2 V
DVSS DVDD P Fig. 3-5: Input pins 29 and 30
N DVSS Fig. 3-2: Input pins 1 and 56 N DVSS Fig. 3-6: Input pins 31 and 32 PVDD P
I2C:PUDIS
DVDD N
PVSS Fig. 3-3: Output pins 2 to17 and 20 to 27 DVSS
N
Comp.
PVDD P
DVSS Fig. 3-7: Input/Output pins 33 to 35
N PVSS DVDD Fig. 3-4: Output pin 28
I2C:D2KIN
DVSS Fig. 3-8: Input pins 36 to 51
Micronas
+ - 1.2 V -
Comp.
+ 1.2 V
33
CIP 3250A
DVDD P P N N DVSS Fig. 3-9: Input pin 54
ADVANCE INFORMATION
Fig. 3-10: Input pin 55
AVDD
-
Opamp
+
P
extern C
92.5 V
AVSS Fig. 3-11: Input pin 59
GND
N P N Fig. 3-12: Input pin 61
AVDD
P
AVSS Fig. 3-13: Input pins 63, 65, and 67
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Micronas
ADVANCE INFORMATION
CIP 3250A
3.6. Electrical Characteristics 3.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI VO VO Parameter Ambient Temperature Storage Temperature Supply Voltage, all Supply Inputs Input Voltage, all Inputs Output Voltage, at Outputs PRIO, SDA, and SCL Output Voltage, at Outputs GL, RC, B, and AVO Min. 0 -40 -0.3 -0.3 -0.3 -0.3 Max. 65 125 6 VSUP+0.3 VSUP+0.3 VEXT+0.3 Unit C C V V V V
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
3.6.2. Recommended Operating Conditions Symbol TA VSUP VEXT fMCLK Parameter Ambient Operating Temperature Supply Voltages Analog and Digital Supply Voltages Output Circuits Clock Frequency DVDD, AVDD PVDD CLK Pin Name Min. 0 4.75 3.1 13.50 Typ. - 5.0 3.3 - Max. 65 5.25 5.25 20.25 Unit C V V MHz
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CIP 3250A
ADVANCE INFORMATION
3.6.3. Characteristics at TA = 0 to 65 C, VSUP = 4.75 to 5.25 V, VEXT = 3.1 to 5.25 V, f = 13.5 to 20.25 MHz for min./max.-values at TA = 20 C, VSUP = 5 V, VEXT = 3.3 V, f = 20.25 MHz for typical values
Symbol IDIG IANA IEXT PTOT ISDTBY Parameter Current Consumption Digital Pin Name DVDD Min. Typ. 80 Max. Unit mA Test Conditions I2C:<06>D2KIN = 1 70 pF load at all outputs
Current Consumption Analog Current Consumption PictureBus Total Power Dissipation
AVDD PVDD
70 40
mA mA 70 pF load at all outputs I2C:<06>D2KIN = 1 70 pF load at all outputs Standby pin = high
950
mW
Standby Current Consumption
DVDD, AVDD, PVDD L[7...0], C[7...0], RC[7...0], GL[7...0], B[7...0], PRIO[2:0], SDA, SCL, FSY, AVI, AVI CLK, RESQ, TMODE, AVO, STANDBY, RV, GY, BU, FB
tbd
mA
II
Leakage Current
1
A
Standby pin = high Uin = 0 V/5 V
CI
Input Capacitance
4
pF
at DC = 0 V, AC = 100 mV f = 10 MHz
3.6.3.1. Characteristics Standby Input
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name STANDBY Min. - 2.0 Typ. - - Max. 0.8 - Unit V V Test Conditions
3.6.3.2. Characteristics Test Input
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name TMODE Min. - 2.0 Typ. - - Max. 0.8 - Unit V V Test Conditions
3.6.3.3. Characteristics Reset Input
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name RESQ Min. - 3.3 Typ. - - Max. 1.3 - Unit V V Test Conditions
36
Micronas
ADVANCE INFORMATION
CIP 3250A
3.6.3.4. Characteristics Main Clock Input
Symbol VMIDC VMIAC tMIH tMIL tMIHL tMILH Parameter M Main Clock Input DC Voltage M Main Clock Input AC Voltage (p-p) M Clock Input High to Low Ratio M Clock Input High to Low Transition Time M Clock Input Low to High Transition Time Pin Name CLK Min. 1.5 0.8 Typ. - - Max. 3.5 2.5 Unit V V Test Conditions
2 3 -
1 1 -
3 2 0.15 fM 0.15 fM
-
-
tMILH
tMIHL
tMIH
tMIL
CLK Input
VMIAC VMIDC 0V
Fig. 3-14: Main clock input
3.6.3.5. Characteristics Active Video Output
Symbol VOL VOH tOD tOH Parameter Output Low Voltage Pin Name AVO Min. - Typ. - Max. 0.4 Unit V Test Conditions Load as described at I2C:<14>LOAD Load as described at I2C:<14>LOAD Load as described at I2C:<14>LOAD
Output High Voltage
2.4
-
-
V
Output Delay TIme after active Clock Transition Output Hold Time after active Clock Transition
-
-
35
ns
6
-
-
ns
CLK Input
see NOTE
tOD tOH VOH VOL
tOD tOH
AVO Output
Fig. 3-15: Active video output
Note: active clock edge depends on I2C:<17>NEGCLK
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CIP 3250A
3.6.3.6. Characteristics Active Video Input
Symbol VIL VIH tIS tIH Parameter Input Low Voltage Pin Name AVI Min. - - 3.3 1.5 7 Typ. - - - - - Max. 1.3 0.8 - - - Unit V V V V ns
ADVANCE INFORMATION
Test Conditions I2C:<17>D2KSYNC = 1 I2C:<17>D2KSYNC = 0 I2C:<17>D2KSYNC = 1 I2C:<17>D2KSYNC = 0
Input High Voltage
Input Setup Time before active Clock Transition Input Hold Time after active Clock Transition
5
-
-
ns
CLK Input
see NOTE
tIS
tIH
AVI Input
VIH VIL
Data valid
Fig. 3-16: Active video input
Note: active clock edge depends on I2C:<17>NEGCLK
3.6.3.7. Characteristics Fsync Input
Symbol VIL VIH tIS tIH Parameter Input Low Voltage Pin Name FSY Min. - - 3.3 1.5 7 Typ. - - - - - Max. 1.3 0.8 - - - Unit V V V V ns Test Conditions I2C: D2KSYNC = 1 I2C: D2KSYNC = 0 I2C: D2KSYNC = 1 I2C: D2KSYNC = 0
Input High Voltage
Input Setup TIme before active Clock Transition Input Hold Time after active active Clock Transition
5
-
-
ns
CLK Input
see NOTE
tIS
tIH
FSY Input
VIH VIL
Data valid
Fig. 3-17: Fsync input
Note: active clock edge depends on I2C:<17>NEGCLK
38
Micronas
ADVANCE INFORMATION
CIP 3250A
3.6.3.8. Characteristics I2C Bus Interface Input/Output
Symbol VIL VIH VOL tF fSCL tI2C3 tI2C4 tI2C1 tI2C2 tI2C5 tI2C6 tI2C7 Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name SDA, SCL Min. - 0.6*VDD - Typ. - - - Max. 0.3*VDD - 0.4 0.6 300 400 - - - - - Unit V V V V ns kHz ns ns ns ns ns II = 3 mA II = 6 mA CL = 400 pF Test Conditions
Signal Fall Time Clock Frequency I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C Start Condition Setup Time I2C Stop Condition Setup Time I2C-Data Setup Time Before Rising Edge of Clock SCL I2C-Data Hold Time after Falling Edge of Clock SCL I2C-Slew Times at I2C-Clock = 1 MHz SCL, SDA SCL
- 0 500 500 120 120 55
- - - - - - -
55
-
-
ns
50
-
-
V/s
3.6.3.9. Characteristics Luma/Chroma Input
Symbol VIL VIH IPUP VPUP tIS tIH Parameter Input Low Voltage Input High Voltage Pullup Current Pin Name L[7..0], C[7..0] C[7 0] Min. - 1.5 1.5 - 1.8 - 7 Typ. - - 2.1 - - - - Max. 0.8 - 3.0 1 3.2 - - Unit V V mA A V V ns
@ 1 Volt / I2C:<06>D2KIN = 1 @ 1 Volt / I2C:<06>D2KIN = 0
Test Conditions
Pullup Voltage
I2C:<06>D2KIN = 1 I2C:<06>D2KIN = 0
Input Setup Time before active Clock Transition Input Hold Time after actice Clock Transition
5
-
-
ns
CLK Input
see NOTE
tIS
tIH
L/C Input
VIH VIL
Data valid
Fig. 3-18: Luma/chroma input
Note: active clock edge depends on I2C:<17>NEGCLK
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CIP 3250A
3.6.3.10. Characteristics Priority Input/Output
Symbol VIL VIH VOL IPUP VPUP tIS tIH tOD tOH tOHL Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name PRIO[2...0] Min. - 1.5 - Typ. - - - Max. 0.8 - 0.6 Unit V V V
ADVANCE INFORMATION
Test Conditions
Load as described at I2C:<14>LOAD @ 1 Volt
Pullup Current Pullup Voltage Input Setup Time before active Clock Transition Input Hold Time after active Clock Transition Output Delay Time after active Clock Transition Output Hold Time after active Clock Transition Output Low Hold Time after active Clock Transition
1.2 1.8 7
- 2.0 -
2.0 2.5 -
mA V ns
5
-
-
ns
-
-
35
ns
Load as described at I2C:<14>LOAD
6
-
-
ns
6
-
15
ns
CLK Input
see NOTE
tIS
tIH
PRIO Input
VIH VIL
Data valid
tOD
tOHL
Data valid
PRIO Output
VPUP VOL tOH
Fig. 3-19: Priority input/output
Note: active clock edge depends on I2C:<17>NEGCLK
40
Micronas
ADVANCE INFORMATION
CIP 3250A
3.6.3.11. Characteristics Picture Output
Symbol VOL VOH Parameter Output Low Voltage Pin Name RC[7...0], GL[7..0], B[7..0] B[7 0] Min. - Typ. - Max. 0.4 Unit V Test Conditions Load as described at I2C:<14>LOAD Load as described at I2C:<14>LOAD I2C:<14>PUDIS = 0 Load as described at I2C:<14>LOAD
Output High Voltage (only in Push-pull Mode)
2.4
-
-
V
tOD tOH tOHL
Output Delay Time after active Clock Transition Output Hold Time after active Clock Transition Output Low Hold Time after active Clock Transition
-
-
35
ns
6
-
-
ns
6
-
15
ns
CLK Input
see NOTE
tOD
PICTURE Output Push-pull Mode
VOH VOL tOHP tOD
Data valid
tOHL
Data valid
PICTURE VPUP Output V Open Drain Mode OL
tOH
Fig. 3-20: Picture output
Note: active clock edge depends on I2C:<17>NEGCLK
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CIP 3250A
3.6.3.12. Characteristics Analog R, G, B Inputs
Symbol VVRT RGB - Path RVIN CVIN VVIN VVINCL VVINCL Input Resistance Input Capacitance Full Scale Input Voltage Input Clamping Level, UV for Binary Code 128 Input Clamping Level, RGB, Y for Binary Code 16 Gain Match QCL ICL-LSB INLICL CICL Clamping DAC Resolution Input Clamping Current per step Clamping DAC Integral Non-Linearity Clamping-Capacitor - 220 -32 0.59 0.85 RV GY BU 5 4.5 0.85 1.0 1.5 1.1 M pF VPP V Parameter Reference Voltage Top Pin Name ADREF Min. 2.4 Typ. 2.6 Max. 2.8 Unit V
ADVANCE INFORMATION
Test Conditions 10 F/10 nF, 1G Probe I2C: <14>LOAD = 3
Code Clamp-DAC=0
Full Scale 0 ... 255 Binary Level = 128 LSB
1.06
V
Binary Level = 16 LSB
tbd 31 1.11 0.5
% steps A LSB
Full Scale @ 1 MHz 6 Bit - I-DAC, bipolar =1.5 VVIN=1 5 V
-
nF
Coupling-Cap. @ Inputs
Dynamic Characteristics for RGB-Path at VEXT = 3.3 V, 70 pF load at all outputs, I2C: <14>LOAD = 0 BW XTALK THD Bandwidth Crosstalk, any Two Video Inputs Total Harmonic Distortion RV GY BU 8 -42 -42 -tbd -tbd MHz dB dB -2 dBr input signal pegel 1 MHz, -2 dBr signal pegel 1 MHz, 5 harmonics, -2 dBr signal pegel 1 MHz, all outputs, -2 dBr signal pegel Code Density, DC-ramp DC ramp
SINAD
Signal to Noise and Distortion Ratio Integral Non-Linearity, Differential Non-Linearity
tbd
tbd 4.0 1.0
dB
INL DNL
LSB LSB
3.6.3.13. Characteristics Analog FBL Input
Symbol RFBIN VFBIN Parameter Input Resistance Full Scale Input Voltage Threshold for FBL-Monitor Dynamic Characteristics for FBL Input at VEXT = 3.3 V, 70 pF load at all outputs, I2C: <14>LOAD = 0 BW THD Bandwidth Total Harmonic Distortion FB 8 -38 -tbd MHz dB -2 dBr input signal pegel 1 MHz, 5 harmonics, -2 dBr signal pegel 1 MHz, all outputs, -2 dBr signal pegel Pin Name FB Min. 5 0.85 0.5 Typ. - 1.0 0.65 Max. - 1.1 0.8 Unit M VPP VPP Full Scale 0 ... 63 Test Conditions
SINAD
Signal to Noise and Distortion Ratio
tbd
-36
dB
42
Micronas
ADVANCE INFORMATION
CIP 3250A
4. Application Circuit
Micronas
43
CIP 3250A
5. Data Sheet History 1. Advance Information: "CIP 3250 Component Interface Processor", May 2, 1995, 6251-403-1AI. First release of the advance information. 2. Advance Information: "CIP 3250A Component Interface Processor", Feb. 16, 1996, 6251-403-2AI. Second release of the advance information. Major changes: - Modifications and new features from CIP 3250 to CIP 3250A - Fig. 3-1: PLCC68 package dimensions changed - section 3.2.: Pin Connections and Short Descriptions new - Correction of errors 3. Advance Information: "CIP 3250A Component Interface Processor", Oct. 9, 1996, 6251-403-3AI. Third release of the advance information. Major changes: - section 2.7.: Modified description of Soft Mixer and Fast Blank Monitor, Fig. 2-4: Fast Blank Processing changed, Fig. 2-5: Fast Blank Monitor, Fig. 2-6: DIGIT 2000 skew data and Fig. 2-7: DIGIT 3000 front sync format new - section 2.9.: Table 2-2: Digital input selection new - section 2.12.: Table 2-3: Digital output selection new - section 2.16.: Table 2-10 modified and description of <04>CLSEL changed; Fig. 2-14: DL2-setup and Fig 2-15: DL2-reset during line 7 changed - section 3.6.3.12. and 3.6.3.13.: new characteristics - section 4.: Application Circuit new
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-403-3AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas


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