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Preliminary GS8182S18/36D-333/300/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
* Simultaneous Read and Write SigmaQuadTM Interface * JEDEC-standard pinout and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * DLL circuitry for wide output data valid window and future frequency scaling * Burst of 2 Read and Write * 1.8 V +150/-100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ mode pin for programmable output drive strength * IEEE 1149.1 JTAG-compliant Boundary Scan * 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package * Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb Burst of 2 DDR SigmaSIO-II SRAM
167 MHz-333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data's destination. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512K addressable index).
SigmaRAMTM Family Overview
GS8182S18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst
Parameter Synopsis
- 333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns
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Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
1M x 18 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/SA (72Mb) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8182S18/36D-333/300/250/200/167
512K x 36 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS/SA (288Mb) Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC/SA (72Mb) D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 NC/SA (36Mb) D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 VSS/SA (144Mb) Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A9 for 36Mb, A3 for 72Mb, A10 for 144Mb, A2 for 288Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. 4. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8182S18/36D-333/300/250/200/167
Pin Description Table Symbol
SA NC R/W BW0-BW1 BW0-BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ D Q VDD VDDQ VSS
Description
Synchronous Address Inputs No Connect Synchronous Read/Write Synchronous Byte Writes Synchronous Byte Writes Input Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Input Clock Output Clock DLL Disable Synchronous Load Pin Output Echo Clock Output Echo Clock Synchronous Data Inputs Synchronous Data Outputs Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input -- Input Input Input Input Input Input Input Input Output Input Input Input Output -- -- Output Output Input Output Supply Supply Supply
Comments
-- -- Active Low x18 Version Active Low x36 Version Active High Active High -- -- -- -- -- -- Active Low Active Low Active Low Active Low Active Low Active High
1.8 V Nominal 1.8 or 1.5 V Nominal --
Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. NC = Not Connected to die or any other pin
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Preliminary GS8182S18/36D-333/300/250/200/167
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. Each of the three SigmaQuad Family SRAMs--SigmaQuad, SigmaCIO, and SigmaSIO--supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM's interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Burst of 2 SigmaSIO-II SRAM DDR Read The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out at the next rising edge of K. Burst of 2 SigmaSIO-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
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Preliminary GS8182S18/36D-333/300/250/200/167
Special Functions
Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0-D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2
BW0
0 1
BW1
1 0
D0-D8
Data In Don't Care
D9-D17
Don't Care Data In
Resulting Write Operation Beat 1 D0-D8
Written
Beat 2 D0-D8
Unchanged
D9-D17
Unchanged
D9-D17
Written
Output Register Control SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
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Preliminary GS8182S18/36D-333/300/250/200/167
Example Four Bank Depth Expansion Schematic
R/W3 LD3 R/W2 LD2 R/W1 LD1 R/W0 LD0 A0-An K D1-Dn Bank 0 A R/W LD K D C
C Q1-Qn Note: For simplicity BWn is not shown.
Bank 1 A R/W LD
Bank 2 A R/W LD
Bank 3 A R/W LD K
Q
K D C
Q
K D C
Q
D C
Q
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Burst of 2 SigmaSIO-II SRAM Depth Expansion
Write B Read C Write D Read E Write F Read G Read H Read J NOP
Rev: 1.03b 1/2004
B C D E F G H J B+1 B D+1 D F F+1 E E+1 H H+1 C C+1 G G+1 J
K
K
Address
LD Bank 1
LD Bank 2
R/W Bank 1
R/W Bank 2
BWx Bank 1
BWx Bank 2
D Bank 1
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D Bank 2
C Bank 1
C Bank 1
Q Bank 1
CQ Bank 1
CQ Bank 1
C Bank 2
C Bank 2
Q Bank 2
CQ Bank 2
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
(c) 2003, Giga Semiconductor, Inc.
CQ Bank 2
Preliminary GS8182S18/36D-333/300/250/200/167
FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM's output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for "0s" occur whenever the SRAM is driving "1s" for the same DQs (and vice-versa for "1s") or the SRAM is in HI-Z.
Separate I/O Burst of 2 SigmaSIO-II SRAM Truth Table A K (tn)
X V V
LD K (tn)
1 0 0
R/W K (tn)
X 1 0
Current Operation K (tn)
Deselect Read Write
D K (tn+1)
X X D0
D K (tn+1)
-- -- D1
Q K (tn+1)
Hi-Z Q0 Hi-Z
Q K (tn+1)
-- Q1 --
Notes: 1. "1" = input "high"; "0" = input "low"; "V" = input "valid"; "X" = input "don't care" 2. "--" indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses.
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Preliminary GS8182S18/36D-333/300/250/200/167
x18 Byte Write Clock Truth Table BW K (tn+1)
T T F F
BW K (tn+2)
T F T F
Current Operation K (tn)
Write Dx stored if BWn = 0 in both data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer
D K (tn+1)
D1 D1 X X
D K (tn+2)
D2 X D2 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more BWn = 0, then BW = "T", else BW = "F".
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Preliminary GS8182S18/36D-333/300/250/200/167
x36 Byte Write Enable (BWn) Truth Table BW3
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
BW2 BW1 BW0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D27-D35
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Data In Data In Data In Data In
D18-D26
Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In
D9-D17
Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In
D0-D8
Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In
x 18 Byte Write Enable (BWn) Truth Table BW1 BW0
1 0 1 0 1 1 0 0
D9-D17
Don't Care Don't Care Data In Data In
D0-D8
Don't Care Data In Don't Care Data In
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Preliminary GS8182S18/36D-333/300/250/200/167
State Diagram
Power-Up
LOAD
NOP
LOAD
LOAD
Load New Address
LOA
LOAD
READ
WRITE
LOAD
DDR Read
DDR Write
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Preliminary GS8182S18/36D-333/300/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature
Value
-0.5 to 2.9 -0.5 to VDD -0.5 to VDDQ -0.5 to VDDQ +0.3 ( 2.9 V max.) -0.5 to VDDQ +0.3 ( 2.9 V max.) +/-100 +/-100 125 -55 to 125
Unit
V V V V V mA dc mA dc
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage 1.8 V I/O Supply Voltage 1.5 V I/O Supply Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
VDD VDDQ VDDQ TA TA
Min.
1.7 1.7 1.4 0 -40
Typ.
1.8 1.8 1.5 25 25
Max.
1.9 1.9 1.6 70 85
Unit
V V V C C
Notes
1 1 2 2
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V VDDQ 1.6 V (i.e., 1.5 V I/O) and 1.7 V VDDQ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
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Preliminary GS8182S18/36D-333/300/250/200/167
HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low VREF DC Voltage Note: Compatible with both 1.8 V and 1.5 V I/O drivers
Symbol
VIH (dc) VIL (dc) VREF (dc)
Min
VREF + 0.1 -0.3 VDDQ (min)/2
Max
VDDQ + 0.3 VREF - 0.1 VDDQ (max)/2
Units
mV mV V
Notes
1 1 1
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 0.2 -- --
Max
-- VREF - 0.2 5% VREF (DC)
Units
mV mV mV
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac) VREF VIL (ac)
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Preliminary GS8182S18/36D-333/300/250/200/167
Undershoot Measurement and Timing
VIH VDD + 1.0 V VSS 50% VSS - 1.0 V 20% tKHKH VIL 50% VDD
Overshoot Measurement and Timing
20% tKHKH
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Output Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2
AC Test Load Diagram
DQ 50 VT = VDDQ/2 RQ = 250 (HSTL I/O) VREF = 0.75 V
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Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Mode Pin Input Current Output Leakage Current
Symbol
IIL IINM IOL
Test Conditions
VIN = 0 to VDD VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDDQ
Min.
-2 uA -100 uA -2 uA -2 uA
Max
2 uA 2 uA 2 uA 2 uA
Notes
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 Vss
Max.
VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/- 15% @ VOH = VDDQ/2 (for: 175 RQ 350). 2. IOL = (VDDQ/2) / (RQ/5) +/- 15% @ VOL = VDDQ/2 (for: 175 RQ 350). 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = -1.0 mA 6. IOL = 1.0 mA
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Operating Currents
-333 0C to 70C
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 95 mA TBD 85 mA TBD TBD TBD TBD TBD TBD 460 mA TBD 400 mA TBD
Rev: 1.03b 1/2004 -300 -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C Test Conditions -250 -200 -167
R and W VIL Max. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min.
Parameter
Org
Symbol
IDD
Operating Current
x36
IDDQ
IDD
TBD TBD TBD TBD
130 mA 5 mA
TBD TBD TBD TBD
TBD TBD
TBD TBD TBD TBD
120 mA 5 mA
TBD TBD TBD TBD
TBD TBD
Operating Current
x18
IDDQ
R and W VIL Max. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min.
17/33
ISB1
Chip Disable Current
x36
ISBQ1
R and W VIH Min. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min.
ISB1
Chip Disable Current
x18
ISBQ1
R and W VIH Min. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Note: Power measured with output pins floating.
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(c) 2003, Giga Semiconductor, Inc.
Preliminary GS8182S18/36D-333/300/250/200/167
AC Electrical Characteristics
Parameter
K Clock Cycle Time C Clock Cycle Time K Clock High Pulse Width C Clock High Pulse Width K Clock Low Pulse Width C Clock Low Pulse Width K Clock High to C Clock High Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data and Byte Write Input Setup Time Data and Byte Write Input Hold Time K Clock High to Data Output Valid C Clock High to Data Output Valid K Clock High to Data Output Hold C Clock High to Data Output Hold K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z K Clock High to Data Output High-Z C Clock High to Data Output High-Z K Clock High to CQ Clock High C Clock High to CQ Clock High K Clock High to CQ Clock Hold C Clock High to CQ Clock Hold CQ Clock High to Data Output Valid CQ Clock High to Data Output Hold CQ Clock High Pulse Width CQ Clock Low Pulse Width CQ Clock High Pulse Width CQ Clock Low Pulse Width
Symbol
tKHKH tCHCH tKHKL tCHCL tKLKH tCLCH tKHCH tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX tKHQV tCHQV tKHQX tCHQX tKHQX1 tCHQX1 tKHQZ tCHQZ tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX tCQHCQL tCQLCQH tCQHCQL1 tCQLCQH1
-333
Min 3.0 1.2 1.2 0 0.4 0.4 0.4 0.4 0.28 0.28 -- -0.45 -0.45 -- -- -0.45 -- -0.25 Max -- -- -- 1.3 -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.25 -- Min 3.3 1.32 1.32 0 0.4 0.4 0.4 0.4 0.3 0.3 --
-300
Max -- -- -- 1.45 -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.27 -- Min 4.0 1.6 1.6 0 0.5 0.5 0.5 0.5
-250
Max -- -- -- 1.8 -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.3 -- Min 5.0 2.0 2.0 0 0.6 0.6 0.6 0.6 0.4 0.4 --
-200
Max -- -- -- 2.3 -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.35 -- Min 6.0 2.4
-167
Max 8.4 -- -- 2.8 -- -- -- -- -- -- 0.5 -- -- 0.5 0.5 -- 0.4 --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
1.49 0 0.7 0.7 0.7 0.7 0.5 0.5 -- -0.5 -0.5 -- -- -0.5 -- -0.4
1 1
0.35 0.35 -- -0.45 -0.45 -- -- -0.45 -- -0.3
-0.45 -0.45 -- -- -0.45 -- -0.27
-0.45 -0.45 -- -- -0.45 -- -0.35
2 2,3 2,3
2 2 2 2 2 2
tKHKL 0.1 tKLKH 0.1 tCHCL 0.1 tCLCH 0.1
tKHKL 0.1 tKLKH 0.1 tCHCL 0.1 tCLCH 0.1
tKHKL 0.1 tKLKH 0.1 tCHCL 0.1 tCLCH 0.1
tKHKL 0.1 tKLKH 0.1 tCHCL 0.1 tCLCH 0.1
tKHKL 0.1 tKLKH 0.1 tCHCL 0.1 tCLCH 0.1
Notes: 1. These parameters apply to control inputs E1, E2, R, and W. 2. These parameters are guaranteed by design through extensive corner lot characterization. 3. These parameters are measured at 50 mV from steady state voltage. Rev: 1.03b 1/2004 18/33 (c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
CHQX Write F CHQV KHBX KHDX DVKH BVKH
C+1 F
Read E
K Controlled Read-First Timing Diagram
Read D
CHQZ CHQX1
C B B+1
KHAX
D
E
Write C
KH#KH
KHBX
D
D+1
E
KLKH
AVKH
KHBX
Read B
KHKL
KHKH
B
BVKH
NOP
Address
BWx
Q
CQHQV CQHQX
CQ
BVKH
CQHQV CQHQX
R/W
C
Rev: 1.03b 1/2004
19/33
CQ
K
K
LD
D
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
Deselect
F+1
E+1
Write F
KHDX
CHQV CHQX CHQX1
CHQZ
C C+1 D D+1
F
K Controlled Write-First Timing Diagram
Write E
Read D
KH#KH
E
E
F
KLKH
KHAX
KHBX
Read C
KHKL
C
DVKH
BVKH
KHKH
KHBX
Write B
AVKH
B
BVKH
B
B+1
NOP
BVKH
R/W
LD
Address
BWx
D
Q
CQHQV CQHQX
CQ
CQHQV CQHQX
KHBX
D
Rev: 1.03b 1/2004
20/33
CQ
K
K
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
CHQX Write F CHQV KHBX KHDX
C+1 F
Read E
C Controlled Read-First Timing Diagram
E
CHQZ CHQX1 KH#KH
C B B+1
Read D
KHAX
D
Write C
KH#KH
KHBX
DVKH
BVKH
D
D+1
E
KLKH
AVKH
KHBX
Read B
KHKL
B
BVKH
KHKL
KHKH
KLKH
NOP
BVKH
R/W
D
C
LD
Address
BWx
C
Q
CQHQV CQHQX
CQ
KHKH
CQHQV CQHQX
C
Rev: 1.03b 1/2004
21/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
CQ
K
K
Preliminary GS8182S18/36D-333/300/250/200/167
Deselect
Read F
E+1
F
D+1
E
CHQZ CHQX1 KH#KH
C C+1
C Controlled Write-First Timing Diagram
Write E
E
KHDX KH#KH
Write D
D
KHBX
KLKH
B+1
KHAX
KHBX
Read C
KHKL
C
DVKH
BVKH
B
KHKL
KHKH
KHBX
Write B
AVKH
B
BVKH
KHKH
KLKH
NOP
BVKH
R/W
D
C
LD
Address
BWx
C
Q
CQHQV CQHQX
CQ
CQHQV CQHQX
D
Rev: 1.03b 1/2004
22/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
CQ
K
K
Preliminary GS8182S18/36D-333/300/250/200/167
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.03b 1/2004
23/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
* * *
108
*
*
*
*
*
*
* *
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
*
***
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents TBD for this part.
Rev: 1.03b 1/2004
24/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
ID Register Contents
Die Revision Code Bit # x72 x36 x32 x18 x16 GSI Technology JEDEC Vendor ID Code Presence Register 0 1 1 1 1 1
Not Used
I/O Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 0 011011001
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
Rev: 1.03b 1/2004
25/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.
Rev: 1.03b 1/2004
26/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU
Code
000 001 010 011
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1
Rev: 1.03b 1/2004
27/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
JTAG TAP Instruction Set Summary
SAMPLE/ PRELOAD GSI RFU BYPASS 100 101 110 111 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO. 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
2.0 -0.3 0.6 * VDD2 -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV --
Max.
VDD3 +0.3 0.8 VDD2 +0.3 0.3 * VDD2 1 100 1 -- 0.4 -- 100 mV
Unit Notes
V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA
Rev: 1.03b 1/2004
28/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
JTAG Port AC Test Conditions
Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
JTAG Port AC Test Load
50 VDDQ/2
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted.
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width Rev: 1.03b 1/2004 Symbol tTKC tTKQ tTKH Min 50 -- 20 Max -- 20 -- 29/33 Unit ns ns ns (c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
JTAG Port AC Electrical Characteristics
TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time tTKL tTS tTH 20 10 10 -- -- -- ns ns ns
Rev: 1.03b 1/2004
30/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1 A aaa D D1
Side View
e
Bottom View
E1 b e
Symbol A A1 b c D Rev 1.0
Min -- 0.40 0.50 0.31 21.9
Typ -- 0.50 0.60 0.36 22.0
Max 1.70 0.60 0.70 0.38 22.1
Units mm mm mm mm mm
Symbol D1 E E1 e aaa
Min -- 13.9 -- -- --
Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15
E
Max -- 14.1 -- -- --
Units mm mm mm mm mm
Thermal Characteristics Package
209 BGA (C)
Junction to Ambient () (C/W) 0 m/s
17.7
1 m/s
16.0
2 m/s
14.1
Junction to Case () (C/W)
2.8
Rev: 1.03b 1/2004
31/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
Ordering Information--GSI SigmaSIO-II SRAM Org
512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 512Kx 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18
Part Number1
GS8182S36D-333 GS8182S36D-300 GS8182S36D-250 GS8182S36D-200 GS8182S36D-167 GS8182S36D-333I GS8182S36D-300I GS8182S36D-250I GS8182S36D-200I GS8182S36D-167I GS8182S18D-333 GS8182S18D-300 GS8182S18D-250 GS8182S18D-200 GS8182S18D-167 GS8182S18D-333I GS8182S18D-300I GS8182S18D-250I GS8182S18D-200I GS8182S18D-167I
Type
SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM
Package
1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA 1 mm Pitch, 165-Pin BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167
TA3
C C C C C I I I I I C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS818x36D-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.03b 1/2004
32/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary GS8182S18/36D-333/300/250/200/167
SigmaSIO-II Revision History File Name
8182Sxx_r1 8182Sxx_r1; 8182Sxx_r1_01 8182Sxx_r1_01; 8182Sxx_r1_02 8182Sxx_r1_02; 8182Sxx_r1_03 Content Content Content
Format/Content
Description of changes
Creation of datasheet * Changed 330 MHz to 333MHz * Removed any references to 133 MHz or 100 MHz * Updated AC spec information * Comprehensive rewrite, including (but not limited to) tables, pinouts, and timing diagrams
Rev: 1.03b 1/2004
33/33
(c) 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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