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19-3385; Rev 0; 8/04
Multiple-Output Network Clock Generator
General Description
The MAX9489 clock generator provides multiple clock outputs, ideal for network routers. The MAX9489 provides 15 buffered clock outputs, each independently programmable to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, or 25MHz. All of the outputs are single-ended LVCMOS. The MAX9489 is controlled through its I2CTM interface. At power-up, the frequency of output CLK1 is set by the tri-level input SEL to 100MHz, 125MHz, or 133MHz, while all other outputs are logic low. All outputs are then programmable to any available frequency through the I2C interface. Additionally, all output frequencies are adjustable up or down, by a margin of 5% or 10%, through the I2C interface. The MAX9489 requires a 25MHz reference that can be either a crystal or an external clock signal. The MAX9489 requires a +3.0V to +3.6V power supply and is available in a 32-pin thin QFN package with an exposed pad for heat removal.
Features
15 LVCMOS Outputs with 10 Independently Programmable Frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, and 25MHz 25MHz Crystal or Clock Input Reference Programmable Through I2C Interface Programmable Output Frequency Margin of 5% or 10% Pin-Selectable Power-Up Frequency for CLK1 Output: 100MHz, 125MHz, or 133MHz Low Output Period Jitter: < 48psRMS Output-to-Output Skew < 200ps Available in 32-Lead, 5mm x 5mm x 0.8mm, Thin QFN Package Operates from +3.0V to +3.6V Power Supply Power Dissipation 450mW (typ) Extended Temperature Range: -40C to +85C
MAX9489
Applications
Network Routers Telecom/Networking Equipment Storage Area Networks/Network Attached Storage
Ordering Information
PART MAX9489ETJ TEMP RANGE -40C to +85C PIN-PACKAGE 32 Thin QFN-EP* 5mm x 5mm x 0.8mm
Pin Configuration
*EP = Exposed pad.
CLK15 CLK14 GND SA1 SA0 VDD VDD TOP VIEW CLK13
Typical Operating Circuit
24 VDD 23 CLK12 22 CLK11 21 CLK10 20 VDD 19 CLK9 18 CLK8
32 31 30 29 28 27 26 25 GND SCL SDA SEL AVDD X1 X2 AGND 1 2 3 4 5 6 7 8 9 CLK1 EXPOSED PAD (GND) 10 11 12 13 14 15 16 CLK2 CLK3 CLK4 CLK5 CLK6 VDD VDD
+3.3V 0.1F AVDD VDD
+3.3V 0.1F x 5
MAX9489
MAX9489
X1 10pF 25MHz 10pF X2 SERIAL INTERFACE SDA SCL SA0 SA1 SEL AGND GND
VDD VDD VDD VDD CLK1 CLOCK OUTPUTS CLK15
17 CLK7
THIN QFN-EP
I 2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Multiple-Output Network Clock Generator MAX9489
ABSOLUTE MAXIMUM RATINGS
VDD to GND .........................................................-0.3V to +4.0V AGND to GND ......................................................-0.3V to +0.3V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Short-Circuit Duration for all CLK_ Outputs ...............Continuous Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.3mW/C above +70C) ....1702mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C ESD Rating (Human Body Model) .......................................2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = AVDD = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25C.) (Note 1)
PARAMETER CLOCK INPUT (X1) Input High Level Input Low Level Input Current CLOCK OUTPUTS (CLK_) IOH = -100A Output High Level VOH IOH = -4mA IOH = -8mA IOL = 100A Output Low Level Output Short-Circuit Current Output Capacitance TRI-LEVEL INPUTS (SEL, SA0, SA1) Input High Level Input Low Level Input Open Level Input Current VIH2 VIL2 VIO2 IIL2, IIH2 VIL2 = 0 or VIH2 = VDD 1.35 -10 0.7 x VDD 0 -1 ISINK = 4mA (Note 2) 0 2.5 0.8 1.90 +10 V V V A VOL IOS CO IOL = 4mA IOL = 8mA CLK_ = VDD or GND (Note 2) VDD 0.2 2.4 2.1 0.2 0.4 0.75 45 5 mA pF V V VIH1 VIL1 IIL1, IIH1 VX_ = 0 to VDD -5 2.0 0.8 +5 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
SERIAL INTERFACE (SCL, SDA) (Note 3) Input High Level Input Low Level Input leakage Current Low-Level Output Input Capacitance VIH VIL IIH, IIL VOL Ci VDD 0.3 x VDD +1 0.4 10 V V A V pF
2
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Multiple-Output Network Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = AVDD = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25C.) (Note 1)
PARAMETER POWER SUPPLIES Digital Power-Supply Voltage Analog Power-Supply Voltage Total Supply Current Total Power-Down Current IPD VDD AVDD CL = 10pf (with all CLK_ outputs at 133MHz) All clock registers = 0x00 3.0 3.0 134 38 3.6 3.6 160 47 V V mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9489
AC ELECTRICAL CHARACTERISTICS
(VDD = AVDD = +3.0V to +3.6V, CL = 10pF, unless otherwise noted. Typical values are at VDD = AVDD = +3.3V, TA = +25C, with all CLK_ outputs at 133MHz.) (Note 2)
PARAMETER OUTPUTS (CLK_) Crystal Frequency Tolerance Output-to-Output Skew Rise Time Fall Time Duty Cycle Output Period Jitter Power-Up Time PLL Lockup Time Margin Accuracy JP tPO tLock RMS VDD > 2.8V to PLL lock PLL dividing ratio set to PLL lock Select 5% or 10% margin -1 fA tSKO tR1 tF1 Any two CLK_ outputs 20% VDD to 80% VDD 80% VDD to 20% VDD 40 53 2 20 +1 1.8 1.8 -50 +50 200 2.5 2.5 60 ppm ps ns ns % ps ms s % SYMBOL CONDITIONS MIN TYP MAX UNITS
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Multiple-Output Network Clock Generator MAX9489
SERIAL INTERFACE TIMING
(VDD = AVDD = +3.3V, TA = -40C to +85C.) (Note 1, Figure 2)
PARAMETER Serial Clock Bus Free Time Between STOP and START Conditions Hold Time, Repeated START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Master Data Hold Time Slave Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of SDA and SCL, Receiving Fall Time of SDA and SCL, Receiving Fall Time of SDA, Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tHD,DAT tSU,DAT tLOW tHIGH tR tF tF,TX tSP Cb (Notes 2, 5) (Notes 2, 5) (Notes 2, 5) (Notes 2, 6) (Note 2) (Note 4) (Note 4) 1.3 0.6 0.6 0.6 15 15 100 1.3 0.7 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0 300 300 250 50 400 900 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s ns ns ns s s ns ns ns ns pF
Note 1: All DC parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: No high output level is specified but only the output resistance to the bus. For I2C, the high-level voltage is provided by pullup resistors on the bus. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3(VDD) and 0.7(VDD). Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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Multiple-Output Network Clock Generator
Typical Operating Characteristics
(VDD = 3.3V, TA = +25C, unless otherwise noted.)
RISE AND FALL TIMES vs. TEMPERATURE
MAX9489 toc02 MAX9489 toc01
MAX9489
SUPPLY CURRENT vs. TEMPERATURE
160 150 SUPPLY CURRENT (mA) 140 130 120 110 100 -40 -15 10 35 60 85 TEMPERATURE (C) 2.3 TRANSITION TIME (ns) 2.1
JITTER vs. TEMPERATURE
133MHz
MAX9489 toc03
70 60 RMS PERIOD JITTER (ps) 50 40 30 20 10 0 25MHz
tFALL 1.9 tRISE 1.7 1.4 1.2 1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
JITTER vs. FREQUENCY
MAX9489 toc04
TYPICAL CLOCK WAVEFORMS
MAX9489 toc05
75
60 RMS PERIOD JITTER (ps)
A 45
30 B
15
0 25 43 61 79 97 115 133 10ns/div A: 100MHz, 100mV/div B: 25MHz, 100mV/div FREQUENCY (MHz)
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Multiple-Output Network Clock Generator MAX9489
Pin Description
PIN 1, 29 2 3 4 5 6 7 8 9 10 11 12, 16, 20, 24, 28, 32 13 14 15 17 18 19 21 22 23 25 26 27 30 31 EP NAME GND SCL SDA SEL AVDD X1 X2 AGND CLK1 CLK2 CLK3 VDD CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 CLK12 CLK13 CLK14 CLK15 SA0 SA1 -- Digital Ground Serial Clock Input. Serial interface clock. Serial Data I/O. Data I/O of serial interface. Frequency Select for CLK1. Selects the frequency for CLK1 at power-up. SEL is a tri-level input. Force SEL high for CLK1 = 100MHz. Leave SEL open for CLK1 = 125MHz. Force SEL low for CLK1 = 133MHz. Power-Supply Input for Analog Circuits Crystal Connection or Clock Input. If using a 25MHz crystal, connect it to X1 and X2. If using a reference clock, connect the clock signal to X1, and leave X2 floating. See the Typical Operating Circuit. Analog GND Clock 1 Output Clock 2 Output Clock 3 Output Power-Supply Input for Digital Circuits Clock 4 Output Clock 5 Output Clock 6 Output Clock 7 Output Clock 8 Output Clock 9 Output Clock 10 Output Clock 11 Output Clock 12 Output Clock 13 Output Clock 14 Output Clock 15 Output Address-Select Inputs for Serial Interface. SA0 and SA1 select the serial interface address, as shown in Table 1. SA0 and SA1 are tri-level inputs, making nine possible address combinations. Exposed pad. Connect to GND. FUNCTION
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Multiple-Output Network Clock Generator
Detailed Description
The MAX9489 clock generator produces 15 clock signals, CLK1 through CLK15. Each output is programmable through control registers to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, or 25MHz. Additionally, the frequency of all outputs can be changed 5% or 10% through the frequency-margin control register. At power-up, the frequency of CLK1 is pin programmable to 100MHz, 125MHz, or 133MHz, and all other CLK outputs are logic low. The required 25MHz input reference frequency can be either a crystal or an external clock signal. Figure 1 shows the MAX9489 functional block diagram. The MAX9489 is programmed through its I 2C serial interface. The I2C address is selected with two, tri-level inputs, allowing up to nine MAX9489 devices to share the same I2C bus. Power-supply and logic interface signals are +3.0V to +3.6V. The operating state of the MAX9489 is set by writing to the control registers, and read by reading the control registers. X2 to GND (see the Typical Operating Circuit). If using an external clock, connect the signal to X1 and leave X2 floating.
MAX9489
Serial Interface
The MAX9489 is programmed through its I 2C serial interface. This interface has a clock, SCL, and a bidirectional data line, SDA. In an I2C system, a master, typically a microcontroller, initiates all data transfers to and from slave devices, and generates the clock to synchronize the data transfers. The MAX9489 operates as a slave device. The timing of the SDA and SCL signals is detailed in Figure 2, the Serial Interface Timing diagram. SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2wire bus, or if the master in a single-master system has an open-drain SCL output.
Bit Transfer
One data bit is transferred during each SCL clock cycle. SDA must remain stable during the high period of SCL, because changes in SDA while SCL is high are START and STOP control signals. Both SDA and SCL idle high.
Reference Frequency Input
A reference frequency is required for the MAX9489. The reference can be a 25MHz crystal or an external clock signal. If using a 25MHz crystal, connect it across X1 and X2, and connect 10pF capacitors from X1 and
START and STOP Conditions
AVDD SEL SCL SDA SA0 SA1 VDD
I2C
MUX
CLK1
A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 2). When communication is complete, a master issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.
Acknowledge Bits
MUX 400MHz PLL1 25MHz OSC DIVIDE BY 3, 4, 5, 6, 12 CLK2
X1 X2
After each 8 bits transferred, the receiving device generates an acknowledge signal by pulling SDA low for the entire duration of the 9th clock pulse. If the receiving device does not pull SDA low, a not-acknowledge is indicated (Figure 3).
400MHz PLL2
DIVIDE BY 2, 3, 4, 5, 10 MUX CLK14
Device Address
The MAX9489 has a 7-bit device address, pin configured by the two tri-level address inputs SA1 and SA0. To select the device address, connect SA1 and SA0 to VDD, GND, or leave open, as indicated in Table 1. The MAX9489 has nine possible addresses, allowing up to nine MAX9489 devices to share the same interface bus.
MAX9489
MUX
CLK15
AGND
GND
Figure 1. MAX9489 Functional Diagram _______________________________________________________________________________________ 7
Multiple-Output Network Clock Generator MAX9489
SDA
tBUF tSU, DAT tLOW SCL tHD, DAT tSU, STA tHD, STA tSU, STO
tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 2. Serial Interface Timing
Table 1. Device I2C Address Selection
PIN SA1 Open Open Open GND GND GND VDD VDD VDD SA0 VDD GND Open VDD GND Open VDD GND Open DEVICE ADDRESS 110 0010 110 0100 110 1000 111 0000 110 1001 110 1100 111 0100 111 0010 111 0001
Reading the MAX9489 Setup
Reading from the MAX9489 registers begins with a START condition and a device address with the write bit set low, then the register address that is to be read, followed by a repeated START condition and a device address with the write bit set high, and finally the data are shifted out (Figure 4). Following a START condition, the first 7 bits comprise the device address. The 8th bit is low to indicate a write operation (to write in the following register address). An acknowledge bit is then generated by the MAX9489, signaling that it recognizes its address. The next 8 bits form the register address, indicating the location of the data to be read, followed by another acknowledge, again generated by the MAX9489. The master then produces a repeated START condition and readdresses the device, this time with the R/W bit high to indicate a read operation (Figure 4). The MAX9489 generates an acknowledge bit, signaling that it recognizes its address. The data byte is then clocked out of the MAX9489. A final notacknowledge bit, generated by the master (not required), and a STOP condition, also generated by the master, complete the communication. To read from the device again, the entire read procedure is repeated; I2C burst read mode is not supported by the MAX9489.
Writing to the MAX9489
Writing to the MAX9489 begins with a START condition (Figures 3 and 4). Following the START condition, each pulse on SCL transfers 1 bit of data. The first 7 bits comprise the device address (see the Device Address section). The 8th bit is low to indicate a write operation. An acknowledge bit is then generated by the MAX9489, signaling that it recognizes its address. The next 8 bits form the register address byte (Table 2) and determine which control register will receive the following data byte. The MAX9489 then generates another acknowledge bit. The data byte is then written into the addressed register of the MAX9489. An acknowledge bit by the MAX9489 followed by a required STOP condition by the master complete the communication. To write to the device again, repeat the entire write procedure; I 2C burst write mode is not supported by the MAX9489.
Device Control Registers
The MAX9489 has 17 control registers. The register addresses and functions are shown in Table 2. The first 16 registers are used to set the 15 outputs, with register 0x00 controlling all outputs simultaneously and the rest mapped to individual outputs. Register 0x10 accesses the frequency-margin control. All other addresses are reserved and are not to be used.
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Multiple-Output Network Clock Generator MAX9489
NOT ACKNOWLEDGE 1 1 A4 A3 A2 A1 A0 R/W ACKNOWLEDGE ACK
SDA
MSB SCL START
LSB
Figure 3. I2C Address and Acknowledge
MASTER-WRITE DATA STRUCTURE START S 1 1 DEVICE ADDRESS A4 A3 A2 A1 R/W 0 REGISTER ADDRESS ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK D7 D6 D5 D4 DATA IN D3 D2 D1 D0 ACK STOP P
MASTER-READ DATA STRUCTURE START S 1 1 DEVICE ADDRESS A4 A3 A2 A1 R/W 0 REGISTER ADDRESS ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
DEVICE ADDRESS RS 1 1 A4 A3 A2 A1 A0
R/W 1 ACK D7 D6 D5 D4
DATA OUT D3 D2 D1 D0 ACK
STOP P
S = START CONDITION A_ = DEVICE ADDRESS ACK = ACKNOWLEDGE ACK = NOT ACKNOWLEDGE
RA_ = REGISTER ADDRESS D_ = DATA P = STOP CONDITION RS = REPEATED START
DATA DIRECTION = MASTER TO SLAVE = SLAVE TO MASTER
Figure 4. I2C Interface Data Structure
Setting the Clock Frequencies
Each CLK_ output has an associated control register. The contents of the registers determine the frequency of their associated outputs. Table 3 provides the frequency mapping for the registers. Example: To program CLK3 to 80MHz, first address the device with R/W low, then send register address byte 0x03 followed by data byte 0x05 (Figure 5).
Bypass each VDD at the device with a 0.1F capacitor. Also bypass AVDD at the device with a 0.1F capacitor. Additionally, use a bulk bypass capacitor of 10F where power enters the circuit board.
Board Layout Considerations
As with all high-frequency devices, board layout is critical to proper operation. Place the crystal as close as possible to X1 and X2, and minimize parasitic capacitance around the crystal leads. Ensure that the exposed pad makes good contact with GND.
Frequency Margin Control
Frequency margin is controlled through control register 0x10. Table 4 provides the mapping for the available margins. A selected margin applies to all outputs. Example: To increase all clock outputs by 5%, address the device, then send register address byte 0x10 followed by data byte 0x01.
Chip Information
TRANSISTOR COUNT: 15,219 PROCESS: CMOS
Power Supply
The MAX9489 uses a 3.0V to 3.6V power supply connected to VDD, and 3.0V to 3.6V connected to AVDD.
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9
Multiple-Output Network Clock Generator MAX9489
Table 2. Register Address Mapping
REGISTER ADDRESS BYTE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 - 0xFF REGISTER FUNCTION Broadcast to all CLK registers CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 CLK12 CLK13 CLK14 CLK15 Frequency margin control Reserved, do not use
Table 3. Output Frequency Control
CLK_ REGISTER DATA BYTE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A OUTPUT FREQUENCY (MHz) Logic low* 133.3 125 100 83.3 80 66.6 62.5 50 33 25
*Power-up default for CLK2 through CLK15.
Table 4. Output Frequency Margin Control
MARGIN REGISTER DATA BYTE 0x00 0x01 0x02 0x07 0x06 OUTPUT FREQUENCY (MHz) 0% 5% 10% -5% -10%
START S 1 1
DEVICE ADDRESS A4 A3 A2 A1
R/W 0 ACK 0 0
REGISTER ADDRESS 0 0 0 0 1 1 ACK 0 0 0 0
DATA IN 0 1 0 1 ACK
STOP P
S = START CONDITION A_ = DEVICE ADDRESS
ACK = ACKNOWLEDGE P = STOP CONDITION
DATA DIRECTION = MASTER TO SLAVE = SLAVE TO MASTER
Figure 5. Example--Setting CLK3 to 80MHz
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Multiple-Output Network Clock Generator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX9489
0.15 C A
D2
C L
D D/2
0.15 C B
b D2/2
0.10 M C A B
k
MARKING
XXXXX
E/2 E2/2 E (NE-1) X e
C L
E2
k L
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
F
1
2
COMMON DIMENSIONS PKG. 32L 5x5 16L 5x5 20L 5x5 28L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
F
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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