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KESRX05
260 to 470MHz ASK Receiver with Power Down Preliminary Information
DS5023 Issue 1.9 August 1999
Features
G G G G G G G
Ordering Information
KESRX05B/KG/QP1S (anti-static tubes) KESRX05B/KG/QP1T (tape and reel) The KESRX05 is a single chip ASK (Amplitude Shift Key) Receiver IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. The receiver offers an exceptionally high level of integration and performance to meet the local oscillator radiation requirements of regulatory authorities world wide. Functionally the device works in the same way as the KESRX01 with the added features of low supply voltage, in-band interference rejection (anti-jamming detector), a 2-stage power down to enable receiver systems to be implemented with less than 1mA supply, and a wide IF bandwidth and drive stage to interface to an external ceramic IF bandpass filter at intermediate frequencies from 0*2MHz to 15MHz. The KESRX05 is an ideal receiver for difficult reception areas where high level interferers would jam the wanted signal. The anti-jamming circuit allows operation to be possible with interfering signals which are more than 20dB stronger than the wanted signal, without the cost penalties of increased IF selectivity and frequency accuracy.
In-band Interference Rejection 20dB max. 2103dBm Sensitivity (IF BW = 470kHz) AGC around LNA and Mixer Low Supply voltage (3 to 6V) 2-Stage Power Down for Low Current Applications Interface for Ceramic IF Filters up to 15MHz All Pins Meet 2kV Human Body Model ESD Protection Requirement G Compliant to ETS 300-220 and FCC Part 15
Applications
G Remote Keyless Entry G Security, tagging G Remote Controlled equipment
Absolute Maximum Ratings
Supply voltage, VCC Storage temperature,Tstg Junction temperature, Tj RF input power 20*5V to 17V 255C to 150C 255C to 150C 120dBm from 50
AGC RF INPUT MIXER LNA SAW FILTER NOISE REDUCTION FILTER VCO CERAMIC IF FILTER DATA FILTER ANTI JAM
RSSI DETECTOR
SLICER SLICED DATA REF
LOOP FILTER
XTAL PHASE DETECTOR
464
PHASE LOCKED LOOP
Figure 1 Typical system application
KESRX05
IFFLT1 IFDC1 IFIN IFDC2 VCC IFOUT VCCRF MIXIP RFOP VEERF RFIN AGC PEAK DATAOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
IFFLT2 RSSI DETB PD XTAL1 XTAL2 DF0 DF1 DF2 VCO1 VCO2 VEE LF DSN
KESRX05
22 21 20 19 18 17 16 15
Figure 2 Pin connections (top view)
DESCRIPTION
The single conversion superheterodyne receiver approach is now generally considered the way forward for ISM band type applications because of lower cost, superior selectivity, lower radiation, and flexibility over other techniques. For power-conscious, hand-held applications KESRX05 provides improved performance and flexibility on a lower 3*0V supply and a power down feature allows faster switch-on times for use in a pulsed power saving mode. Although this is a relatively simple receiver, the flexibility of using an external IF filter allows the designer to choose both the selectivity and the IF in order to optimise Pin 1 Name IFFLT1 Function Noise reducing IF filter A simple LC noise reduction filter (L5 and C7) is connected between pins 1 (IFFLT1 ) and 28 (IFFLT2) to reduce the noise contribution from the earlier stages of the logathrimic amplifier. The LC filter helps to reduce the bandwidth of the log amplifier from approximately 45MHz to typically 1MHz, preventing wideband noise from being detected as a signal. To reduce the Q of the simple LC circuit, an external damping resistor in parallel with L5, C7. However, the preferred method to a damping resistor is to lower the Q of L5 or increase the tolerances of L5 and C7. For further information refer to the IFAmp /RSSI Detector section of the Functional Description.
Table 1 Pin descriptions Cont...
the performance for a wide range of applications and locations world wide. The KESRX05, with its anti-jamming detector circuit, is an ideal ASK/ OOK receiver for difficult reception areas caused by interference such as amateur radio repeater stations and wireless stereo headphones. Operation is possible with interfering signals which are more than 20dB stronger than the wanted signal (IF bandwidth = 470kHz.), without the cost penalities of increased IF selectivity and frequency accuracy. Figure 1 is the system block diagram, with an external ceramic IF filter, SAW fillter and noise reduction filter. Schematic
VCC 10k IFFLT1 10k IFFLT2
2
KESRX05
Pin 2
Name IFDC1
Function Log Amplifier DC Blocking Capacitor Capacitors C3 and C4 provide DC blocking within the high gain stage of the log amplifier. The log amplifier has a small gain of greater than 80dB between pins 3 (IFIN) and 27 (RSSI output) Capacitors C3 and C4 eliminate DC offsets, allowing the amplification of AC signals only. For further information, refer to the IF Amp/RSSI Detector section of the Functional Description.
Schematic
181k IFDC1 3*1k
181k IFDC 950
IFIN
3
IFIN
Log Amp Input (IFamplifier input) The bandwidth of KESRX05 is set by the external ceramic filter CF1. Impedance matching from the output of the ceramic filter to the input of the log amplifier is achieved by an external shunt resistor R9 in parallel with an internal resistor. For further information please refer to the IF Interface section of the Functional Description.
C3
INTERNAL IFDC1 181k
R9 FROM CF1 IFIN
3*1k
Matching circuit for CF1
4 5 6
IFDC2 VCC IFOUT
Log amplifier DC stability capacitor Positive supply IF output The IF output drive is a voltage drive with a low output impedance of 300 via an internal series resistor. The IFOUT pin is designed for direct connection to an external 10*7MHz FM ceramic filter with a typical input impedance of 300. For further information refer to the IF Interface section of the Functional Description.
See pin 2
300 IFOUT 50A
7 8
VCCRF MIXIP
Positive supply for RF circuits Mixer input To a first order approximation the input impedance of the mixer at UHF frequencies is set by the internal bias resistor and capacitor network. Effects of internal and external stray parasitics ignored. For further information refer to the AC Electrical Characteristics.
Table 1 Pin descriptions (continued)
MIXIP 2k 2p VEERF
Cont...
3
KESRX05
Name RFOUT Function Output from internal RF amplifier The RF amplifier has a high output impedance. The internal 300 resistor is used to improve the ESD protection of RFOUT. For further information refer to the AC Electrical Characteristics. 10 11 VEERF RFIN Negative supply for RF circuits nternal input RF amplifier To a first order approximation the input impedance of the RF amplifier at UHF frequencies is set by the internal bias resistor and capacitor network. Effects of internal and external stray parasitics ignored. For further information please refer to the AC Electrical Characteristics. 12 AGC RF AGC time constant The attack and decay time constant of the AGC is set by the internal series resistor, current sink and the external capacitor C8. Increasing the decay time constant of the AGC circuit will impair the time to good data of the receiver from power up PD0 to PD2. For further information please refer to the IF Amp/ RSSI Detector section of the Functional Description. 13 PEAK Data signal peak detector output The peak detector output is designed to be a low impedance output. The peak detector monitors the peak of the signal at pin 20 (DF2). For further information please refer to the Baseband section of the Functional Description. 14 DATAOP Sliced data output The data output is the inverted sense of the input signal at pin 20 (DF2) and is designed as a high impedance output via two internal sink and source current generators
Table 1 Pin descriptions (continued)
HIGH
240A RFIN 1k 5p 830 10p VEERF
Pin 9
Schematic
RFOP 300
240A (AGC OFF)
360 AGC 6A
300 PEAK 190k VEE
120A
DATAOP LOW
220A
Cont...
4
KESRX05
Pin 15
Name DSN
Function Data slice reference level The DSN pin is defined internally by the Slice voltage VREF. The DSN slice voltage can be offset from the internal reference VREF by connecting a resistor from the DSN pin to VEE and/or the peak detector output. For further information please refer to the Baseband section of the Functional Description.
Schematic
DF2 3k DSN 100k VREF (VBE) VEE HYSTERESIS 25mV 3k
16
LF
PLL loop filter connection
UP
The phase detector output current is derived by two internal current sources. The nominal linear average output current is 115A (5A/radian). For further information please refer to the Phase Lock Loop VCO section of the Functional Description 17 18 VEE VCO2 Negative supply Voltage controlled oscillator The voltage controlled oscillator circuit is designed from two cross coupled transistors. The centre frequency of the VCO is set by the external tank circuit. For further information please refer to the Voltage Controlled Oscillator (VCO) Circuit Design / Layout section of the Functional Description 19 20 VCO1 DF2 Voltage controlled oscillator Data Filter Output The data filter is configured as a unity gain amplifier with a low impedance output. Tracking of the received baseband signal is achieved by an internal current source. For further information please refer to the Baseband section of the Functional description. 21 DF1 Data filter input Input to data filter. Bandwidth of second order Sallen and Key data filter is set by external components R10, R1 1, C5 and C6. For further information please refer to the Baseband section of the Functional Description.
Table 1 Pin descriptions (continued)
115A
LF DOWN
215A
VCC 1*4k 50 VCO1 1*4k 50 VCO2
300A
See pin 18
DF2 3k DSN 100k VREF (VBE) VEE HYSTERESIS 25mV 3k
DF1
Cont...
5
KESRX05
Name DF0 Function Anti-jam detector circuit output
DF0 7A
Pin 22
Schematic
23
XTAL2
Crystal oscillator input This pin is directly connected to the base of the Colpitts oscillator input transistor. The value of the feedback capacitors C13, C14 connected between XTAL1 and XTAL2 are set by the parallel load capacitance of the external crystal. Connecting a 200k resistor from XTAL 1 to ground (in parallel with C14 ) will maintain oscillation of the crystal in PD0 mode but increase the receiver current consumption by approx 20A.
6k 12k XTAL2 XTAL1 18*7k 200k 42A
VCC
24 25
XTAL1 PD
Crystal oscillator input Power down input This tristate input pin is designed to power-up the device in two modes PD0 to PD2 and PD1 to PD2. For further information please refer to the Functional Description.
See pin 23
VCC
300k PD 124k
VEE
26
DETB
Anti-jam detector input DETB input is configured as a high impedance input where the signal is DC restored on the peak of the signal, with the aid of capacitor C10. For further information please refer to the Anti Jamming Circuit
VCC 3A DETB
27
RSSI
RSSI output The RSSI output is configured as a low impedance output. Tracking of the receive baseband signal is achieved by an internal current source. See pins 3 and 11. For further information please refer to IF Amp/RSSI Detector
RSSI 7A VEE
28
IFFLT2
Noise reducing IF filter
Table 1 Pin descriptions (continued)
See pin 1
6
KESRX05 Electrical Characteristics - Test Conditions
These characteristics are guaranteed by either production test or design over the following range of operating conditions unless otherwise stated: TAMB = 240C to 1105C, VCC = 3*0V to 6*0V Value
Characteristic
Symbol VCC TAMB
Min.
3*0 240
Typ.
Max.
6*0 1105
Units
V C MHz
Conditions
Supply voltage Ambient temperature Test frequency
470
Local oscillator frequency
VCO
480*7
550 470
MHz MHz
Local oscillator frequency configured for high side injection, except where otherwise specified (Note 9) 240C to 185C 240C to 1105C
DC Electrical Characteristics
These characteristics are guaranteed by either production test or design over the following range of operating conditions unless otherwise stated: TAMB = 240C to 1105C, VCC = 3*0V to 6*0V, application circuit Figure 25 Value
Characteristic
Symbol
Min.
Typ.
Max.
Units
Conditions
Supply Current Receive mode (PD2) Power down 1 (PD1) Power down 2 (PD0)
ICC ICC1 ICC2
3*9 0*35 29
5*5 0*55 57
mA mA A
All. PD = high, RF input ,250dBm (Figure 24) All. PD = VCC/2 or high impedance source VCC = 3*0V to 6*0V (Note 4 and Figure 20) All. PD = VEE (Figure 22)
AC Electrical Characteristics (1)
These characteristics are guaranteed by either production test or design over the following range of operating conditions unless otherwise stated: TAMB = 240C to 1105C, VCC = 3*0V to 6*0V, application circuit Figure 25 Value Characteristic Input frequency range Intermediate frequency Test fixture functionality Sensitivity (application), receiver BW = 470kHz Sensitivity (application), receiver BW = 50kHz Overload performance PLL control line (pin 16) to achieve 90% of final value PD1 and PD2 PLL control line (pin 16) to achieve 90% of final value PD1 and PD2 Data output voltage high Data output voltage low Conducted emissions Symbol fS IF VIN(MIN) VIN(MIN) VIN(MIN) VIN(MAX) tS2 Min. 260 0*2 8*0 (289) 1*5 1*12 (2103) (2106) 0*79 0*56 (2109) (2112) 2*23 0*5 3*5 2*0 Typ. Max. 470 15 23 (280) 0*89 (2 08) 1 0*45 (21 14) 6*0 Units MHz MHz Vrms (dBm) Vrms (dBm) Vrms (dBm) Vrms ms Conditions All (Notes 9 and 10) All (Notes 8 and 11) 20kb/s data rate at 470MHz (Note 1) 2kb/s data rate, VCC = 5V, f0 = 433*92MHz (Figure 19, Notes 3 and 11) 2kb/s data rate, VCC = 5V, f0 = 433*92MHz (Figure 20, Notes 10 and 11) 20kb/s data rate at 470MHz (Note 2) All, local oscillator low side injection 423*33MHz, VCC = 5V (Figures 7 and 18, Notes 5 and 11) All, local oscillator low side injection 423*33MHz, VCC = 5V (Figures 7 and 18, Notes 5 and 11) IOH = 120A (Figure 20) IOL = 220A (Figure 20) All, LO low side injection 423*33MHz, with SAW filter (Figure 26, Notes 6 and 11) All, LO low side injection 423*33MHz, SAW filter removed (Figure 25, Notes 6 and 11) VCC = 5V (Figure 8, Notes 7 and 11)
tS3
0*20
0*35
1*5
ms
VOH VCC20*7 VOL 5*6 Antenna (292) (LO)
Anti-jam rejection
Jam
V V mVrms (dBm) 100 mVrms (260) (dBm) 112 120 dB 0*7
7
KESRX05
AC Electrical Characteristics (2)
These characteristics are typical values measured for a limited sample size. They are not guaranteed by production test. They are only given as a guide to assist in the design-in phase of KESRX05 (refer to Note 11) All characteristics measured at TAMB = 25C and VCC = 5V unless otherwise stated. Value Characteristic Internal RF Amplifier Parallel input impedance Parallel output impedance Noise figure Noise matching impedance 1dB compression point Amplifier gain Mixer Parallel input impedance Output impedance Noise figure (double sideband measurement Mixer conversion gain Symbol Min. Typ. 2*8//1*8 1*78//1*7 10//1*1 18//1*1 4*5 1*0//4*6 220 13 Max. Units Conditions
RFIN RFOUT NF RFIN RFIN RFAMP
fS = 434MHz fS = 315MHz fS = 434MHz fS = 315MHz fS = 434MHz, matched 50 environment input and output k//nH fS = 434MHz dBm Input referred, fS = 434MHz, matched 50 environment input and output dB fS = 434MHz, output matched to mixer input impedance k//pF k//pF k//pF k//pF dB k//pF k//pF dB dB fS = 434MHz fS = 315MHz fS = 10*7MHz fS = 434MHz, matched 50 environment input and output fS = 434MHz,fS = 434MHz, measured at input to ceramic filter. Include 6dB matching loss fS = 10*7MHz All (Figures 14 and 15)
MIXIP IF1 NF AMIX
1*6//1*8 1*6//1*8 300 10 9
IF Strip (RSSI) IF input impedance IF gain of log amp
IFIN ALOG
3*1 80
k dB
NOTES 1. The Sensitivity of the test fixture is degraded by loading the input to RF amplifier with 50, lack of image rejection and increasing the data filter bandwidth from 5 to 50kHz Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0*01 where the input signal is a return to zero pulse at 470MHz,with an average duty cycle of 50%, 20kb/s data rate with the receiver bandwidth set to 470kHz. 2. Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to 17dBm for 50 input impedance, Where the input signal is a return to zero pulse at 470MHz with an average duty cycle of 50% and 20kB/s data rate with the receiver bandwidth set to 470kHz. 3. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0*01 where the input signal is a return to zero pulse with an average duty cycle of 50%, 2kb/s data rate. Equivalent to 2103dBm for 50 input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz 3dB bandwidth and a data filter bandwidth of 5kHz. The results shown in Figure 20 and in the AC Electrical Characteristics (1) on page 7 are with the simple LC circuit L5//C7 tuned correctly to 10*7MHz. 4. The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0C. However, the time to good data of PD0 to PD2 can be improved by connecting a 200k in parallel wth C14 (see Table 1, pin 23). 5. Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve within 470kHz of the final frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12, C1 and R2) and the crystal oscillator components (XTAL1, C13 and C14). The dominant term for PLL aquistion is the start-up time of the crystal oscillator circuit, provided the PLL loop filter settling time is much less than the crystal oscillator start-up time. Figure 7 illustrates a suitable test setup for measuring the acquisition time of the PLL and the results are shown in Figure 18. The electrical characterisation parameters are based on the following sets of conditions: Crystal oscillator circuit PLL loop filter Ident Value Ident Value C13 = C14 15pF C12 1*5nF XTAL1 6*6128MHz C1 180pF ESR 15*3 R1 10k L 85*36mH C0 1*83pF C1 6*8pF The performance of the crystal oscillator can be improve by increasing the value of ESR (100 max.) or bt maintaining the crystaloscillator in PD0 mode by connecting a 200k resistor in parallel with C14 (see Table 1, pin 23). The typical time to valid data of the receiver at a data rate of 2kb/s is shown in Figure 17, which is accurate to 6250s since the duration of the SPACE at 2kb/s = 250s. 6. Local oscillator power fed back into 50 source at antenna input (RF input). Measured with RF input matching network shown in Figures 25 and 26.
8
KESRX05
NOTES (continued) 7. In-band interference rejection for an unmodulated interfering signal at 100kHz low side from the wanted modulated signal at 433.92MHz to achieve a Bit Error Rate = 0*01. Figure 6 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver. Wanted signal = 290dBm at 433*92MHz (2kb/. 50% duty cycle), interfering signal = 278dBm at 433*82MHz. (unmodulated). Interference rejection typically equals +12dBm i.e. in-band interfering signal is 12dBm above the wanted signal level at -90dBm. 8. Actual intermediate frequency determined by choice of crystal and external ceramic filter. 9. For temperatures between 85C and 105C the maximum frequency of operation of the VCO local oscillator must be limited to 470MHz. The recommended components to limit the maximum free running frequency of the VCO to less than 470MHz, for an operating supply range of 5V65%, are: Ident D1 C11 C18 L2 Value BB833 6*8pF 10pF 39nH Tolerance 69% 60*1pF 60*1pF 62%
The component values recommended in Tables 5 and 6 are to allow the KESRX05 to operate below VCC = 3V by maintaining the PLL lock voltage at approximately 1*5V (VCC/2) so that the VCO maximum free running frequency can exceed 470MHz. Thus, the recommended VCO component values for D!, C11, C18 and L2 given in Tables 5 and 6 cannot be used at temperatures above 85C. 10.Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error rate of 0*01 where the input signal is a return to zero pulse with an average duty cycle of 50%, 2kb/s data rate. Equivalent to 2109dBm for a 50 input impedance. Does not include the insertion loss of a front end SAW filter at the R F input but does include the IF filter of 50kHz 3dB bandwidth and a data filter bandwidth of 5kHz. The results shown in Figure 20 and in the AC Electrical Characteristics (1) on page 7 are with the simple LC circuit L5//C7 tuned correctly to 10*7MHz. 11. This parameter is not 100% tested by production.
FUNCTIONAL DESCRIPTION Power Down
The PD pin, a tristate input, provides a 2-stage power down for the receiver. The receiver is fully operational when the pin is held high and is fully powered down when the pin is taken to ground as shown in Table 2. Pin 25 PD0 PD1 PD2 Status Low (0V) Receiver powered down VCC/2 Crystal oscillator running High (VCC) Receive mode
Table 2
an antenna or to an input SAW filter with a maximum insertion loss of 3dB. The RF amplifier gain is about 1 3dB at 460MHz when matched into the mixer, while the RF amplifer noise figure is about 4*5dB when fed from a 50 source. The internal RF amplifier feeds a double balanced mixer through an external impedance matching circuit, RFOP to MIXIP. The AGC circuit monitors the mixer signal output level. Control is fed back, applying AGC to the RF amplifier to prevent overloading in the mixer and the generation of unwanted distortion products. This also has the effect of reducing the RSSI characteristic slope and extending its range of operation by more than 20dB at high signal levels (Figure 13). The AGC circuit also applies mixer booster current to improve the linearity of the mixer at high signal levels. This can be confirmed by monitoring the current consumption of the receiver with applied RF signal level (Figure 16). The AGC circuit comes into operation at mixer output signals greater than approximately 225dBm and reduces the RF amplifer gain by 6dB at an input signal level of approximaely 230dBm. Since the AGC operates on the mixer output signal level then the exact point where the AGC comes into opera tion depends on the RF amplifer to mixer matching circuits and RF amplifer gain.
PD0 = Low None of the receiver circuits are functional. Current ICC2, is reduced to its lowest level of ,50A (VCC applied). A longer settling time (t S2) is required to restore full performance after switching to receive mode PD0 to PD2 (Figures 7, 17 and 18). The settling time (time to valid data) of the receiver can be improved by maintaining the oscillation of the crystal in PD0 mode by placing a 200K resistor in parallel with C14. The addition of this resistor will increase the current consumption of the receiver by approximately 20A (see Table 1, pin 23). PD1 = VCC/2 or High-Z source (CMOS tristate) A non-receiving state with some critical circuits running including the crystal oscillator. Current consumption ICC1, is reduced to about 330A. When switching to the receive state, PD1 to PD2 (Figures 7, 17 and 18), data can start to be recovered within 1ms (tS2) for signals close to maximum sensitivity. PD2 = High The receiver is fully functional and ready to receive data.
IF Interface
Unlike KESRX01 there is no internal integrated IF filter. This is to provide a more flexible design and allows the system designer to use a low IF or high IF up to 15MHz. Typically, a 10*7MHz ceramic IF filter connected between IFOUT and IFIN would be used together with an input RF SAW filter to give very good image channel rejection. The
RF Down-Converter
An internal RF amplifier is designed to interface directly to
9
KESRX05
choice of bandwidth for the 10*7MHz ceramic filter depends on frequency tolerancing of the transmitter, receiver, data rate and component cost. The IF filter drive, IFOUT, is a voltage drive with a 300 series resistance (see Table 1, pin 6). This allows impedance matching to the ceramic IF filter to be set by an external series resistor. A 10*7MHz ceramic filter with, typically, a 300 input impedance does not require an external matching resistor at IFOUT. The input to the log amp, IFIN, is high impedance with an internal 3k shunt resistor. Impedance matching to the output of the ceramic filter is achieved by an external shunt resistor R9 between IFIN and IFDC1 (see Table 1, pin 3). 4. Note that the LO level is , 265 dBm, range = 300 to , 500MHz. 5. Vary the value of the PSU input to confirm that there is a corresponding change in LO frequency. Set the PSU at VCC/2. If the VCO does not oscillate at VCC/2, characterise the LO at an alternative voltage. 6. Using a plot of the varactor characteristic determine the varactor capacitance at VCC/2. e.g. for a 2V VCC design the Siemens BB833 capacitance at 1V = 10pF (approx.). 7. Using the following equation deduce the value of the total stray parasitic capacitance CP. 1 CP = ~2p3fLO23L2!2CV
Phase Lock Loop VCO
The local oscillator (LO) is a VCO locked to a crystal reference by a phase lock loop (PLL). The VCO gain is nominally 26MHz/V depending on the external varactor used. The LO frequency is divided by 64 and fed into the phase-frequency detector, where the reference frequency is provided from the crystal oscillator. The AC phase detector output current into the PLL loop filter is nominally 615A. The maximum loop filter bandwidth is 50kHz.
@
#
where CV = varactor capacitance at VCC/2 8. Using the following equation select the nearest value for L2 to centre the VCO at VCC/2. L2 = 1 ~2p3fLO2!3~CP1CV!
VCO Circuit Design and Layout
The Local Oscillator (LO) frequency is controlled by a parallel resonant tuned circuit. The frequency of the local oscillator is controlled by a Phase Locked Loop (PLL), referenced to the crystal frequency. Designing for VCO Track Parasitics To remove the effect of track parasitics the following procedure should be adopted. 1. Open circuit the control feed back from the PLL control loop by removing R1. 2. Connect an external Power Supply Unit (PSU = VCC/ 2) in place of R1, LF output (Figure 3). 3. Using a spectrum analyser, monitor the LO level at the RFIN port. Alternatively use a small pick-up coil to loosely couple to the signal generated across L2.
9. By varying the PSU voltage confirm that the LO is centred correctly at VCC/2, and that the oscillator operates over the range 0V to VCC. 10. Disconnect the PSU and reconnect R1. Measure the value at LF output using a 310 probe and an oscilloscope. This should be a direct voltage with no ripple at VCC/2 (60.3V). If not repeat steps 1 to 8. To compensate for non standard inductor values vary the value of C18 and C11 to vary the capacitance of the varactor to centre the VCC at VCC/2. NOTE: It is important to minimise stray capacitance in the VCO circuit to ensure that the VCO starts oscillating. The use of a varactor with a low capacitance at zero bias is advisable. Similarly, reducing the values of C11 and C18 whilst increasing L2 will help to reduce the capacitance of the varactor at 0V, improving the reliability of the oscillator. A compact design methodology is recommended for the VCO circuit components L2, C11, C18 and D1.
10
KESRX05
KESRX05
19 VCO1
C11
R4
VCO
18 VCO2
L2 C18
D1
CONNECTOR CHARACTERISATION
464
R1 C12 XTAL1
23/24 XTAL1/2
+-
RTEST (=R1)
PSU
PHASE DETECTOR
16 LF
C1
R2
Figure 3 Characterising the VCO/PLL operation
IF Amp/RSSI Detector
This is a log amplifierwith a small signal gain .80dB and an RSSI output used as the detector. The 3dB bandwidth of the IF log amplifier is typically 45MHz to allow for high IFs to be used. However, normally, this wide IF bandwidth would limit the overall sensitivity of the receiver due to the amplified wideband noise generated in the first IF stage. Since the RSSI detector is not frequency selective, any wide band noise introduced after the intermediate filter CF1 will be detected as signal. A simple LC noise reduction filter is therefore positioned part way down the log amplifier to reduce the noise power from the earlier stages. Typically this filter only needs to be a fixed component parallel LC filter (L5 and C7) between pins IFFLT1 and IFFLT2 with a 1 MHz bandwidth (i.e. Q ~10). There are two internal 20k damping resistors across these pins which will determine the Q and the choice of L and C values (AC equivalent circuit = 20k), i.e: L= 23104 2pfIF Q C= 1 (2pfIF)2 L path to remove any DC voltage offsets at the output of the high gain log amplifier, RSSI pin 27. Further improvement in sensitivity can be gained by increasing the Q of the parallel LCfilter, provided that tolerancing of the LC filter is taken into account. For a low IF receiver, ,1 MHz, a low pass filter can be used for both the IF and noise reduction filter. Such a receiver, however, will have virtually no image rejection capability, and will thus have a 3dB penality in noise factor, impairing the ultimate sensitivity of the receiver by a minimum of 3dB. The RSSI output transfer characteristic, at the RSSI pin, has a slope of about 16mV/d B. A typical transfer characteristic from RFIN input to RSSI output is plotted in Figures 14 and 15, measured with a constant wave (n0 modulation RF input signal. This shows the effect of the AGC in extending the range of the detector to .110dBm RF input signal and includes the effect of the AGC circuit adapting to this signal level. Because the RF amplifier AGC has a fast attack time and slow decay time characteristic, the gain of the stage remains constant during the data burst. This means that the change in output for a given extinction ratio also remains constant at approximately 16mV/dB up to peak input signal levels .110dBm. This requires the decay time constant to exceed the transmitted bit period and no long period of zero signal power has been transmitted. Increasing the decay time constant of the AGC circuit by increasing the value of C8 will impair the settling time (time to good data) of the receiver. When duty cycling the
An external damping resistor can be used to lower the Q of the tuned LC circuit. This will alter the gain of the log amplifier, i.e., slope and gradient of Figure 15. The objective of the damping resistor is to prevent mis-tuning of the LC circuit due to component tolerancing and thus degrading the sensitivity of the receiver. The sensitivity results shown in Figures 19 and 20 and in the AC Electrical Characterisics (1) apply with no external damping resistor and the LC circuit correctly tuned to 10*7MHz. The preferred alternative to a damping resistor is to lower the Q of the the inductor L5 or to increase the tolerance of C6. A ceramic resonator or filter is not a recommended here as the external LC filter provides a low impedance DC
11
KESRX05
operation to the receiver between PDO and PD2 to lower power consumption of the receiver. When Duty cycling the receiver between PD1 and PD2 the settling time of the receiver is independent of C8. In the application circuit Figures 25 and 26 the value of C8 is configured for minimum settling time. The times to valid data with C8 = 10nF are shown in Figure 18 for PD0 to PD2 and PD1 to PD2. the data rate or increasing the mark/space ratio will require a corresponding increrase in the value of C10. Figure 6 illustrates a suitable test setupforcharacterising the interference rejection and selectivity of the receiver. Figure 8 illustrates the in-band interference rejection with the anti-jam circuit connected as shown in Figure 10 and bypassed (Figure 11) at VCC = 3V and TAMB = 25C. Note the improvement in interference rejection between the two modes of operation over the wanted signal range of 294 to 0dBm. Note also the 40dB improvement in signal handling capability with the anti- jam circuit connected and the 20dB improvement with the SAW filter removed Figure 9 illustrates the difference in receiver selectivity with the ant-jam circuit connected and bypassed. Note the improvement in receiver selectivity between the two modes of operation over the frequency range 433*92MHz 65kHz and the ability of the anti-jam circuit to improce the selectivity of the SAW filter over the frequency range 433MHz to 434*5MHz. Also note the 20dB improvement in the in-band signal handling capability demonstrated in Figure 8 with the SAW filter not used. This can be used to improve the out-of-band blocking capability of the application without SAW filter (Figure 25); this design option can reduce the overall cost of the receiver by, typically, 1 to 2 US Dollars.The selectivity curve with the anti-jam circuit by-passed is governed by the response of the front end IF ceramic filter, secondary IF filter and data filter. Figures 8 and 8 were recorded with the component specifications given in Table 3. Component specification (Figure 11) R6 C2 L5//C7 Data filter BW IF BW SAW BW/No SAW BW OOK modulation 12k N/A 1MHz at 10*7MHz 5kHz 470kHz 750kHz/1MHz 2kb/s (50% duty cycle)
Anti-jamming Circuit
The output of the RSSI is AC coupled by C10 into the Antijamming circuit where the signal is DC restored on the peak signal level (Figure 10). The coupling capacitor charges to the appropriate DC level, which is related to the final slice level for the data comparator. The antijamming circuit amplifies the peak of the signal to recover the data signal component even in the presence of jamming signals. The interferer causes modulation of the wanted signal at the beat frequency of the two signals and reduces the amplitude of the wanted data component making it more difficult to recover. The action of the antijamming circuit centres the bandwidth of the receiver around the wanted signal proportional to the data filter bandwidth to suppress the interfering beat frequency recovering the wanted signal. Bypassing the anti-jamming circuit (Figure 11) will result in data corruption for interfering RF signal levels 6dB below the wanted signal (Figures 8 and 9). The DC restoration circuit has a fast attack time and slow decay time, both controlled by the value of coupling capacitor chosen between RSSI and DETB pins. Reducing Component specification (Figure 10) R6 C2 L5//C7 Data filter BW IF BW SAW BW/No SAW BW OOK modulation 130k 270pF 1MHz at 10*7MHz 5kHz 470kHz 750kHz/1MHz 2kb/s (50% duty cycle)
Table 3 Component specification for Figures 10 and 11. The values given are changes from those given in Table 5 necessary to obtain the results shown in Figures 8 and 9.
12
KESRX05
Improving Anti-Jamming Performance G Interference rejection (dB) = Interferer (dBm)2Wanted (dBm). The interference rejection of the receiver for different modulation schemes can be improved by:
G
for sensitivity, squelch and optimum interference rejection the slice level can be offset from the internal reference by a high value resistor from the DSN pin to Vee and/or the peak detector output (Figures 25 and 26). The data comparator (slicer) output, DATAOP, is CMOS compatible but is only capable of driving small capacitive loads, ,20pF, depending on data rate. With the anti-jam circuit connected, data output has the inverted sense of the input signal at DF2. To invert the sense of the data output with the anti-jam circuit connected, the buffer transistor circuit shown in Figure 4 can be used.
VCC CIN RBIAS
Changing the value of C2. Increasing the value of C2 may result in pulse stretching of the recovered signal. Adjusting the comparator reference level (DSN) by offsetting the internal reference (Figure 6) by a high value resistor from the DSN pin to VEE and or the peak detector output. (Figures 25 and 26). Reducing the bandwidth of the data fillter, intermediate frequency filter CF1 and/or the noise reduction filter (L5 C7). Thebandwidth of the receiver must accommodate tolerancing of the data, transmitter and receiver. Increasing the value of AGC capacitor C8 to maintain the level of the AGC controi during the off period of the wanted modulation signal. This will improve the interference rejection of the receiver but increase the time to good data from power-up PD0 to PD2. The application circuit Figure 26 has been optimised for time to good data. Changing the value of C10 to allow the anti-jam circuit to detect/recover alternative data modulation schemes such as PWM.
G
G
G
FROM DATAOP
RIN
BUFFERED DATAOP ROUT VEE
Figure 4 G
Data state High Low Data Data
Table 4
Buffered state Low High VEE VCC
Baseband The RSSI output will contain wide band demodulated noise and signals which are within the RF and IF filter pass bands. An additional low pass data filter is therefore used to improve overall sensitivity. KESRX05 has an integrated second-order Sallen and Key data filter whose characteristic is set by R10, R11, C5 and C6. Figure 10 showsthe connections and calculation for the 23dB cut-off frequency and filter type. The cut-off frequency is determined from the data rate and the level of pulse distortion which can be tolerated. The data filter cut off frequency is usually set at 3 to 5 times the minimum pulse width period, i.e: 1 fC = 53 Data pulse width The output from this filter, DF2, is directly coupled into the inverting input of the data comparator with a fixed slice level applied to the non-inverting input, DSN. A peak detector recovers the signal amplitude on the capacitor. Normally, the comparator reference level used is the internal reference, a capacitor at Pin DSN serving to remove noise pick-up. In order to fine tune the slice level
NOTE Buffered DATAOP will squelch low if the input data signal remains continuously in a high or low state. The time taken for the buffered data output to squelch low is governed by the time constant CINRIN. The output drive current is nominally 650A so that a system using high data rates or higher capacitive loads, e.g. Iong track lengths, may need to incorporate a buffer transistor to provide the necessary edge speeds to the following logic circuits.The comparator has 20mV hysteresis built-in to reduce edge chatter. The sense of the squelch on the data output is low when no signal is present. This may be confusing, as a low output during the data burst also corresponds to the on period, i.e. the MARK, of the RF OOK signal. However, it is the very first pulse of the data signal which causes the DC restoration capacitor of the anti-jamming circuit to charge to the correct level appropriate to the final slice level. As a consequence of this the very first pulse of the data transmission may be lost as the receiver adapts to the incoming signal level.
13
KESRX05
RFOP
9
MIXIP
8
VCCRF
7
IFOUT IFIN
6 2
IFDC1 IFFLT2 IFFLT1 IFDC2
1 28 4 2
RSSI DETB
27 26
DF0 DF1
22 21
DF2
20 13
PEAK
PEAK DET ANTI-JAM AGC
12
DATA FILTER DATA SLICER 100k
14
DATAOP
AGC 464
LOG AMP PHASE/ FREQUENCY DETECTOR REFERENCE CRYSTAL OSCILLATOR
25 5 17 16 23 24
15
DSN
RFIN
11
LNA
VCO
+ -
VREF
10
18
19
VEERF
VCO2
VCO1
PD
VCC
VEE
LF
XTAL2
XTAL1
Figure 5 Block schematic of KESRX05
VARIABLE DELAY LINE
4kb/s 50% DUTY CYCLE OOK INPUT BUFFER AMPLIFIER WANTED SIGNAL 433*92MHz RX CLK
PULSE GENERATOR
SIGNAL GENERATOR 1
KESRX05 PCB
RF NC NC RFIN GND GND VCC DATA PD NC
BIT ERROR RATE ANALYSER
TRIGGER
SIGNAL GENERATOR 2
INTERFERING SIGNAL 433*82MHz
RFIN HYBRID COMBINER
DC PSU 3V TO 6V
DATA O/P
OSCILLOSCOPE
NOTES 1. Variable delay line used to equalise the propagation delay of the receiver. 2. Buffer amplifier used to drive the low input impedance of the Bit Error Rate analyser. 3. High impedance (310) oscilloscope probe recommended.
Figure 6 Characterising selectivity and interference rejection
KESRX05 PCB
RF NC NC RFIN GND GND VCC DATA PD NC
PLL
SPECTRUM ANALYSER OSCILLOSCOPE 1 6470kHz
POWER DOWN TRIGGER
t
DC PSU 3V TO 6V
POWER DOWN SWITCH (SEE TABLE 2, PAGE 9) NC
NOTES 1. High impedance (310) oscilloscope probe recommended. 2. Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement. 3. Time taken for PLL to achieve 90% of final voltage within 6470kHz of final frequency (423*33MHz). 4. Spectrum analyser set to PLL lock frequency (423*33MHz), zero span 470kHz IF bandwidth, tSWEEP 20ms.
Figure 7 Characterising the PLL acquisition time from power-up
14
KESRX05
20
INTERFERENCE REJECTION RATIO (dB)
10
NO SAW SAW ANTI-JAM CIRCUIT CONNECTED
0
ANTI-JAM 40dB IMPROVEMENT NO SAW 40dB IMPROVEMENT
210
NO SAW SAW ANTI-JAM CIRCUIT BYPASSED
220
230 240 2100
290
280
270
260
250
240
230
220
210
0
NOTE Unmodulated interfering signal is 100kHz low side from wanted signal. Both signals are within the passband of the receiver (ceramic filter) i.e. Wanted signal = 433*92 MHz at 2kb/s, 290 to 0dBm (50% duty cycle) Interfering signal = 433*82MHz continuous carrier, 290 to 0dBm
WANTED SIGNAL LEVEL (dBm)
Figure 8 In-band interference rejection of the receiver
100
SAW NO SAW
80
ANTI-JAM CONNECTED
ANTI-JAM CONNECTED ANTI-JAM BYPASSED
60
SELECTIVITY (dB)
ANTI-JAM BYPASSED 40
20
0
220
431 431*5 432 432*5 433 433*5 434 434*5 435 435*5 436 FREQUENCY (MHz) NOTE The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433*92 MHz, 20kb/s, 50% duty cycle, 290dBm Also notice the ability of the receiver to achieve the same selectivity performance over the frequency range 433 to 434.5 MHz with and wthout a SAW filter.
Figure 9 KESRX05 selectivity response
15
KESRX05
C5 L5 C7 IFIN
3
R10 C10 RSSI
28 27
R11 C6
C2 DETB
26
IFLT1
1
IFLT2
DF0
22
DF1
21
DF2
20 13
100k RSSI O/P ANTI-JAM CIRCUIT
PEAK
AMP A
AMP B
AMP C
14
DATAOP DSN
REF
SALLEN-KEY DATA FILTER
SLICER
15
KESRX05
100k INTERNAL REFERENCE VOLTAGE
Figure 10 Anti-jam circuit and data filter. Component idents refer to Figure 25, Figure 26 and Table 5.
Sallen and Key Filter Components Cut-off frequency = fC, therefore vC = 2pfCY 2Q C5 = RvC 1 C6 = 2QRvC
Example To implement a filter response with a 10kHz 3dB cutoff frequency and with R10 = R11 = 100k, Bessel filter: Butterworth filter:
C5
where, for a Bessel response, Q = 0*557 and Y = 1*732 and, for a Butterworth response, Q = 0*71 and Y = 1*0.
C5 = 106pF, C6 = 80pF C5 = 150pF, C6 = 150pF
L5 C7 IFIN
3
C10
R10
R11 C6
IFLT1
1
IFLT2
28
RSSI
27
DETB
26
DF0
22
DF1
21
DF2
20 13
100k RSSI O/P ANTI-JAM CIRCUIT
PEAK C6
AMP A
AMP B
AMP C
14
DATAOP
R6
REF
SALLEN-KEY DATA FILTER
SLICER
15
DSN
KESRX05
100k INTERNAL REFERENCE VOLTAGE
Figure 11 Bypassing the anti-jam circuit (use component revisions recommended in Table 3)
16
KESRX05
SIGNAL GENERATOR 2
10*7 MHz
250 100n REMOVE IF FILTER BEFORE CONNECTING
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
IFIN SPECTRUM ANALYSER
FET PROBE
RSSI
OSCILLOSCOPE 1
V
AGC
KESRX05
IFOUT
RF NC NC RFIN GND
KESRX05 PCB
VCC DATA PD NC
GND
SIGNAL GENERATOR 1
433*92MHz
A DC PSU 3V TO 6V
NOTES 1. The 250 resistor added to the output of signal generator 2 modifies its characteristic impedance to mimic the output of the ceramic filter. 2. The 100nF capacitor brevents de-biasing of IFIN/
Figure 12 Characterising the receiver performance (Figures 13 to 16)
The characteristics shown in Figures 13 to 24 are typical results measured from a a limited sample of production devices (see notes on page 19)
30 25
CONVERSION GAIN (dB)
20 15
AT VCC = 3V and 6V
10 5 0
25
210 215 2100 290 280 270 260 250 240 230 220 210
0 10
RFIN UNMODULATED CARRIER AT 433*92MHz (dBm)
Figure 13 RFIN to IFOUT conversion gain (see RF Down-Converter, page 9)
17
KESRX05
1*8
1*4
RSSI VOLTAGE, PIN 27 (V)
1*2
1
VCC = 3V VCC = 6V
0*8 0*6
0*4 0*2
2100
280
260
240
220
28
24
0
4
8
RFIN UNMODULATED AT 433*92MHz (dBm)
Figure 14 RFIN to RSSI output transfer characteristic (see IF Amp/RSSI Detector, page 11)
1*60
1*40
RSSI VOLTAGE, PIN 27 (V)
1*20
1*0
VCC = 3V VCC = 6V
0*80
0*60
0*40
0*40
2100
280
260
240
220
28
24
0
4
8
IFIN UNMODULATED CARRIER AT 10*7MHz (dBm)
Figure 15 IFIN to RSSI output transfer characteristic (see IF Amp/RSSI Detector, page 11)
18
KESRX05
7*0
CURRENT CONSUMPTION, ICC (mA)
6*5
6*0
VCC = 3V VCC = 6V
5*5
5*0 4*5
4*0 3*5
2100
280
260
240
220
0
20
RFIN UNMODULATED CARRIER AT 433*92MHz (dBm)
Figure 16 Receiver current consumption v. received signal strength RFIN (see RF Down-converter, page 9)
NOTES 1. Conversion gain of the receiver is limited by the insertion loss of the front end SAW filter. 2. Dynamic range of the RSSI output transfer characteristic (Figure 14) is governed by the noise figure of the receiver, which is limited by the insertion loss of the front end SAW filter and the bandwidth of the 10*7MHz ceramic filter. 3. Reduction in conversion gain and increase in receiver current consumption coincides with lift-off of the AGC control line (pin 12). Action of the AGC applies additional mixer booster current to improve the linearity of the mixer at high signal levels.
6
PD0 TTVD MAX PD0 TTVD TYP PD0 TTVD MIN
5
TIME TO VALID DATA AT 2 kb/s (ms)
4
3
PD1 TTVD MAX PD1 TTVD TYP PD1 TTVD MIN
2
1
0
240
0
NOTE Time to valid data of PD0 to PD2 can be improved by maintaining the crystal oscillator in PD0 mode (see Power Down, page 9 and Table 1, pin 23.)
25 85 TEMPERATURE (C)
105
110
Figure 17 PD0 to PD2 and PD1 to PD2 time to valid data (see Power Down, page 9)
19
KESRX05
LF VOLTAGE ACHIEVING 90% OF FINAL VALUE (ms)
6
5
PD0 LF LOCK MAX PD0 LF LOCK TYP PD0 LF LOCK MIN
4
3
2
PD2 LF LOCK MAX PD2 LF LOCK TYP PD2 LF LOCK MIN
1
0
240
0
NOTE Time to PLL acquisition of PD0 to PD2 can be improved by maintaining the crystal oscillator in PD0 mode (see Power Down, page 9 and Table 1, pin 23).
25 85 TEMPERATURE (C)
105
110
Figure 18 PD0 to PD2 and PD1 to PD2 time to PLL acquisition (tS1 and tS2, AC Electrical Characteristics (1), page 7)
2103 2103*5
SENSITIVIY AT 433*92MHz (dBm)
2104 2104*5 2105 2105*5 2106 2106*5 2107 240
25 85 OPERATING TEMPERATURE (C) 110
MAX SENSITIVITY TYP SENSITIVITY MIN SENSITIVITY
Figure 19 Receiver sensitivity v. temperature at VCC = 5V (VIN, AC Electrical Characteristics (1), page 7)
20
KESRX05
6
5
DATA OUTPUT VOLTAGE (V)
4
DATAOP VOH MAX DATAOP VOH TYP DATAOP VOH MIN
3
2
1
DATAOP VOL MAX DATAOP VOL TYP DATAOP VOL MIN
0
240
0
25 85 TEMPERATURE (C)
105
110
Figure 20 DATAOP I/O voltage drive at 620A (VOH/VOH, AC Electrical Characteristics (1), page 7)
80 60 40
DATAOP IOH MAX DATAOP IOH TYP DATAOP IOH MIN
CURRENT DRIVE (A)
20
0
220 240 260 280 240
0 25 85 TEMPERATURE (C) 105 110
DATAOP IOL MAX DATAOP IOL TYP DATAOP IOL MIN
Figure 21 DATAOP I/O current drive at 620A (see Baseband, page 13)
21
KESRX05
30 29*5
CURRENT CONSUMPTION, ICC2 (A)
29 28*5 28
ICC2 2MAX ICC2 TYP ICC2 MIN
27*5 27 26*5 26
240
0
25 85 TEMPERATURE (C)
105
110
Figure 22 Receiver current consumption in PD0 mode, DC Electrical Characteristics, page 7
360 355 350 345 340
ICC1 MAX ICC1 TYP ICC1 MIN
CURRENT CONSUMPTION, ICC1 (A)
335 330 225
240
0
25 85 TEMPERATURE (C)
105
110
Figure 23 Receiver current consumption in PD1 mode, DC Electrical Characteristics, page 7
22
KESRX05
4*2 4*1
CURRENT CONSUMPTION, ICC (mA)
4 3*9 3*8
ICC MAX ICC TYP ICC MIN
3*7 3*6 3*5 3*4
240
0
25 85 TEMPERATURE (C)
105
110
Figure 24 Receiver current consumption in PD2 mode, DC Electrical Characteristics, page 7
23
KESRX05
C7 L6 VCC C25 C26 R9 C3
1 2 3 4
KESRX05
IFFLT1 IFDC1 IFIN IFDC2 VCC IFOUT VCCRF MIXIP RFOP VEERF RFIN AGC PEAK DATAOP IFFLT2 RSSI DETB PD XTAL1 XTAL2 DF0 DF1 DF2 VCO1 VCO2 VEE LF DSN
28 27 26 25 24 23 22 21 20 19 18 17 16 15
C10 PD C23 XTAL1 R10 C2 C5 L2 C11 D1 C18 R1 C1 R2 R4 C12 R11 C6 C15
C4
3
VCC
5 6
C14 C13
CF1
O/P GND 2 I/P
1
VCC C28 C29 L1 C9
7 8 9 10
C21 RF IN C19 C8
L3
11 12 13
R7 DATA C22 R6
14
Figure 25 Application circuit diagram for KESRX05 with NO SAW filter
C7 L6 VCC C25 C26 R9 C3
1 2 3 4
KESRX05
IFFLT1 IFDC1 IFIN IFDC2 VCC IFOUT VCCRF MIXIP RFOP VEERF RFIN AGC PEAK DATAOP IFFLT2 RSSI DETB PD XTAL1 XTAL2 DF0 DF1 DF2 VCO1 VCO2 VEE LF DSN
28 27 26 25 24 23 22 21 20 19 18 17 16 15
C10 PD C23 XTAL1 R10 C2 C5 L2 C11 D1 C18 R1 C1 R2 R4 C12 R11 C6 C15
CF1
3 O/P GND 2 I/P 1
C4
VCC
5 6
C14 C13
VCC C28
8 GND I/P GND I/P GND 3
7
C29 L1
7 GND O/P GND O/P GND 4 6 5
8
C9
9 10
BS3550
1
L4 RF IN C19
2
L3
11 12
C8 R7
13 14
DATA C22 R6
Figure 26 Application circuit diagram for KESRX05 with SAW filter
24
KESRX05
Ident C1 C2 C3 C4 C5 C6 C7 (1) C8 C9 C10 C11 (1) C12 C13 C14 C15 C18 (1) C19 (2) C21 (3) C22 C23 C25 C26 C28 C29 R1 R2 R4 R6 R7 R9 (1) R10 R11 D1 CF1 (1) SAWF L1 (2) L2 (2) L3 (2, 3) L3 (1,3) L4 (2,4) L5 (1) XTAL1 (2) KESRX05
Value 150ph 270pF 10nF 10nF 270pF 270pF 47pF 10nF 56pF 1F 12pF 1*5nF 18pF 18pF 100pF 12pF 2pF 220pF 1F 100pF 100pF 1F 1F 100pF 4.7k 10k 4.7k 100k 100k 360 100k 100k BB833 SFE10.7MA26 B3550 39nH 27nH 68nH 100nH 33nH 4.7H 6*61281MHz
Part No./tolerance GRM39C0G151J GRM39C0G271J GRM39X7R103K GRM39X7R103K GRM39SL271J GRM39SL271J GRM39COG470G GRM39Y5V103K GRM39COG560J GRM40Y5V105Z GRM39COG120J GRM39X7R152K GRM39COG180J G RM39COG180J GRM39COG101J GRM39COG120J GRM39COG2R0C GRM39COG221J GRM40Y5V105Z GRM39COG101J GRM39COG101J GRM40Y5V105Z GRM40Y5V105Z GRM39COG101J N/A N/A N/A N/A N/A N/A N/A N/A 4 to 10pF 3dB BW = 230kHz 3dB BW = 230kHz LL2012-F39NJ LL2012-F27NJ LL2012-F68NJ LL1608-FHR10J LL2012-F33NJ FLU25204R7J 6100 PPM
Supplier Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Rohm Rohm Rohm Rohm Rohm Rohm Rohm Rohm Siemens Murata TOKO TOKO TOKO TOKO TOKO TOKO TOKO Kinseki / Quartz Tek Mitel Semiconductor
Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0805 0805 0603 0603 0603 0603 0805 0603 0603 0603 0603 SOD323 Radial 5mm2 2012 2012 1608 1608 2021 2520 HC49/4H QP28
Table 5 Components for Figures 25 and 26
NOTES 1. Adjust for alternative IF/ceramic filter. 2. Adjust for alternative centre frequency. 3. Without SAW filter (Figure 25). 4. With SAW filter (Figure 26).
25
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