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(R)
FAST CMOS PARITY BUS TRANSCEIVER
DESCRIPTION:
IDT54/74FCT833A IDT54/74FCT833B
Integrated Device Technology, Inc.
FEATURES:
* Equivalent to AMD's Am29833 bipolar parity bus transceiver in pinout/function, speed and output drive over full temperature and voltage supply extremes * High-speed bidirectional bus transceiver for processororganized devices * IDT54/74FCT833A equivalent to Am29833A speed and output drive * IDT54/74FCT833B 30% faster than Am29833A * Buffered direction and three-state controls * Error flag with open-drain output * IOL = 48mA (commercial) and 32mA (military) * TTL input and output level compatible * CMOS output level compatible * Substantially lower input current levels than AMD's bipolar Am29800 series (5A max.) * Available in plastic DIP, CERDIP, LCC and SOIC * Product available in Radiation Tolerant and Radiation Enhanced versions * Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT833s are high-performance bus transceivers designed for two-way communications. They each contain an 8-bit data path from the R (port) to the T (port), an 8-bit data path from the T (port) to the R (port), and a 9-bit parity checker/generator. The error flag can be clocked and stored in a register and read at the ERR output. The clear (CLR) input is used to clear the error flag register. The output enables OET and OER are used to force the port outputs to the high-impedance state so that the device can drive bus lines directly. In addition, OER and OET can be used to force a parity error by enabling both lines simultaneously. This transmission of inverted parity gives the designer more system diagnostic capability. The devices are specified at 48mA and 32mA output sink current over the commercial and military temperature ranges, respectively.
FUNCTIONAL BLOCK DIAGRAM
RI
8 8
TI
PARITY OET OER
8 8
S
MUX
9
9-BIT PARITY TREE D P CLK CP CLR
2557 drw 01
Q Q
ERR
CLR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1992 Integrated Device Technology, Inc.
MAY 1992
DSC-4621/2
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OER R0 R1 R2 R3 R4 R5 R6 R7 ERR CLR GND
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22
P24-1, D24-1, S024-2 & E24-1
21 20 19 18 17 16 15 14 13
ERR CLR GND NC CLK OE T PARITY
Vcc T0 T1 T2 T3 T4 T5 T6 T7 PARITY OET CLK
INDEX
R2 R3 R4 NC R5 R6 R7
R1 R0 OER NC Vcc T0 T1
4 5 6 7 8 9 10 32 1 28 27 26 25 24 23 22 21 20
L28-1
11 19 12 13 14 15 16 17 18
T2 T3 T4 NC T5 T6 T7
2557 drw 02
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
PIN DESCRIPTION
Pin Name I/O I I/O O Description RECEIVE enable input. 8-bit RECEIVE data input/output. Output from fault registers. Register detection of odd parity fault on rising clock edge (CLK). A registered ERR output remains LOW until cleared. Open drain output, requires pull up resistor. Clears the fault register output. 8-bit TRANSMIT data input/output. 1-bit PARITY output. TRANSMIT enable input. External clock pulse input for fault register flag.
2557 tbl 01
ERROR FLAG OUTPUT FUNCTION TABLE(1,2)
OER
RI
CLR
H H H L
Inputs CLK --
Internal Output To Device Pre-State Point "P" H -- L --
ERR ERRn-1
H L -- --
Output
ERR
H L L H
Function Sample (1's Capture) Clear
2557 tbl 02
ERR
CLR
TI PARITY
I I/O I/O I I
OET
CLK
NOTES: 1. OET is HIGH and OER is LOW. 2. H = HIGH L = LOW = LOW-to-HIGH transition of clock - = Don't Care or Irrelevant
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(2)
Inputs Outputs TI Incl Parity CLK -- H or L -- RI ( or H's) H (Odd) H (Even) L (Odd) L (Even) NA NA NA NA -- -- -- H or L (Odd) H or L (Even) H (Odd) H (Even) L (Odd) L (Even) ( of H's) NA NA NA NA H (Odd) H (Even) L (Odd) L (Even) -- -- -- -- -- NA NA NA NA RI NA NA NA NA H H L L NA Z Z Z Z NA NA NA NA TI H H L L NA NA NA NA NA Z Z Z Z H H L L Parity L H L H NA NA NA NA NA Z Z Z Z H L H L
OE OET
L L L L H H H H -- H H H H L L L L
OE OER
H H H H L L L L -- H H H H L L L L
CLR
H H H H H H H H L H L H H H H H H
ERR(1)
H L H L H L H L H * H H L L H L H
Function Transmit data from R Port to T Port with parity; receiving path is disabled. Receive data from T Port to R Port with parity test resulting in flag: transmitting path is disabled. Clear the state of error flag register. Both transmitting and receiving paths are disabled. Parity logic defaults to transmit mode. Forced-error checking.
NOTES: 1. Output state assumes HIGH output pre-state. 2. H = HIGH L = LOW = LOW-to-HIGH transition of clock *No change to stored Error State
2557 tbl 03
Z= NA = -=
High Impedance Not Applicable Don't Care or Irrelevant
Odd = Even = I =
Odd number of logic one's Even number of logic one's 0, 1, 2, 3, 4, 5, 6, 7
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
(2)
CAPACITANCE (TA = +25C, f = 1.0MHz)
Military Unit V Symbol Parameter(1) CIN CI/O Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
tbl 05
Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Commercial -0.5 to +7.0
-0.5 to +7.0
VTERM(3)
-0.5 to VCC
-0.5 to VCC
V
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 0.5 120
-55 to +125 -65 to +135 -65 to +150 0.5 120
C C C W mA
NOTE: 2557 1. This parameter is guaranteed by characterization but not tested.
NOTES: 2557 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Inputs and VCC terminals. 3. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IIH IIL VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Except I/O Pins) Input LOW Current (Except I/O Pins) Input HIGH Current (I/O Pins Only) Input LOW Current (I/O Pins Only) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage (Except ERR) Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI =VCC VI = 2.7V VI = 0.5V VI = GND VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND Vcc = Min., IN = -18mA Vcc = Max.(3), VO = GND Vcc = 3V, VIN = VLC or VHC, IOH = -32A Vcc = Min. IOH = -300A IOH = -15mA MIL. VIN = VIH or VIL IOH = -24mA COM'L. Vcc = 3V, VIN = VLC or VHC, IOL = 300A Vcc = Min. Except IOL = 300A VIN = VIH ERR IOL = 32 mA MIL. IOL = 48mA COM'L. or VIL ERR IOL = 48mA Min. 2.0 -- -- -- -- -- -- -- -- -- -- -60 VHC VHC 2.4 2.4 -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 15 15(4) -15(4) -15 -1.2 -- -- -- -- -- VLC VLC(4) 0.5 0.5 0.5 Unit V V A
A
V mA V
VOL
Output LOW Voltage
V
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested.
2557 tbl 06
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Outputs Open Test Conditions(1) Vcc = Max.; VIN VHC, VIN VLC Vcc = Max. VIN = 3.4V(3) Vcc = Max. VIN VHC VIN VLC OET = OER = GND One Input Toggling 50% Duty Cycle Vcc = Max. VIN VHC Outputs Open VIN VLC fCP = 10MHz (FCT) 50% Duty Cycle OET = GND VIN = 3.4V OER = VCC VIN = GND fi = 2.5MHz One Bit Toggling Vcc = Max. VIN VHC Outputs Open VIN VLC fCP = 10MHz (FCT) 50% Duty Cycle OET = GND VIN = 3.4V fi = 2.5MHz VIN = GND OER = VCC Eight Bits Toggling Min. -- -- -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2.0 0.25 Unit mA mA mA/ MHz
IC
Total Power Supply Current(6)
--
1.4
3.4
mA
--
1.9
5.4
--
4.0
7.8(5)
--
6.2
16.8(5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2557 tbl 07
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT833A Com'l. Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tREM tW tW tPHL tPLH tPLH tPHL Parameter Propagation Delay RI to TI, TI to RI Propagation Delay RI to PARITY Output Enable Time Conditions(1) CL = 50pF CL = 300pF(3) CL = 50pF CL = 300pF CL = 50pF CL = 300pF
(3) (3)
IDT54/74FCT833B Com'l. Max. 14.0 21.5 20.0 27.5 16.0 23.5 14.7 16.0 -- -- -- -- -- 16.0 20.0 20.0 27.5 Min.(2) -- -- -- -- -- -- -- -- 8.5 0 10.5 5.5 5.5 -- -- -- -- Max. 7.0 14.5 10.5 18.0 8.5 16.0 7.2 8.5 -- -- -- -- -- 8.5 15.0 10.5 18.0 Mil. Min.(2) -- -- -- -- -- -- -- -- 11.0 0 14.0 7.0 7.0 -- -- -- -- Max. 10.0 17.5 14.0 21.5 11.0 18.5 9.8 11.0 -- -- -- -- -- 11.0 18.0 14.0 21.5
2557 tbl 08
Mil. Min.(2) -- -- -- -- -- -- -- -- 16.0 0 20.0 9.5 9.5 -- -- -- --
Min.(2) -- -- -- -- -- -- -- -- 12.0 0 15.0 7.0 7.0 -- --
Max. 10.0 17.5 15.0 22.5 12.0 19.5 10.7 12.0 -- -- -- -- -- 12.0 16.0 15.0 22.5
Unit ns
ns
ns
OER, OET to RI, TI OER, OET to RI, TI
TI, PARITY to CLK Set-up Time TI, PARITY to CLK Hold Time Clear Recovery Time CLR to CLK Clock Pulse Width HIGH or LOW Clear Pulse Width LOW Propagation Delay CLK to ERR Propagation Delay CLR to ERR Propagation Delay
Output Disable Time CL = 5pF(3) CL = 50pF CL = 50pF
ns
ns ns ns ns ns ns ns ns
CL = 50pF CL = 300pF
(3)
-- --
OER to PARITY
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested.
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 V OUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: 2557 tbl 09 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM 3V 1.5V 0V 3V 1.5V 0V tH 3V 1.5V 0V 3V 1.5V 0V
PULSE WIDTH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
t SU
tH
PROPAGATION DELAY
3V 1.5V tPLH OUTPUT t PLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V t PHL 0V VOH 1.5V VOL
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V t PHZ 0.3V 1.5V 0V V OH 0V t PLZ DISABLE 3V 1.5V 0V 3.5V V OL
SAME PHASE INPUT TRANSITION
NOTES 2557 drw 04 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXX Temperature Range FCT X Device Type X Package X Process/ Temperature Range Blank B P D L SO E 833A 833B 54 75 Commercial (0C to +70C) Military (-55C to +125) Compliant to MIL-STD-883, Class B Plastic DIP CERDIP Leadless Chip Carrier Small Outline IC CERPACK Non-inverting Parity Bus Transceiver Fast Non-inverting Parity Bus Transceiver -55C to +125C 0C to +70C
2557 drw 03
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