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GS71116TP/J/U SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features * Fast access time: 10, 12, 15ns * CMOS low power operation: 100/85/70 mA at min. cycle time. * Single 3.3V 0.3V power supply * All inputs and outputs are TTL compatible * Byte control * Fully static operation * Industrial Temperature Option: -40 to 85C * Package line up J: 400mil, 44 pin SOJ package TP: 400mil, 44 pin TSOP Type II package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package 64K x 16 1Mb Asynchronous SRAM SOJ 64K x 16 Pin Configuration A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 10, 12, 15ns 3.3V VDD Center VDD & VSS Top view 44 pin SOJ Description The GS71116 is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS71116 is available in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ and 400 mil TSOP Type-II packages. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC Pin Descriptions Symbol A0 to A15 DQ1 to DQ16 CE LB UB WE OE VDD VSS NC Description Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3V power supply Ground No connect Fine Pitch BGA 64K x 16 Bump Configuration 1 2 3 4 5 6 A B C D E F G H LB DQ16 OE UB A0 A3 A5 NC NC A8 A10 A13 A1 A4 A6 A7 NC A9 A11 A14 A2 CE DQ2 DQ4 DQ5 DQ7 WE A15 NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC DQ14 DQ15 VSS VDD DQ13 DQ12 DQ11 DQ10 DQ9 NC NC A12 6mm x 8mm, 0.75mm Bump Pitch Top View Rev: 1.06 6/2000 1/15 (c) 1999, Giga Semiconductor, Inc. M Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U TSOP-II 64K x 16 Pin Configuration A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC Top view 44 pin TSOP II Block Diagram A0 Address Input Buffer Row Decoder Memory Array A15 CE WE Control OE _____ UB LB _____ Column Decoder I/O Buffer DQ1 DQ16 Rev: 1.06 6/2000 2/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Truth Table CE H OE X WE X LB X L UB X L H L L H L X H DQ1 to DQ8 Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z DQ9 to DQ16 Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z VDD Current ISB1, ISB2 L L H L H L L X L L H IDD L L H X H X X H Note: X: "H" or "L" Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature Symbol VDD VIN VOUT PD TSTG Rating -0.5 to +4.6 -0.5 to VDD+0.5 ( 4.6V max.) -0.5 to VDD+0.5 ( 4.6V max.) 0.7 -55 to 150 Unit V V V W oC Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Rev: 1.06 6/2000 3/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Recommended Operating Conditions Parameter Supply Voltage for -12/15 Supply Voltage for -10 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Symbol VDD VDD VIH VIL TAc TAI Min 3.0 3.135 2.0 -0.3 0 -40 Typ 3.3 3.3 - Max 3.6 3.6 VDD+0.3 0.8 70 85 Unit V V V V o C C o Note: 1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns. 2. Input undershoot voltage should be greater than -2V and not exceed 20ns. Capacitance Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN=0V VOUT=0V Max 5 7 Unit pF pF Notes: 1. Tested at TA=25C, f=1MHz 2. These parameters are sampled and are not 100% tested DC I/O Pin Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol IIL ILO VOH VOL Test Conditions VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = - 4mA ILO = + 4mA Min -1uA -1uA 2.4 Max 1uA 1uA 0.4V Rev: 1.06 6/2000 4/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Power Supply Currents 0 to 70C Parameter Symbol Test Conditions 10ns Operating Supply Current CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2V All other inputs VDD - 0.2V or 0.2V -40 to 85C 15ns 10ns 12ns 15ns 12ns IDD (max) 100mA 85mA 70mA 115mA 100mA 85mA Standby Current ISB1 (max) 45mA 40mA 35mA 50mA 45mA 40mA Standby Current ISB2 (max) 10mA 15mA Rev: 1.06 6/2000 5/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U AC Test Conditions Parameter Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load Conditions VIH=2.4V VIL=0.4V tr=1V/ns tf=1V/ns 1.4V 1.4V Fig. 1& 2 Output Load 1 DQ 50 VT=1.4V 30pF1 Output Load 2 3.3V DQ 5pF1 589 434 Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. Rev: 1.06 6/2000 6/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Byte disable to output in High Z (UB, LB) * These parameters are sampled and are not 100% tested Symbol tRC tAA tAC tAB tOE tOH tLZ* tOLZ* tBLZ* tHZ* tOHZ* tBHZ* -10 Min 10 --------3 3 0 0 ------- -12 Max --10 10 4 4 --------5 4 3.5 -15 Max --12 12 5 5 --------6 5 3.5 Min 12 --------3 3 0 0 ------- Min 15 --------3 3 0 0 ------- Max --15 15 6 6 --------7 6 4 Unit ns ns ns ns ns ns ns ns ns ns ns --- Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL tRC Address tAA tOH Data Out Previous Data Data valid Rev: 1.06 6/2000 7/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Read Cycle 2: WE = VIH tRC Address tAA CE tAC tLZ UB, LB OE tBLZ tOE Data Out tOLZ High impedance tAB tBHZ tOHZ Data valid tHZ Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z * These parameters are sampled and are not 100% tested Symbol tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -10 Min 10 7 7 7 5 0 7 0 0 0 3 --- -12 Max ----------------------4 -15 Max ----------------------5 Min 12 8 8 8 6 0 8 0 0 0 3 --- Min 15 10 10 10 7 0 10 0 0 0 3 --- Max ----------------------6 Unit ns ns ns ns ns ns ns ns ns ns ns ns Rev: 1.06 6/2000 8/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Write Cycle 1: WE control tWC Address tAW OE tCW CE tBW UB, LB tAS WE tDW Data In tWHZ Data Out tDH Data valid tWLZ High impedance tWP tWR Write Cycle 2: CE control tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1 High impedance Rev: 1.06 6/2000 9/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Write Cycle 3: UB, LB control tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1 High impedance Rev: 1.06 6/2000 10/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U 44 Pin, 400 mil SOJ Symbol A A1 A2 HE GE E B B1 1 e 22 A D 44 23 L c Dimension in inch min nom max 0.025 0.018 0.008 0.148 - Dimension in mm min nom max 0.635 2.667 0.660 28.44 9.144 2.083 0o 2.794 0.457 0.711 0.203 28.58 1.27 9.398 2.210 3.759 2.921 0.813 28.70 9.652 2.70 0.102 7o 0.105 0.110 0.115 0.026 0.028 0.032 1.120 1.125 1.130 0.05 - c D E e 0.395 0.400 0.405 10.033 10.160 10.287 0.435 0.440 0.445 11.049 11.176 11.303 0.360 0.370 0.380 0.082 0.087 0.106 0o 0.004 7o A A2 A1 y B B1 Detail A HE Q GE L y Q Note: 1. Dimension D& E do not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion Rev: 1.06 6/2000 11/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U 44 Pin, 400 mil TSOP-II Dimension in inch Dimension in mm Symbol min nom max min nom max A A1 HE A 44 D 23 c 0.002 0.01 - - 0.047 - 0.05 0.95 0.25 - 1.00 0.35 0.15 1.20 1.05 0.45 - E A2 B c D E e HE L 0.037 0.039 0.041 0.014 0.018 0.006 - 1 A2 e 22 B 0.721 0.725 0.729 18.31 18.41 18.51 0.396 0.400 0.404 10.06 10.16 10.26 0.031 0.40 0 o 0.80 0.50 0.80 - 0.60 0.10 5o A 0.455 0.463 0.471 11.56 11.76 11.96 0.016 0.020 0.024 0 o A1 y L1 L L1 y Q 0.031 - 0.004 5 o Detail A Q Note: 1. Dimension D& E do not include interlead flash 2. Dimension B does not include dambar protrusion / intrusion 3. Controlling dimension: mm Rev: 1.06 6/2000 12/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U 6mm x 8mm Fine Pitch BGA 8.00 0.10 6.00 0.10 0.22 0.05 3 2 1 6 0.75(typ). 13/15 (c) 1999, Giga Semiconductor, Inc. Top View 1.20(max) pin A1 index Bottom View pin A1 index 5 4 Rev: 1.06 6/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Ball Dia. 0.35 Pitch 0.75 3.75 5.25 0.36(typ) 0.10 G C D H A B E F D units: mm GS71116TP/J/U Ordering Information Part Number* GS71116TP-10 GS71116TP-12 GS71116TP-15 GS71116TP-10I GS71116TP-12I GS71116TP-15I GS71116J-10 GS71116J-12 GS71116J-15 GS71116J-10I GS71116J-12I GS71116J-15I GS71116U-10 GS71116U-12 GS71116U-15 GS71116U-10I GS71116U-12I GS71116U-15I * Package 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Access Time 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns Temp. Range Commercial Commercial Commercial Industrial Industrial Industrial Commercial Commercial Commercial Industrial Industrial Industrial Commercial Commercial Commercial Industrial Industrial Industrial Status Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example: GS71116TP-10T Rev: 1.06 6/2000 14/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71116TP/J/U Revision History Rev. Code: Old; New GS711Rev1.05 10/19991/ 2000K;Rev 5 2/2000L GS71116 Rev 1.05 2/2000;Rev1.06 2/2000M (not posted) GS71116 Rev1.05 2/2000; Rev1.06 6/2000 (previous rev not posted) Types of Changes Page #/Revisions/Reason Format or Content Format/Content Content Content 1. 2. 1. 2. 1. 2. GSI Logo Took all referenced to 8ns and 9ns speed bins out. Heading, Power Supply Currents, Read and Writ eCycle table, Ordering information. Added Standby Current numbers back into Power Supply Currents table Noted that numbers were max. Rev: 1.06 6/2000 15/15 (c) 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
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