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8
r. ANALOG L.III DEVICES
FEATURES 8- and 10-Bit Resolution 20llS Conversion Time Microprocessor Compatibility Very Low Power Dissipation Parallel and Serial Outputs Ratiometric Operation TTL/DTL/CMOS Logic Compatibility CMOS Monolithic Construction
CMOS 10-BitMonolithic ID Converter A
OBS
8
GENERAL DESCRIPTION
8
The AD7570 is a monolithic CMOS 10-bit successive approximation AID converter on a 120 by 13 5 mil chip, requiring only an external comparator, reference and passive clocking components. Ratiometric operation is inherent, since an extremely accurate multiplying DAC is used in the feedback loop.
The AD7570 parallel output data lines and Busy line utilize three-state logic to permit bussing with other AID output and control lines or with other I/O interface circuitry. Two enables are available: one controls the two MSBs; the second controls the remaining 8 LSBs. This feature provides the control interface for most microprocessors which can accept only an 8-bit byte.
OLE
FUNCTIONAL
OUT1
AIN VREF CaMP STRT ClK
DIAGRAM
TE
OUT2
I
I
10
,..,....--0 DB9 (MSB) DB8 18 19 28 8 SRO 27 BSEN HBEN lBEN - SYNC DB1 DBO (lSBI BUSY
8
The AD7570 also provides a serial data output line to be used in conjunction with the serial synchronization line. The clock can be driven externally or, with the addition of a resistor and a capacitor, can run internally as high as 0.6MHz allowing a total conversion time (8 bits) of typically 201ls. An 8-bit short cycle control pin stops the clock after exercising 8 bits, normally used for the "J" version (8-bit resolution). The AD7570 requires two power supplies, a +15V main supply and a +5V (for TTL/DTL logic) to + 15V (for CMOS logic) supply for digital circuitry. Both analog and digital grounds are available. The AD7570 is a monolithic device using a proprietary CMOS process featuring a double layer metal interconnect, on-chip thin-film resistor network and silicon nitride passivation ensuring high reliability and excellent long term stability.
SUCCESSIVE APPROXIMATION lOGIC
20 21 9
L-221-13l-1l-6T220 Vcc 236 16 DGND voo 66 AGND
-l
8
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringementS of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
P.O. Box 280; Tel:617/329-4700 Telex: 924491
Norwood,
Massachusetts 02062 U.S. Twx: 710/394-65' Cables: ANALOG NORWOODMA:
--
(VOO SPECIFICATIONS 0=+15V, VCC 0=+5V, VREF0=:!:lOV unless otherwise
PARAMETERI
ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Temperature ANALOG INPUTS Coefficient
noted)
TEST CONDITIONS
-
VERSIONS
TA = +25C 8 Bits min 10 Bits min :!:1/2LSB max ILSB max 0.3% Reading typ
OVER SPECIFIED TEMP. RANGE
' '-8 Bits min 10 Bits min :!:1/2LSB max ILSB max
J L J, L 1.L J, L J, L ---------------J, L
SC8 = Logic "0" SC8 = Logic "I" fCLK = 100kHz See Figure 5
0
8
5ppm Reading per 0 C typ
10kQ typ -150ppm/C typ 10kQ typ -I 5.9"p_n1/C- ty I' ---------------
10ppm Reading per --------.-.----------.-------
C max
OBS
DIGITAL INPUTS VINL 2 VINH2 VINL2 VINH2 IINL' IINH 3 CLK Input Current CLK Input Current
Analog Input Resistance Analog Input Resistance Tempco Reference Input Resistance Reference Input Resistance Tempco ANALOG OUTPUTS Output Leakage Current (OUT!, OUT2) Output Capacitance OUTI OUT2 OUT! OUT2
5kQ Olin, 20kQ max 5kQ min, 20kQ max
1.L
J, L J, L
J, L J, L 1.L 1.L J, L
lUnA typ 120pF typ 40pF typ 40pF typ 120pF typ
200nA
max
Voun, 2 = OV DBOthrough DB9 = Logic "I"
DBO through DB9 = Logic "0"
----------.-
1.L J, L J, L J, L J, L J, L J, L 1.L
+1.4V +2.4V +1.5V +13-5V
typ, +0.8V max min, + 1.4V typ max min
+0_8V max +2.4V Olin + 1.5V max + 13.5V min
Vcc = +5V
Vcc = +15V VIN = 0 to VCC During Conversion Vcc = +5V; 2_4V VIN Vcc
I
:!:O_IIlA typ, :!:IOIlA max +0.4011\ typ, +lmA max typ, +3mA max
+1.7m1\
CLK Input Current
:!:IIlA typ
Cm
u
J, L
---.
2pF typ
DIGITAL VOUTL YOUTH VOUTL YOUTH
OUTPUTS
CoUT (Floating) (SYNC, SRO, DBO thro~gh
BUSY, DB9)
J, L 1.L 1.L J, L J, L
and
+0.5V max +2.4V min +1.5V max +13.5V min 5pF typ
OLE
+0_8V max +2.4V +1.5V min max +13.5V min 40lls max 120llS max
TE
Vcc = +5V, ISINK = 1.6mA VCC = +5V, IsOURCE = 40llA VCC = +15V, ISINK = 3mA VCC = +15V, ISOURCE = ImA VCC = +5V to +15V SRO and SYNC; Conversion Complete BUSY; BSEN = Logic "0" DBO-DB9; HBEN, LBEN = Logic "0" VCC = +5V to +15V SRO and SYNC; Conversion Complete BUSY; BSEN = Logic "0" DBO-DB9; HBEN, LBEN = Logic "0" VOUT = OV and VCC See Figure 5 Vcc = +5V; CLK Duty Cycle = 50%, R = 33k, C = 760pF VCC = +15V, CLK Duty Cycle = 50%, R = lOk; C = 2500pF Vcc = +5V LBEN, HBEN = OV to +3V Data Bit Load = 5k, 16pF Measured from 50% of Enable Input to 50% Point of Data Bit Output Vcc = +5V BSEN = OV to +3V BUSY Load = 5k, 16pF Measured from 50% Point of BSEN Input Waveform to 50% Point of BUSY Output Waveform
During Conversion VCC = +15V; 10V VIN VCC Vcc = +5V to +15V Conversion Complete or CLK IN VINL
I
ILKG (Floating) (SYNC, SRO, BUSY and DBO through DB9)
:!:5nA typ
t
DYNAMIC PERFORMANCE Conversion Time Internal CLK Frequency (See Figure 2, and Section 6 of Pin Function Description) LBEN, HBEN Propagation tON IoFF Delay
J L J, L
1.L
20lls typ, 40lls max 40lls typ, 120lls max 100kHz typ 100kHz typ
J, L 1.L
650ns typ 200ns typ
BSEN Propagation tON tOFF
Delay J, L 1.L 450ns typ 200ns ryp
Convert Pulse
Start Duration
(STRT)4 Requirement
,
'
-~
J, L
0.51ls Olin
~
.--
" -2-W
i
-
----------
8
- -----VDD VCC IDD
PARAMETER
I
VERSIONS
TA
~ +25C
OVER SPECIFIED TEMP_RANGE
TEST CONDITIONS See Figures 3 and 4
POWER SUPPLIES
J. L J. L J. L J. L
J, L
+5V to +15V typ +5V to VDD typ 0.2mA typo 2mA max
VDD~
+15V, Continuous Cycle)
fCLK ~ 0 to 100kHz Conversion (80% Duty
Icc
0.02mA typ, 2mA max
VCC ~ +5V. fcLK ~ 0 to 100kHz Continuous Conversion (80% Duty Cycle) VCC = +15V, Continuous Cycle) fcLK = 0 to 100kHz Conversion (80% Duty
O_lmA typ, 2mA max
2
..
OBS
Specifications subject to change without notice.
, "J" version parameters specified for SC8 ~ O. VJNL and VJNH specifications applicable to all digital inputs except COMP. COMP terminal must be driven with CMOS levels (i.e., comparator output pullup must be tied to VCc). 'IJNL,IJNH specifications not applicable to CLK terminal. See "CLK input current" in specifications table. . STRT falling edge should not coincide with CLK in falling edge.
8
ABSOLUTE
MAXIMUM
RATINGS
8
VootoGND VcctoGND VcctoVOO"""""""""""""'" VREFtoGND AnaloglnputtoGND Digital Input Voltage
Range.
. . . . . . . . . . . . . VOO to GND
'oUTl,'oUTZ O.3V,VoO Power Dissipation (package) upto+50c IOOOmW Derate above +50C by. - . . . . . . . . . . . . . . . . . . IOmW/C Operating Temperature. . . . . . . . . . . . . . . . -25C to +85C Storage Temperature. . . . . . . . . . . . . . . . -65C to +150C
OLE
+17V +17V +OAV :t25V :t25V
ORDERING INFORMATION
Resolution
8-Bit
----
la-Bit
Suffix D:
Ceramic
PIN CONFIGURATION
TE
Temperature -25C Range to +85C AD7570j AD7570L Package
TOP VIEW
VDD
1.
2a 27 26 25 24 23 22 21 20
rmw
BSEN
8
CAUTION:
1. Do not apply voltages higher than V cc or less than
VREF AIN
oun OUT2 AGND COMP SAD SYNC
STAT ClK DGND Vcc lBEN HBEN DBa IlSB) DBI DB2 DB3 DB4
GND to any input/output or AIN.
terminal
except
VREF
2. The digital control inputs are zener protected; however permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. 3. Vcc should never exceed Voo by more than OAV, especially during power ON or OFF sequencing.
(MSB) B9 D
DBa DB7 DB6 DB5
10
11 12
19 18 17 16 15
8
-
-3-
TYPICAL PERFORMANCE CHARACTERISTICS
1000.0 VDD : +15V CLK IN : 0 TO +3V (VCC : +5VI, 0 TO +15V IVcc : +15VI CONVERSION.TO.STANDBY DUTY CYCLE: 100,0 HBEN, LBEN, BSEN, COMP, +0.25 +0.20 80% >+0.15
AD7570J +0,10
SClf.: Vcc
t
~
~
.y
0 _0
~
10.0
;::. +0.05 ~'jj 0'" z= 0 }AD7570L
~
~
-0.10
-0,15 .0.20
1.0
is
0.1 100 lk 10k lOOk
-0,25 5 10 11 12 13 14 15
OBS
Figure " IDD, Ice vs. fCLK at Different
1M lOOk 1---,-
CLOCK FREOUENCY - H,
VDD - VOL TS
Temperatures
Figure
3,
Differential
Nonlinearity
vs. VDD
0.35
:I:
,
~ u
VDD: +15V TA:25C
Vcc
R
10k
~
C GENERATING
~ ~
[ II
22
24
AD7570 INTERNAL CLK
OLE
0.30
8
~ ."
0.25
~
" 0.20
0:
,
0 0: 0: w z
0.15
~
0.10
0.05
0.00
lk 10
100 CAPACITANCE
-
lk
pF
10k
5
VDD
-
TE
10 11 12 13 14 15
VOL TS
8
Figure
2.
fCLK vs. Rand
Cat
Vce = +5V, +15V
Figure
4,
Gain Error vs. VDD (Normalized
for VDD = 15V)
TEST CIRCUITS
-10V +5V SW.l 0 TO .10V +15V
8
3k
I (MSBI
I BIT 10
BIT 11 BIT 12 (LSBI
--
BIT 1
~3
12 BIT DAC
LBENI21
HBEN BSEN 27 1M 10 BIT TEST 250k 8 BIT TEST 10.BIT, TEST DUT 23 sc8126 AD7570 7 161 DB3 20
-
rv
ANALOG DITHER INPUT 5-40 H, SINE WAVE. lOV P1' 100kH, CLOCK
8B'J1, TESV
..9:.!i STRT
OSCILLOSCOPE
18 24
25
19
D80 (LSB) 10 BIT TEST
CONVERT START 0.5", PULSE DN 130", INTERVALS. TRAILING EDGE SYNCED TO CLOCK LEADING EDGEI
28 I BUSY
20k
HORIZONTAL (X) INPUT NOTE, ADJUST COMPARATOR
6
-4-
01 02 VERTICAL (YI INPUT 10k DUAL "D" TYPE LATCH
e
III
IAD311 I OFFSET TO LESS THAN O1mV.
Figure 5. Dynamic Crossplot Accuracy Test
8
PIN FUNCTION
INPUT CONTROLS
DESCRIPTION
1. Convert Start (pin 25 - STRT) When the start inpu t goes to Logical" 1 ", the MS B data latch is set to Logic "1" and all other data latches are set to Logic "0". When the start input returns low, the conversion sequence begins. The start command must remain high for at least 500 nanoseconds. If a start command is reinitiated during conversion, the conversion sequence starts over. 2. High Byte Enable (pin 20 - HBEN) This is a three-state enable for the bit 9 (MSB) and bit 8. When the control is low, the output data lines for bits 9 and 8 are floating. When the control is high, digital data from the latches appears on the data lines. bits 0 (LSB)
8. Vcc (pin 22) Vcc is the logic power supply. If +5V is used, all control inputs/outputs (with the exception of comparator terminal) are DTL/TTL compatible. If +15V is applied, control inputs/outputs are CMOS compatible.
OUTPUT FUNCTIONS
1. Busy (pin 28 - BUSY) The Busy line indicates whether conversion is complete or in process. Busy is a three-state output and floats until the Busy-Enable line is addressed with a Logic "1 ". When addressed, Busy will indicate either a "1" (conversion complete) or a "0" (conversion in process).
~
OBS
8 <8
shows the internal CLK frequency
2. Serial Output (pin 8
-
SRO)
3. Low Byte Enable (pin 21 - LBEN) Same as High Byte Enable pin, but controls through 7.
4. Busy Enable (pin 27 - BSEN) This is an interrogation input which requests the status of the converter, i.e., conversion in process or convert complete. The converter status is addressed by applying a Logic "1" to the Busy Enable. (See Busy under Output Functions.)
5. Short Cycle 8 Bits (pin 26 - SCS) With a Logic "0" input, the conversion stops after 8 bits reducing the conversion time by 2 clock periods. This control should be exercised for proper operation of the "J" version. When a Logic "1" is applied, a complete 10-bit conversion takes place ("L" version).
6. Clock (pin 24 - CLK) With an external RC connected, as shown in the figure below, clock activity begins upon receipt of a Convert-Start command to the A/D and ceases upon completion of conversion. An external clock (CMOS or TTL/DTL levels) can directly drive the clock terminals, if required. Figure 2
versus Rand
OLE
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MNEMONIC VDD VREF AIN
Provides output data in serial format. Data is available only during conversion. When the A/D is not converting, the Serial Output line "floats." The Serial Sync (see next function) must be used, along with the Serial Output terminal to avoid misinterpreting data. Provides 10 positive edges, which are synchronized to the Serial Output pin. Serial Sync is floating if conversion is not taking place.
3. Serial Synchronization (pin 9 - SYNC)
Note that all digital inputs/outputs
when Vcc is +5V, and CMOS compatible
TE
are TTL/DTL FUNCTION
compatible
when VCC is +15V.
oun
OUT2 AGND COMP SRO SYNC DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO HBEN LBEN VCC DGND CLK STRT SC8 BSEN BUSY
C. If V cc
~
8
is <4.75V,
the internal
CLK will not operate.
+5V
(
R
24
AD7570
CI
Generating Internal Clock Frequency
~
8
7. VDD (pin 1)
VDD is the positive supply for all analog circuitry plus some digital logic circuits that are not part of the TTL compatible input/output lines (back-gates to the P-channel devices). Nominal supply voltage is +15V.
Positive Supply (+ 15V) Voltage REFerence (:t10V) Analog INput DAC Current OUTput 1 DAC Current OUTput 2 Analog GrouND COMParator SeRial Output Serial SYNChronization Data Bit 9 (MSB) Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 (LSB) High Byte ENable Low Byte ENable Logic Supply (+ 5V to + 15V) Digital GrouND CLocK STaRT Short Cycle 8 Bits BuSy ENable BUSY
Table 1. Function
Table
-5-
FUNCTIONAL
ANALYSIS
(STRT) goes HIGH, the MSB(DB9) is set to the Logic "1" state, while DBO through DB8 are reset to the "0" state. Two clock pulses plus 200ns after STRT retUrns LOW, the MSB decision is made, and DB8 is tried. Each succeeding trial and decision is made at tCLK + 200ns.
BASIC DESCRIPTION
The AD7570 is a monolithic CMOS AID converter which uses the successive approximations technique to provide up to 10 bits of digital data in a serial and parallel format. Most AID applications require the addition of only a comparator and a voltage or current reference. In the successive approximations technique, successive bits, starting with the most significant bit (DB9) are applied to the input of the 01 A converter. The DAC output is then compared to the unknown analog input voltage (AIN) using a zero crossing detector (comparator). If the DAC output is greater than AIN, the data latch for the trial bit is reset to zero, and the next smaller data bit is tried. If the DAC output is less than AIN, the trial data bit stays in the "1" state, and the next smaller data bit is tried.
t
Serial NRZ data is available during conversion at the SRO terminal. SYNC provides 10 positive edges which occur in the middle of each serial output bit. SYNC out must be used in conjunction with SRO to avoid misinterpretation of data. Both SYNC and SRO "float" when conversion is not taking place. 8-BIT SHORT CYCLE NOTES If the AD7570 is short cycled to 8 bits (SC8 = OV), the following will occur: 1. The SYNC terminal output pulses. will provide 8, instead of 10, positive
OBS
TIMING DESCRIPTION
Each successive bit is tried, compared to AIN, and set or reset in this manner until the least significant bit (DBO) decision is made. At this time, the AD7570 output is a valid digital representation of the analog input, and will remain in the data latches until another convert start (STRT) is applied.
Figure 6 is the AD7570 timing diagram, showing the successive trials and decisions for each data bit. When convert start
ClK1 STRT2 SYNC3, 4,8
SROS,8 OB9 (MSB)6,7 0B87
II
, :///////1 ////////1T
OLE
IMSBI8 17 f6l 5 14 13 1211 E DB8DECISION
I~ DB7 DECISION
2. OBI goes "high" coincident with the LSB (DB2 is the LSB when short cycled to 8 bits) decision, and remains high until another STRT is initiated. DBO remains in the "0" state.
t
3. BUSY goes "high" one clock period after the DB2 (DB2 is the LSB when short cycled) decision is made.
---------
!LSBr---------
TRYMSB1-- MSB DECISION RY'D BB-! TRYDB7--/
TE
t
OB77 ////////1
OB67 ////////1 OB57 ///////~ 0B47 ////////1 OB37 :///////~
TRY DB6==:/ TRY DB5
E
DB6 DECISION
~
d
E ~
DBS DECISION
t
DECISION
TRY DB4
E
DB4 DECISION
TRY DB3
E
DB3 DECISION EDB2
OB27 ////////1
OB17 ////////1 DBa (lSB)7 BSEN2 BUSY
NOTES: 1. 2. 3. 4.
TRY DB2==:1
TRY DB1 ==:/
E
DB1 DECISION
all////~
TRY LSB ==:/
E
BUSY
DBO (LSBI DECISION
--
,
JCONVERT L.. - - COMPLETE
INTERNAL CLOCK RUNS ONLY DURING CONVERSION CYCLE (EXTERNAL CLOCK SHOWN!. EXTERNALLY INITIATED. SERIAL SYNC LAGS CLOCK BY '" 200ns. DOTTED LINES INDICATE "FLOATING" STATE. 5. FOR ILLUSTRATIVE PURPOSES,SERIAL OUTSHOWNAS 1101001110. 6. CROSS HATCHING INDICATES "DON'T CARE" STATE. 7. SET AND RESET OF OUTPUT DATA BITS LAGS CLOCK POSITIVE EDGE BY '" 200ns.
411
8.
SHOWN
FOR sca
= 1.
Figure 6. AD7570 Conversion Timing Sequence -6--
DYNAMIC
~
PERFORMANCE
(8
The upper clock frequency limitation (hence the conversion speed limitation) of the AD7570 is due to the output settling characteristics of the current weighting DAC in conjunction with the propagation delay of the comparator, not to speed limitations in the digital logic. DAC EQUIVALENT CIRCUIT
Worst case settling requirements occur when a trial bit causes the OUTI terminal to charge towards a final value which is precisely 1/2 LSB beyond zero crossing. When this occurs, the trial bit must settle and remain within 1/2 LSB of final val ue, or an incorrect decision will be made by the comparator.
The Df A converter section of the AD75 70 is a precision lO-bit multiplying DAc. The simplified DAC circuit, shown in Figure 7, consists of ten single-pole-double-throw current steering switches and an "inverted" R-2R current weighting network. (For a complete description of the DAC, refer to the AD7520 data sheet.)
For 10-bit accuracy, the first MSB must settle to within 0.1 % of final value; the second MSB to within 0.2%. The LSB settling requirement is only 50% of the LSB value. Figure 8 illustrates the settling time available during a given clock period. The pulse shown on the OUTI terminal falling midway between to and q is a feed through from internal clock mechanisms and is due primarily to bonding wire and header capacitance. Two methods may be used to reduce the OUTI settling time: 1. Load OUTI with a lk resistor. This reduces the time
J
. , (8
OBS
10k VREF 10k 10k
2Ok 20k 20k
The output resistance and capacitance at OUTI (and OUT2) are code dependent, exhibiting resistive variations from 0.5 "R" to 0.75 uR", and capacitive variations from 40pF to l20pF.
constant by a factor of 10. Further reduction of the lkD. load reduces the amount of comparator overdrive, thus increasing the comparator propagation delay, resulting in a reduction of available settling time (tl - to on Figure 8). 2. Use a zero input impedance comparator. Figure 9 illustrates a comparator circuit which has an input impedance of approximately 26D.. Proper circuit layout will provide lO-bit accuracy for clock frequencies >500kHz.
ClK IN
.
8
SETTLING
I I oB9
I
I oB8
I I oB7
Figure 7. DAC Circuit TIME ANALYSIS
OLE
20k 20k
A / ANALOG GNo OUT2
1
oun
AIN
COMPARATOR INPUT louni
NOTES'
Due to the changing COUTI and ROUTl, the time constant on OUTI falls anywhere between 250 and 900ns, depending on the instantaneous state of the AD7570 digital output code.
1 "',mUNG" "1 . '01 IS THE TIME REOUIRED FOR THE oun TERMINAL TO SETTLE WITHIN .1/2LS6 OF THE FINAL VALUE. 2. "'COM'" 11, . 1, I IS THE COMPARATOR SWITCHING TIME 3 "'O'lAY" 11, - 1,IIS AN INTERNAllY GENERATED TIME DELAY EOUAL TO APPROXIMATEL Y 400 NANOSECONDS.
4 COMPARATOR OUTPUT IS LATCHES AT TIME
TE
"
Figure 8. Expanded Timing Diagram
Vcc
-
8
R1 1k 0.01%
+5V
R2 1k 0.01%
R6 1k
OUT1 AD7570
I
OUT2
R4
7.5k 0.05%
R3U
R5 100
7.5k 0.05%
.
(8
CaMP \AI
-15V
!
Figure 9. Current Comparator With Low Input Impedance -7-
OPERATION
UNIPOLAR
GUIDELINES
OPERATION ADJUSTMENT PROCEDURES UNIPOLAR OPERATION
BINARY
Figure 10 shows the circuit connections required for unipolar analog inputs. If positive analog inputs are to be quantized, VREF must be negative, and the OUT1 (pin 4) terminal of the AD7570 must be connected to the "+" comparator input. For negative analog inputs, VREF must be positive, and the OUT1 terminal connected to the "-" input of the comparator. For clarity, the digital control functions have been omitted from the diagram. For proper use of the digital input/output control functions, refer to the pin function description. The input voltage/output code relationship for unipolar operation is shown in Table 2. Due to the inherent multiplying capability of the internal D/A converter, the AD7570 can accurately quantize full scale ranges of 10V to 1V. It should be noted, however, that for smaller full scale ranges, the resolution and speed limitations of the comparator impose a limitation on the maximum conversion rate. BIPOLAR (OFFSET BINARY) OPERATION
Gain Adjustment 1. Apply continuous AD7570.
start commands
to the STRT input of the to AIN. under zero offset
t
2. Apply full scale minus 1-1/2LSB 3. Observe the S RO terminal
as described
procedure above, and adjust the gain potentiometer (R4) until the LSB flickers between 0 and I, and all other data bits equal "I". An alternate instead of using R4. vcc method is to adjust VREF
+5V TO +15V VDD +15V +15V 22
4 R2 3k
OBS
R2 20k 20k R1 BIPOLAR ANALOG INPUT
+10V TO -10V
I oun
~fJv
VREF. 2
R3 20011
AD7570
~N:ci"~~o~N
Figure 11 shows the AD7570 configured for offset binary (modified 2's complement) operation. Input voltage/output codes are shown in Table 3.
Amplifier AI, in conjunction with resistors R1, R2, and R3, 0ffsets the bipolar analog input by full scale, and reduces its gain by a factor of 2. The analog signal applied to the AIN terminal is, therefore, a unipolar signal of 0 to +V or 0 to -V, depending on the polarity of VREF'
OLE
GAI~kADJ
~
R4
3
t
23
I
NOTE: IF POSITIVE VREF IS USED. THE ANALOG INPUT RANGE IS 0 TO -VREF. AND THE COMPARATOR'S (-) INPUT SHOULD BE CONNECTED TO oun (PIN 4) OF THE AD7570.
Figure 10. Unipolar Operation Vcc
VREF -10V
VDD
+15V
+5V TO
+15V
TE
+15V
t
R6 3k
2
t
R3 10k
R5 200
VREFI
2
22
R5 1k 4 rUTl 5 OUT2'
3
AD7570 AGND 3
7
COMP
A
NOTE: IF POSITIVE VREF IS USED, CONNECT TO oun (PIN 4) OF THE AD7570. MINUS INPUT OF COMPARATOR
Figure 11. Bipolar Operation
I
-8-
(8
Notes
Table 2. Unipolar Operation Analog Input (AIN) 1, 2, 3 Digital Output MSB 1111111111 1111111110 1100000000 1000000001 1000000000 01111 11 111 0100000000 0000000001 0000000000 Code LSB
Table 3. Bipolar Operation Analog Input (AIN) Notes 1, 2, 3
+(FS - 1LSB) +(FS - 2LSB) +(1/2 FS) +(1LSB) 0 -(1LSB) -(1/2 FS) -(FS - lLSB) -FS Digital Output MSB 1111111111 1111111110 1100000000 1000000001 1000000000 0111111111 0100000000 0000000001 0000000000 Code LSB
OBS
(8
NOTES: 1. Analog inputs of code. (-VREF) (2-10).
FS - lLSB FS - 2LSB 3/4 FS 1/2 FS + lLSB 1/2 FS 1/2 FS - lLSB 1/4 FS lLSB 0
shown are nominal
2. "FS" is full scale, i.e., (-VREF)' 3. For 8-bit operation, lLSB equals (-VREF) (Z-8); for to-bit operation, lLSB equals
(8
ADJUSTMENT Gain Adjustment
PROCEDURES
BIPOLAR
OLE
(-VREF)
center
values
NOTES: 1. Analog inputs of code.
shown are nominal
center
values
2. "FS" is full scale; i.e., (VREF)' 3. For 8-bit operation, lLSB equals (Z-7); for to-bit operation, lLSB (2-9).
(-VREF) equals
OPERATION
1. Apply continuous the AD7570.
start commands
to the STRT input of
6. If an external clock is used, the negative transition of STRT should not coincide with the trailing edge of the clock input.
TE
greater than V cc or lower
2. Apply 1-1/2LSB less than positive full scale (FS = VREF) to the bipolar analog input of Figure 11. 3. Trim the gain potentiometer R4 for a flickering LSB, and all other data bits equal to Logic "1". Observe the SRO terminal, as described in zero offset procedure above.
OPERA TING PRECAUTIONS 1. Do not allow Vcc to exceed VDD' In cases where Vcc could exceed VDD' the diode protection scheme in Figure 12 is recommended.
2. Do not apply voltages than
(8
ground to any digital output ply >20mA. APPLICATION HINTS
from sources
which can sup-
1. Unused CMOS digital inputs should be tied to their appropriate logic level and not left floating. Open digital inputs may cause undesired digital activity in the presence of noise. 2. Analog and digital grounds 3. Load the OUTI time constant >50kHz. terminal should have separate retUrns.
3. Do not apply voltages (from a source which can supply more than SmA) lower than ground to the OUTI or OUT2 terminal (see Figure 12). Vcc Voo 1N459, 1N914 HP5082-2811
22
with a 1k resistor to reduce the at clock frequencies
when operating
(8
4. For 10-bit operation, the comparator offset should be adjusted to less than ImV. Each millivolt of comparator offset will cause approximately 0.015% of differential nonlinearity when a 10V reference is used. 5. The comparator input and output should be isolated to prevent oscillations due to stray capacitance. (See layout on the next page).
4 .OUT1 AD7570
Figure 12. Diode Protection Scheme -9-
APPLICA nONS
OPTIMIZED LAYOUT
'j
i ~ ..
~ ~ AD7570-t
t
oun
Ik LOAD
OBS
IVREF
0 TO +IOV).
~
NOTES: 1. ALL PC TRACES ON BOTTOM OF BOARD. 2. LAYOUT SHOWN TERMINATES oun INTO + INPUT OF AD311 TYPE COMPARATOR.
t
.
-JOY. AIN'
BUSING MULTIPLE
AD7570
OUTPUTS
Several AD7570's may be paralleled to a data bus to provide an AID converter per analog channel, this providing increased system throughput rate. For example, Figure 14 shows such a system for 12 AD7570's in parallel. The three-state output logic enables of each AD7570 is controlled by its own BUSY (status) outputs. Thus, data is
OLE
Figure 13. PC Layout (Top View)
available at the AID output only after conversion is complete, and until another "convert start" is initiated. The timing diagram of Figure 15 illustrates how the STRT signals of the twelve AD7570's might be staggered to provide a total system throughput twelve times as great as the classic method of data acquisition (an analog multiplexer feeding multichannel analog data to a single AID converter).
TE
~
READ1
t
STRT 1
BSEN1 AIN 1 A07570 NO.1
OB9 (MSB)
.
I I I I/O CLK
t
DATA
STRn CD REA01 BUSY 1
I
lOBO (LSB) I I
LBEN CLK 0
BUSY 1
--,
VREF STRT12 BSEN 12 AIN 12
A07570 LBEN NO. 12 I BUSY 3 lOBO (LSB) OB9 (MSB) . I I I
BUSS.
-11
,OB9,OB8,OB7,OB6,OB5,084,OB3,OB2,081,OBO, CONVERSION IN PROCESS
L-
~
CD STRn
BUSY2 STRT 12 BUSY 12
~ REA02 ~
CONVERSION
IN PROCESS
---1L READ 2 ~ ~
READ 12
CD CONVERSION IN PROCESS
n
NOTE: STRT SIGNAL 0.5!,s PULSE WIDTH, LEADING EDGE SYNCHRONIZED TO CLK TRAILING EDGE.
8
NOTE:
BSEN ON EACH A07570 IS "ENABLEO"
(LOGIC 1).
Figure 14. Busing Multiple AD7570's
Figure 15. Timing Diagram
-10-
MICROPROCESSOR
INTERFACE
3. LBEN is enabled, and the eight least significant data bits (DBO-DB7) are applied to the data bus for subsequent transfer to the 8080. When the data transfer is complete, LBEN is disabled, and DBO-DB7 return to their floating state. 4. HBEN is enabled, and the two most significant AD7570 data bits (DB8 and DB9) are applied to the data bus for subsequent transfer to the 8080. When the data transfer is complete, HBEN is disabled, and DB8 and DB9 return to their floating state. 5. The 8080 (in conjunction with the programmed Read Only Memory) performs a binary to decimal conversion. 6. SWE (Status Word Enable) on the UAR/T transmitter is
8
Since most 8-bitmicroprocessors utilize a bidirectio~al data bus, each input peripheral (such as the AD7570) must be capable of isolating itself from the data bus when other I/O devices, memory, or the CPU takes control of the bus. The AD7570 output data and status (BUSY) lines all utilize threestate logic to provide this requirement. Figure 16 illustrates a method of interfacing a TTY keyboard and printer to the AD7570, using an 8080 microprocessor as the interface controller. The program (stored in Read Only Memory) waits for a keystroke on the TTY keyboard. When a keystroke is detected, an AID conversion is started. When conversion is complete, the 8080 reads in the binary data from the AD7570, converts it to ASCII, and prints out the decimal number (preceded by a carriage return and line feed) on the teletype printer. the main sequence of events would be as
~
OBS
8
More specifically, follows: complete, and BSEN is disabled, its floating state.
enabled, applying XBMT (Transmitter Buffer Empty) to the data bus. When a Logic "1" is detected by the 8080, SWEis disabled, and XBMT returns to a floating state. 7. TDS (Transmitter Data Strobe) strobes the converted decimal number into the UAR/T transmitter for subsequent serial clocking into the keyboard.
1. When a TTY keystroke is detected by the CPU (via the UAR/T Receiver), a "convert start" (STRT) is applied to the AD7570.
2. BSEN is enabled, placing BUSY (conversion status) on the data bus. When the 8080 detects BUSY = 1, conversion is causing BUSY to return
~
8
A15 A8 A7
OLE
to
ADDRESS BUSS
The interface scheme shown below is only one example of a myriad of possible data acquisition/control systems which could conveniently use the AD7570 to provide digital data to a microprocessor or minicomputer bus.
DBFLlN . MEMR . A2 I DBFLlN . MEMR . A4
AO
DBFLlN
TE
5 4 3 2 1 (lSB) BDO 03 D2 D1 DO MEMR D Q ClK O.MEMR :J1
BSEN
HBEN AD7570 ADC
~
8
DBFLlN 8080
. MEMR
-,
(MSBI BOSY DB9 8
,
7
6
DATA DO-D7 DO
BUSS DO DO D7 D1 Dol DO D7 D6 07'
RDA FROM KEYBOARD WR DBFLlN SYNC WR RSI UAR/T RDAR REC SWE TDS UAR/T
XBMT
XMT
RDE
.AO
DBFLlN
WR A2 TO PRINTER
.
8
DBFLlN
. MEMR
.AO
. SYNC
. MEMR . AT
Figure
16.
Microprocessor
Controlled
TTY IADC Interface
-11..
TERMINOLOGY
Resolution Resolution is the relative value of the LSB, or Z-n for binary devices, for n-bit converters. It may be expressed as 1 part in Zn, as a percentage, in parts-per-million, or simply by "n bits." Relative Accuracy Relative accuracy error is the difference between the nominal and actUal ratios to full scale of the analog value corresponding to a given digital input, independently of the full-scale calibration. This error is a function of the linearity of the converter, and is usually specified at less than :!:l/2LSB. Gain Error The "gain" of a converter is that analog scale factor setting that establishes the nominal conversion relationship, e.g., lOV full scale. It is adjusted either by setting the feedback resistor of a DAC, the input resistor in a current-comparing ADC, or the reference (voltage or current). Output Leakage Current Current which appears at the OUT1 terminal when all digital output (DBO through DB9) are LOW, or on the OUTZ terminal when all digital outputs are HIGH. The effect of output leakage current will be on the offset of the AID converter. Differential Nonlinearity In a converter, differential linearity error describes the variation in the analog value of transitions between adjacent pairs of digital numbers, over the full range of the digital input or output. If each transition is equal to its neighbors (i.e., 1LSB), the differential nonlinearity is zero. If a transition differs from one of its neighbors by more than 1LSB (e.g., if, at the transition OIl. .11 to 100. . .00, the MSB is low by 1.1LSB), a DI A converter can be non-monotonic, or an AID converter using it may miss one or more codes. A sp,ecified maximum differential nonlinearity of 1 LSB ensures that monotonic behavior exists.
4
OBS
[2.j~1 M.AX
I
OUTLINE
Dimensions
DIMENSIONS
L
~~~~~c=J~~~~li~ .
1414[35921 138 135061'
I
r
0.065 0.045
"
OLE
shown in inches and (mm).
4
~012
.
,
~.--
~
--11-[1.661 [1151 LEADS 0.02 0015 10.5081 [0381}
--1
0105 0.095
f-[2671 12.42}
~
0125
t
I
1--~--1
1318}
0.606
[1541
1:
L
[1531
::::::::
LEAD NO 1 IDENTIFIED BY DOT OR NOTCH ARE GOLD PLATED [50 MICROINCHES MIN[ KOVAR
OR ALLOY 42
TE
4
28 Pin Ceramic Dip
4
~
-12-

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