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Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* Two LVCMOS / LVTTL outputs * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 350MHz * Output skew: 15ps (maximum) * Part-to-part skew: 600ps (maximum) * Additive phase jitter, RMS: 0.03ps (typical) * Small 8 lead SOIC package saves board space * 3.3V core, 3.3V, 2.5V or 1.8V output operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer and HiPerClockSTM a member of the HiPerClockS TM family of High Perfor mance Clock Solutions from ICS. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
IC S
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD CLK nCLK OE 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND
Q0 CLK nCLK Q1 OE
ICS83026I-01
8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View
VDD CLK nCLK OE
1 2 3 4
8 7 6 5
VDDO Q0 Q1 GND
ICS83026I-01
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Type Description Positive supply pin. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Output enable. When HIGH, outputs are enabled. When LOW, outputs are in Pullup High Impedance State. LVCMOS / LVTTL interface levels. Power supply ground. Clock output. LVCMOS / LVTTL interface levels. Clock output. LVCMOS / LVTTL interface levels. Output supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 Name VDD CLK nCLK OE GND Q1 Q0 VDDO Power Input Input Input Power Output Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor VDD, VDDO = 3.3V Output Impedance VDD = 3.3V, VDDO = 2.5V VDD = 3.3V, VDDO = 1.8V VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V VDD = 3.465V, VDDO = 1.95V 51 51 7 8 10 Test Conditions Minimum Typical 4 17 16 15 Maximum Units pF pF pF pF k k
TABLE 3. CONTROL FUNCTION TABLE
Input OE 0 1 Outputs Q0, Q1 HiZ Active
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Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 112.7C/W (0 lfpm) 101.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA 8 Lead SOIC 8 Lead TSSOP Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.71V TO 3.465V, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 1.71 Typical 3.3 3.3 2.5 1. 8 Maximum 3.465 3.465 2.625 1.89 10 3 Units V V V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.375V TO 3.465V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE OE OE OE VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDDO = 3.135V VDDO = 2.375V -150 2.6 1.8 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 Units V V A A V V V
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, "Output Load Test Circuit" diagrams.
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH VOL
83026BMI-01
Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage OE OE OE OE
Test Conditions
Minimum 2 -0.3
Typical
Maximum VDD + 0.3 0.8 5
Units V V A A V V
VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V IOH = -100A IOH = -2mA IOL = 100A IOL = 2mA
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-150 VDDO - 0.2 VDDO - 0.45 0. 2 0.45
V V
REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions nCLK CLK nCLK CLK VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.71V TO 3.465V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage; NOTE 1
VCMR Common Mode Input Voltage; NOTE 2, 3 GND + 0.5 NOTE 1: VPP can exceed 1.3V provided that there is sufficient offset level to keep VIL > 0V. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD t sk(o) t sk(pp) tjit t R / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 350MHz 1.3 1. 9 Test Conditions Minimum Typical Maximum 350 2.5 15 900 0.03 20% to 80% 66MHz 67MHz 166MHz 150 48 45 800 52 55 Units MHz ns ps ps ps ps % % %
167MHz 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 6.
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions 350MHz Minimum 1. 5 Typical 2.0 Maximum 350 2.6 15 750 0.03 20% to 80% 66MHz 67MHz 166MHz 150 48 46 800 52 54 Units MHz ns ps ps ps ps % % %
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD t sk(o) t sk(pp) tjit tR / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle
167MHz 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD t sk(o) t sk(pp) tjit tR / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 350MHz 1.9 2.5 Test Conditions Minimum Typical Maximum 350 3.1 15 600 0.03 20% to 80% 66MHz 67MHz 166MHz 200 48 43 900 52 57 Units MHz ns ps ps ps ps % % %
167MHz 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.03ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V0.103V 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.40.125V 0.9V0.45V V DD
V DD VDDO
SCOPE
Qx
nCLK
V
PP
Cross Points
V
CMR
LVCMOS
GND
CLK
GND
-0.9V0.45V
3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
PART 1
2
V
DDO
DDO
Qx
Qx
2
PART 2
V
DDO
V
DDO
Qy
2 tsk(o)
Qy
2 tsk(pp)
OUTPUT SKEW
83026BMI-01
PART-TO-PART SKEW
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
nCLK CLK
80%
Q0, Q1
VDDO 2 t
80% 20%
PD
Clock Outputs
20% tR tF
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
V
DDO
Q0, Q1 t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
LVCMOS drivers. In this example, series termination approach is shown. Additional termination approaches are shown in the LVCMOS Termination Application Note.
SCHEMATIC EXAMPLE
Figure 3 shows an application schematic example of ICS83026I01. The ICS83026I-01 CLK/nCLK input can directly accepts various types of differential signal. In this example, the input is driven by an LVDS driver. The ICS83026I-01 outputs are
VDD 3.3V R3 1K Zo = 50 Ohm VDD 1 2 3 4 VDD CLK nCLK OE VDDO Q0 Q1 GND 8 7 6 5 VDDO R1 43 Zo = 50 Ohm LVCMOS C2 0.1u Zo = 50 Ohm U1 ICS83026I-01 C1 0.1u Zo = 50 Ohm
R4 100 LVDS
VDD=3.3V VDDO= 3.3V, 2.5V or 1.8V
R2
43 LVCMOS
FIGURE 3. ICS83026I-01 SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 5A. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE5B. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
200
90.5C/W
500
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS83026I-0I is: 260
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
TABLE 6B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
83026BMI-01
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REV. A JANUARY 16, 2006
Integrated Circuit Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Marking 3026BI01 3026BI01 026BI01L 026BI01L 26B01 26B01 TBD TBD Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83026BMI-01 ICS83026BMI-01T ICS83026BMI-01LF ICS83026BMI-01LFT ICS83026BGI-01 ICS83026BGI-01T ICS83026BGI-01LF ICS83026BGI-01LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83026BMI-01
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REV. A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Added 8 Lead TSSOP package to Pin Assignment. Absolute Maximum Ratings - added 8 Lead TSSOP to Package Thermal Impedance. Added 8 Lead TSSOP Reliability Information table. Added 8 Lead TSSOP Package Outline and Package Dimensions. Ordering Information Table - added 8 Lead TSSOP ordering information. Additive Phase Jitter - corrected X axis on plot. LVCMOS DC Characteristics - corrected Test Conditions for IIH and IIL. Features Section - added lead-free bullet Added Recommendations for Unused Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. Date
Rev
Table
Page 1 3 11 12 13 6 3 1 9 13
A T7 A A A T7 T3C
6/25/04
8/2/05 8/12/05 1/16/06
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