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PRELIMINARY
Data Sheet No. PD60303
IRS20955(S)PbF
PROTECTED DIGITAL AUDIO DRIVER
Features
* * * * * * * * Floating PWM input enables easy half-bridge implementation Programmable bidirectional over-current protection with self-reset function Programmable preset deadtime for improved THD performances High noise immunity 100 V ratings deliver up to 500 W in output power 3.3 V/5 V logic compatible input Operates up to 800 kHz RoHS compliant
Product Summary
VOFFSET (max) Gate driver Selectable deadtime Propagation delay OC protection delay Shutdown propagation delay Io+ Io 100 V 1.0 A 1.2 A 15 ns, 25 ns, 35 ns, 45ns 90 ns 500 ns (max) 250 ns (max)
Description
The IRS20955 is a high voltage, high speed MOSFET driver with a floating PWM input designed for Class D audio amplifier applications. Bi-directional current sensing detects over-current conditions during positive and negative load currents without any external shunt resistors. A built-in protection control block provides a secure protection sequence against overcurrent conditions and a programmable reset timer. The internal deadtime generation block enables accurate gate switching and optimum deadtime setting for better audio performance, such as lower THD and lower audio noise floor.
16-Lead PDIP 16-Lead SOIC
Package
Typical Connection
IRS20955 (S)
VDD CSD IN PWM VSS NC VREF OCSET DT CSH VB HO VS NC VCC LO COM
+B
Speaker
(Please refer to Lead Assignments for correct pin configuration. This diagram shows electrical connections only)
Vcc 12V
-B
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IRS20955(S)PbF
PRELIMINARY Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS; all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VCSH VCC VLO VDD VSS VIN VCSD VDT VOCSET VREF IDDZ ICCZ IBSZ IOREF d VS /dt d VSS /dt d VSS /dt PD Rth,JA TJ TS TL
Definition
High-side floating supply voltage High-side floating supply voltage (Note1) High-side floating output voltage CSH pin input voltage Low-side fixed supply voltage (Note1) Low-side output voltage Floating input supply voltage Floating input supply voltage (Note1) PWM input voltage CSD pin input voltage DT pin input voltage OCSET pin input voltage VREF pin voltage Floating input supply Zener clamp current (Note1) Low side supply Zener clamp current (Note1) Floating supply Zener clamp current (Note1) Reference output current Allowable VS voltage slew rate Allowable VSS voltage slew rate (Note2) Allowable VSS voltage slew rate upon power-up (Note3) Maximum power dissipation Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-0.3 VB-20 Vs-0.3 Vs-0.3 -0.3 -0.3 -0.3 (See IDDZ) VSS -0.3 VSS -0.3 -0.3 -0.3 -0.3 -55 -
Max.
220 VB+0.3 VB+0.3 VB+0.3 20 VCC +0.3 210 VDD+0.3 VDD+0.3 VDD+0.3 VCC +0.3 VCC +0.3 VCC +0.3 10 10 10 5 50 50 50 1.0 115 150 150 300
Units
V
mA
V/ns W C/W C
Note1: VDD - VSS, VCC -COM and VB - VS contain internal shunt Zener diodes. Please note that the voltage ratings of these can be limited by the clamping current. Note2: For the rising and falling edges of step signal of 10 V. Vss=15 V to 200 V. Note3: Vss ramps up from 0 V to 200 V.
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IRS20955(S)PbF
PRELIMINARY Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset ratings are tested with supplies biased at IDD=5 mA, VCC=12 V and VB-VS=12 V.
Symbol
VB VS IDDZ VSS VHO VCC VLO VIN VCSD VDT IOREF VOCSET TA
Definition
High-side floating supply absolute voltage High-side floating supply offset voltage Floating input supply zener clamp current Floating input supply absolute voltage High-side floating output voltage Low-side fixed supply voltage Low-side output voltage PWM input voltage CSD pin input voltage DT pin input voltage Reference output current to COM (Note 2) OCSET pin input voltage Ambient temperature
Min.
Vs+10 Note 1 1 0 Vs 10 0 VSS 0 0.3 0.5 -40
Max.
Vs+18 100 5 200 VB 18 VCC VDD VCC 0.8 5 125
Units
V mA
V
mA V C
Note 1: Logic operational for VS equal to -5 V to +200 V. Logic state held for VS equal to -5 V to -VBS. Note 2: Nominal voltage for VREF is 5 V. IOREF of 0.3 mA - 0.8 mA dictates total external resistor value on VREF to be 6.3 k to 16.7 k.
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IRS20955(S)PbF
PRELIMINARY Electrical Characteristics
VCC ,VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V,CL=1 nF and TA=25 C unless otherwise specified.
Symbol Definition Low-Side Supply
UVCC+ UVCCIQCC VCLAMPL UVBS+ UVBSIQBS ILKH VCLAMPH UVDD+ UVDDIQDD VCLAMPM ILKM VCC supply UVLO positive threshold VCC supply UVLO negative threshold Low-side quiescent current Low-side Zener diode clamp voltage High-side well UVLO positive threshold High-side well UVLO negative threshold High-side quiescent current High-side to low-side leakage current High-side Zener diode clamp voltage VDD, VSS floating supply UVLO positive threshold VDD, VSS floating supply UVLO negative threshold Floating input quiescent current Floating input Zener diode clamp voltage Floating input side to low-side leakage current Logic high input threshold voltage Logic low input threshold voltage Logic "1" input bias current Logic "0" input bias current
Min
8.4 8.2 19.6 8.0 7.8 19.6 8.2 7.7 9.8 2.3 -
Typ
8.9 8.7 20.4 8.5 8.3 20.4 8.7 8.2 10.2 1.9 1.9 -
Max
9.4 9.2 3 21.6 9.0
Units
V mA V
Test Conditions
VDT = VCC ICC=5 mA
High-Side Floating Supply
V 8.8 1 50 21.6 9.2 8.7 1 10.8 50 1.5 40 1 V mA V A mA A V VB=VS =200 V IBS=5 mA VSS =0 V VSS =0 V VDD=9.5 V +VSS IDD=5 mA VDD=VSS =200 V
Floating Input Supply
Floating PWM Input
VIH VIL IIN+ IINV A VIN =3.3 V VIN = VSS
Protection
VREF Vth,OCL Vth,OCH Vth,1 Vth,2 ICSD+ ICSDtSD tOCH tOCL Reference output voltage Low-side OC threshold in Vs High-side OC threshold in VCSH CSD pin shutdown release threshold CSD pin self reset threshold CSD pin discharge current CSD pin charge current Shutdown propagation delay from VCSD > VSS + Vth,OCH to shutdown Propagation delay time from VCSH > Vth,OCH to shutdown Propagation delay time from Vs> Vth,OCL to shutdown Output high short circuit current (source) Output low short circuit current (sink) Low level output voltage LO - COM, HO - VS 4.8 1.1 1.1+ VS 0.62 x VDD 0.26 x VDD 70 70 5.1 1.2 1.2+ VS 0.70 x VDD 0.30 x VDD 100 100 5.4 1.3 1.3+ VS 0.78 x VDD 0.34 x VDD 130 130 250 500 500 ns V IOREF =0.5 mA OCSET=1.2 V, Fig. 3 VS=200 V, Fig. 4 VSS =0 V A VSD = VSS +5 V Fig. 2 Fig. 4 Fig. 3
Gate Driver
Io+ IoVOL 1.0 1.2 0.1 V A VO =0 V, PW<10 s VO =12 V, PW<10 s
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IRS20955(S)PbF
PRELIMINARY Electrical Characteristics (cont.)
VCC ,VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V,CL=1 nF and TA=25 C unless otherwise specified. VOH tr tf ton,1 toff,1 ton,2 toff,2 DT1 DT2 DT3 DT4 VDT1 VDT2 VDT3 High level output voltage VCC - LO, VB - HO Turn-on rise time Turn-off fall time High-side and low-side turn-on propagation delay, floating inputs High-side and low-side turn-off propagation delay, floating inputs High-side and low-side turn-on propagation delay, non-floating inputs High-side and low-side turn-off propagation delay, non-floating inputs Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4 DT mode select threshold 2 DT mode select threshold 3 DT mode select threshold 4 8 15 20 25 0.51(V cc) 0.32(V cc) 0.21(V cc) 15 10 105 90 105 90 15 25 35 45 0.57(V cc) 0.36(V cc) 0.23(V cc) 1.4 22 35 50 60 0.63(V cc) 0.40(V cc) 0.25(V cc) V ns VDT = VCC, VS = 100 V, VSS = 100 V VDT = VCC, VS = 100V, VSS = COM VDT>VDT1, VSS = COM VDT1>VDT> VDT2, VSS = COM VDT2>VDT> VDT3, VSS = COM VDT3>VDT> VDT4, VSS = COM V IO=0 A
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IRS20955(S)PbF
PRELIMINARY Lead Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol
VDD CSD IN VSS NC VREF OCSET DT COM LO VCC NC VS HO VB CSH
Description
Floating input positive supply Shutdown timing capacitor, referenced to VSS PWM non-inverting input, in phase with HO Floating input supply return 5 V reference output for setting OCSET Low-side over current threshold setting, referenced to COM Input for programmable deadtime, referenced to COM Low-side supply return Low-side output Low-side logic supply High-side floating supply return High-side output High-side floating supply High-side over current sensing input, referenced to VS
VDD CSD IN VSS NC VREF OCSET DT
1 2
16 15
CSH VB HO VS NC VCC LO COM
4 5 6 7 8
IRS20955(S)
3
14 13 12 11 10 9
IRS20955(S) 16-Lead SOIC (narrow body) 16-Lead PDIP
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IRS20955(S)PbF
PRELIMINARY
Block Diagram
FLOATING INPUT
VDD
UV DETECT
UV DETECT
CSH
VB
HIGH SIDE CS
UV Q
IN
10.4V
INPUT LOGIC
HO
20.8V
HV LEVEL SHIFT
VSS
HV LEVEL SHIFT
FLOATING HIGH SIDE
HV LEVEL SHIFT
VS
5V REG
CHARGE/ DISCHARGE
VCC
UV DETECT
CSD
DEAD-TIME
DT
PROTECTION CONTROL
HV LEVEL SHIFT
HV LEVEL SHIFT
20.8V
SD
LO
COM
LOW SIDE CS
OCSET
5.1V REFERENCE
VREF
DT
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IRS20955(S)PbF
PRELIMINARY
IN
50% t o n (L ) t o ff(H ) 90%
50%
t o ff(L ) t o n (H )
VS
VthOCL
LO 10% D T H O -L O HO D T L O -H O 90%
LO
90%
10%
tOCL
Figure 1. Switching Time Waveform Definitions
Figure 3. VS > VTH,OCL to Shutdown Waveform
Vth1
CSD
CSH VS
VthOCH
90%
90%
HO/LO
HO
tSD
tOCH
Figure 2. CSD to Shutdown Waveform Definitions
Figure 4. VS > VTH,OCL to Shutdown Waveform
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IRS20955(S)PbF
PRELIMINARY Functional Description
Floating PWM Input The IRS20955S accepts floating inputs, enabling easy half-bridge implementation. VDD, CSD and IN refer to VSS. As a result, the PWM input signal can directly feed into IN while referencing VSS, which is typically the midpoint between the positive and negative DC bus voltages in a half-bridge configuration. The IRS20955S also accepts a non-floating input when VSS is tied to COM.
VDD
Over-Current Protection (OCP) The IRS20955S features over-current protection to protect the power MOSFETs during abnormal load conditions. The IRS20955S engages a sequence of events when it detects the over-current condition during high-side or low-side turn on. As soon as either the high-side or low-side current sensing block detects over-current: 1. The OC Latch (OCL) flips logic states and shutdowns the outputs LO and HO. 2. The CSD pin starts discharging the external capacitor Ct. 3. When VCSD, the voltage across Ct, falls below the lower threshold Vth2, an output signal from COMP2 resets OCL. 4. The CSD pin starts charging the external capacitor Ct. 5. When VCSD goes above the upper threshold Vth1, the logic on COMP1 flips and the IC resumes operation. As long as the over current condition exists, the IC will repeat the over current protection sequence.
IN 10.4V
HV LEVEL SHIFT
CSD
PROTECTION
VSS
Floating Bias 0V - 200V COM
Floating Input Isolation
IRS20955
Figure 5. Floating PWM Input Structure
Figure 6. Over-Current Protection Timing Chart
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IRS20955(S)PbF
PRELIMINARY
VDD
Vth1
COMP1
CSD
OC
S R
Q
UVLO(VB)
Ct VSS
COMP2 Vth2
OC DET (H)
HV LEVEL SHIFT
FLOATING INPUT
HV LEVEL SHIFT
HV LEVEL SHIFT
FLOATING HIGH SIDE
LOW SIDE
OC DET (L) UVLO(VCC) PWM SD DEAD TIME
HO LO
Figure 7. Shutdown Functional Block Diagram
Protection Control The internal protection control block dictates the operational mode-norma, or shutdown, using the input of the CSD pin. The IC functions as expected in the normal mode. In shutdown mode, the IC forces LO and HO to output 0 V with respect to COM and VS to turn off the power MOSFETs. The CSD pin provides five functions. 1. Power up delay timer 2. Self-reset timer 3. Shutdown input 4. Latched protection configuration 5. Shutdown status output (host I/F) Self Reset Protection By putting a capacitor between CSD and VSS, the IRS20955S can reset itself after entering shutdown mode.
VDD CSD CSH
Designing Ct
The timing capacitor, Ct, is used to program tRESET and tSU. * tRESET, is the amount of time that elapses from when the IC enters shutdown mode to the time when the IC resumes operation. tRESET should be long enough to avoid over heating the MOSFET from the repetitive sequence of shutting down and resuming operation during over current conditions. In most of applications, the minimum recommended time for tRESET is 0.1. * tSU is the amount of time between powering up the IC in shutdown mode to the moment the IC releases shutdown to begin normal operation. The values chosen for tRESET and tSU will determine the capacitance of Ct using the given equations:
Ct =
t RESET I CSD 1.1 VDD
t SU I CSD 0.7 VDD
[F]
VB
HO VS NC VCC LO COM
Ct
IN VSS NC VREF OCSET DT
Ct =
[F]
Figure 8. Self Reset Protection Configuration
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where ICSD = the charge/discharge current at the CSD pin VDD = the supply voltage with respect to VSS.
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IRS20955(S)PbF
PRELIMINARY
Shutdown Input When VCSD falls below Vth2, the IRS20955S begins to charge Ct in an attempt to resume operation. Once the voltage of the CSD pin rises above the upper threshold, Vth1, the IC begins to operate normally again.
VDD CSD IN
SHUTDOWN
Interfacing with System Controller
The IRS20955S can communicate with an external system controller through a simple interfacing circuit such as the one shown in Figure 11. A generic PNP transistor, shown as U1, can detect the sink current at the CSD pin during an OCP event and output a shutdown signal to an external system controller. Another generic NPN transistor, shown as U2, can then reset the internal protection logic by pulling the CSD voltage below Vth2 for a minimum of 200 ns. Note that the CSD pin is configured to operate in latched OCP. After the power up sequence, a reset signal to the CSD pin is required to release the IC from shutdown mode.
CSH
VB
HO VS NC VCC LO COM
VSS NC VREF OCSET DT
Figure 9. Shutdown Input Latched Protection
Connecting CSD to VDD through a 10 k or less resistor configures the over current protection latch. The latch locks the IC in shutdown mode after over current is detected. An external reset switch can be used to bring CSD below the lower threshold Vth2 for a minimum of 200 ns to properly reset the latch. After the power up sequence, a reset signal to the CSD pin is required to release the IC from shutdown mode.
VDD CSH
VB
Figure 11. Interfacing with System Controller Programming OCP Trip Level
In a Class D audio amplifier, the direction of the load current alternates with the audio input signal. An over-current condition can therefore occur during either a positive current cycle or a negative current cycle. The IRS20955 uses the RDS(ON) of the output MOSFETs as current sensing resistors. Due to the structural constraints of high voltage ICs, current sensing is implemented differently for high side and low side. If the measured current exceeds a predetermined threshold, the OCP block outputs a signal to the protection block to shutdown the MOSFET to protect the switching devices.
<10k
RESET
CSD IN VSS NC VREF OCSET DT
HO VS NC VCC LO COM
Figure 10. Latched Protection Configuration
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IRS20955(S)PbF
PRELIMINARY
R2
UV DETECT
D1 +B R1
CSH VB
HIGH SIDE CS
UV Q
R3
HO
Dbs Q1
Cbs OUT
HV LEVEL SHIFT
FLOATING HIGH SIDE
5V REG UV DETECT
HV LEVEL SHIFT
VS
VCC
Vcc
DEAD TIME
SD
LO
Q2
COM
-B R5
LOW SIDE CS
OCSET
R4
VREF
Figure 12. Bi-directional Over Current Protection Low-side Over Current Sensing For negative load currents, low-side over current sensing monitors the load condition and shuts down switching operation if the load current exceeds the preset trip level. Low-side current sensing is based on the measurement of VDS across the low side MOFET during low-side turn on. In order to avoid triggering OCP from overshoot, a blanking interval inserted after LO turn on disables over current detection for 450 ns. The OCSET pin is used to program the threshold for low-side over current sensing. When the VDS measured across the low-side MOSFET exceeds the voltage at the OCSET pin with respect COM, the IRS20955S begins the OCP sequence described earlier. Since the voltage from VS to COM is compared to the voltage at the OCSET pin, the voltage at OCSET determines the trip level for over-current detection. By selecting the trip level for over-current, the voltage at OCSET can be calculated using the equation below. VOCSET = VDS(LOW SIDE) = ITRIP+ x RDS(ON) In order to minimize the effect of the input bias current at the OCSET pin, select resistor values for R4 and R5 such that the current through the voltage divider is 0.5 mA or more. * Note: Using VREF to generate an input to OCSET through a resistive divider provides improved immunity from fluctuations in VCC.
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IRS20955(S)PbF
+B
PRELIMINARY
Q1
OC REF
OCREF 5.1V R4
0.5mA OCSET
VS
OUT
+ OC Comparator
OC
R5 COM
LO
LO
Q2
IRS20955
-B
Figure 13. Low-side Over-Current Sensing High-side current sensing is based on the measurement of VDS across the high-side MOFET during high-side turn on through pins CSH and VS. In order to avoid triggering OCP from overshoot, a blanking interval inserted after HO turn on disables over current detection for 450 ns. In contrast to low-side current sensing, the threshold at which the CSH pin engages OC protection is internally fixed at 1.2 V. An external resistive divider R2 and R3 can be used to program a higher threshold. An external reverse blocking diode, D1, is required to block high voltages from feeding into the CSH pin while the high-side is off. Due to a forward voltage drop of 0.6 V across D1, the minimum threshold required for high-side over current protection is 0.6 V.
VCSH = R3 (V DS ( HIGHSIDE ) + V F ( D1) ) R 2 + R3
Low-Side Over-Current Setting Let the low-side MOSFET have an RDS(ON) of 100 m and set the current trip level to 30 A. VOCSET is given by: VOCSET = ITRIP+ x RDS(ON) = 30 A x 100 m = 3.0 V Choose R4+R5=10 k to properly load the VREF pin.
R5 = = VOCSET 10 k VREF
3.0 V 10 k 5.1 V
= 5.8 k
where VREF = 5.1 V Based on the E-12 series of resistor values, choose R5 to be 5.6 k and R4 to be 3.9 k to complete the design. In general, RDS(ON) has a positive temperature coefficient that needs to be considered when setting the threshold level. Variations in RDS(ON) will affect the selection of external or internal component values. High-Side Over-Current Sensing For positive load currents, high-side over current sensing also monitors the load condition and shuts down the switching operation if the load current exceeds the preset trip level.
where VDS(HIGH SIDE) = the drain to source voltage of the high-side MOSFET during high-side turn on VF(D1) = the forward drop voltage of D1 Since VDS(HIGH SIDE) is determined by the product of drain current ID and RDS(ON) of the high-side MOSFET. VCSH can be rewritten as:
VCSH = R3 (RDS ( ON ) I D + VF ( D1) ) R 2 + R3
Note: The reverse blocking diode D1 is forward biased by a 10 k resistor R1 when the high-side MOSFET is on.
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IRS20955(S)PbF
PRELIMINARY
CSH CSH Comparator OC + VB
R2 R1 R3
D1
+B
1.2V
HO
HO
Q1
VS
OUT Vcc
LO
Q2
IRS20955
-B
Figure 14. Programming High-Side Over-Current Threshold High-Side Over-Current Setting Figure 14 demonstrates the typical circuitry used for high-side current sensing. In the following example, the over current protection level is set to trip at 30 A using a MOSFET with an RDS(ON) of 100 m. The component values of R2 and R3 can be calculated using the following formula: Let R2 + R3=10 k.
R3 = 10 k VthOCH VDS + VF
W, a 200 V, 50 ns high speed switching diode, is more than sufficient. Deadtime Generator Deadtime is a blanking period inserted between high-side turn on and low-side turn on to prevent shoot through. In the IRS20955S, an internal deadtime generation block allows the user to select the optimum deadtime from a range of preset values. Selecting a preset deadtime through the DT/SD pin voltage can easily be done through an external voltage divider. This way of setting deadtime prevents outside noise from modulating the switching timing, which is critical to the audio performances. How to Determine Optimal Deadtime The effective deadtime in an actual application differs from the deadtime specified in this datasheet due to the switching fall time, tf.. The deadtime value in this datasheet is defined as the time period between the beginning of turn-off on one side of the switching stage and the beginning of turn-on on the other side as shown in Figure 15. The fall time of MOSFET gate voltage must be subtracted from the deadtime value in the datasheet to determine the effective deadtime of a Class D audio amplifier. (Effective deadtime) = (Deadtime in datasheet) - tf.
where VthOCL = 1.2 V VF = the forward voltage of reverse blocking diode D1 = 0.6 V. VDS@ID=30A = the voltage drop across the high-side MOSFET when the MOSFET current is 30 A. Therefore, VDS@ID=30A = ID x RDS(ON) = 30 A x 100 m =3V Based on the formulas above, R2 = 6.8 k and R3 = 3.3 k.
Choosing the Right Reverse Blocking Diode The selection of the appropriate reverse blocking diode used in place of D1 depends on its voltage rating and speed. To effectively block bus voltages, the reverse voltage must be higher than the voltage difference between +B and -B and the reverse recovery time must be as fast as the boot strap charging diode. A diode such as the Philips BAV21 www.irf.com
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IRS20955(S)PbF
Programming Deadtime
90%
PRELIMINARY
Effective dead - time
HO (or LO)
10%
tf LO (or HO) Dead-time in datasheet
10%
Figure 15. Effective Deadtime A longer deadtime period is required for a MOSFET with a larger gate charge value because of the longer tf.. Although a shorter effective deadtime setting is beneficial to achieving better linearity in Class D amplifiers, the likelihood of shoot-through current increases with narrower deadtime settings. Negative values of effective deadtime may cause excessive heat dissipation in the MOSFETs, leading to potentially serious damage. To calculate the optimal deadtime in a given application, the fall time tf for both HO and LO in the actual circuit need to be taken into account. In addition, variations in temperature and device parameters could also affect the effective deadtime in the actual circuit. Therefore, a minimum effective deadtime of 10 ns is recommended to avoid shootthrough current over the range of operating temperatures and supply voltages.
The IRS20955S selects the deadtime from a range of preset deadtime values based on the voltage applied at the DT pin. An internal comparator translates the DT input to a predetermined deadtime by comparing the input with internal reference voltages. These internal reference voltages are set in the IC through a resistive voltage divider using VCC. The relationship between the operation mode and the voltage at DT pin is illustrated in the Figure16 below.
Dead- time
15nS 25nS 35nS 45nS VDT
0.23 xVcc
0.36 xVcc
0.57 xVcc
Vcc
Figure 16. Deadtime vs. VDT Table 1 suggests pairs of resistor values used in the voltage divider for selecting deadtime. Resistors with up to 5% tolerance are acceptable when using these values.
IRS20955
>0.5mA
Vcc
R1
DT
R2
COM
Figure 17. External Voltage Divider
Table 1 Recommended Resistor Values for Deadtime Selection Deadtime Mode R1 R2 DT/SD Voltage DT1 Open 1.00(VCC) <10 k DT2 0.71(VCC) 3.3 k 8.2 k DT2 0.46(VCC) 5.6 k 4.7 k DT4 0.29(VCC) 8.2 k 3.3 k
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IRS20955(S)PbF
PRELIMINARY
Supplying VDD VDD is designed to be supplied with an internal Zener diode clamp. IDD, the supply current for VDD, can be estimated by: IDD 1.5 mA x 300 x 10-9 x switching frequency + 0.5 mA + 0.5 mA (Dynamic power consumption) (Static) (Zener bias) The value of RDD used to supply IDD should meet the following requirement:
RDD V+ B - 10.8 V I DD
[]
The value of this charging resistor is subject to several constraints: - The minimum value of RCHARGE is limited by the leakage current of the bootstrap voltage supply through RCHARGE, which would limit the maximum PWM modulation index of the system. - The maximum value of RCHARGE is limited by the current charge capability of the resistor during startup: I CHARGE > I QBS where ICHARGE = the current through RCHARGE IQBS = the high side quiescent current.
IQBC
Example: In the case where the average PWM switching frequency is 400 kHz, the required IDD is 1.18 mA. Based on this calculation, a 50 V power supply voltage would require RDD to be 33 k or less. Furthermore, make sure IDD is below the maximum zener diode bias current, IDDZ, during static state conditions.
I DDZ V+ B - 10.8 V - 0.5 mA Rdd
Rdd
IQBS
Figure 19. Boot Strap Supply Pre-charging Start-up Sequence (UVLO) The protection control block in the IRS20955S monitors the status of VDD and VCC to ensure that both voltage supplies are above the UVLO (undervoltage lockout) threshold before beginning normal operation. If either VDD or VCC is below the under voltage threshold, LO and HO are disabled in shutdown mode until both VDD and VCC rise above the voltage threshold. Power-down Sequence
-B
IRS20955S
VDD CSD IN PWM VSS NC VREF OCSET DT 10.4V CSH VB HO VS NC VCC LO COM
+B
Vcc 12V
Figure 18. Supplying VDD Charging VBS Prior to Start The high-side bootstrap capacitor can be charged through a resistor from the positive supply bus to the VB pin by utilizing an internal 20.8 V Zener diode between VB and VS. This scheme eliminates the need to charge the boot strap capacitor through lowside turn on during start-up. www.irf.com
As soon as VDD or VCC falls below the UVLO threshold, protection logic in the IRS20955S turns off LO and HO, shutting off the power MOSFETs.
Figure 20. IRS20955 UVLO Timing Chart 16
20.8V
20.8V
IRS20955(S)PbF
PMID = PZDD + PLDD
Power Supply Decoupling As the IRS20955S contains analog circuitry, careful attention must be given to decoupling the power supplies for proper operation. Ceramic capacitors of 0.1 F or more should be placed close to the power supply pins of the IC on the board. Please refer to the application note AN-978 for general design considerations of a high voltage gate driver IC. VSS Negative Bias Clamping VSS can go below COM when a negative supply is missing in a dual supply configuration. In this case, excessive negative VSS voltage with respect to COM could damage the IRS20955S. Having a diode to clamp potential negative biases to VSS is recommended to protect the IC. A standard recovery diode with a current rating of 1 A such as the 1N4002 is sufficient for this purpose.
VDD CSD IN VSS NC VREF Negative VSS Clamping Diode OCSET DT CSH VB HO VS NC VCC LO COM
V - VDD + BUS VDD RDD
PRELIMINARY
where PZDD = the power dissipation from the internal Zener diode clamping VDD PLDD = the power dissipation from the internal logic circuitry V+BUS = the positive bus voltage feeding VDD RDD = the resistor feeding VDD from V+BUS *For obtaining the value of RDD, refer to the section "Supplying VDD." 2. PLSM: Power Dissipation of the Input Level Shifter PLSM = 2 nC x fsw x VSS,BIAS where fSW = the PWM switching frequency VSS,BIAS = the bias voltage of VSS with respect to COM
3. PLOW: Power Dissipation in Low-Side
-Vbus
Figure 21. Negative VSS Clamping Junction Temperature Estimation The power dissipation in the IRS20955S is dominated by the following items: - PMID: Power dissipation of the floating input logic and protection circuitry - PLSM: Power dissipation of the input level shifter - PLOW: Power dissipation in low-side - PLSH: Power dissipation of the high-side level shifter - PHIGH: Power dissipation in high-side 1. PMID: Power Dissipation of the Floating Input Logic and Protection Circuitry The power dissipation of the floating input section is given by:
The power dissipation in low-side comes from the losses of the logic circuitry and the losses of driving LO.
PLOW = PLDD + PLO RO = (I QCC VCC ) + Vcc Qg f SW RO + Rg + Rg (int) where PLDD = the power dissipation from the internal logic circuitry
PLO = the power dissipation from the gate drive stage to LO RO = the output impedance of LO, typically 10 for the IRS20955S Rg(int) = the internal gate resistance of the low side MOSFET driver, typically 10 for the IRS20955S Rg = the external gate resistance of the low side MOSFET Qg = total gate charge of the low side MOSFET 17
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IRS20955(S)PbF
PRELIMINARY
4. PLSH: Power Dissipation of the High-Side Level Shifter PLSH = 0.4 nC x fsw x VBUS where fSW = the PWM switching frequency VBUS = the difference between the positive bus voltage and negative bus voltage Total power dissipation, Pd, is given by
Pd = PMID + PLSM + PLOW + PHSM + PHIGH .
Given Rth,JA, the thermal resistance between the ambient and junction temperature, TJ, the junction temperature, can be calculated from the formula provided below.
TJ = Rth , JA Pd + TA < 150 C
5. PHIGH: Power Dissipation in High-side The power dissipation in high-side comes from the losses of the logic circuitry and the losses of driving LO.
PHIGH = PLDD + PHO RO = (I QBS VBS ) + VBS Qg f SW RO + Rg + Rg (int) where
PLDD = the power dissipation from the internal logic circuitry PLO = the power dissipation from the gate drive stage to HO RO = equivalent output impedance of HO, typically 10 for the IRS20955S Rg(int) = the internal gate resistance of the highside MOSFET driver, typically 10 for the IRS20955S Rg = external gate resistance of the high-side MOSFET Q g = total gate charge of the high- side MOSFET
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IRS20955(S)PbF
PRELIMINARY
NOTES: 1. DIMENSIONING & TOLERANCING PER ANSI Y14.5W-1982 2. CONTROLLING DIMENSION. MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETER [INCHES] 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AC 5. DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE 6. DIMENSION DOES NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.15 [.006] 16-Lead SOIC (narrow body)
16-Lead PDIP
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01-6015 01-3065 00 (MS-001A)
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IRS20955(S)PbF
PRELIMINARY
LOADED TAPE FEED DIRECTION
B
A
H
D F C
NOTE : CONTROLLING DIM ENSION IN M M
E G
CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60
16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062
F
D C E B A
G
H
REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724
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IRS20955(S)PbF
PRELIMINARY
ORDER INFORMATION
16-Lead PDIP IRS20955PBF 16-Lead SOIC IRS20955SPbF 16-Lead SOIC Tape & Reel IRS20955STRPbF
SO-16 package is MSL3 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at IR's Web Site http://www.irf.com/
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice 12/11/2006
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