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Micrel, Inc.
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L Precision Edge(R) PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge(R)
FEATURES
Guaranteed AC performance * > 2.0GHz fMAX output toggle * > 3.0GHz fMAX input * < 800ps tPD (matched-delay between banks) * < 15ps within-device skew * < 190ps rise/fall time Low jitter design * < 1psRMS cycle-to-cycle jitter * < 10psPP total jitter Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) Precision differential LVDS outputs Matched delay: all outputs have matched delay, independent of divider setting TTL/CMOS inputs for select and reset/disable Two LVDS output banks (matched delay) * Bank A: Buffered copy of input clock (undivided) * Bank B: Divided output (/2, /4, /8, /16), two copies 3.3V power supply Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) package Precision Edge(R)
DESCRIPTION
This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89873L is part of Micrel's high-speed Precision Edge(R) timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram. All support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
SONET/SDH line cards Transponders High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
/RESET Enable FF Enable MUX
TYPICAL APPLICATION
622MHz/155.5MHz SONET Clock Generator
QA /QA
VREF-AC
IN 50 VT 50 /IN Divided by 2, 4, 8 or 16
QB0 /QB0 QB1 /QB1
622MHz LVPECL IN Clock In /IN
OC-12 or OC-3 Clock Gen
QA /QA
622MHz LVDS Clock Out
QB 155.5MHz LVDS Clock Out /QB
Bank B: 155.5MHz: For OC-3 line card Set to divide-by-4 Bank A: 622MHz: For OC-12 line card Set to pass-through
S0 Decoder S1
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
Rev.: F Amendment: /0
1
Issue Date: February 2007
Micrel, Inc.
Precision Edge(R) SY89873L
PACKAGE/ORDERING INFORMATION
VCC GND S0 S1
Ordering Information(1)
Part Number
12 11 10 9
16
15
14
13
Package Operating Type Range MLF-16 MLF-16 MLF-16 MLF-16 Industrial Industrial Industrial Industrial
Package Marking 873L 873L 873L with Pb-Free bar line indicator 873L with Pb-Free bar line indicator
Lead Finish Sn-Pb Sb-Pb NiPdAu Pb-Free NiPdAu Pb-Free
QB0 /QB0 QB1 /QB1
1 2 3 4 5 6 7 8
IN VT VREF-AC /IN
SY89873LMI SY89873LMITR(2) SY89873LMG(3) SY89873LMGTR(2, 3)
/QA
/RESET /DISABLE
QA
VCC
16-Pin MLF(R) (MLF-16)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number 1, 2, 3, 4 5, 6 7, 14 8 Pin Name QB0, /QB0 QB1, /QB1 QA, /QA VCC /RESET, /DISABLE IN, /IN VREF-AC VT GND S0, S1 Pin Function Differential Buffered Output Clocks: Divide by 2, 4, 8, 16. LVDS compatible. Differential Buffered Undivided Output Clock: LVDS compatible. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors. TTL/CMOS Compatible Output Reset and Disable: Internal 25k pull-up. Input threshold is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when LOW, Banks A and B will be disabled. Differential Input: Internal 50 termination resistors to VT input. See "Input Interface Applications" section. Reference Voltage: Equal to VCC-1.4V (approx.), and used for AC-coupled applications. Maximum sink/source current is 0.5mA. See "Input Interface Applications" section. Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise, see "Input Interface Applications" section. Ground: Exposed pad is internally connected to GND and must be connected to a ground plane for proper thermal operation. Select Pins: LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
12, 9 10 11 13 16, 15
TRUTH TABLE
/RESET /DISABLE 1 1 1 1 0 S1 0 0 1 1 X S0 0 1 0 1 X Bank A Output Input Clock Input Clock Input Clock Input Clock QA = LOW, /QA = HIGH(1) Bank B Outputs Input Clock / 2 Input Clock / 4 Input Clock / 8 Input Clock / 16 QB0 = LOW, /QB0 = HIGH(2) QB1 = LOW, /QB1 = HIGH(2)
Notes: 1. On the next negative transition of the input signal. 2. Asynchronous Reset/Disable function. See "Timing Diagram." M9999-020707 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89873L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................. -0.5V to +4.0V Input Voltage (VIN) .................................. -0.5V to VCC+0.3 LVDS Output Current (IOUT) .................................... 10mA Input Current IN, /IN (IIN) .......................................... 50mA VREF-AC Input Sink/Source Current (IVREF-AC)(3) ............ 2mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ...................................... +3.3V 10% Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance MLF(R) (JA) Still-Air ............................................................. 60C/W 500 lfpm ........................................................... 54C/W MLF(R) (JB)(4) Junction-to-Board ............................................ 38C/W
DC ELECTRICAL CHARACTERISTICS(5)
TA= -40C to +85C; Unless otherwise stated. Symbol VCC ICC RIN VIH VIL VIN VDIFF_IN |IIN| VREF-AC Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input High Voltage IN, /IN Input Low Voltage IN, /IN Input Voltage Swing Differential Input Voltage Swing Input Current IN, /IN Reference Voltage Note 6 Note 6 Notes 6, 7 Notes 6, 7, 8 Note 6 Note 9 No load, Max VCC 90 0.1 -0.3 0.1 0.2 45 VCC -1.525 VCC-1.425 VCC-1.325 Condition Min 3.0 Typ 3.3 85 100 Max 3.6 115 110 VCC+0.3 VCC+0.2 3.6 Units V mA V V V V mA V
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Due to the internal termination (see "Input Buffer Structure" ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! 7. See "Timing Diagram" for VIN definition. VIN(max) is specified when VT is floating. 8. See Figures 1c and 1d for VDIFF definition. 9. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89873L
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS(10)
VCC = 3.3V 10%; TA = -40C to +85C; Unless otherwise stated. Symbol VOUT VOH VOL VOCM VOCM Parameter Output Voltage Swing Output High Voltage Output Low Voltage Output Common Mode Voltage Change in Common Mode Voltage Condition Notes 11, 12 Note 11 Note 11 Note 11 0.925 1.125 -50 1.275 50 Min 250 Typ 350 Max 450 1.475 Units mV V V V mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(10)
VCC = 3.3V 10%; TA = -40C to +85C; Unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current -125 Condition Min 2.0 0.8 20 -300 Typ Max Units V V A A
Notes: 10. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 11. Measured as per Figure 1a, 100 across Q and /Q outputs. 12. See Figure 1c.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY89873L
AC ELECTRICAL CHARACTERISTICS(13)
VCC = 3.3V 10%; TA = -40C to +85C; Unless otherwise stated. Symbol fMAX Parameter Maximum Output Toggle Frequency (Bank A and Bank B) Maximum Input Frequency tPD tSKEW Differential Propagation Delay (IN-to-Q) Within-Device Skew (diff.) (QB0-to-QB1) Within-Device Skew (diff.) (Bank A-to-Bank B) Part-to-Part Skew (diff.) trr Tjitter tr, tf Reset Recovery Time Cycle-to-Cycle Jitter Total Jitter Rise / Fall Time (20% to 80%) Condition Output Swing: 200mV Note 14 Input Swing < 400mV Input Swing 400mV Note 15 Note 15 Note 15 Note 16 Note 17 Note 18 60 110 600 1 10 190 Min 2.0 3.2 550 500 660 610 7 12 800 750 15 30 250 Typ Max Units GHz GHz ps ps ps ps ps ps psRMS psPP ps
Notes: 13. Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100 between Q and /Q, unless otherwise stated. 14. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output /2, /4, /8, /16) can accept an input frequency >3GHz, while Bank A will be slew-rate limited. 15. Skew is measured between outputs under identical transitions. 16. See "Timing Diagram." 17. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn-Tn+1, where T is the time between rising edges of the output signal. 18. Total jitter definition: with an ideal clock input, of frequency fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
5
Micrel, Inc.
Precision Edge(R) SY89873L
LVDS OUTPUT
50 1% VOUT VOH, VOL VOH, VOL 100 1% 50 1% VOCM, VOCM
GND
GND
Figure 1a. LVDS Differential Measurement
Figure 1b. LVDS Common Mode Measurement
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
VIN, VOUT 350mV (Typical)
VDIFF_IN, VDIFF_OUT 700mV (Typical)
Figure 1c. Single-Ended Swing
Figure 1d. Differential Swing
TIMING DIAGRAM
/RESET
VCC/2 tRR
IN /IN
VIN (Swing)
tPD
QB VOUT (Swing) /QB
QA /QA
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
6
Micrel, Inc.
Precision Edge(R) SY89873L
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25C, unless otherwise stated.
Output Amplitude vs. Frequency
350 QA AMPLITUDE (mV) 300 250 200 150 100 50 0 0 500 1000 1500 2000 2500 FREQUENCY (MHz) PROPAGATION DELAY (ps) 800
Nominal Propagation Delay vs. Input Swing
700
600
500
400
0
200 400 600 800 1000 1200 INPUT SWING (mV)
Nominal Propagation Delay vs. Temperature
800 PROPAGATION DELAY (ps)
700
600
500
400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C)
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
7
Micrel, Inc.
Precision Edge(R) SY89873L
FUNCTIONAL CHARACTERISTICS
Conditions: VCC = 3.3V, TA = 25C, unless otherwise stated.
QA @ 622MHz and QB @ 155.5MHz (Divided-by-4)
QA
QA Output @ 1.25GHz
Output Swing (100mV/div.)
/QA QB
/4
622MHz
/QB
155MHz
Output Swing (50mV/div.)
TIME (1ns/div.)
TIME (100ps/div.)
QA Output @ 2.0GHz
Q
Output Swing (50mV/div.)
/Q
TIME (100ps/div.)
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
8
Micrel, Inc.
Precision Edge(R) SY89873L
INPUT BUFFER STRUCTURE
VCC
VCC
1.86k
1.86k
25k S0 S1 /RESET
R
1.86k IN 50 VT 50 /IN GND
1.86k
R
GND
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified TTL/CMOS Input
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
9
Micrel, Inc.
Precision Edge(R) SY89873L
INPUT INTERFACE APPLICATIONS
VCC = 3.3V
VCC = 3.3V VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
IN LVPECL /IN SY89873L GND VCC-2V* VT .01F 50 NC VCC
* Bypass with 0.01F to VCC
IN CML /IN SY89873L GND NC NC VT VREF-AC
IN CML /IN SY89873L GND VCC VT VREF-AC 0.01F
VREF-AC
Figure 3a. DC-Coupled CML Input Interface
Figure 3b. AC-Coupled CML Input Interface
Figure 3c. DC-Coupled LVPECL Input Interface
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
IN LVPECL /IN 100 100 VCC GND GND 0.01F VT VREF-AC SY89873L
GND NC NC LVDS
IN /IN SY89873L VT VREF-AC
Figure 3d. AC-Coupled LVPECL Input Interface
Figure 3e. LVDS Input Interface
Figure 3f. HSTL Input Interface
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY89871U SY89872U Function 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination 2.5V 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer w/Internal Termination MLF(R) Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy89871u.shtml www.micrel.com/product-info/products/sy89872u.shtml www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf www.micrel.com/product-info/products/solutions.shtml
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
10
Micrel, Inc.
Precision Edge(R) SY89873L
16-PIN MicroLeadFrame(R) (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
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