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SY89856U
2GHz, Low-Power, 1:6 LVPECL Fanout Buffer with 2:1 Input MUX and Internal Termination
General Description
The SY89856U is a 2.5V/3.3V precision, highspeed, 1:6 fanout capable of handling clocks up to 2.0GHz. A differential 2:1 MUX input is included for redundant clock switchover applications. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the device to interface to any differential signal (AC- or DCcoupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are LVPECL (100k, temperature compensated), with extremely fast rise/fall times guaranteed to be less than 200ps. The SY89856U operates from a 2.5V 5% supply or a 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89856U is part of Micrel's high-speed, Precision (R) Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* 6 ultra-low skew copies of the selected input * 2:1 MUX input included for clock switchover applications * Low power: 225mW typical (2.5V) * 2.5V to 3.3V supply voltage * Unique input isolation design minimizes crosstalk * Guaranteed AC performance over temperature and voltage: - Clock frequency range: DC to >2.0GHz - <400ps IN-to-OUT tpd - <200ps tr/tf times - <30ps skew (output-to-output) * Ultra-low jitter design: - <1psRMS random jitter - <10psPP total jitter (clock) - <1psRMS cycle-to-cycle jitter - <0.7psRMS crosstalk-induced jitter * Unique input termination and VT pin accepts DCand AC-coupled inputs (CML, PECL, LVDS) * 100k LVPECL compatible output swing * -40C to +85C industrial temperature range * Available in 32-pin (5mm x 5mm) MLF(R) package
Functional Block Diagram
Applications
* * * * * * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame registered are trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
Redundant clock distribution All SONET/SDH clock/data distribution All Fibre Channel distribution All Gigabit Ethernet clock distribution
Markets
LAN/WAN Enterprise servers ATE Test and measurement
February 2007
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Micrel, Inc.
SY89856U
Ordering Information(1)
Part Number SY89856UMG SY89856UMGTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
(2)
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY89856U with Pb-Free bar-line indicator SY89856U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF(R) (MLF-32)
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SY89856U
Pin Description
Pin Number 1,4 5, 8 Pin Name IN0, /IN0 IN1, /IN1 Pin Function Differential Input: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVp-p). Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VTI pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The MUX select switchover function is asynchronous. No connect. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible. Differential Outputs: These 100k (temperature compensated) LVPECL output pairs are low skew copies of the selected input. Unused output pins may be left floating. Please refer to the "LVPECL Output Interface Applications" for details.
2, 6
VT0, VT1
31
SEL
10 11, 16, 18, 23, 25, 30 29, 28 27, 26 22, 21 20, 19 15, 14 13, 12 9, 17, 24, 32 3, 7
NC VCC Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, Q4, /Q4, Q5, /Q5 GND, Exposed Pad VREF-AC0 VREF-AC1
Ground: Ground pins and exposed pad must be connected to the same ground plane. Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs (IN, /IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Maximum sink/source current is 1.5mA. Due to the limited drive capability use for input at the same package only.
LVPECL Output Interface Applications
SEL 0 1 Output IN0 Input Selected IN1 Input Selected
February 2007
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Micrel, Inc.
SY89856U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ..........................-0.5V to +4.0V Input Voltage (VIN) ..................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous ................................................. 50mA Surge........................................................ 100mA Termination Current Source or sink current on VT .................. 100mA VREF-AC Source or sink current............ ......... 2.0mA Lead Temperature (soldering, 20 sec.) ..........+260C Storage Temperature (Ts)..................-65C to 150C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ..................................................... 35C/W MLF(R) (JB) Junction-to-Board .................................... 16C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to an absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Power Supply Voltage Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| IN-to-VT (IN, /IN) Output Reference Voltage
Condition
Min 2.375 3.0
Typ 2.5 3.3 90 50 100
Max 2.625 3.6 140 55 110 VCC VIH-0.1 1.7
Units V V mA V V V V
No load, max VCC. 45 90 VIH-1.2 0 See Figure 1a. See Figure 1b. 0.1 0.2
1.28 VCC-1.3 VCC-1.2 VCC-1.1
V V
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SY89856U
LVPECL Outputs DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50 to VCC - 2V, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF-OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1.1 800 1.6 Typ Max VCC-0.895 VCC-1.695 Units V V mV V
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89856U
AC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated.
Symbol fMAX tpd Parameter Maximum Operating Frequency Differential Propagation Delay (IN0 or IN1-to-Q) (SEL-to-Q) tpd Tempco tSKEW tJITTER Differential Propagation Delay Temperature Coefficient Output-to-Output Part-to-Part Clock Cycle-to-Cycle Jitter Deterministic Jitter (DJ) Random Jitter (RJ) Total Jitter (TJ) Adjacent Channel Crosstalk-Induced Jitter tr, tf
Notes: 7. 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Output-to-output skew is measured between outputs under identical input conditions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
Condition VOUT 400mV
Min 2.0 200 140
Typ 3.0 280
Max
Units GHz
400 460
ps ps fs/oC
65 Note 8 Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 Full swing, 20% to 80%. 75 130 10 30 150 1 10 1 10 0.7 200
ps ps ps(rms) ps(rms) ps(pp) ps(pp) ps(rms) ps
Output Rise/Fall Time
10. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 11. Deterministic Jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2 -1 PRBS pattern. 12. Random Jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 13. Total Jitter definition: with an ideal clock input of frequency 12 23
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SY89856U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, VIN 400mV, tr/tf 300ps, TA = 25C, unless otherwise stated.
Output Swing vs. Frequency
900 800
OUTPUT SWING (mV)
700 600 500 400 300 200 100 0 0 1000 2000 3000 4000 5000 6000 FREQUENCY (MHz)
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN 400mV, tr/tf 300ps, TA = 25C, unless otherwise stated.
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SY89856U
Singled-Ended and Differential Swings
VDIFF_IN DIFF_OUT ,V
VIN, VOUT 800mV (typical)
1600mV t ypical) (
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagrams
IN /IN tpd Q /Q Input-to-Q tpd
SEL tpd Q /Q Select-to-Q tpd tpd
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SY89856U
Input and Output Stages
VCC
VCC
IN 50 VT 50 /IN GND
/Q Q
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
Input Interface Applications
VCC
VCC
VCC IN CML /IN
IN
LVPECL
IN
LVPECL
VCC GND RP 0.1F
/IN SY89856U VT NC VREF-AC
/IN RP GND GND RP VCC 0.1F VT VREF-AC
For 3.3V, RP For 2.5V, RP
SY89856U
GND NC NC VT
SY89856U
Note: For 3.3V, RP For 2.5V, RP
VREF-AC
Option: may connect VT to VCC Figure 3c. CML Interface (DC-Coupled)
Figure 3a. LVPECL Interface (DC-Coupled)
VCC
Figure 3b. LVPECL Interface (AC-Coupled)
VCC IN LVDS /IN
IN CML /IN VCC GND 0.1F VT VREF-AC SY89856U
GND NC NC
SY89856U VT VREF-AC
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface (DC-Coupled)
February 2007
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SY89856U terminating the LVPECL output: Parallel Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
LVPECL Output Interface Applications
LVPECL has a high input impedance and a very low output impedance (open emitter), and a small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100-controlled impedance transmission lines. There are several techniques for
+3.3V
+3.3V
Z Z
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
source
destination Rb C1 0.01F (optional)
VCC
R2 82
R2 82
Notes:
Notes: 1. For 2.5V systems, R1 = 250, R2 = 62.5.
2. Power-saving alternative to Thevenin termination. 3. Place termination resistors as close to destination inputs as possible. 4. Rb resistor sets the DC bias voltage, equal to VT. 5. For 2.5V systems, Rb = 19.
Figure 4a. Parallel Termination-Thevenin Equivalent
Figure 4b. Parallel Termination (3-Resistors)
Related Documentation
Part Number
SY58035U
Function
4.5GHz, 1:6 LVPECL Fanout Buffer with 2:1 MUX Input and Internal Termination MLF Application Note
(R)
Data Sheet Link
www.micrel.com/product-info/products/sy58035u.html www.amkor.com/products/notes_papers/MLFappnote.pdf www.micrel.com/product-info/products/solutions.shtml
HBW Solutions
New Products and Applications
February 2007
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Micrel, Inc.
SY89856U
32-Pin MicroLeadFrame(R) (MLF-32)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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