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NBSG14 2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL* Outputs
*Reduced Swing ECL
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The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for ultra-low skew and jitter. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
MARKING DIAGRAM*
SG 14 LYW
* * * * * * *
Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output 50 W Internal Input Termination Resistors
FCBGA-16 BA SUFFIX CASE 489
QFN-16 MN SUFFIX CASE 485G
SG14 ALYW
* * Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NBSG14BA NBSG14BAR2 Package 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units/Tray 500 / Tape & Reel
NBSG14MN
123 Units / Rail
NBSG14MNR2
3000 / Tape & Reel
Board NBSG14BAEVB
Description NBSG14BA Evaluation Board
(c) Semiconductor Components Industries, LLC, 2003
1
August, 2003 - Rev. 7
Publication Order Number: NBSG14/D
NBSG14
1 A 2 3 4 VEE 16
VTCLK
Q0 15
Q0 14
VCC 13
Exposed Pad (EP)
Q3
Q3
Q2
VTCLK B
CLK VEE VCC Q2
1 2 NBSG14 3 4
12 Q1 11 Q1 10 Q2 9 Q2
CLK CLK
C
CLK
VEE
VCC
Q1
VTCLK D
VTCLK
Q0
Q0
Q1
5 VEE
6 Q3
7 Q3
8 VCC
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin BGA D1 C1 QFN 1 2 Name VTCLK CLK I/O - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - RSECL Output RSECL Output - RSECL Output RSECL Output RSECL Output RSECL Output RSECL Output RSECL Output - Description Internal 50 W Termination pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
CLK
Noninverted Differential Input. Internal 75 kW to VEE.
A1 B2,C2 A2* A3* B3,C3 A4* B4* C4* D4* D3* D2* N/A
4 5,16 6 7 8,13 9 10 11 12 14 15 -
VTCLK VEE Q3 Q3 VCC Q2 Q2 Q1 Q1 Q0 Q0 EP
Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Inverted Differential Output 3. Typically Terminated with 50 W to VTT = VCC - 2 V* Noninverted Differential Output 3. Typically Terminated with 50 W to VTT = VCC - 2 V* Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Inverted Differential Output 2. Typically Terminated with 50 W to VTT = VCC - 2 V* Noninverted Differential Output 2. Typically Terminated with 50 W to VTT = VCC - 2 V* Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V* Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V* Inverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC - 2 V* Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC - 2 V* Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no signal is applied then the device will be susceptible to self-oscillation. *Devices in BGA package typically terminated with 50 W to VTT = VCC-1.5 V.
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VCC Q3 Q3 VTCLK 36.5 KW 50 W CLK CLK 50 W VTCLK 75 KW 75 KW Q2 Q2
Q1 Q1
VEE
Q0 Q0
Figure 3. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK and VTCLK to VCC Connect VTCLK and VTCLK Together Bias VTCLK and VTCLK Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques An External Voltage (VTHR) should be Applied to the Unused Differential Input. Nominal VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification.
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Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor (CLK, CLK) Internal Input Pullup Resistor (CLK) ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Human Body Model Machine Model FCBGA-16 QFN-16 Oxygen Index: 28 to 34 Value 75 kW 36.5 kW > 2 kV > 100 V Level 3 Level 1 UL 94 V-0 @ 0.125 in 158
Table 4. MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI VINPP IIN IOUT TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |CLK-CLK| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 2S2P (Note 3) 2S2P (Note 4) < 15 Seconds 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w 2.8 V VCC - VEE < 2.8 V Static Surge Continuous Surge 16 FCBGA 16 QFN VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC-VEE| 45 80 25 50 -40 to +70 -40 to +85 -65 to +150 108 86 41.6 35.2 5 4.0 225 Units V V V V V mA mA mA mA C C C/W C/W C/W C/W C/W C/W C
qJC Tsol
Thermal Resistance (Junction-to-Case) Wave Solder
2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOUTPP VIH VIL VTHR VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 6) Output Amplitude Voltage Input HIGH Voltage (Single-Ended) (Notes 8 and 10) Input LOW Voltage (Single-Ended) (Notes 9 and 10) Input Threshold Voltage (Single-Ended) (Note 10) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 45 1525 315 VCC- 1435 VIH- 2500 VEE + 1125 1.2 Typ 60 1575 405 VCC- 1000* VCC- 1400* Max 75 1625 495 VCC VIH- 150 VCC- 75 2.5 Min 45 1550 315 VCC- 1435 VIH- 2500 VEE + 1125 1.2 25C Typ 60 1610 405 VCC- 1000* VCC- 1400* Max 75 1650 495 VCC VIH- 150 VCC- 75 2.5 70C(BGA)/85C(QFN)** Min 45 1575 315 VCC- 1435 VIH- 2500 VEE + 1125 1.2 Typ 60 1635 405 VCC- 1000* VCC- 1400* Max 75 1675 495 VCC VIH- 150 VCC- 75 2.5 Unit mA mV mV mV mV mV V
RTIN IIH IIL
45
50 80 25
55 150 100
45
50 80 25
55 150 100
45
50 80 25
55 150 100
W mA mA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.5 V. 6. All outputs loaded with 50 W to VCC - 1.5 V for BGA package and VCC - 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical). 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 8. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 9. VIL always VEE. |VIL - VTHR| < 2600 mV. 10. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C. Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11) -40C Symbol IEE VOH VOUTPP VIH VIL VTHR VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 12) Output Amplitude Voltage Input HIGH Voltage (Single-Ended) (Notes 14 and 16) Input LOW Voltage (Single-Ended) (Notes 15 and 16) Input Threshold Voltage (Single-Ended) (Note 16) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 45 2325 350 VCC- 1435 VIH- 2500 VEE + 1125 1.2 Typ 60 2375 440 VCC- 1000* VCC- 1400* Max 75 2425 530 VCC VIH- 150 VCC- 75 3.3 Min 45 2350 350 VCC- 1435 VIH- 2500 VEE + 1125 1.2 25C Typ 60 2410 440 VCC- 1000* VCC- 1400* Max 75 2450 530 VCC VIH- 150 VCC- 75 3.3 70C(BGA)/85C(QFN)** Min 45 2375 350 VCC- 1435 VIH- 2500 VEE + 1125 1.2 Typ 60 2435 440 VCC- 1000* VCC- 1400* Max 75 2475 530 VCC VIH- 150 VCC- 75 3.3 Unit mA mV mV mV mV mV V
RTIN IIH IIL
45
50 80 25
55 150 100
45
50 80 25
55 150 100
45
50 80 25
55 150 100
W mA mA
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.165 V. 12. All outputs loaded with 50 W to VCC - 1.5 V for BGA package and VCC - 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical). 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 14. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 15. VIL always VEE. |VIL - VTHR| < 2600 mV. 16. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C.
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Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 17) -40C Symbol IEE VOH VOUTPP Characteristic Negative Power Supply Current Output HIGH Voltage (Note 18) Output Amplitude Voltage -3.465 V v VEE v -3.0 V -3.0 V < VEE v -2.375 V Input HIGH Voltage (Single-Ended) (Notes 20 and 22) Input LOW Voltage (Single-Ended) (Notes 21 and 22) Input Threshold Voltage (Single-Ended) (Note 22) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 45 -975 350 315 VCC- 1435 VIH- 2500 VEE + 1125 VEE + 1.2 Typ 60 -925 440 405 VCC- 1000* VCC- 1400* Max 75 -875 530 495 VCC VIH- 150 VCC- 75 0.0 Min 45 -950 350 315 VCC- 1435 VIH- 2500 VEE + 1125 VEE + 1.2 25C Typ 60 -890 440 405 VCC- 1000* VCC- 1400* Max 75 -850 530 495 VCC VIH- 150 VCC- 75 0.0 70C(BGA)/85C(QFN)** Min 45 -925 350 315 VCC- 1435 VIH- 2500 VEE + 1125 VEE + 1.2 Typ 60 -865 440 405 VCC- 1000* VCC- 1400* Max 75 -825 530 495 VCC VIH- 150 VCC- 75 0.0 mV mV mV V W mA mA Unit mA mV mV
VIH VIL VTHR VIHCMR
RTIN IIH IIL
45
50 80 25
55 150 100
45
50 80 25
55 150 100
45
50 80 25
55 150 100
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 17. Input and output parameters vary 1:1 with VCC. 18. All outputs loaded with 50 W to VCC -1.5 V for BGA package and VCC - 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical). 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 20. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 21. VIL always VEE. |VIL - VTHR| < 2600 mV. 22. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C.
Table 8. AC CHARACTERISTICS for FCBGA-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4) (Note 23) Propagation Delay to Output Differential Duty Cycle Skew (Note 24) Within-Device Skew (Note 25) Device-to-Device Skew (Note 26) RMS Random Clock Jitter (Figure 4) (Note 28) fin < 10 GHz Peak-to-Peak Data Dependent Jitter (Note 29) fin < 10 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 27) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q 75 20 30 Min 10.7 100 Typ 12 125 2 6 25 0.2 150 10 15 50 1 Max Min 10.7 100 25C Typ 12 125 2 6 25 0.2 10 2600 55 75 20 30 2600 55 75 20 30 2600 55 mV ps 150 10 15 50 1 Max Min 10.7 100 70C Typ 12 125 2 6 25 0.2 150 10 15 50 1 Max Unit GHz ps ps
tJITTER
ps
VINPP tr tf
23. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC - 1.5 V. Input edge rates 40 ps (20% - 80%). 24. See Figure 6. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 25. Within-Device skew is measured between outputs under identical transitions and conditions on any one device. 26. Device-to-device skew for identical transitions at identical VCC levels. 27. VINPP (MAX) cannot exceed VCC - VEE (applicable only when VCC-VEE < 2600 mV). 28. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz. 29. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 231-1 data at 10 Gb/s.
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Table 9. AC CHARACTERISTICS for QFN-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4) (Note 30) Propagation Delay to Output Differential Duty Cycle Skew (Note 31) Within-Device Skew (Note 32) Device-to-Device Skew (Note 33) RMS Random Clock Jitter (Figure 4) (Note 35) fin < 10 GHz Peak-to-Peak Data Dependent Jitter (Note 36) fin < 10 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 34) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q 75 15 30 Min 10.5 90 Typ 12 125 3 6 25 0.2 160 15 15 50 1 Max Min 10.5 90 25C Typ 12 125 3 6 25 0.2 10 2600 55 75 20 30 2600 55 75 20 30 2600 55 mV ps 160 15 15 50 1 Max Min 10.5 90 85C Typ 12 125 3 6 25 0.2 160 15 15 50 1 Max Unit GHz ps ps
tJITTER
ps
VINPP tr tf
30. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%) 31. See Figure 6. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 32. Within-Device skew is measured between outputs under identical transitions and conditions on any one device. 33. Device-to-device skew for identical transitions at identical VCC levels. 34. VINPP (MAX) cannot exceed VCC - VEE (applicable only when VCC-VEE < 2600 mV). 35. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz. 36. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 231-1 data at 10 Gb/s. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 10 9 400 OUTPUT AMPLITUDE 300 8 JITTERout ps (RMS) 7 6 5 4 3 2 1 0
200
100
CCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCC NNNN CCCCCCCCCCCCCCCCCC NNNN CCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCC NNNNNNN CCCCCCCCCCCCCCCCCC NNNNNNN CCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCC
OUTPUT P-P SPEC (AMPLITUDE GUARANTEE) RMS JITTER 0 1 2 3 4 5 6 7 8 9 10 11 12 INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
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X = 17 ps/DIV, Y = 53 mV/DIV
Figure 5. Eye Diagram at 10.8 Gbps (VCC - VEE = 3.3 V @ 255C with Input Data Pattern of 2^31-1 PRBS. Total Pk-Pk System Jitter Including Signal Generator is 18 ps. This Data was taken by Acquiring 7000 Waveforms.)
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D/CLK VINPP = = VIH(CLK) - VIL(CLK) D/CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPLH tPHL
Figure 6. AC Reference Measurement
Zo = 50 W Q Driver Device Q 50 W 50 W Zo = 50 W D D Receiver Device
VTT VTT = VCC - 1.5 V (BGA PACKAGE) VTT = VCC - 2.0 V (QFN PACKAGE)
Figure 7. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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PACKAGE DIMENSIONS
FCBGA-16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
-X- D M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC
-Y- K E
M 0.20
3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D
e
4
3
2
1
3
16 X
b 0.15 0.08
M M
S VIEW M-M
ZXY Z
5 0.15 Z A A2 -Z-
A1
16 X
4 DETAIL K
0.10 Z
ROTATED 90 _ CLOCKWISE
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PACKAGE DIMENSIONS
16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE A
-X- A M -Y-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
DIM A B C D E F G H J K L M N P R
C K -T-
SEATING PLANE
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
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