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MC74LVX574 Octal D-Type Flip-Flop with 3-State Outputs The MC74LVX574 is an advanced high speed CMOS octal flip-flop with 3-state outputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. This 8-bit D-type flip-flop is controlled by a clock pulse input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. Features http://onsemi.com MARKING DIAGRAMS 20 SOIC-20 DW SUFFIX CASE 751D 1 LVX574 AWLYYWW * * * * * * * * * High Speed: tPD = 8.5 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available* 20 1 20 TSSOP-20 DT SUFFIX CASE 948E 1 LVX 574 ALYW 20 1 20 VCC 20 O0 19 O1 18 O2 17 O3 16 O4 15 O5 14 O6 13 O7 12 CP 11 20 1 SOEIAJ-20 M SUFFIX CASE 967 1 74LVX574 AWLYWW 1 OE 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 GND A L, WL Y, YY W, WW = = = = Assembly Location Wafer Lot Year Work Week Figure 1. 20-Lead Pinout (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2005 1 March, 2005 - Rev. 2 Publication Order Number: MC74LVX574/D MC74LVX574 D0 2 C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D 11 1 19 Q0 D1 3 18 Q1 D2 4 17 PIN NAMES Q2 Pins OE CP D0-D7 O0-O7 Function Output Enable Input Clock Pulse Input Data Inputs 3-State Latch Outputs D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 FUNCTION TABLE INPUTS OE CP D H L X X OUTPUT Q H L No Change Z D7 9 12 Q7 CP OE L L L H L, H, X Figure 2. Logic Diagram ORDERING INFORMATION Device MC74LVX574DWR2 MC74LVX574DWR2G MC74LVX574DT MC74LVX574DTR2 MC74LVX574M MC74LVX574MG MC74LVX574MEL MC74LVX574MELG Package SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 1000 Tape & Reel 1000 Tape & Reel 75 Units / Rail 2500 Tape & Reel 40 Units / Rail 40 Units / Rail 2000 Tape & Reel 2000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I I III I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I III I I II I I I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I III I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. DC ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS MAXIMUM RATINGS Symbol Symbol SymbolIIIIIIIIIIIIIIIIIIIIII Parameter Dt/DV VOH VCC VCC Vout Vout VOL Tstg VIH ICC ICC IOK IOZ Iout VIL Vin Vin PD TA IIK Iin Quiescent Supply Current Maximum 3-State Leakage Current Input Leakage Current Low-Level Output Voltage (Vin = VIH or VIL) High-Level Output Voltage (Vin = VIH or VIL) Low-Level Input Voltage High-Level Input Voltage Input Rise and Fall Time Operating Temperature, All Package Types DC Output Voltage DC Input Voltage DC Supply Voltage Storage Temperature Power Dissipation DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage Parameter Parameter IOH = -50mA IOH = -50mA IOH = -4mA Vin = VCC or GND Vin = VIL or VIH Vout = VCC or GND Vin = 5.5V or GND IOL = 50mA IOL = 50mA IOL = 4mA Test Conditions http://onsemi.com MC74LVX574 3 VCC V 3.6 3.6 3.6 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.6 2.0 3.0 3.6 1.9 2.9 2.58 Min 1.5 2.0 2.4 TA = 25C Typ 0.0 0.0 2.0 3.0 0.1 0.1 0.36 Max 0.2 5 0.1 0.5 0.8 0.8 4.0 -0.5 to VCC +0.5 TA = - 40 to 85C Min -65 to +150 -0.5 to +7.0 -0.5 to +7.0 -40 2.0 1.9 2.9 2.48 Min 0 0 0 1.5 2.0 2.4 Value 180 -20 75 25 20 0.1 0.1 0.44 40.0 2.5 1.0 0.5 0.8 0.8 Max Max VCC +85 100 5.5 3.6 Unit Unit mW mA mA mA mA _C mA mA mA V V V V V V V ns/V Unit _C V V V MC74LVX574 III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I III I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I III I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I III I I II I I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I IIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbol fmax Parameter TA = 25C Typ 115 60 TA = - 40 to 85C Min 50 40 65 45 Max Test Conditions Min 60 45 80 50 Max Unit ns Maximum Clock Frequency (50% Duty Cycle) VCC = 2.7V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF VCC = 3.3 0.3V VCC = 2.7V 125 75 tPLH, tPHL Propagation Delay CP to O 9.2 11.5 8.5 11.0 9.8 11.4 14.5 18.0 13.2 16.7 15.0 18.5 12.8 16.3 19.1 15.0 1.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 17.5 21.0 15.5 19.0 18.5 22.0 15.0 18.5 22.0 17.0 1.5 1.5 ns VCC = 3.3 0.3V VCC = 2.7V RL = 1kW tPZL, tPZH Output Enable Time OE to O ns VCC = 3.3 0.3V RL = 1kW VCC = 2.7V RL = 1kW 8.2 10.7 tPLZ, tPHZ Output Disable Time OE to O 12.1 11.0 ns VCC = 3.3 0.3V RL = 1kW VCC = 2.7V VCC = 3.3 0.3V CL = 50pF tOSHL tOSLH Output-to-Output Skew (Note 1) CL = 50pF CL = 50pF ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design. CAPACITIVE CHARACTERISTICS TA = 25C Typ 4 6 TA = - 40 to 85C Min Max 10 Symbol Cin Parameter Min Max 10 Unit pF pF pF Input Capacitance Cout CPD Maximum Three-State Output Capacitance Power Dissipation Capacitance (Note 2) 28 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package) TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.5 -0.5 Max 0.8 -0.8 2.0 0.8 Unit V V V V TIMING REQUIREMENTS (Input tr = tf = 3.0ns) TA = 25C Symbol tw(h) tsu th Parameter Minimum Pulse Width, CP Minimum Setup Time, D to CP Minimum Hold Time, D to CP Test Conditions VCC = 2.7V VCC = 3.3 0.3V VCC = 2.7V VCC = 3.3 0.3V VCC = 2.7V VCC = 3.3 0.3V Typ Limit 6.5 5.0 5.0 3.5 1.5 1.5 TA = - 40 to 85C Limit 7.5 5.0 5.0 3.5 1.5 1.5 Unit ns ns ns http://onsemi.com 4 MC74LVX574 SWITCHING WAVEFORMS CP 50% tw 1/fmax tPLH tPHL VCC GND Q 50% VCC Figure 3. OE 50% tPZL O 50% VCC tPZH O 50% VCC tPHZ tPLZ VCC VOL +0.3V GND HIGH VOL -0.3V IMPEDANCE D 50% tsu CP HIGH IMPEDANCE th 50% VALID VCC GND VCC GND Figure 4. Figure 5. TEST CIRCUITS TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 6. Propagation Delay Test Circuit Figure 7. Three-State Test Circuit http://onsemi.com 5 MC74LVX574 PACKAGE DIMENSIONS SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G D A 11 X 45 _ q H M B M 20 10X 0.25 E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 1 10 20X B 0.25 M B TA S B S A SEATING PLANE h 18X e A1 T C TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B 20X K REF M L 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 L PIN 1 IDENT 1 10 B -U- J J1 N 0.15 (0.006) T U S A -V- N F C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E http://onsemi.com 6 IIII IIII IIII SECTION N-N M DETAIL E 20 11 K K1 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M MC74LVX574 PACKAGE DIMENSIONS SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032 20 11 LE Q1 M_ L DETAIL P E HE 1 10 Z D e VIEW P A c b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 7 MC74LVX574 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74LVX574/D |
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