View ICM722805_729943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ICM7228
Data Sheet December 6, 2005 FN3160.8
8-Digit, Microprocessor-Compatible, LED Display Decoder Driver
The Intersil ICM7228 display driver interfaces microprocessors to an 8-digit, 7-segment, numeric LED display. Included on chip are two types of 7-segment decoder, multiplex scan circuitry, LED display segment drivers, LED display digit drivers and an 8-byte static memory as display RAM. Data can be written to the ICM7228A and ICM7228B's display RAM in sequential 8-digit update or in single-digit update format. Data is written to the ICM7228C display RAM in parallel random access format. The ICM7228A and ICM7228C drive common anode displays. The ICM7228B drives common cathode displays. All versions can display the RAM data as either Hexadecimal or Code B format. The ICM7228A and ICM7228B incorporate a No Decode mode allowing each bit of each digit's RAM word to drive individual display segments resulting in independent control of all display segments. As a result, bargraph and other irregular display segments and formats can be driven directly by this chip. The Intersil ICM7228 is an alternative to both the Maxim ICM7218 and the Intersil ICM7218 display drivers. Notice that the ICM7228A/B has an additional single digit access mode. This could make the Intersil ICM7218A/B software incompatible with ICM7228A/B operation.
Features
* Pb-Free Plus Anneal Available (RoHS Compliant) * Improved 2nd Source to Maxim ICM7218 * Fast Write Access Time of 200ns * Multiple Microprocessor Compatible Versions * Hexadecimal, Code B and No Decode Modes * Individual Segment Control with "No Decode" Feature * Digit and Segment Drivers On-Chip * Non-Overlapping Digits Drive * Common Anode and Common Cathode LED Versions * Low Power CMOS Architecture * Single 5V Supply
Applications
* Instrumentation * Test Equipment * Hand Held Instruments * Bargraph Displays * Numeric and Non-Numeric Panel Displays * High and Low Temperature Environments where LCD Display Integrity is Compromised
Ordering Information
PART NUMBER ICM7228AIBI ICM7228AIBIZ (Note) ICM7228AIPI ICM7228AIPIZ (Note) ICM7228BIBI ICM7228BIBIZ (Note) ICM7228BIPI ICM7228BIPIZ (Note) ICM7228CIBI PART MARKING ICM7228AIBI 7228AIBIZ ICM7228AIPI ICM7228AIPI ICM7228BIBI ICM7228BIBIZ ICM7228BIPI ICM7228BIPIZ ICM7228CIBI DATA ENTRY PROTOCOL Sequential Sequential Sequential Sequential Sequential Sequential Sequential Sequential Random Random Random Random DISPLAY TYPE Common Anode Common Anode Common Anode Common Anode Common Cathode Common Cathode Common Cathode Common Cathode Common Anode Common Anode Common Anode Common Anode TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 28 Ld SOIC 28 Ld SOIC (Pb-free) 28 Ld PDIP 28 Ld PDIP* (Pb-free) 28 Ld SOlC 28 Ld SOlC (Pb-free) 28 Ld PDIP 28 Ld PDIP (Pb-free) 28 Ld SOlC 28 Ld SOlC (Pb-free) 28 Ld PDIP 28 Ld PDIP (Pb-free) PKG. DWG. # M28.3 M28.3 E28.6 E28.6 M28.3 M28.3 E28.6 E28.6 M28.3 M28.3 E28.6 E28.6
ICM7228CIBIZ (Note) ICM7228CIBIZ ICM7228CIPI ICM7228CIPI
ICM7228CIPIZ (Note) ICM7228CIPI
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ICM7228 Pinouts
ICM7228A (PDIP, SOIC) COMMON ANODE TOP VIEW ICM7228B (PDIP, SOIC) COMMON CATHODE TOP VIEW
SEG c 1 SEG e 2 SEG b 3 DP 4 ID6 (HEXA/CODE B) 5 ID5 (DECODE) 6 ID7 (DATA COMING) 7 WRITE 8 MODE 9 ID4 (SHUTDOWN) 10 ID1 11 ID0 12 ID2 13 ID3 14
28 VSS 27 SEG a 26 SEG g 25 SEG d 24 SEG f 23 DIGIT 3 22 DIGIT 6 21 DIGIT 7 20 DIGIT 4 19 VDD 18 DIGIT 8 17 DIGIT 5 16 DIGIT 2 15 DIGIT 1
DIGIT 4 1 DIGIT 6 2 DIGIT 3 3 DIGIT 1 4 ID6 (HEXA/CODE B) 5 ID5 (DECODE) 6 ID7 (DATA COMING) 7 WRITE 8 MODE 9 ID4 (SHUTDOWN) 10 ID1 11 ID0 12 ID2 13 ID3 14
28 VSS 27 DIGIT 7 26 DIGIT 5 25 DIGIT 2 24 DIGIT 8 23 SEG g 22 SEG f 21 SEG e 20 SEG c 19 VDD 18 SEG d 17 SEG b 16 SEG a 15 DP
ICM7228C (PDIP, SOIC) COMMON ANODE TOP VIEW
SEG c 1 SEG e 2 SEG b 3 DP 4 DA0 (DIGIT ADDRESS 0) 5 DA1 (DIGIT ADDRESS 1) 6 ID7 (INPUT DP) 7 WRITE 8 HEXA/CODE B/SHUTDOWN 9 DA2 (DIGIT ADDRESS 2) 10 ID1 11 ID0 12 ID2 13 ID3 14 28 VSS 27 SEG a 26 SEG g 25 SEG d 24 SEG f 23 DIGIT 3 22 DIGIT 6 21 DIGIT 7 20 DIGIT 4 19 VDD 18 DIGIT 8 17 DIGIT 5 16 DIGIT 2 15 DIGIT 1
2
ICM7228 Functional Block Diagram
ICM7228A, ICM7228B ID0 - ID7 INPUT DATA 8 DECODE HEXA/CODE B CONTROL LOGIC 1 SHUTDOWN THREE LEVEL INPUT LOGIC ID4 - ID7 CONTROL INPUTS MODE 1 4
ICM7228C
8
WRITE 1
HEXADECIMAL/ CODE B/ SHUTDOWN 1
DA0 - DA2 ID0 - ID3 ID7 DIGIT DATA INPUT WRITE ADDRESS 5 1 3
1
SHUTDOWN
1
1 1 7 4
8-BYTE STATIC RAM
8 8
WRITE ADDRESS COUNTER 1 1
8 8-BYTE STATIC RAM
WRITE ADDRESS COUNTER
8
8
READ ADDRESS, DIGIT MULTIPLEXER 3
4
8
READ ADDRESS MULTIPLEXER 5
HEXADECIMAL/ CODE B DECODER 7
7 MULTIPLEX OSCILLATOR HEXADECIMAL/ CODE B DECODER
1
1
MULTIPLEX OSCILLATOR
DECODE NO-DECODE 8 7 DECIMAL POINT 8 SEGMENT DRIVERS 1 INTERDIGIT BLANKING 8 DIGIT DRIVERS 7 DECIMAL POINT 8 SEGMENT DRIVERS 8 DIGIT DRIVERS 8 1 INTERDIGIT BLANKING
3
ICM7228
Absolute Maximum Ratings
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Input Voltage (Note 1) (Any Terminal) . . (VSS -0.3V)Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD or less then VSS may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM7228 should be turned on first. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
Electrical Specifications
PARAMETER Supply Voltage Range, VSUPPLY
VDD = +5.0V 10%, VSS = 0V, Unless Otherwise Specified TA = 25oC TEST CONDITIONS Operating Power Down Mode MIN 4 2 200 50 20 10 TYP 1 2.5 200 100 250 175 1 1 25 12 1 1 MAX 6 100 100 450 450 450 450 100 100 50 50 -40oC TO 85oC MIN 4 2 175 40 20 10 TYP 1 2.5 200 100 250 175 1 1 1 1 MAX 6 100 100 450 450 450 450 100 100 50 50 A mA A mA A A UNITS V
Quiescent Supply Current, IQ
Shutdown, ICM7228A, IMC7228B Shutdown, 7228C
Operating Supply Current, IDD
Common Anode, ICM7228A/C Segments = ON; Outputs = OPEN Common Anode, ICM7228A/C Segments = OFF; Outputs = OPEN Common Cathode, ICM7228B Segments = ON; Outputs = OPEN Common Cathode, ICM7228B Segments = OFF; Outputs = OPEN
Digit Drive Current, IDIG
Common Anode, ICM7228A/C VOUT = VDD - 2.0V Common Cathode, ICM7228B VOUT = VSS + 1.0V
Digit Leakage Current, IDLK
Shutdown Mode, VOUT = 2.0V Common Anode, ICM7228A/C Shutdown Mode, VOUT = 5.0V Common Cathode, 7228B
Peak Segment Drive Current, ISEG
Common Anode, ICM7228A/C VOUT = VSS + 1.0V Common Cathode, 7228B VOUT = VDD - 2.0V
Segment Leakage Current, ISLK
Shutdown Mode, VOUT = VDD Common Anode, ICM7228A/C Shutdown Mode, VOUT = VSS Common Cathode, ICM7228B
4
ICM7228
Electrical Specifications
PARAMETER Input Leakage Current, IIL VDD = +5.0V 10%, VSS = 0V, Unless Otherwise Specified (Continued) TA = 25oC TEST CONDITIONS All Inputs Except Pin 9, ICM7228C, VIN = VSS All Inputs Except Pin 9, ICM7228C, VIN = 5.0V Display Scan Rate, fMUX Inter-Digit Blanking Time, tIDB Logical "1" Input Voltage, VINH Floating Input, VINF Logical "0" Input Voltage, VINL Three Level Input Impedance, ZIN Logical "1" Input Voltage, VIH Logical "0" Input Voltage, VIL Three Level Input: Pin 9 ICM7228C, Hexadecimal VDD = 5V Three Level Input: Pin 9 ICM7228C, Code B, VDD = 5V Three Level Input: Pin 9 ICM7228C, Shutdown, VDD = 5V VCC = 5V, Pin 9 of ICM7228C All Inputs Except, Pin 9 of ICM7228C, VDD = 5V All Inputs Except, Pin 9 of ICM7228C, VDD = 5V Per Digit MIN 2 4.2 2.0 50 2.0 TYP 390 10 MAX 1 -1 3.0 0.8 0.8 -40oC TO 85oC MIN 2 4.2 2.0 50 2.0 TYP 390 MAX 1 -1 3.0 0.8 0.8 Hz s V V V k V V UNITS A
SWITCHING SPECIFICATIONS VDD = +5.0V 10%, VSS = 0V, VIL = +0.4V, VIH = +2.4V Write Pulsewidth (Low), tWL Write Pulsewidth (High), tWH Mode Hold Time, tMH Mode Setup Time, tMS Data Setup Time, tDS Data Hold Time, tDH Digit Address Setup Time, tAS Digit Address Hold Time, tAH ICM7228C ICM7228C ICM7228A, ICM7228B ICM7228A, ICM7228B 200 850 0 250 250 0 250 0 100 540 -65 150 160 -60 110 -60 250 1200 0 250 250 0 250 0 ns ns ns ns ns ns ns ns
5
ICM7228 Timing Diagrams
MODE tMS MODE tWL WRITE tDS INPUT DATA VALID tDH tWH tMH WRITE (D1) WRITE DATA 8 PULSES (D8) DON'T CARE CONTROL WORD TYPE OF DECODER?ID6 DECODE/NO DECODE? ID5 SHUTDOWN? ID4 DATA COMING ID7
CONTROL WORD TYPE OF DECODER?ID6 DECODE/NO DECODE? ID5 SHUTDOWN?ID4 DATA COMING ID7
FIGURE 1. ICM7228A/B WRITE CYCLE
FIGURE 2. ICM7228A/B SEQUENTIAL 8-DIGIT RAM UPDATE
DIGIT ADDRESS DAO-DAZ WRITE
VALID tAS tWL tDS tAH tWH tDH VALID DATA
DATA
FIGURE 3. ICM7228C WRITE CYCLE
10s (TYP) FREE RUNNING INTERDIGIT BLANKING INTERNAL SIGNAL D2 D5 INTERDIGIT BLANKING D1 D7 TYPICAL DIGITS OUTPUT PULSES D8 D6 D4 D3
320s (TYP) FREE RUNNING (PER DIGIT)
FIGURE 4. DISPLAY DIGITS MULTIPLEX (COMMON ANODE DISPLAY)
6
ICM7228 Typical Performance Curves
0 100 200 ISEG (mA) IDIG (mA) 300 400 500 -55oC 0 5.0 4.0 3.0 VDD-VDIG (V) 2.0 1.0 0 0 1.0 2.0 3.0 VSEG (V) 4.0 5.0 25oC -55oC 25oC 125oC 80 60 40 20 125oC -55oC 25oC
125oC
FIGURE 5. COMMON ANODE DIGIT DRIVER IDIG vs (VDD - VDIG)
FIGURE 6. COMMON ANODE SEGMENT DRIVER ISEG vs VSEG
0 -55oC 25oC
10
125oC
20 IDIG (mA) ISEG (mA)
300 -55oC 200 125oC 25oC
30
40
100 0 0 1.0 2.0 3.0 VDIG (V) 4.0
50
5.0
5.0
4.0
3.0 VDD-VSEG (V)
2.0
1.0
0
FIGURE 7. COMMON CATHODE DIGIT DRIVER IDIG vs VDIG
FIGURE 8. COMMON CATHODE SEGMENT DRIVER ISEG vs (VDD - VSEG)
TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. 1 2 3 4 5 SEG c SEG e SEG b DP ID6, (HEXA/CODE B) ID5, (DECODE) ID7, (DATA COMING) WRITE Input When "MODE" Low: Display Data Input, Bit 7. When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. When "MODE" Low: Display Data Input, Bit 6. When "MODE" High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode. When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data. When "MODE" High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. NAME FUNCTION Output DESCRIPTION LED Display Segments c, e, b and Decimal Point Drive Lines.
6 7
Input Input
8
Input
7
ICM7228
TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. 9 10 MODE ID4, (SHUTDOWN) ID1 NAME FUNCTION Input Input DESCRIPTION Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. When "MODE" Low: Display Data Input, Bit 5. When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. When "MODE" Low: Display Data Input, Bit 2. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 1. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, LSB, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 3. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 4. When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B LED Display Digits 1, 2, 5 and 8 Drive Lines.
11
Input
12
ID0
Input
13
ID2
Input
14
ID3
Input
15 16 17 18 19 20 21 22 23 24 25 26 27 28
DIGIT 1 DlGlT 2 DIGIT 5 DlGlT 8 VDD DIGIT 4 DlGlT 7 DlGlT 6 DIGlT 3 SEG f SEG d SEG g SEG a VSS
Output
Supply Output
Device Positive Power Supply Rail. LED Display Digits 4, 7, 6 and 3 Drive Lines.
Output
LED Display Segments f, d, g and a Drive Lines.
Supply
Device Ground or Negative Power Supply Rail.
TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. 1 2 3 4 5 NAME DIGIT 4 DlGlT 6 DIGIT 3 DlGlT 1 ID6, (HEXA/CODE B) ID5, (DECODE) ID7, (DATA COMING) Input When "MODE" Low: Display Data Input, Bit 7. When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. When "MODE" Low: Display Data Input, Bit 6. When "MODE" High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode. When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data. When "MODE" High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. FUNCTION Output DESCRIPTION LED Display Digits 4, 6, 3 and 1 Drive Lines.
6 7
Input Input
8
ICM7228
TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. 8 9 10 NAME WRITE MODE ID4, (SHUTDOWN) ID1 FUNCTION Input Input Input DESCRIPTION Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. When "MODE" Low: Display Data Input, Bit 5. When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. When "MODE" Low: Display Data Input, Bit 2. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 1. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, LSB, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 3. When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update Mode. When "MODE" Low: Display Data Input, Bit 4. When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B. LED Display Decimal Point and Segments a, b, and d Drive Lines
11
Input
12
ID0
Input
13
ID2
Input
14
ID3
Input
15 16 17 18 19 20 21 22 23 24 25 26 27 28
DP SEG a SEG b SEG d VDD SEG c SEG e SEG f SEG g DIGIT 8 DIGIT 2 DIGIT 5 DIGIT 7 VSS
Output
Supply Output
Device Positive Power Supply Rail. LED Display Segments c, e, f and g Drive Lines.
Output
LED Display Digits 8, 2, 5 and 7 Drive Lines.
Supply
Device Ground or Negative Power Supply Rail.
TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. 1 2 3 4 5 6 7 8 SEG c SEG e SEG b DP DA0 DA1 ID7, (INPUT DP) WRITE Input Input Input Input Digit Address Input, Bit 1 LSB. Digit Address Input, Bit 2. Display Decimal Point Data Input, Negative True. Data Input Will Be Written to Display RAM on Rising Edge of WRITE. NAME FUNCTION Output DESCRIPTION LED Display Segments c, e, band Decimal Point Drive Lines.
9
ICM7228
TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME HEXA/CODE B/SHUTDOWN DA2 ID1 ID0 ID2 ID3 DIGIT 1 DlGlT 2 DIGIT 5 DlGlT 8 VDD DIGIT 4 DlGlT 7 DlGlT 6 DIGlT 3 SEG f SEG d SEG g SEG a VSS Supply Device Ground or Negative Power Supply Rail. Output LED Display Segments f, d, g and a Drive Lines. Supply Output Device Positive Power Supply Rail. LED Display Digits 4, 7, 6 and 3 Drive Lines. Output LED Display Digits 1, 2, 5 and 8 Drive Lines. FUNCTION Input Input Input DESCRIPTION Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator, and Display Disabled. Digit Address Input, Bit 3, MSB. Display Data Inputs.
Detailed Description
System Interfacing and Data Entry Modes, ICM7228A and ICM7228B
The ICM7228A/B devices are compatible with the architectures of most microprocessor systems. Their fast switching characteristics makes it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM7228A/B inputs, including MODE, feature a 250ns minimum setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 9 shows a generic method of driving the ICM7228A/B from a microprocessor bus. To the microprocessor, each device appears to be 2 separate I/O locations; the Control Register and the Display RAM. Selection between the two is accomplished by the MODE input driven by address line A0. Input data is placed on the lD0 - lD7 lines. The WRITE input acts as both a device select and write cycle timing pulse. See Figure 1 and Switching Specifications Table for write cycle timing parameters. The ICM7228A/B have three data entry modes: Control Register update without RAM update, sequential 8-digit update and single digit update. In all three modes a control word is first written by pulsing the WRITE input while the
MODE input is high, thereby latching data into the Control Register. The logic level of individual bits in the Control Register select Shutdown, Decode/No Decode, Hex/Code B, RAM bank A/B and Display RAM digit address as shown in Tables 1 and 2. The ICM7228A/B Display RAM is divided into 2 banks, called bank A and B. When using the Hexadecimal or code B display modes, these RAM banks can be selected separately. This allows two separate sets of display data to be stored and displayed alternately. Notice that the RAM bank selection is not possible in No-Decode mode, this is because the display data in the No-Decode mode has 8 bits, but in Decoded schemes (Hex/Code B) is only 4 bits (lD0 - lD3 data). It should also be mentioned that the decimal point is independent of selected bank, a turned on decimal point will remain on for either bank. Selection of the RAM banks is controlled by lD3 input. The lD3 logic level (during Control Register update) selects which bank of the internal RAM to be written to and/or displayed.
Control Register Update without RAM Update
The Control Register can be updated without changing the display data by a single pulse on the WRITE input, with MODE high and DATA COMING low. If the display is being decoded (Hex/Code B), then the value of lD3 determines which RAM bank will be selected and displayed for all eight digits.
10
ICM7228
Sequential 8-Digit Update
The logic state of DATA COMING (lD7) is also latched during a Control Register update. If the latched value of DATA COMING (lD7) is high, the display becomes blanked and a sequential 8-digit update is initiated. Display data can now be written into RAM with 8 successive WRITE pulses, starting with digit 1 and ending with digit 8 (See Figure 2). After all 8 RAM locations have been written to, the display turns on again and the new data is displayed. Additional write pulses are ignored until a new Control Register update is performed. All 8 digits are displayed in the format (Hex/Code B or No Decode) specified by the control word that preceded the 8 digit update. If a decoding scheme (Hex/Code B) is to be used, the value of lD3 during the control word update determines which RAM bank will be written to.
Single Digit Update
In this mode each digit data in the display RAM can be updated individually without changing the other display data. First, with MODE input high, a control word is written to the Control Register carrying the following information; DATA COMING (lD7) low, the desired display format data on lD4 - lD6, the RAM bank selected by lD3 (if decoding is selected) and the address of the digit to be updated on data lines lD0 - lD2 (See Table 4). A second write to the ICM7228A/B, this time with MODE input low, transfers the data at the lD0 - lD7 inputs into the selected digit's RAM location. In single digit update mode, each individual digit's data can be specified independently for being displayed in Decoded or No-Decode mode. For those digits which decoding scheme (Hex/Code B) is selected, only one can be effective at a time. Whenever a control word is written, the specified decoding scheme will be applied to all those digits which selected to be displayed in Decoded mode.
DATA BUS D0-D7
ID0 MICROPROCESSOR SYSTEM D0 - D7 I/O OR MEMORY WRITE PULSE ID7 DECODER ENABLE INTERSIL ICM7228A/B
LED DISPLAY
DEVICE SELECT AND WRITE PULSE WRITE A0 MODE
SEGMENTS DRIVE
ADDRESS DECODER A1-A15
DIGITS DRIVE
ADDRESS BUS A0 - A15
FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING TABLE 4. DIGITS ADDRESS, ICM7228A/B INPUT DATA LINES 1D2 0 0 0 0 1 1 1 1 lD2 0 0 1 1 0 0 1 1 lD0 0 1 0 1 0 1 0 1 SELECTED DIGIT DlGlT 1 DlGlT 2 DIGlT 3 DlGlT 4 DIGIT 5 DlGlT 6 DlGlT 7 DlGlT 8
setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 10 shows a generic method of driving the ICM7228C from a microprocessor bus. To the microprocessor, the 8 bytes of the Display RAM appear to be 8 separate I/O locations. Loading the ICM7228C is quite similar to a standard memory write cycle. The address of the digit to be updated is placed on lines DA0 - DA2, the data to be written is placed on lines ID0 - lD3 and ID7, then a low pulse on WRITE input will transfer the data in. See Figure 3 and Switching Characteristics Table for write cycle timing parameters. The ICM7228C does not have any control register, and also does not provide the No Decode display format. Hexadecimal or Code B character selection and shutdown mode are directly controlled through the three level input at Pin 9, which is accordingly called HEXA/CODE B/SHUTDOWN. See Table 3 for input and output definitions of the ICM7228C.
System Interfacing, ICM7228C
The ICM7228C is directly compatible with the architecture of most microprocessor systems. Its fast switching characteristics make it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM7228C inputs, excluding HEXA/CODE B/SHUTDOWN, feature a 250ns minimum 11
ICM7228
Display Formats
The ICM7228A and ICM7228B have three possible display formats; Hexadecimal, Code B and No Decode. Table 5 shows the character sets for the decode modes and their corresponding input code. The display formats of the ICM7228A/B are selected by writing data to bits ID4, ID5 and ID6 of the Control Register (See Table 1 and 2 for input Definitions). Hexadecimal and Code B data is entered via ID0-lD3 and ID7 controls the decimal point.
TABLE 5. DISPLAY CHARACTER SETS INPUT DATA CODE ID3 0 0 0 ID2 0 0 0 ID1 0 0 1 ID0 0 1 0 DISPLAY CHARACTERS HEXADECIMAL 0 1 2 CODE B 0 1 2 ID3 0 0 0 0 0 1 1 1 1 1 1 1 1 TABLE 5. DISPLAY CHARACTER SETS (Continued) INPUT DATA CODE ID2 0 1 1 1 1 0 0 0 0 1 1 1 1 ID1 1 0 0 1 1 0 0 1 1 0 0 1 1 ID0 1 0 1 0 1 0 1 0 1 0 1 0 1 DISPLAY CHARACTERS HEXADECIMAL 3 4 5 6 7 8 9 A b C d E F CODE B 3 4 5 6 7 8 9 E H L P (Blank)
DATA BUS D0 - D7 MICROPROCESSOR SYSTEM I/O OR MEMORY WRITE PULSE
5 ID0 - ID3 AND ID7 INTERSIL ICM7228C SEGMENTS DRIVE WRITE
LED DISPLAY
DECODER ENABLE
DEVICE SELECT AND WRITE PULSE
ADDRESS DECODER A3 - A15 A0 - A2 DA0 - DA2 DIGITS DRIVE
ADDRESS BUS A0 - A15
FIGURE 10. ICM7228C MICROPROCESSOR SYSTEM INTERFACING
a f g e d c
DP
b
An input high level turns on the respective segment, except for the decimal point, which is turned on by an input low level on ID7. The No Decode mode can be used in different applications such as bar graph or status panel driving where each segment controls an individual LED. The ICM7228C has only the Hexadecimal and Code B character sets. The HEXA/CODE B/SHUTDOWN input, pin 9, requires a three level input. Pin 9 selects the Hexadecimal format when pulled high, the Code B format when floating or driven to mid-supply, and the shutdown mode when pulled low (See Table 3). Table 5 also applies to the ICM7228C.
FIGURE 11. DIGITS SEGMENT ASSIGNMENTS
The No Decode mode of the ICM7228A and ICM7228B allows the direct segment-by-segment control of all 64 segments driven by the device. In the No Decode mode, the input data directly control the outputs as shown in Table 6.
TABLE 6. NO DECODE SEGMENT LOCATIONS DATA INPUT Controlled Segment ID7 Decimal Point ID6 a ID5 b ID4 c ID3 e ID2 g ID1 f ID0 d
Shutdown and Display Banking
When shutdown, the ICM7228 enters a low power standby mode typically consuming only 1A of supply current for the ICM7228A/B and 2.5A for the ICM7228C. In this mode the ICM7228 turns off the multiplex scan oscillator as well as the digit and segment drivers. However, input data can still be
12
ICM7228
entered when in the shutdown mode. Data is retained in memory even with the supply voltage as low as 2V. The ICM7228A/B is shutdown by writing a control word with Shutdown (lD4) low. The ICM7228C is put into shutdown mode by driving pin 9, HEXA/CODE B/SHUTDOWN, low. The ICM7228 operating current with the display blanked is within 100A - 200A for all versions. All versions of the ICM7228 can be blanked by writing Hex FF to all digits and selecting Code B format. The ICM7228A and ICM7228B can also be blanked by selecting No Decode mode and writing Hex 80 to all digits (See Tables 5and 6). ghosting (a faint display of data from previous digit superimposed on the next digit). The interdigit blanking time is 10s typical with a guaranteed 2s minimum. The ICM7228 turns off both the digit drivers and the segment drivers during the interdigit blanking period. The digit multiplexing sequence is: D2, D5, D1, D7, D8, D6, D4 and D3. A typical digit's drive pulses are shown on Figure 4. Due to the display multiplexing, the driving duty cycle for each digit is 12% (100 x 1/8) This means the average current for each segment is 1/8 of its peak current. This must be considered while designing and selecting the displays.
Common Anode Display Drivers, ICM7228A and ICM7228C
The common anode digit and segment driver output schematics are shown in Figure 12. The common anode digit driver output impedance is approximately 4. This provides a nearly constant voltage to the display digits. Each digit has a minimum of 200mA drive capability. The N-Channel segment driver's output impedance of 50 limits the segment current to approximately 25mA peak current per segment. Both the segment and digit outputs can directly drive the display, current limiting resistors are not required. Individual segment current is not significantly affected by whether other segments are on or off. This is because the segment driver output impedance is much higher than that of the digit driver. This feature is important in bar graph applications where each bar graph element should have the same brightness, independent of the number of elements being turned on.
Driving Larger Displays
If very high display brightness is desired, the ICM7228 display driver outputs can be externally buffered. Figures 14 thru 16 show how to drive either common anode or common cathode displays using the ICM7228 and external driver circuit for higher current displays. Another method of increasing display currents is to connect two digit outputs together and load the same data into both digits. This drives the display with the same peak current, but the average current doubles because each digit of the display is on for twice as long, i.e., 1/4 duty cycle versus 1/8 .
VDD DIGIT STROBE INTERDIGIT BLANKING
P 200mA
Common Cathode Display Driver, ICM7228B
The common cathode digit and segment driver output schematics are shown in Figure 13. The N-channel digit drivers have an output impedance of approximately 15. Each digit has a minimum of 50mA drive capability. The segment drivers have an output impedance of approximately 100 with typically 10mA peak current drive for each segment. The common cathode display driver output currents are only 1/4 of the common anode display driver currents. Therefore, the ICM7228A and ICM7228C common anode display drivers are recommended for those applications where high display brightness is desired. The ICM7228B common cathode display driver is suitable for driving bubble-lensed monolithic 7 segment displays. They can also drive individual LED displays up to 0.3 inches in height when high brightness is not required.
N N N 2k
COMMON ANODE DIGIT OUTPUT
VSS SHUTDOWN
N 2k VSS
NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also stays low. FIGURE 12A. DIGIT DRIVER
Display Multiplexing
Each digit of the ICM7228 is on for approximately 320s, with a multiplexing frequency of approximately 390Hz. The ICM7228 display drivers provide interdigit blanking. This ensures that the segment information of the previous digit is gone and the information of the next digit is stable before the next digit is driven on. This is necessary to eliminate display
13
ICM7228
VDD P SEGMENT DATA INTERDIGIT BLANKING SHUTDOWN N
VDD
VDD
2k
COMMON ANODE SEGMENT OUTPUT ICM7228A/C VDD SEGMENT OUTPUT VDD DIGIT OUTPUT
UP TO 4A
75
VSS
FIGURE 12B. SEGMENT DRIVER FIGURE 12. COMMON ANODE DISPLAY DRIVERS
10K
VDD P DIGIT STROBE INTERDIGIT BLANKING SHUTDOWN N
2k
COMMON CATHODE DIGIT OUTPUT
VSS
VSS
FIGURE 14. DRIVING HIGH CURRENT DISPLAY, COMMON ANODE ICM7228A/C TO COMMON ANODE
VDD VDD
15
VSS
100
SEGMENT OUTPUT 2N2219
FIGURE 13A. DIGIT DRIVER
ICM7228B VDD
VDD SEGMENT DATA INTERDIGIT BLANKING 100 N N
14 (100mAPEAK)
P
200mA
COMMON CATHODE SEGMENT OUTPUT N
DIGIT OUTPUT
14mA 2N6034 1.4APEAK VSS
15
VSS
2k 2k
VSS N
VSS SHUTDOWN
FIGURE 15. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228B TO COMMON CATHODE DISPLAY
NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also stays low. FIGURE 13B. SEGMENT DRIVER FIGURE 13. COMMON CATHODE DISPLAY DRIVERS
14
ICM7228
Power Supply Bypassing
VDD VDD 1K VDD 1.4APEAK 2N6034
100 ICM7228B VDD
SEGMENT OUTPUT
Connect a minimum of 47F in parallel with 0.1F capacitors between VDD and VSS of ICM7228. These capacitors should be placed in close proximity to the device to reduce the power supply ripple caused by the multiplexed LED display drive current pulses.
DIGIT OUTPUT N
300
1K
25 (100mAPEAK) 2N2219
15
VSS
1K
VSS
FIGURE 16. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228B TO COMMON ANODE DISPLAY
Three Level Input, ICM7228C
As mentioned before, pin 9 is a three level input and controls three functions: Hexadecimal display decoding, Code B display decoding and shutdown mode. In many applications, pin 9 will be left open or permanently wired to one state. When pin 9 can not be permanently left in one state, the circuits illustrated in Figure 17 can be used to drive this three level input.
HIGH = HEX LOW = SHUTDOWN HIGH = HEX OR SHUTDOWN LOW = CODE B HIGH = HEX LOW = SHUTDOWN HIGH = HEX OR SHUTDOWN LOW = CODE B HIGH = CODE B LOW = HEX HIGH = SHUTDOWN LOW = CODE B HIGH = SHUTDOWN LOW = HEX HIGH = SHUTDOWN LOW = CODE B CD4069 PIN 9 OPEN DRAIN OR OPEN COLLECTOR OUTPUT PIN 9 CD4069 1N4148 PIN 9 CD4069 1N4148 PIN 9 CONTROL CD4016 CD4066 PIN 9 74C126 THREE-STATE BUFFER PIN 9
FIGURE 17. ICM7228C PIN 9 DRIVE CIRCUITS
15
ICM7228
Test Circuit
1 2 3 ID6 (HEXA/CODE B) ID5 (DECODE) ID7 (DATA COMING) WRITE MODE ID4 (SHUTDOWN) ID1 ID0 ID2 ID3 VDD + 5V VSS 4 5 6 7 8 9 10 11 12 13 14 VDD 47F +0.1F VSS D8 COMMON ANODE DISPLAY D7 D6 D5 D4 D3 D2 D1 ICM7228A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 f d g a c e b DP
FIGURE 18. FUNCTIONAL TEST CIRCUIT #1
16
ICM7228 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
17
ICM7228 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18

▲Up To Search▲

Price & Availability of ICM722805

	To Download ICM722805 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .