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| EtronTech Features * Single power supply voltage of 2.7V to 3.6V * Power down features using CE1# and CE2 * Low operating current : 25mA(max. for 70 ns) * Maximum Standby current : 10A at 3.6 V * Data retention supply voltage: 1.5V to 3.6V * Direct TTL compatibility for all input and output * Wide operating temperature range: -40C to 85C * Package type: 36-ball TFBGA, 6x8mm EM562081 256K x 8 Low Power SRAM Preliminary, Rev 1.0 7/2001 asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40C to 85C, the EM562081 can be used in environments exhibiting extreme temperature conditions. Pin Assignment Ordering Information Part Number EM562081BC-70 EM562081BC-85 Speed 70 ns 85 ns IDDS2 10 A 10 A Package 6x8 BGA 6x8 BGA 1. 36-Ball BGA (CSP), Top View 1 2 3 4 5 6 A A0 A1 CE 2 A3 A6 A8 Pin Names Symbol A0 - A17 DQ0-DQ7 CE1#,CE2 OE# WE# GND VDD NC B DQ 4 A2 WE# A4 A7 DQ 0 Function Address Inputs Data Inputs/Outputs Chip Enable Inputs Output Enable Read/Write Control Input Ground C DQ 5 NC A5 DQ 1 D G ND V DD E V DD G ND F DQ 6 NC A1 7 DQ 2 G DQ 7 O E# C E 1# A16 A15 DQ 3 Power Supply No Connection H A9 A1 0 A1 1 A12 A13 A14 Overview The EM562081 is a 2,097,152-bit SRAM organized as 262,144 words by 8 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.7V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram EM562081 A0 VDD MEMORY CELL ARRAY 256KX8 GND A17 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SENSE AMP COLUMN ADDRESS DECODER WE# CE1# CE2 OE# POWER DOWN CIRCUIT Preliminary 2 Rev 1.0 July 2001 EtronTech Operating Mode Mode Read Write Output Deselect Standby X L X X CE1# L L L H CE2 H H H X OE# L X H X WE# H L H X EM562081 DQ0~DQ7 DOUT DIN High-Z High-Z High-Z Power Active Active Active Standby Standby Note: X = don't care. H = logic high. L = logic low. Absolute Maximum Ratings Supply voltage, VDD Input voltages, VIN Input and output voltages, VI/O Operating temperature, TOPR Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD -0.3 to +4.6V -0.3 to +4.6V -0.5 to VDD + 0.5V -40 to +85C -55 to +150C 240C 0.6 W DC Recommended Operating Conditions (Ta=-40 C to 85 C) Symbol VDD VIH VIL VDR Parameter Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage Min 2.7 2.2 -0.3 (2) Typ - - - - Max 3.6 VDD + 0.3 0.6 3.6 (1) Unit V V V V 1.5 Note: (1) Overshoot : VDD +2.0V in case of pulse width 20ns (2) Undershoot : -2.0V in case of pulse width 20ns Preliminary 3 Rev 1.0 July 2001 EtronTech DC Characteristics (Ta = -40 C to 85 C, VDD = 2.7V to 3.6V) Parameter Input low current Output low voltage Output high voltage Symbol IIL VOL VOH IDD1 Operating current IDD2 IDDS1 Standby current IIN = 0V to VDD IOL = 2.1 mA IOH = -1.0 mA VDD = 3.6 V , CE1# = VIL and CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL CE1# = VIH or CE2 = VIL Cycle time = min Cycle time = 1s Test Conditions EM562081 Min -1 2.2 - - - - Typ* - - - 10 - - 1 Max Unit 1 0.4 - 25 mA 5 0.5 10 mA A A V V IDDS2** CE1# VDD - 0.2V or CE2 0.2V, (Note) Notes: * Typical value are measured at Ta = 25C, and not 100% tested. ** In standby mode with CE1# VDD - 0.2V, these limits are assured for the condition CE2 VDD - 0.2V or CE2 0.2V. Capacitance (Ta = 25 C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN Min - Typ - Max 10 Unit pF Test Conditions VIN = GND COUT - - 10 pF VOUT = GND Notes: This parameter is periodically sampled and is not 100% tested. Preliminary 4 Rev 1.0 July 2001 EtronTech Read Cycle EM562081 AC Characteristics and Operating Conditions (Ta = -40 C to 85 C, V DD = 2.7V to 3.6V) EM562081 Symbol Parameter -85 -70 Unit - 70 70 70 35 - - 25 25 - ns Min Max Min Max tRC tAA tCO1 tCO2 tOE tLZ tOLZ tHZ tOHZ tOH Write Cycle EM562081 Symbol Parameter -85 -70 Unit - - - - - 30 - - - ns Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Output Data Hold Time 85 - - - - 10 3 - - 10 - 85 85 85 45 - - 35 35 - 70 - - - - 10 3 - - 10 Min Max Min Max tWC tWP tCW tAS tWR tWHZ tOW tDS tDH Write cycle time Write pulse width Chip Enable to end of write Address setup time Write Recovery time WE# Low to Output in High-Z WE# High to Output in Low-Z Data Setup Time Data Hold Time 85 55 70 0 0 - 5 35 0 - - - - - 35 - - - 70 55 60 0 0 - 5 30 0 AC Test Condition * Output load: 50pF + one TTL gate * Input pulse level: 0.4V, 2.4V * Timing measurements: 0.5 x VDD * tR, tF: 5ns Preliminary 5 Rev 1.0 July 2001 EtronTech Read Cycle (See Note 1) tRC EM562081 A ddr es s tAA tOH tCO1 CE 1# CE 2 tCO2 tHZ tOE O E# tOHZ tOLZ tLZ D O UT VALID DATA OUT Preliminary 6 Rev 1.0 July 2001 EtronTech Write Cycle1 (WE# Controlled)(See Note 4) tW C EM562081 A d d re s s tA S tW P tW R W E# tC W CE 1 # CE 2 tC W tW H Z t OW D O UT (S e e N o te 2 ) (S e e N o te 3 ) tD S t DH D IN (S e e N o te 5 ) V A L ID D A T A IN (S e e N o te 5 ) Preliminary 7 Rev 1.0 July 2001 EtronTech Write Cycle 2 (CE1# Controlled)(See Note 4) tWC EM562081 Addres s tA S tWP tWR W E# t CW C E1# C E2 t CW tW H Z D OU T tL Z t DS t DH D IN ( S e e N ot e 5 ) V A L ID DA TA I N Preliminary 8 Rev 1.0 July 2001 EtronTech Write Cycle 3 (CE2 Controlled)(See Note 4) tWC EM562081 Addres s tA S tWP tWR W E# t CW C E1# C E2 t CW tW H Z D OU T tL Z t DS t DH D IN ( S e e N ot e 5 ) V A L ID DA TA I N Preliminary 9 Rev 1.0 July 2001 EtronTech Write Cycle4 (UB#, LB# Controlled)(See Note 4) tWC EM562081 Addres s tWP tWR W E# t CW C E1# C E2 t CW t W HZ D OU T tL Z t DS t DH D IN ( S e e N ot e 5 ) V A L ID DA TA I N Note: (1) WE# remains HIGH for the read cycle. (2) If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. (3) If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. (4) If OE# is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 1.0 July 2001 EtronTech Data Retention Characteristics (Ta = -40 C to 85 C) Symbol Data Retention Supply Voltage Parameter CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V VDD = 1.5V, CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V Min EM562081 Typ Max Unit VDR 1.5 - 3.6 V IDR tSDR tRDR Data Retention Current - 0 tRC 0.5 - - 3 - - A ns ns Chip Deselect to Data Retention Mode Time Recovery Time CE1# Controlled Data Retention Mode (see Note1) t SDR VDD 2.7V Data Retention Mode tRDR 2.2V VDR CE1# GND Note 1 CE2 Controlled Data Retention Mode (see Note2) VD D 2.7 V CE2 tSD R tRDR D at a R et e nt io n M od e VD R No te 2 0 .4 V GND Note: (1) If CE1# controlled data retention mode, minimum standby current mode is entered when CE2 0.2V or CE2 VDD - 0.2V. (2) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 0.2V. Preliminary 11 Rev 1.0 July 2001 EtronTech BGA (CSP) Package Diagrams 36-Ball (6.00mm x 8.00mm) BGA (CSP) Units in mm T OP VIEW EM562081 BO TTO M VIE W 0.10 S 0.25 S C C PIN 1 CORNER A B PIN 1 CORNER 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 -B0.75 -A3.75 0.20( 4X) 0.15 -C SEA TING P LA NE Preliminary 12 Rev 1.0 July 2001 |
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