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ISL29004
Data Sheet December 21, 2006 FN6221.0
Light-to-Digital Output Sensor with Address Selection, High Sensitivity, Gain Selection, Interrupt Function and I2C Interface
The ISL29004 is an integrated light sensor with a 16-bit integrating type ADC, I2C user programmable Lux range select for optimized counts/Lux, and I2C multi-function control and monitoring capabilities. The internal ADC provides 16-bit resolution while rejecting 50Hz and 60Hz flicker caused by artificial light sources. In normal operation, power consumption is typically 300A. Futhermore, an available software power-down mode controlled via the I2C interface reduces power consumption to less than 1A. The device also support a hardware interrupt that remains asserted low until the host clears it through I2C interface. The ISL29004 is in an 8 Ld ODFN package and has two I2C address pins for multiple devices on the same bus. The ISL29003 is a similar light sensor with a hardwired I2C address that is available in ODFN6 package. Designed to operate on supplies from 2.5V to 3.3V, the ISL29004 are specified for operation over the -40C to +85C ambient temperature range.
Features
* Range select via I2C - Range1 = 1000Lux - Range2 = 4000Lux - Range3 = 16,000Lux - Range4 = 64,000Lux * Human eye response (540nm peak sensitivity) * Temperature compensated * 16-bit resolution * Adjustable resolution: up to 65 counts per Lux * User-programmable upper and lower threshold interrupt * Simple output code, directly proportional to Lux * 50Hz/60Hz rejection * 2.5V to 3.3V supply * 8 Ld ODFN (3mmx3mm) * I2C address selection
Applications
* Ambient light sensing * Backlight control * Temperature control systems
Ordering Information
PART NUMBER (Note) ISL29004IROZ ISL29004IROZ-T7 TAPE & REEL 7" PACKAGE (Pb-Free) 8 Ld ODFN PKG. DWG. # MDP0052
* Contrast control * Camera light meters * Lighting controls
8 Ld ODFN Tape MDP0052 and Reel
ISL29004IROZ-EVALZ Evaluation Board (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
1 PHOTODIODE 1 GAIN/RANGE INT TIME MODE SHDN
COMMAND REGISTER DATA REGISTER 8 SDA SCL A0 A1
MUX
INTEGRATING ADC
Pinout
ISL29004 (8 LD ODFN) TOP VIEW
VDD GND REXT A0 1 2 3 4 THERMAL PAD 8 7 6 5 SDA SCL INT A1
PHOTODIODE 2 IREF FOSC 216 COUNTER 3 REXT 2 GND EXT TIMING
I2C
7 4
INT INTERRUPT
5
6 INT
ISL29004
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL29004
Absolute Maximum Ratings (TA = +25C)
VDD Supply Voltage between VDD and GND . . . . . . . . . . . . . 3.6V I2C Address Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 3.6 I2C Bus Pin Voltage (SCL, SDA) . . . . . . . . . . . . . . . . . -0.2V to 5.5V I2C Bus Pin Current (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . <10mA Rext Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 3.6V Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-45C to +100C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C ESD, Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV ESD, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VDD IDD IDD1 FOSC1 FOSC2 FI2C DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 VREF VTL VTH ISDA IINT IIL IIH NOTES:
VDD = 3V, TA = +25C, REXT = 100k 1% tolerance, unless otherwise specified, Internal Timing Mode operation (See Principles of Operation). CONDITION MIN 2.25 0.29 Software disabled Gain/Range = 1 or 2 Gain/Range = 3 or 4 (Note 2) E = 0Lux, Mode1, Gain/Range = 1 290 580 1 1 0.1 327 655 TYP MAX 3.63 0.33 1 364 728 400 5 65535 Mode0 Mode1 Mode0 Mode1 Mode0 Mode1 Mode0 Mode1 E = 300Lux, fluorescent light, Gain/Range = 1 (Note 1) 13,800 20,200 2,020 5,050 505 1,262 126 316 32 500 (Note 3) (Note 3) 3 3 A0 = A1 = GND A0 = A1 = VDD 1.05 1.95 5 5 0.1 0.1 24,400 UNIT V mA A kHz kHz kHz Counts Counts Counts Counts Counts Counts Counts Counts Counts Counts mV V V mA mA A A
DESCRIPTION Power Supply Range Supply Current Supply Current Disabled Internal Oscillator Frequency Internal Oscillator Frequency I2C Clock Rate Diode1 and Diode2 Dark ADC Code Full Scale ADC Code Diode1 ADC Code Gain/Range = 1 accuracy Diode2 ADC Code Gain/Range = 1 accuracy Diode1 ADC Code Gain/Range = 2 accuracy Diode2 ADC Code Gain/Range = 2 accuracy Diode1 ADC Code Gain/Range = 3 accuracy Diode2 ADC Code Gain/Range = 3 accuracy Diode1 ADC Code Gain/Range = 4 accuracy Diode2 ADC Code Gain/Range = 4 accuracy Voltage of REXT Pin SCL, SDA, A0 and A1 Threshold LO SCL and SDA Threshold HI SDA Current Sinking Capability INT Current Sinking Capability A0 and A1 Input Current LO A0 and A1 Input Current HI
E = 300Lux, fluorescent light, Gain/Range = 2 (Note 1)
E = 300Lux, fluorescent light, Gain/Range = 3 (Note 1)
E = 300Lux, fluorescent light, Gain/Range = 4 (Note 1)
1. Fluorescent light is substituted by a white LED during production. 2. Minimum I2C Clock Rate is guaranteed by design. 3. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD.
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ISL29004 Pin Descriptions
PIN NUMBER ISL29003 1 2 3 4 5 6 N/A N/A PIN NUMBER ISL29004 1 2 3 6 7 8 4 5 PIN NAME VDD GND REXT INT SCL SDA A0 A1 DESCRIPTION Positive supply; connect this pin to a regulated 2.5V to 3.3V supply Ground pin. External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100k resistor Interrupt pin; LO for interrupt/alarming. The INT pin is an open drain. I2C serial clock I2C serial data Bit 0 of the I2C address. Bit 1 of the I2C address. The address pins have an open gate equivalent circuit. These are the least-significant bits of the I2C address. The 4 possible addresses are 44(hex) through 47(hex). The I2C bus lines can pulled above VDD, 5.5V max.
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ISL29004 Principles of Operation
Photodiodes
The ISL29004 contain two photodiodes. Diode1 is sensitive to both visible and intrared light, while Diode2 is mostly sensitive to infrared light. The spectral response of the two diodes are independent from one another. See Figure Spectral Response vs Wavelength in the performance curves section. The photodiodes convert light to current. Then, the diodes' current outputs are converted to digital by a single built-in integrating type 16-bit Analog-to-Digital Converter (ADC). An I2C command mode determines which photodiode will be converted to a digital signal. Mode0 is Diode1 only. Mode1 is Diode2 only. Mode3 is a sequential Mode0 and Mode1 with an internal subtract function (Diode1 - Diode2). Analog-to-Digital Converter. The converter is a charge-balancing integrating type 16-bit ADC. The chosen method for conversion is best for converting small current signals in the presense of an AC periodic noise. A 100ms integration time, for instance, highly rejects 50Hz and 60Hz power line noise simultaneously. See Integration Time and Noise Rejection section. The built-in ADC offers user flexibility in integration time or conversion time. Two timing modes are available. Internal Timing Mode and External Timing Mode. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between two consecutive I2C External Timing Mode commands. See External Timing Mode example. A good balancing act of integration time and resolution depending on the application is required for optimal results. The ADC has four I2C programmable range select to dynamically accomodate various lighting conditions. For very dim conditions, the ADC can be configured at its lowest range. For very bright conditions, the ADC can be configured at its highest range. are four 8-bit data Read Only registers. Two bytes for the sensor reading and another two bytes for the timer counts. The data registers contain the ADC's latest digital output, and the number of clock cycles in the previous integration period. The ISL29004's I2C interface slave address is pin-selectable by pins A0 and A1. These pins can be tied or driven either high or low. They comprise the least-significant two bits of the I2C address, while the 5 most-significant bits are hardwired as 100001{A1}{A0}. The four possible addresses are therefore 44(hex) through 47(hex). The ISL29003's I2C interface slave address is hardwired internally as 44(hex). Figure 1 shows a sample one-byte read. Figure 2 shows a sample one-byte write. Figure 3 shows a sync_iic timing diagram sample for externally controlled integration time. The I2C bus master always drives the SCL (clock) line, while either the master or the slave can drive the SDA (data) line. Every I2C transaction begins with the master asserting a start condition (SDA falling while SCL remains high). The following byte is driven by the master, and includes the slave address and read/write bit. The receiving device is responsible for pulling SDA low during the acknowledgement period. Every I2C transaction ends with the master asserting a stop condition (SDA rising while SCL remains high). For more information about the I2C standard, please consult the Philips(R) I2C specification documents.
Interrupt Function
The active low interrupt pin is an open drain pull-down configuration. The interrput pin serves as an alarm or monitoring function to determine whether the ambient light exceeds the upper threshold or goes below the lower threshold. The user can also configure the persistency of the interrupt pin. This eliminates any false triggers such as noise or sudden spikes in ambient light conditions. An unexpected camera flash for example can be ignored by setting the persistency to 8 integration cycles.
I2C Interface
There are eight (8) 8-bit registers available inside the ISL29004. The command and control registers define the operation of the device. The command and control registers do not change until the registers are overwritten.There are two 8bit registers that set the high and low interrupt thresholds. There 4
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ISL29004
Start DEVICE ADDRESS
W
I2C DATA
A
REGISTER ADDRESS
A
STOP
START
DEVICE ADDRESS
A
DATA BYTE0
A
STOP
I2C SDA In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
A6
A5
A4
A3
A2
A1
A0
W
A
SDA DRIVEN BY ISL29003
NAK
I2C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
D7
D6
D5
D4
D3
D2
D1
D0
A
I2C CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 1. I2C READ TIMING DIAGRAM SAMPLE
I2C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
FUNCTIONS
A
STOP
I2C SDA In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
B7
B6
B5
B4
B3
B2
B1
B0
A
I2C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
I2C CLK In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE
I2C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A Stop
I2C SDA In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
I2C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
I2C CLK In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 3. I2C sync_iic TIMING DIAGRAM SAMPLE
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ISL29004
Register Set
There are eight registers that are available in the ISL29004. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET ADDR (HEX) 00 REGISTER NAME Command Bit(s) 7 6 5 4 3:2 FUNCTION NAME enable adcPD Timing_Mode reserved mode<1:0> Selects ADC work mode 0: Diode1's current to unsigned 16-bit data 1: Diode2's current to unsigned 16-bit data 2: Difference between diodes (I1 - I2) to signed 15-bit data 3: reserved number of clock cycles; n-bit resolution 0: 216 cycles 1: 212 cycles 2: 28 cycles 3: 24 cycles Always set to logic 0. Factory use only. Always set to logic 0 0: Interrupt is cleared or not yet triggered 1: Interrupt is triggered Always set to logic 0. Factory use only. Selects the gain so range is 0: 0 - 1000Lux 1: 0 - 4000Lux 2: 0 - 16000Lux 3: 0 - 64000Lux Interrupt is triggered after 0: 1 integration cycle 1: 4 integration cycles 2: 8 integration cycles 3: 16 integration cycles High byte of HI interrupt threshold. Default is 0xFF High byte of the LO interrupt threshold. Default is 0x00 Read-Only data register that contains the least significant byte of the latest sensor reading Read-Only data register that contains the most significant byte of the latest sensor reading Read-Only data register that contains the least significant byte of the timer counter value corresponding to the latest sensor reading. Read-Only data register that contains the most significant byte of the timer counter value corresponding to the latest sensor reading. 0: disable adc-core 1: enable adc-core 0: Normal operation 1: Power Down Mode 0: Integration is internally timed 1: Integration is externally sync/controlled by I2C host FUNCTIONS/DESCRIPTION
1:0
width<1:0>
01
Control
7 6 5 4 3:2
ext_mode test_mode int_flag reserved gain<1:0>
1:0
int_persist <1:0>
02 03 04 05 06 07
Interrupt threshold HI Interrupt threshold LO LSB_sensor MSB_sensor LSB_timer MSB_timer
7:0 7:0 7:0 7:0 7:0 7:0
Interrupt threshold HI Interrupt threshold LO LSB_sensor MSB_sensor LSB_timer MSB_timer
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d
TABLE 2. WRITE ONLY REGISTERS ADDRESS b1xxx_xxxx REGISTER NAME sync_iic FUNCTIONS/ DESCRIPTION Writing a logic 1 to this address bit ends the current adc-integration and starts another. Used only with External Timing Mode. Writing a logic 1 to this address bit clears the interrupt.
Mode3 is a sequential Mode0 and Mode1 with an internal subtract function (Diode1 - Diode2).
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3 BITS 3:2 0:0 0:1 1:0 MODE Mode0. ADC integrates or converts Diode1 only. Current is converted to an n-bit unsigned data.* Mode1. ADC integrates or coverts Diode2 only. Current is converted to an n-bit unsigned data.* MODE3. A sequential Mode0 then Mode1 operation. The difference current is an (n-1) signed data.* No operation.
bx1xx_xxxx
clar_int
Command Register 00(hex)
The Read/Write command register has five functions: (1) Enable; Bit 7.This function either resets the ADC or enables the ADC in normal operation. A logic 0 disables ADC to reset-mode. A logic 1 enables adc to normal operation.
TABLE 3. ENABLE BIT 7 0 1 OPERATION Disable ADC-core to reset-mode (default) Enable ADC-core to normal operation
1:1
* n = 4, 8, 12,16 depending on the number of clock cycles function. (5) Width; Bits 1 and 0. This function determines the number of clock cycles per conversion. Changing the number of clock cycles does more than just change the resolution of the device. It also changes the integration time, which is the period the device's analog-to-digital (A/D) converter samples the photodiode current signal for a Lux measurement.
TABLE 7. WIDTH BITS 1:0 0:0 0:1 1:0 1:1 NUMBER OF CLOCK CYCLES 2^16 = 65,536 2^12 = 4,096 2^8 = 256 2^4 = 16
(2) AdcPD; Bit 6. This function puts the device in a power down mode. A logic 0 puts the device in normal operation. A logic 1 powers down the device.
TABLE 4. adcPD BIT 6 0 1 OPERATION Normal operation (default) Power Down
Control Register 01(hex)
The Read/Write control register has three functions: (1) Interrupt flag; Bit 5. This is the status bit of the interrupt. The bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. Writing a logic low clears/resets the status bit.
TABLE 8. INTERRUPT FLAG BIT 5 0 1 OPERATION Interrupt is cleared or not triggered yet Interrupt is triggered
(3) Timing Mode; Bit 5. This function determines whether the integration time is done internally or externally. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between two consecutive external-sync sync_iic pules commands.
TABLE 5. TIMING MODE BIT 5 0 OPERATION Internal Timing Mode. Integration time is internally timed determined by fosc, REXT, and number of clock cycles. External Timing Mode. Integration time is externally timed by the I2C host.
1
(4) Photodiode Select Mode; Bits 3 and 2. This function controls the mux attached to the two photodiodes. At Mode0, the mux directs the current of Diode1 to the ADC. At Mode1, the mux directs the current of Diode2 only to the ADC.
(2) Range/Gain; Bits 3 and 2. The Full Scale Range can be adjusted by an external resistor Rext and/or it can be adjusted via I2C using the Gain/Range funtion. Gain/Range has four possible values, Range(k) where k is 1 through 4. Table 9 lists the possible values of Range(k) and the resulting FSR for some typical value REXT resistors. When Gain/Range is set to Range1 or Range2, the fosc runs at 327kHz. When Gain/Range is set to Range3 or Range4 fosc runs at twice the rate at 655kHz. The automatic fosc adjustment feature improves signal-to-noise ratio for low Lux measurements.
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TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES FSR LUX FSR LUX FSR LUX RANGE@ RANGE@ RANGE@ BITS 3:2 k RANGE(k) REXT = 100k REXT = 50k REXT = 500k 0:0 0:1 1:0 1:1 1 2 3 4 973 3892 15,568 62,272 973 3892 15,568 62,272 1946 7784 31,136 124,544 195 778 3114 12,454 07 ADDRESS (hex) 04 05 06 TABLE 11. DATA REGISTERS CONTENTS Least-significant byte of most recent sensor reading. Most-significant byte of most recent sensor reading. Least-significant byte of timer counter value corresponding to most recent sensor reading. Most-significant byte of timer counter value corresponding to most recent sensor reading.
Interrupt persist; Bits 1 and 0. The interrupt pin and the interrupt flag is triggered/set when the data sensor reading is out of the interrupt threshold window after m consecutive number of integration cycles. The interrupt persist bits determine m.
TABLE 10. INTERRUPT PERSIST BITS 1:0 0:0 0:1 1:0 1:1 NUMBER OF INTEGRATION CYCLES 1 4 8 16
Calculating Lux
The ISL29004's output codes, DATA, are directly proportional to Lux.
E = x DATA (EQ. 1)
The proportionality constant is determined by the Full Scale Range, FSR, and the n-bit ADC which is user defined in the command register. The proportionality constant can also be viewed as the resolution; The smallest Lux measurement the device can measure is .
FSR = -----------n 2 (EQ. 2)
Interrupt Threshold HI Register 02(hex)
This register sets the the HI threshold for the interrupt pin and the interrupt flag. By default the Interrupt threshold HI is FF(hex). The 8-bit data written to the register represents the upper MSB of a 16-bit value. The LSB is always 00(hex).
Full Scale Range, FSR, is determined by the software programmable Range/Gain, Range(k), in the command register and an external scaling resistor REXT which is referenced to 100k.
100k FSR = Range ( k ) x ----------------R EXT (EQ. 3)
Interrupt Threshold LO Register 03(hex)
This register sets the the LO threshold for the interrupt pin and the interrupt flag. By default the Interrupt threshold LO is 00(hex). The 8-bit data written to the register represents the upper MSB of a 16-bit value. The LSB is always 00(hex).
The transfer function effectively for each timing mode becomes:
INTERNAL TIMING MODE 100k Range ( k ) x ----------------R EXT E = ---------------------------------------------------- x DATA n 2 EXTERNAL TIMING MODE 100k Range ( k ) x ----------------R EXT E = ---------------------------------------------------- x DATA COUNTER (EQ. 5) (EQ. 4)
Sensor Data Register 04(hex) and 05(hex)
When the device is configured to output a 16-bit data, the most significant byte is accessed at 04(hex), and the least significant byte can be accessed at 05(hex). The sensor data register is refreshed after very integration cycle.
Timer Data Register 06(hex) and 07(hex)
Note that the timer counter value is only available when using the External Timing Mode. The 06(hex) and 07(hex) are the LSB and MSB respectively of a 16-bit timer counter value corresponding to the most recent sensor reading. Each clock cycle increments the counter. At the end of each integration period, the value of this counter is made available over the I2C. This value can be used to eliminate noise introduced by slight timing errors caused by imprecise external timing. Microcontrollers, for example, often cannot provide high-accuracy command-to-command timing, and the timer counter value can be used to eliminate the resulting noise. 8
n = 4, 8, 12, or 16. This is the number of clock cycles programmed in the command register. Range(k) is the user defined range in the Gain/Range bit in the command register. REXT is an external scaling resistor hardwired to the REXT pin. DATA is the output sensor reading in number of counts available at the data register. 2n represents the maximum number of counts possible in Internal Timing Mode. For the External Timing Mode the
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ISL29004
maximum number of counts is stored in the data register named COUNTER COUNTER is the number increments accrued for between integration time for External Timing Mode. constant is referenced to fixed constants 100k and 655kHz:
1 100k fosc1 = -- x ----------------- x 655 kHz 2 R EXT 100k fosc2 = ----------------- x 655 kHz R EXT (EQ. 6)
Gain/Range, Range(k)
The Gain/Range can be programmed in the control register to give Range (k) determining the FSR. Note that Range(k) is not the FSR. See Equation 3. Range(k) provides four constants depending on programmed k that will be scaled by REXT. See Table 9. Unlike REXT, Range(k) dynamically adjusts the FSR. This function is especially useful when light conditions are varying drastically while maintaining excellent resolution.
(EQ. 7)
fosc1 is oscillator frequency when Range1 or Range2 are set. This is nominally 327kHz when REXT is 100k. fosc2 is the oscillator frequency when Range3 or Range4 are set. This is nominally 655kHz when REXT is 100k. When the Range/Gain bits are set to Range1 or Range2, fosc runs at half speed comapred to when Range/Gain bits are set to Range3 and Range4.
1 f osc 1 = -- ( f osc 2 ) 2 (EQ. 8)
Number of Clock Cycles, n-bit ADC
The number of clock cycles determines "n" in the n-bit ADC; 2n clock cycles is a n-bit ADC. n is programmable in the command register in the width function. Depending on the application, a good balance of speed, and resolution has to be considered when deciding for n. For fast and quick measurement, choose the smallest n = 4. For maximum resolution without regard of time, choose n = 16. Table 12 compares the tradeoff between integration time and resolution. See Equations 10 and 11 for the relation between integration time and n. See Equation 3 for the relation of n and resolution.
TABLE 12. RESOLUTION AND INTEGRATION TIME SELECTION RANGE1 fosc = 327kHz n 16 12 8 4 TINT (ms) 200 12.8 0.8 0.05 RESOLUTION LUX/COUNT 0.01 0.24 3.90 62.5 RANGE4 fosc = 655kHz TINT (ms) 100 6.4 0.4 0.025 RESOLUTION (LUX/COUNT) 1 16 250 4000
The automatic fosc adjustment feature allows significant improvement of signal-to-noise ratio when detecting very low Lux signals.
Integration Time or Conversion Time
Integration time is the period during which the device's analog-to-digital ADC converter samples the photodiode current signal for a Lux measurement. Integration time, in other words, is the time to complete the conversion of analog photodiode current into a digital signal-number of counts. Integration time affects the measurement resolution. For better resolution, use a longer integration time. For short and fast conversions use a shorter integration time. The ISL29004 offer user flexibility in the integration time to balance resolution, speed and noise rejection. Integration time can be set internally or externally and can be programmed in the command register 00(hex) bit 5. INTEGRATION TIME IN INTERNAL TIMING MODE This timing mode is programmed in the command register 00(hex) bit 5. Most applications will be using this timing mode. When using the Internal Timing Mode, fosc and n-bits resolution determine the integration time. Tint is a function of the number of clock cycles and fosc.
n 1T int = 2 x ------------ For Internal Timing Mode Only f osc
REXT = 100k
External Scaling Resistor REXT and fosc The ISL29004 use an external resistor REXT to fix its internal oscillator frequency, fosc. Consequently, REXT determines the fosc, integration time and the FSR of the device. Fosc, a dual speed mode oscillator, is inversely proportional to REXT. For user simplicity, the proportionality
(EQ. 9)
n = 4, 8, 12, and16. n is the number of bits of resolution. 2n therefore is the number of clock cycles. n can be programmed at the command register 00(hex) bits 1 and 0.
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Since fosc is dual speed depending on the Gain/Range bit, Tint is dual time. The integration time as a function of REXT and n is:
R EXT n T int 1 = 2 x --------------------------------------------327kHz x 100k (EQ. 10)
Tint1 is the integration time when the the device is configured for Internal Timing Mode and Gain/Range is set to Range1 or Range2.
R EXT n T int 2 = 2 x --------------------------------------------655kHz x 100k (EQ. 11)
The internal oscillator, fOSC, operates identically in both the internal and external timing modes, with the same dependence on REXT. However, in External Timing Mode, the number of clock cycles per integration is no longer fixed at 2n. The number of clock cycles varies with the chosen integration time, and is limited to 216 = 65,536. In order to avoid erroneous Lux readings the integration time must be short enough not to allow an overflow in the counter register.
65,535 T int < ----------------f OSC (EQ. 13)
Tint2 is the integration time when the the device is configured for Internal Timing Mode and Gain/Range is set to Range3 or Range4.
TABLE 13. INTEGRATION TIMES FOR TYPICAL REXT VALUES RANGE1 RANGE2 n = 16-BIT 100 200 400 1000 n = 12-BIT 6.4 13 26 64 RANGE3 RANGE4 n = 12-BIT 13 26 52 128 n=4 0.013 0.025 0.050 0.125
fosc = 327kHz*100k/REXT. When Range/Gain is set to Range1 or Range2. fosc = 655kHz*100k/REXT. When Range/Gain is set to Range3 or Range4.
Noise Rejection
In general, integrating type ADC's have an excellent noiserejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. For instance, a 60Hz AC unwanted signal's sum from 0ms to k*16.66ms (k = 1,2...ki) is zero. Similarly, setting the device's integration time to be an integer multiple of the periodic noise signal, greatly improves the light sensor output signal in the presence of noise. Design Example 1 The ISL29004 will be designed in a portable system. The ambient light conditions that the device will be exposed to is at most 500Lux which is a good office lighting. The light source has a 50/60Hz power line noise which is not visible by the human eye. The I2C clock is 10kHz. Solution 1 - Using Internal Timing Mode In order to achieve both 60Hz and 50Hz AC noise rejection, the integration time needs to be adjusted to coincide with an integer multiple of the AC noise cycle times. Tint = i(1/60Hz) = j(1/50Hz). The first instance of integer values at which Tint rejects both 60Hz and 50Hz is when i = 6, and j= 5. Tint = 6(1/60Hz) = 5(1/50Hz) Tint = 100ms Next, the Gain/Range needs to be determined. Based on the application condition given, Lux(max) = 500Lux, a range of 1000Lux is desirable. This corresponds to a Gain/Range Range1 mode. Also impose a resolution of n = 16-bit. Hence we choose equation 10 to determine REXT.
T x 327kHz x 100 k int R EXT = ---------------------------------------------------------------n 2 R EXT = 50k
REXT (k) 50 100** 200 500
*Integration time in milliseconds **Recommended REXT resistor value
INTEGRATION TIME IN EXTERNAL TIMING MODE This timing mode is programmed in the command register 00(hex) bit 5. External Timing Mode is recommended when integration time can be synchronized to an external signal such as a PWM to eliminate noise. For Mode0 or Mode1 operation, the integration starts when the sync_iic command is sent over the I2C lines. The device needs two sync_iic commands to complete a photodiode conversion. The integration then stops when another sync_iic command is received. Writing a logic 1 to the sync_iic bit ends the current adc integration and starts another one. For Mode3, the operation is a sequential Mode0 and Mode1. The device needs three sync_iic commands to complete two photodiode measurments. The 1st sync_iic command starts the conversion of the diode1. The 2nd sync_iic completes the conversion of diode1 and starts the conversion of diode2. The 3rd sync_iic pules ends the conversion of diode2 and starts over again to commence conversion of diode1. The integration time, Tint, is determined by the following equation:
i I2C T int = ---------f I2C (EQ. 12)
(EQ. 14)
iI2C is the number of I2C clock cycles to obtain the Tint. fI2C is the I2C operating frequency 10
for Internal Timing Mode and Gain/Range is set to Range3 or Range
FN6221.0 December 21, 2006
ISL29004
The Full Scale Range, FSR, needs to be determined. From Equation 3:
100k FSR = 1000Lux ----------------50k FSR = 2000Lux TABLE 15. SOLUTION2 SUMMARY TO EXAMPLE DESIGN PROBLEM DESIGN PARAMETER Tint REXT Gain/Range Mode FSR # of clock cycles Transfer Function VALUE 100ms 100k Range1 = 1000Lux 1000Lux COUNTER = 1000 DATA E = ------------------------------- x 1000Lux COUNTER
The effective transfer function becomes:
data E = ------------ x 2000Lux 16 2 TABLE 14. SOLUTION1 SUMMARY TO EXAMPLE DESIGN PROBLEM DESIGN PARAMETER Tint REXT Gain/Range Mode FSR # of clock cycles Transfer Function VALUE 100ms 50k Range1 = 1000Lux 2000Lux 216 DATA E = ---------------- x 2000Lux 16 2
Light Source Detection and Infra-Red Rejection
Any filament type light source has a high presence of infrared component invisible to the human eye. A white fluorescent lamp, on the other hand has a low IR content. As a result, output sensitivity may vary depending on the light source. Maximum attenuation of IR can be achieved by properly scaling the readings of Diode1 and Diode2. The user obtains data reading from sensor diode 1, D1, which is sensitive to visible and IR, then reading from sensor diode 2, D2 which is mostly sensitive from IR. The graph on Figure 7 shows the effective spectral response after applying Equation 15 of the ISL29003 from 400nm to 1000nm. The equation below describes the method of cancelling IR in internal timing mode.
D3 = n ( D1 - kD2 ) (EQ. 15)
Solution 2 - Using External Timing Mode From solution 1, the desired integration time is 100ms. Note that the REXT resistor only determines the inter oscillator frequency when using external timing mode. Instead the integration time is the time between two sync_iic commands sent through the I2C. The programmer determines how many I2C clock cycles to wait between two external timing commands. iI2C = fI2C * Tint = number of I2C clock cycles iI2C = 10kHz *100ms iI2C = 1,000 I2C clock cycles. An external sync_iic command sent 1,000 cycles after another sync_iic command rejects both 60Hz and 50Hz AC noise signals. Next is to pick an arbitrary REXT = 100k and to choose the Gain/Range Mode. For a maximum 500Lux, Range1 is adequate. From Equation 3:
100k FSR = 1000lux ----------------100k FSR = 1000Lux
Where: D3 = Lux amount in number of counts less IR presence D1 = data reading of Diode 1 D2 = data reading of Diode 2 n = 1.355. This is a fudge factor to scale back the sensitivity up to ensure Equation 4 is valid. k = 3.355. This is a scaling factor for the IR sensitive Diode 2.
Flat Window Lens Design
A window lens will surely limit the viewing angle of the ISL29004. The window lens should be placed directly on top of the device. The thickness of the lens should be kept at minimum to minimize loss of power due to reflection and also to minimize loss of loss due to absorption of energy in the plastic material. A thickness of t = 1mm is recommended for a window lens design. The bigger the diameter of the window lens the wider the viewing angle is of the ISL29001. Table 16 shows the recommended dimensions of the optical window to ensure both +35 and +45 viewing angle. These
The effective transfer function becomes:
DATA E = ------------------------------- x 1000Lux COUNTER
DATA is the sensor reading data located in data registers 04(hex) and 05(hex) COUNTER is the timer counter value data located in data registers 06(hex) and 07(hex). In this sample problem, COUNTER = 1000.
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FN6221.0 December 21, 2006
ISL29004
dimensions are based on a window lens thickness of 1.0mm and a refractive index of 1.59.
WINDOW LENS
TABLE 16. RECOMMENDED DIMENSIONS FOR A FLAT WINDOW DESIGN DTOTAL 1.5 D1 0.50 1.00 1.50 2.00 2.50 DLENS @ 35 VIEWING ANGLE 2.25 3.00 3.75 4.30 5.00 DLENS @ 45 VIEWING ANGLE 3.75 4.75 5.75 6.75 7.75
t
2.0
DTOTAL
2.5 3.0 3.5
D1
ISL29003/4
DLENS
t=1 D1 DLENS DTOTAL
= VIEWING ANGLE
Thickness of lens Distance between ISL29001 and inner edge of lens Diameter of lens Distance constraint between the ISL29001 and lens outer edge
* All dimensions are in mm. FIGURE 4. FLAT WINDOW LENS
Window with Light Guide Design
If a smaller window is desired while maintaining a wide effective viewing angle of the ISL29004, a cylindrical piece of transparent plastic is needed to trap the light and then focus and guide the light on to the device. Hence the name light guide or also known as light pipe. The pipe should be placed directly on top of the device with a distance of D1 = 0.5mm to achieve peak performance. The light pipe should have minimum of 1.5mm in diameter to ensure that whole area of the sensor will be exposed. See Figure 5.
DLENS
D2 > 1.5mm LIGHT PIPE
t D2 DLENS
L
ISL29003/ISL29004
FIGURE 5. WINDOW WITH LIGHT GUIDE/PIPE
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FN6221.0 December 21, 2006
ISL29004
even in significantly noisy environments. There are only a few considerations that will ensure best performance. Route the supply and I2C traces as far as possible from all sources of noise. Use two power-supply decoupling capacitors, 4.7F and 0.1F, placed close to the device.
Typical Circuit
A typical application for the ISL29004 is shown in Figure 7. Additional I2C address select pins A0 and A1 are available for the ISL29004 so a maximum of four ISL29004 devices can be tied on the same I2C bus line.
Soldering Considerations
Dimensions in mm
FIGURE 6. SUGGESTED PCB FOOTPRINT
Suggested PCB Footprint
Footprint pads should be a nominal 1-to-1 correspondence with package pads. The large exposed central die-mounting paddle in the center of the package has no electrical connection. It is, however, recommended to have the thermal pad soldered to GND for package reliability.
Convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. The ISL29004's plastic ODFN package does not require a custom reflow soldering profile, and is qualified up to +260C. A standard reflow soldering profile with a +260C maximum is recommended.
Special Handling
ODFN8 is rated as JEDEC moisture level 4. Standard JEDEC Level 4 procedure should be followed: 72hr floor life at less than +30C 60% RH. When baking the device, the temperature required is +110C or less due to its special molding compound.
Layout Considerations
The ISL29004 is relatively insensitive to layout. Like other I2C devices, it is intended to provide excellent performance
I2C MASTER MICROCONTROLLER
SDA SCL
R1 10K R2 10K VDD C1 1 0.1uF 2 REXT1 100K 4 3 GND REXT A0 SCL INT A1 7 6 5 REXT2 100K 4 VDD SDA 8 0.1uF 2 3 GND REXT A0 SCL INT A1 7 6 5 REXT3 RES1 4
I2C SLAVE_44
C2
VDD 1
I2C SLAVE_45
C3 VDD SDA 8 0.1uF
VDD 1 2 3
I2C SLAVE_46
C4 VDD GND REXT A0 SDA SCL INT A1 8 0.1uF 7 6 5 REXT4 RES1
VDD 1 2 3 4
I2C SLAVE_47
VDD GND REXT A0 SDA SCL INT A1 8 7 6 5
ISL29004
ISL29004
ISL29004
ISL29004
FIGURE 7. ISL29004 TYPICAL CIRCUIT
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FN6221.0 December 21, 2006
ISL29004 Typical Performance Curves (REXT = 100k)
14 NUMBER OF COUNTS 60k 50k 40k 30k 20k 10k 400 500 600 700 800 WAVELENGTH (nm) 900 1000 1100 1k 2k 3k 4k 5k 6k 7k LUMINANCE (LUX) 8k 9k D1 D2 FLUORESCENT LIGHT SOURCE RANGE3 13 12 11 10 9 8 7 6 10k D1/D2 RATIO
NORMALIZED RESPONSE (%)
100 90 80 70 60 50 40 30 20 10 0 300
D3 EFFECTIVE RESPONSE
D3 = n(D1 - kD2) n = 1.3, k = 3.355
D1 NORMALIZED D2 NORMALIZED
FIGURE 8. SPECTRAL RESPONSE
FIGURE 9. D1 AND D2 FLUORESCENT LIGHT SOURCE RESPONSE
60k NUMBER OF COUNTS 50k 40k 30k 20k 10k 0 0
D1
NUMBER OF COUNTS
HALOGEN LIGHT SOURCE RANGE3
1k
2k
3k
4k
5k
6k
7k
D2 8k 9k
14 13 12 11 10 9 8 7 6 5 4 3 2 10k
60k SUNLIGHT SOURCE RANGE3 50k D1 40k 30k 20k 10k 0 0 1k 2k 3k 4k 5k 6k 7k 8k 9k D2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 10k
D1/D2 RATIO
D1/D2 RATIO
LUMINANCE (LUX)
LUMINANCE (LUX)
FIGURE 10. D1 AND D2 HALOGEN LIGHT SOURCE RESPONSE
FIGURE 11. D1 AND D2 SUNLIGHT RESPONSE
60k NUMBER OF COUNTS 50k 40k 30k 20k 10k 1k
D1
INCANDESCENT BULB RANGE3 D2
2k
3k
4k
5k
6k
7k
8k
9k
15 14 13 12 11 10 9 8 7 6 5 4 3 2 10k
RADIATION PATTERN
LUMINOSITY ANGLE
D1/D2 RATIO
LUMINANCE (LUX)
RELATIVE SENSITIVITY
FIGURE 13. RADIATION PATTERN
FIGURE 12. D1 AND D2 INCANDESCENT LIGHT SOURCE RESPONSE
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FN6221.0 December 21, 2006
ISL29004 Typical Performance Curves (REXT = 100k)
320 TA = +27C COMMAND = 00H SUPPLY CURRENT (A) 306 5000 LUX 292 OUTPUT CODE (COUNTS)
(Continued)
10 TA = +27C COMMAND = 00H 0 LUX RANGE 2
8
6
278 200 LUX 264
4
2
250 2.0
2.3
2.6
2.9
3.2
3.5
3.8
0 2.0
2.3
2.6
2.9
3.2
3.5
3.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 15. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE
1.015 OUTPUT CODE RATIO (% FROM 3V) OSCILLATOR FREQUENCY (kHz) TA = +27C COMMAND = 00H 0 LUX
320.0
1.010
5000 LUX
319.5
1.005
319.0
1.000 200 LUX 0.995
318.5
0.990 2.0
2.3
2.6
2.9
3.2
3.5
3.8
318.0 2.0
2.3
2.6
2.9
3.2
3.5
3.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 16. OUTPUT CODE vs SUPPLY VOLTAGE
FIGURE 17. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE
315 VDD = 3V COMMAND = 00H SUPPLY CURRENT (A) 305 5000 LUX 295 OUTPUT CODE (COUNTS)
10 VDD = 3V COMMAND = 00H 0 LUX
8
6
285 200 LUX 275
4
2
265 -60
-20
20 TEMPERATURE (C)
60
100
0 -60
-20
20 TEMPERATURE (C)
60
100
FIGURE 18. SUPPLY CURRENT vs TEMPERATURE
FIGURE 19. OUTPUT CODE FOR 0 LUX vs TEMPERATURE
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FN6221.0 December 21, 2006
ISL29004 Typical Performance Curves (REXT = 100k)
OUTPUT CODE RATIO (% FROM +25C) 1.080 OSCILLATOR FREQUENCY (kHz) VDD = 3V COMMAND = 00H 1.048 5000 LUX RANGE 3 1.016 200 LUX RANGE 1
(Continued)
330 VDD = 3V 329
328
0.984
327
0.952
326
0.920 -60
-20
20 TEMPERATURE (C)
60
100
325 -60
-20
20 TEMPERATURE (C)
60
100
FIGURE 20. OUTPUT CODE vs TEMPERATURE
FIGURE 21. OSCILLATOR FREQUENCY vs TEMPERATURE
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FN6221.0 December 21, 2006
ISL29004 Optical Dual Flat No-Lead Family (ODFN)
A 4 5 D 4 0.10 C 2X E 0.10 C 2X
MDP0052
OPTICAL DUAL FLAT NO-LEAD FAMILY SYMBOL A A1 b ODFN5 0.70 0.02 0.30 0.20 2.00 1.35 2.10 0.65 0.65 1.30 0.35 ODFN6 0.70 0.02 0.30 0.20 2.00 1.35 2.10 0.65 0.65 1.30 0.35 ODFN8 0.70 0.02 0.30 0.20 3.00 2.29 3.00 1.40 0.65 1.95 0.40 TOLERANCE 0.05 +0.03/-0.02 0.05 Reference Basic Reference Basic Reference Basic Basic 0.05 Rev. 4 5/06 NOTES: 3 3 2 NOTE
B
1 5
2
3
c
TOP VIEW 3
D D2 E
(D2) e1 4 5 L TYP. 3 (E2) PIN #1 I.D. b 0.10 BOTTOM VIEW 5 LD ODFN (2.0x2.1 BODY) 3 (D2) e1 45 CAB
E2 e e1 L
3 e
2
1
1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Exposed lead at side of package is a non-functional feature. 3. Dimension D2 and E2 define the size of the exposed pad. 4. ODFN 5 Ld version has no center lead (shown as dashed line).
6 L TYP.
5
3 (D2) e1 7 6
8 L TYP.
3 (E2) PIN #1 I.D. b 0.10 BOTTOM VIEW 6 LD ODFN (2.0x2.1 BODY)
3
(E2) PIN #1 I.D.
3 e
2
1
CAB
4 e
3
2
1
b 0.10 CAB
BOTTOM VIEW 8 LD ODFN (3.0x3.0 BODY)
0.10 C C SEATING PLANE 0.08 C (ALL LEADS and EXPOSED PAD) SEE DETAIL "X" C A (C) 2
A1 DETAIL X
SIDE VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6221.0 December 21, 2006

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