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FEATURES
Preliminary Technical Data
Blackfin(R) Embedded Processor ADSP-BF539/ADSP-BF539F
External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI(R), external memory
1.0 V to 1.2 V core VDD with on-chip voltage regulation 3.3 V tolerant I/O with specific 5 V tolerant pins 316-ball Pb-free mini-BGA package Up to 500 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler friendly support Advanced debug, trace, and performance monitoring
PERIPHERALS
Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Four dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I2S(R) channels Two DMA controllers supporting 26 channels Controller area network (CAN) 2.0B controller Media transceiver (MXVR) for connection to a MOST(R) network Three SPI-compatible ports Three timer/counters with PWM support Three UARTs with support for IrDA(R) Two TWI controllers compatible with I2C(R) industry standard 38 general purpose I/O pins (GPIO) 16 general purpose flag pins (GPF) Real time clock Watchdog timer Debug/JTAG interface On-chip PLL capable of 0.5x To 64x frequency multiplication
MEMORY
148K bytes of on-chip memory: 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K x 16-bits or 256K x 16-bits of flash memory (ADSP-BF539F only) Four dual-channel memory DMA controllers Memory management unit providing memory protection
JTAGTESTAND EM ULATION
EVENT CONTROLLER/ CORETIMER
WATCHDOGTIMER MXVR REALTIMECLOCK PPI / GPF CAN2.0B TIMER0, 1, 2 UART0, 1, 2
VOLTAGE REGULATOR
B
L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY CORE/ SYSTEMBUSINTERFACE
GPIO TWI0, 1 DMA CONTROLLER SPORT0, 1, 2, 3
SPI PORT BOOT ROM EXTERNALPORT FLASH, SDRAM CONTROL 256KX16-BITOR 512KX16-BIT FLASHMEM ORY
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADSP-BF539/ADSP-BF539F
TABLE OF CONTENTS
General Description ................................................. 4 Low Power Architecture ......................................... 4 System Integration ................................................ 4 ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 4 Blackfin Processor Core .......................................... 5 Memory Architecture ............................................ 5 DMA Controllers ................................................ 10 Real Time Clock ................................................. 10 Watchdog Timer ................................................ 11 Timers ............................................................. 11 Serial Ports (SPORTs) .......................................... 11 Serial Peripheral Interface (SPI) Ports ...................... 11 Two Wire Interface ............................................. 12 UART Port ........................................................ 12 Programmable I/O Pins ........................................ 12 Parallel Peripheral Interface ................................... 13 Controller Area Network (CAN) Interface ................ 14 Media Transceiver MAC layer (MXVR) ................... 14 Dynamic Power Management ................................ 15 Voltage Regulation .............................................. 16 Clock Signals ..................................................... 16 Booting Modes ................................................... 17 Instruction Set Description ................................... 18 Development Tools ............................................. 18 Designing an Emulator Compatible Processor Board ... 19 Example Connections and Layout Considerations ...... 19 Voltage Regulator Layout Guidelines ....................... 19 MXVR Board Layout Guidelines ............................ 19 Pin Descriptions .................................................... 22 Specifications ........................................................ 27 Recommended Operating Conditions ...................... 27 Recommended Operating Conditions --Applies to 5V Tolerant pins ............................. 27
Preliminary Technical Data
Electrical Characteristics ....................................... 27 Absolute Maximum Ratings ................................... 28 Package Information ............................................ 28 ESD Sensitivity ................................................... 28 Timing Specifications ........................................... 29 Clock and Reset Timing ..................................... 30 Asynchronous Memory Read Cycle Timing ............ 31 Asynchronous Memory Write Cycle Timing ........... 35 SDRAM Interface Timing .................................. 37 External Port Bus Request and Grant Cycle Timing .. 38 Parallel Peripheral Interface Timing ...................... 41 Serial Ports Timing ........................................... 44 Serial Peripheral Interface (SPI) Port --Master Timing ........................................... 48 Serial Peripheral Interface (SPI) Port --Slave Timing ............................................. 49 Universal Asynchronous Receiver-Transmitter (UART) Port Timing ..................................... 50 Programmable Flags Cycle Timing ....................... 51 Timer Cycle Timing .......................................... 52 JTAG Test And Emulation Port Timing ................. 53 TWI Controller Timing ..................................... 54 MXVR Timing ................................................ 58 CAN Timing ................................................... 59 Output Drive Currents ......................................... 60 Power Dissipation ............................................... 62 Test Conditions .................................................. 62 Environmental Conditions .................................... 65 316-Ball Mini-BGA Pinout ....................................... 66 Outline Dimensions ................................................ 69 Ordering Guide ..................................................... 70
REVISION HISTORY
5/06--Revision PrE: Added Maximum Duty Cycle for Input Transient Voltage 28 Added Package Information ..................................... 28 Added values in Power Dissipation ............................ 61 Added graphs in Output Drive Currents ...................... 59 Added graphs in Capacitive Loading .......................... 62 Changes Ordering Guide .......................................... 67 12/05--Revision PrD: Changes number of GPIO and GPF pins Peripherals ........ 1 Changes wording in System Integration ........................ 4 Changes voltage regulator range in ADSP-BF539 processor Peripherals ............................................................ 4
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Preliminary Technical Data
Changes voltage regulator range in Voltage Regulation .... 15 Changes to Figure 8 and MXVR Board Layout Guidelines 19 Modified Example connections of ADSP-BF539 to MOST Network ............................................................... 19 Changes to CAN, MXVR., and UART pullup in Pin Descriptions .......................................................... 20 Adds footnotes to Recommended Operating Conditions .. 25 Adds footnotes to Absolute Maximum Ratings .............. 26 Adds die temperature specification Absolute Maximum Ratings 26 Adds table and figure to Asynchronous Memory Read Cycle Timing ................................................................. 29 Adds table and figure to Asynchronous Memory Write Cycle Timing ................................................................. 31 Deletes footnotes in External Port Bus Request and Grant Cycle Timing ................................................................. 34 Adds tWBR to External Port Bus Request and Grant Cycle Timing 34 Replaced Figure 17, Figure 18, Figure 19, and Figure 20 ... 38 Added footnotes in Serial Ports--External Clock and Serial Ports--Internal Clock .............................................. 39 Changes to lower diagram in Serial Ports ...................... 40 Changes to External Late Frame Sync (Frame Sync Setup < tSCLKE/2) ............................................................ 41 Replace section Power Dissipation .............................. 57 Added overbar to AOE in 316-Ball Sparse Mini-BGA Pin Assignment (Alphabetically by Signal) ......................... 63 Adds section Surface Mount Design ............................ 65
ADSP-BF539/ADSP-BF539F
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ADSP-BF539/ADSP-BF539F
GENERAL DESCRIPTION
The ADSP-BF539/ADSP-BF539F processors are a members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF539/ADSP-BF539F processors are completely code compatible with other Blackfin processors, differing only with respect to performance, peripherals, and on-chip memory. Specific performance, peripherals, and memory configurations are shown in Table 1 on Page 4. Table 1. Processor Features
ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8 Maximum Performance Instruction SRAM/Cache Instruction SRAM Data SRAM/Cache Data SRAM Scratchpad Flash SPORTs SPI TWI UARTs PPI CAN MXVR 500 MHz 500 MHz 1000 MMACs 1000 MMACs 16K bytes 64K bytes 32K bytes 32K bytes 4K bytes Not applicable 4 3 2 3 1 1 1 16K bytes 64K bytes 32K bytes 32K bytes 4K bytes 256K x 16-bit 4 3 2 3 1 1 1 316 500 MHz 1000 MMACs 16K bytes 64K bytes 32K bytes 32K bytes 4K bytes 512K x 16-bit 4 3 2 3 1 1 1 316
Preliminary Technical Data
substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life and lower heat dissipation.
SYSTEM INTEGRATION
The ADSP-BF539/ADSP-BF539F processor is a highly integrated system-on-a-chip solution for the next generation of industrial and automotive applications including audio and video signal processing. By combining advanced memory configurations, such as on-chip flash memory, with industrystandard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a MOST(R) Network Media Transceiver (MXVR), three UART ports, three SPI ports, four serial ports (SPORT), one CAN interface, two Two-Wire-Interfaces (TWI), four general purpose timers (three with PWM capability), a real-time clock, a watchdog timer, a Parallel Peripheral Interface, general purpose I/O, and general purpose flag pins.
ADSP-BF539/ADSP-BF539F PROCESSOR PERIPHERALS
The ADSP-BF539/ADSP-BF539F processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). The general purpose peripherals include functions such as UART, Timers with PWM (Pulse Width Modulation) and pulse measurement capability, general purpose flag I/O pins, a Real Time Clock, and a Watchdog Timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the device. In addition to these general purpose peripherals, the ADSP-BF539/ADSP-BF539F processor contains high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions. An MXVR transceiver transmits and receives audio and video data and control information on a MOST(R) automotive multimedia network. A CAN 2.0B controller is provided for automotive control networks. An interrupt controller manages interrupts from the on-chip peripherals or external sources. And power management control functions tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general purpose I/O, CAN, TWI, Real Time Clock, and timers, are supported by a flexible DMA structure. There are also four separate memory DMA controllers dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF539/ADSP-BF539F processor includes an on-chip voltage regulator in support of the ADSP-BF539/ADSP-BF539F processor Dynamic Power Management capability. The voltage
Package option 316
By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like programmability, multimedia support and leading edge signal processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a
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Preliminary Technical Data
regulator provides a range of core voltage levels from a single 2.7 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion.
ADSP-BF539/ADSP-BF539F
memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while Supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 6, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit Index, Modify, Length, and Base registers (for circular buffering), and eight additional 32-bit pointer registers (for C style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction
MEMORY ARCHITECTURE
The ADSP-BF539/ADSP-BF539F processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3 on Page 7. The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high bandwidth data movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.
Internal (On-chip) Memory
The ADSP-BF539/ADSP-BF539F processor has three blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory, consisting of 80K bytes SRAM, of which 16K bytes can be configured as a four way setassociative cache. This memory is accessed at full processor speed.
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ADSP-BF539/ADSP-BF539F
ADDRESS ARITHMETIC UNIT
Preliminary Technical Data
I3 I2 I1 I0 DA1 DA0 TO MEMORY 32 32
L3 L2 L1 L0
B3 B2 B1 B0
M3 M2 M1 M0 DAG1 DAG0
SP FP P5 P4 P3 P2 P1 P0
32 RAB
32 PREG
SD LD1 LD0
32 32 32
32 32
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.H R0.L BARREL SHIFTER 16 8 8 8 16 8 DECODE ALIGN
40 40 40
40
LOOP BUFFER
A0
A1
CONTROL UNIT
32
32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The second on-chip memory block is the L1 data memory, consisting of two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.
1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory.
Flash Memory (ADSP-BF539F only)
The ADSP-BF539F4 and ADSP-BF539F8 processors contain a separate flash die, connected to the EBIU bus, within the package of the ADSP-BF539F processors. Figure 4 on Page 7 shows how the flash memory die and Blackfin processor die are connected. The ADSP-BF539F4 contains a 4 Mbit (256K x 16-bits) bottom boot sector flash memory. The ADSP-BF539F8 contains an 8 Mbit (512K x 16-bits) bottom boot sector flash memory. Features include the following. * access times as fast as 70 ns (EBIU registers be set appropriately) * sector protection * one million write cycles per sector * 20 year data retention The Blackfin processor connects to the flash memory die with address, data, chip enable, write enable, and output enable controls as if it were an external memory device.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a
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Preliminary Technical Data
0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (32K BYTE) 0xFFA0 8000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTE) 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 RESERVED 0x2040 0000 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) OR ON-CHIP FLASH 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) OR ON-CHIP FLASH 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) OR ON-CHIP FLASH 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE - 128M BYTE) 0x0000 0000
EXTERNAL MEMORY MAP INTERNAL MEMORY MAP
ADSP-BF539/ADSP-BF539F
Flash Memory Programming The ADSP-BF539F4 and ADSP-BF539F8 flash memory may be programmed before or after mounting on the printed circuit board. To program the flash prior to mounting on the printed circuit board, use a hardware programming tool that can provide the data, address, and control stimuli to the flash die through the external pins on the package. During this programming, VDDEXT and GND must be provided to the package and the Blackfin must be held in reset with bus request (BR) asserted and a CLKIN provided. The VDSP++ tools may be used to program the flash memory after the device is mounted on a printed circuit board. Flash Memory Sector Protection To use the sector protection feature, a high voltage (+12 V nominal) must be applied to the flash FRESET pin. Refer to the flash datasheet for details.
0xFFB0 0000
ASYNC MEMORY BANK 3 (1M BYTE) OR ON-CHIP FLASH
I/O Memory Space
Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.
Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map
ADDr19-1 ARE AWE ARDY DatA15-0 GND VDDEXT
Booting
A18-0 OE WE RY/BY DQ15-0 VSS VCC BYTE CE RESET
Blackfin die
GND VDDEXT AMS3-0 RESET
flash die
ADDR19-1 ARE AWE ARDY DATA15-0
The ADSP-BF539/ADSP-BF539F processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF539/ADSP-BF539F processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 17.
Event Handling
The event controller on the ADSP-BF539/ADSP-BF539F processor handles all asynchronous and synchronous events to the processor. The ADSP-BF539/ADSP-BF539F processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. * Reset - This event resets the processor.
ADSP-BF539F package
RESET AMS3-0 FCE FRESET
Figure 4. Internal Connection of Flash Memory
The flash chip enable pin FCE must be connected to AMS0 or AMS3-1 through a printed circuit board trace. When connected to AMS0 the Blackfin processor can boot from the flash die. When connnected to AMS3-1 the flash memory will appear as non-volatile memory in the processor memory map shown in Figure 3 on Page 7.
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ADSP-BF539/ADSP-BF539F
* Non-Maskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. * Exceptions - Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF539/ADSP-BF539F processor Event Controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general purpose interrupts of the CEC.
Preliminary Technical Data
cessor. Table 2 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 2. Core Event Controller (CEC)
Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control Reset Non-Maskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX -- IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Core Event Controller (CEC)
The CEC supports nine general purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general purpose interrupts, the two lowest priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF539/ADSP-BF539F pro-
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general purpose interrupt inputs of the CEC. Although the ADSP-BF539/ADSP-BF539F processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Table 3. System and Core Event Mapping
Event Source PLL Wakeup Interrupt DMA Controller 0 Error DMA Controller 1 Error PPI Error Interrupt SPORT0 Error Interrupt SPORT1 Error Interrupt SPORT2 Error Interrupt SPORT3 Error Interrupt MXVR Synchronous Data Interrupt SPI0 Error Interrupt SPI1 Error Interrupt SPI2 Error Interrupt Core Event Name IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7
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Preliminary Technical Data
Table 3. System and Core Event Mapping (Continued)
Event Source UART0 Error Interrupt UART1 Error Interrupt UART2 Error Interrupt CAN Error Interrupt Real Time Clock Interrupts DMA0 Interrupt (PPI) DMA1 Interrupt (SPORT0 RX) DMA2 Interrupt (SPORT0 TX) DMA3 Interrupt (SPORT1 RX) DMA4 Interrupt (SPORT1 TX) DMA12 Interrupt (SPORT2 RX) DMA13 Interrupt (SPORT2 TX) DMA14 Interrupt (SPORT3 RX) DMA15 Interrupt (SPORT3 TX) DMA5 Interrupt (SPI0) DMA18 Interrupt (SPI1) DMA19 Interrupt (SPI2) DMA6 Interrupt (UART0 RX) DMA7 Interrupt (UART0 TX) DMA20 Interrupt (UART1 RX) DMA21 Interrupt (UART1 TX) DMA22 Interrupt (UART2 RX) DMA23 Interrupt (UART2 TX) Timer0, Timer1, Timer2 Interrupts TWI0 Interrupt TWI1 Interrupt CAN Receive Interrupt CAN Transmit Interrupt MXVR Status Interrupt MXVR Control Message Interrupt MXVR Asynchronous Packet Interrupt Programmable Flags Interrupt MDMA0 Stream 0 Interrupt MDMA0 Stream 1 Interrupt MDMA1 Stream 0 Interrupt MDMA1 Stream 1 Interrupt Software Watchdog Timer Core Event Name IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13
ADSP-BF539/ADSP-BF539F
Event Control
The ADSP-BF539/ADSP-BF539F processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: * CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may also be written to clear (cancel) latched events. This register may be read while in supervisor mode and may only be written while in supervisor mode when the corresponding IMASK bit is cleared. * CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) * CEC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 8. * SIC Interrupt Mask Registers (SIC_IMASKx)- These registers control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in these registers masks the peripheral event, preventing the processor from servicing the event. * SIC Interrupt Status Registers (SIC_ISRx) - As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. * SIC Interrupt Wakeup Enable Registers (SIC_IWRx) - By enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 15.) Because multiple interrupt sources can map to a single general purpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
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ADSP-BF539/ADSP-BF539F
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
Preliminary Technical Data
DMA transfers can be controlled by a very flexible descriptor based methodology or by a standard register based autobuffer mechanism.
REAL TIME CLOCK
The ADSP-BF539/ADSP-BF539F processor Real Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 KHz crystal external to the ADSP-BF539/ADSP-BF539F processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 KHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hour counter, and an 32,768 day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSPBF539/ADSP-BF539F processor from Sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the ADSP-BF539/ADSP-BF539F processor from Deep Sleep mode, and wake up the on-chip internal voltage regulator from a powered down state. Connect RTC pins RTXI and RTXO with external components as shown in Figure 5.
RTXI R1 RTXO
DMA CONTROLLERS
The ADSP-BF539/ADSP-BF539F processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF539/ADSP-BF539F processor internal memories and any of its DMA capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA capable peripheral has at least one dedicated DMA channel. The MXVR peripheral has its own dedicated DMA controller, which supports its own unique set of operating modes. The ADSP-BF539/ADSP-BF539F processor DMA controllers support both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the ADSP-BF539/ADSPBF539F processor DMA controller include: * A single, linear buffer that stops upon completion * A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer * 1-D or 2-D DMA using a linked list of descriptors * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are four memory DMA channels provided for transfers between the various memories of the ADSP-BF539/ADSP-BF539F processor system. This enables transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory
X1 C1 C2
SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE-MO UNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFI CATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 5. External Components for RTC
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Preliminary Technical Data
WATCHDOG TIMER
The ADSP-BF539/ADSP-BF539F processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF539/ADSP-BF539F processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK.
ADSP-BF539/ADSP-BF539F
* Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 to 32 bits in length, transferred most significant bit first or least significant bit first. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1024 channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.
TIMERS
There are four general purpose programmable timer units in the ADSP-BF539/ADSP-BF539F processor. Three timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK. The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the three general purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF539/ADSP-BF539F processors incorporate three SPI compatible ports that enable the processor to communicate with multiple SPI compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSIx, and master input-slave output, MISOx) and a clock pin (serial clock, SCKx). An SPI chip select input pin (SPIxSS) lets other SPI devices select the processor. For SPI0, seven SPI chip select output pins (SPI0SEL7-1) let the processor select other SPI devices. The SPI select pins are reconfigured GPIO pins. SPI1 and SPI2 have a single SPI select for SPI point-to-point communication. Using these pins, the SPI ports provide a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI ports' baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. Each SPI's DMA controller can only service unidirectional accesses at any given time. The SPI port clock rate is calculated as: f SCLK SPI Clock Rate = -------------------------------2 x SPI_Baud Where the 16-bit SPI_Baud register contains a value of 2 to 65,535.
SERIAL PORTS (SPORTS)
The ADSP-BF539/ADSP-BF539F processor incorporates four dual-channel synchronous serial ports for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.
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ADSP-BF539/ADSP-BF539F
During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
Preliminary Technical Data
The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA(R)) Serial Infrared Physical Layer Link Specification (SIR) protocol.
PROGRAMMABLE I/O PINS
The ADSP-BF539/ADSP-BF539F processor has numerous peripherals that may not all be required for every application. Many of the pins thus have a secondary function, as general purpose I/O pins. There are two types of programmable I/O pins on the ADSP-BF539/ADSP-BF539F processor, with slightly different functionality: programmable flags and general purpose I/O.
TWO WIRE INTERFACE
The ADSP-BF539/ADSP-BF539F processor incorporates two Two Wire Interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation, support for 7-bit addressing and multimedia data arbitration. The TWI also includes master clock synchronization and support for clock low extension. The TWI interface uses two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400 kbits/sec. The TWI interface pins are compatible with 5V logic levels.
Programmable Flags (PFx)
The ADSP-BF539/ADSP-BF539F processor has 16 bi-directional, general purpose Programmable Flag (PF15-0) pins. Each programmable flag can be individually controlled by manipulation of the flag control, status and interrupt registers: * Flag Direction Control Register - Specifies the direction of each individual PFx pin as input or output. * Flag Control and Status Registers - The ADSPBF539/ADSP-BF539F processor employs a "write one to modify" mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags. Four control registers are provided. One register is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the flags. * Flag Interrupt Mask Registers - The two Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two Flag Control Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable interrupt function, and the other Flag Interrupt Mask register clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts. * Flag Interrupt Sensitivity Registers - The two Flag Interrupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify--if edge-sensitive--whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
UART PORT
The ADSP-BF539/ADSP-BF539F processor incorporates three full-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which are fully compatible with PC standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA supported, asynchronous transfers of serial data. The UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: * PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O mapped UART registers. The data is double buffered on both transmit and receive. * DMA (Direct Memory Access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: * Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. * Supporting data formats from 7 to12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port's clock rate is calculated as: f SCLK UART Clock Rate = ---------------------------------------------16 x UART_Divisor Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8 bits). In conjunction with the general purpose timer functions, autobaud detection is supported.
General Purpose I/O
The ADSP-BF539/ADSP-BF539F has 38 General Purpose I/O pins that are multiplexed with other peripherals. They are arranged into Port C, D, E as shown in Table 4 on Page 13. The GPIO differ from the Programmable Flags in that the GPIO pins cannot generate interrupts to the processor.
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Preliminary Technical Data
The general purpose I/O pins may be individually controlled by manipulation of the control and status registers. These pins will not cause interrupts to be generated to the processor, but may be polled to determine their status. * GPIO Direction Control Register - Specifies the direction of each individual GPIOx pin as input or output. * GPIO Control and Status Registers - The ADSPBF539/ADSP-BF539F processor employs a "write one to modify" mechanism that allows any combination of individual GPIO to be modified in a single instruction, without affecting the level of any other GPIO. Four control registers and a Data register are provided for each GPIO port. One register is written in order to set GPIO values, one register is written in order to clear GPIO values, one register is written in order to toggle GPIO values, and one register is written in order to specify a GPIO input or output. Reading the GPIO Data allows software to determine the state of the input GPIO pins. Note that the GP pin is used to specify the status of the GPIO ports C9-C4 at power up. If GP is tied high, then ports C9-C4 are configured as GPIO pins after reset. The ports cannot be reconfigured through software and special care must be taken with the MLF pin. If the GP pin is tied low, then the ports are configured as MXVR pins after reset, but may be reconfigured as GPIO pins through software. Table 4. Programmable Flag / GPIO Ports
Peripheral PPI SPORT0 SPORT1 SPORT2 SPORT3 SPI0 SPI1 SPI2 UART0 UART1 UART2 CAN MXVR TWI0 TWI1 GPIO Port D11-10 GPIO Port D13-12 GPIO Port C1-0 GPIO Port C9-4 GPIO Port D4-0 GPIO Port D9-5 GPIO Port E7-0 GPIO Port E15-8 Alternate Programmable Flag / GPIO Port Function PF15-0
ADSP-BF539/ADSP-BF539F
up to 16 data pins. The input clock supports parallel data rates up to fSCLK/2 MHz, and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general purpose and ITU-R 656 modes of operation. In general purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to 3 frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex, bi-directional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported.
General Purpose Mode Descriptions
The General Purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: * Input Mode - Frame Syncs and data are inputs into the PPI. * Frame Capture Mode - Frame Syncs are outputs from the PPI, but data are inputs. * Output Mode - Frame Syncs and data are outputs from the PPI.
Input Mode
This mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_Count register. Data widths of 8, 10, 11, 12, 13, 14, 15 and 16-bits are supported, as programmed by the PPI_CONTROL register.
Frame Capture Mode
This mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF539/ADSP-BF539F processor controls when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output.
Output Mode
This mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling. ITU-R 656 Mode Descriptions The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct submodes are supported: * Active Video Only Mode * Vertical Blanking Only Mode * Entire Field Mode
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF539/ADSP-BF539F processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, video encoders and decoders, and other general purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and
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ADSP-BF539/ADSP-BF539F
Active Video Only Mode
This mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI will not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI will ignore incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_Count register).
Preliminary Technical Data
The electrical characteristics of each network connection are very stringent, therefore the CAN interface is typically divided into 2 parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks. The ADSP-BF539/ADSP-BF539F CAN module represents the controller part of the interface. This module's network I/O is a single transmit output and a single receive input, which connect to a line transceiver. The CAN clock is derived from the processor System Clock (SCLK) through a programmable divider and therefore does not require an additional crystal.
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval (VBI) data.
MEDIA TRANSCEIVER MAC LAYER (MXVR)
The ADSP-BF539/ADSP-BF539F processor provides a Media Transceiver (MXVR) MAC layer, allowing the processor to be connected directly to a MOST(R) network through just an FOT or Electrical PHY. The MXVR is fully compatible with the industry standard standalone MOST controller devices, supporting 22.579 Mbps or 24.576 Mbps data transfer. It offers faster lock times, greater jitter immunity, a sophisticated DMA scheme for data transfers, and the high-speed internal interface to the core and L1 memory allows the full bandwidth of the network to be utilized. The MXVR can operate as either the network master or as a network slave. The MXVR supports synchronous data, asynchronous packets, and control messages using dedicated DMA engines which operate autonomously from the processor core moving data to and from L1 memory. Synchronous data is transferred to or from the synchronous data channels through eight programmable DMA engines. The synchronous data DMA engines can operate in various modes including modes which trigger DMA operation when data patterns are detected in the receive data stream. Furthermore two DMA engines support asynchronous traffic and a further two support control message traffic. Interrupts are generated when a user defined amount of synchronous data has been sent or received by the processor or when asynchronous packets or control messages have been sent or received. The MXVR peripheral can wake up the ADSP-BF539/ADSPBF539F processor from Sleep mode when a wakeup preamble is received over the network or based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F processor from Deep Sleep or Hibernate mode, and wake up the on-chip internal voltage regulator from a powered-down state. These features allow the ADSP-BF539/ADSP-BF539F to operate in a low-power state when there is no network activity or when data is not currently being received or transmitted by the MXVR. The MXVR clock is provided through a dedicated external crystal or crystal oscillator. For 44.1 KHz frame syncs, a 45.1584 MHz crystal or oscillator should be used; or for 48 KHz frame syncs, a 49.152 MHz crystal or oscillator should be used.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. The MXVR supports synchronous data, asynchronous packets and control messages. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core.
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF539/ADSP-BF539F processor provides a CAN controller that is a communication controller implementing the Controller Area Network (CAN) V2.0B protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. CAN is well suited for control applications due to its capability to communicate reliably over a network since the protocol incorporates CRC checking message error tracking, and fault node confinement. The CAN controller is based on a 32 entry mailbox RAM and supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B. Each mailbox consists of eight 16-bit data words. The data is divided into fields, which includes a message identifier, a time stamp, a byte count, up to 8 bytes of data, and several control bits. Each node monitors the messages being passed on the network. If the identifier in the transmitted message matches an identifier in one of it's mailboxes, then the module knows that the message was meant for it, passes the data into it's appropriate mailbox, and signals the processor of message arrival with an interrupt. The CAN Controller can wake up the ADSP-BF539/ADSPBF539F processor from Sleep mode upon generation of a wakeup event, such that the processor can be maintained in a low power mode during idle conditions. Additionally, a CAN wakeup event can wake up the ADSP-BF539/ADSP-BF539F processor from Deep Sleep or Hibernate mode, and wake up the on-chip internal voltage regulator from a powered-down state.
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Preliminary Technical Data
DYNAMIC POWER MANAGEMENT
The ADSP-BF539/ADSP-BF539F processor provides five operating modes, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF539/ADSP-BF539F processor peripherals also reduces power consumption. See Table 5 for a summary of the power settings for each mode.
ADSP-BF539/ADSP-BF539F
Deep Sleep Operating Mode--Maximum Dynamic Power Savings
The Deep Sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals such as the RTC may still be running, but will not be able to access internal resources or external memory. This powered down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in Deep Sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in Deep Sleep mode causes the processor to transition to the Full On mode.
Full-On Operating Mode--Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the powerup default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.
Hibernate Operating Mode--Maximum Static Power Savings
The Hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Since VDDEXT is still supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up either by a Real Time Clock wakeup, by CAN bus traffic, by asserting the RESET pin or by MOST bus traffic causing the MRXON pin to assert.
Active Operating Mode--Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories. In the Active mode, it is possible to disable the PLL through the PLL Control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes. Table 5. Power Settings
PLL Bypassed System Clock (SCLK) Core Clock (CCLK) Core Power
Mode
PLL
Power Savings
As shown in Table 6, the ADSP-BF539/ADSP-BF539F processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF539/ADSP-BF539F processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of Dynamic Power Management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains. Table 6. Power Domains
Power Domain RTC crystal I/O and logic MXVR crystal I/O MXVR PLL analog and logic All internal logic except RTC and MXVR PLL All I/O except RTC and MXVR crystals VDD Range VDDRTC MXEVDD MPIVDD VDDINT VDDEXT
Full On Active Sleep Hibernate
Enabled Enabled Disabled
No
Enabled Enabled On Enabled Enabled On Disabled Enabled On Disabled Disabled On Disabled Disabled Off
Enabled/ Disabled Yes
Deep Sleep Disabled
Sleep Operating Mode--High Dynamic Power Savings
The Sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the Full On mode. If BYPASS is enabled, the processor will transition to the Active mode. When in the Sleep mode, system DMA access to L1 memory is not supported.
The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25%
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ADSP-BF539/ADSP-BF539F
results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. The Dynamic Power Management feature of the ADSPBF539/ADSP-BF539F processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The savings in power dissipation can be modeled using the Power Savings Factor and % Power Savings calculations. The Power Savings Factor is calculated as: Power Savings Factor T RED f CCLKRED V DDINTRED 2 = -------------------- x ------------------------- x ------------ f CCLKNOM V DDINTNOM T NOM where the variables in the equations are: * fCCLKNOM is the nominal core clock frequency * fCCLKRED is the reduced core clock frequency * VDDINTNOM is the nominal internal supply voltage * VDDINTRED is the reduced internal supply voltage * TNOM is the duration running at fCCLKNOM * TRED is the duration running at fCCLKRED The Power Savings Factor is calculated as: % Power Savings = ( 1 - Power Savings Factor ) x 100%
I/O POWER PINS
Preliminary Technical Data
100 F 10 H 0.1 F 100 F 1 F ZHCS1000
INTERNAL POWER PINS
2.7 V - 3.6 V INPUT VOLTAGE RANGE FDS9431A
VROUT1-0 EXTERNAL COMPONENTS NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 6. Voltage Regulator Circuit
If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF539/ADSP-BF539F processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 7. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator that can generate processor core voltage levels 1.0 V(-5%/+10%) to 1.2V(-5% / +10%) from an external 2.7 V to 3.6 V supply. Figure 6 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while I/O power (VDDRTC, MXEVDD, VDDEXT) is still supplied. While in Hibernate mode, I/O power is still being applied, eliminating the need for external buffers. The voltage regulator can be activated from this power-down state either through an RTC wakeup, a CAN wakeup, an MXVR wakeup, or by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user's discretion.
CLKIN BLACKFIN PROCESSOR
XTAL
CLKOUT
Figure 7. External Crystal Connections
CLOCK SIGNALS
The ADSP-BF539/ADSP-BF539F processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.
As shown in Figure 8 on Page 17, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 0.5x to 64x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed
See EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors.
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Preliminary Technical Data
"FINE" ADJUSTMENT REQUIRES PLL SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
ADSP-BF539/ADSP-BF539F
BOOTING MODES
The ADSP-BF539/ADSP-BF539F processor has three mechanisms (listed in Table 9) for automatically loading internal L1 instruction memory after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. Table 9. Booting Modes
BMODE1-0 Description
/ 1, 2, 4, 8 CLKIN PLL 0.5x-64x
CCLK
VCO / 1:15 SCLK
SCLK CCLK SCLK 133MHz
00 01 10 11
Execute from 16-bit external memory (bypass boot ROM) Boot from 8-bit or 16-bit flash (ADSP-BF539 only) or Boot from onboard flash (ADSP-BF539F only) Boot from SPI serial master Boot from SPI serial slave EEPROM /flash (8-,16-, or 24-bit address range, or Atmel AT45DB041, AT45DB081, or AT45DB161serial flash)
Figure 8. Frequency Modification Methods
into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 7 illustrates typical system clock ratios: Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz) SSEL3-0 VCO/SCLK VCO SCLK 0001 0110 1010 1:1 6:1 10:1 100 300 500 100 50 50
The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from 8-bit external flash memory - The 8-bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. If FCE is connected to AMS0, then the on-chip flash is booted from the ADSPBF539F. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit addressable, or Atmel AT45DB041, AT45DB081, or AT45DB161) - The SPI uses the PF2 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable device is detected, and begins clocking data into the beginning of the L1 instruction memory. * Boot from SPI host device - The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor asserts a GPIO pin, called host wait (HWAIT), to signal the host device not to send any more bytes until the flag is deasserted. The flag is chosen by the user and this information is transferred to the Blackfin processor via bits 10:5 of the FLAG header. For each of the boot modes, a 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address.
The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). Note that when the SSEL value is changed, it will affect all the peripherals that derive their clock signals from the SCLK signal. The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1-0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 8. This programmable core clock capability is useful for fast core frequency modifications. Table 8. Core Clock Ratios
Signal Name CSEL1-0 00 01 10 11 Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1 Example Frequency Ratios VCO 300 300 500 200 CCLK 300 150 125 25
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ADSP-BF539/ADSP-BF539F
Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM. In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. To augment the boot modes, a secondary software loader is provided that adds additional booting mechanisms. This secondary loader provides the capability to boot from 16-bit flash memory, fast flash, variable baud rate, and other sources. In all Boot modes except Bypass, program execution starts from on-chip L1 memory address 0xFFA0 0000.
Preliminary Technical Data
VisualDSP++(R) development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF539/ADSP-BF539F processor. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to processor assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information). * Insert breakpoints. * Set conditional breakpoints on registers, memory, and stacks. * Trace instruction execution. * Perform linear or statistical profiling of program execution. * Fill, dump, and graphically plot the contents of memory. * Perform source level debugging. * Create custom debugger windows. The VisualDSP++ IDDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. * A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU plus two load/store plus two pointer updates per cycle. * All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers. * Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.
DEVELOPMENT TOOLS
The ADSP-BF539/ADSP-BF539F processor is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
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Preliminary Technical Data
The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VCSE is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF539/ADSP-BF539F processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non intrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third party software tools include DSP libraries, real time operating systems, and block diagram design tools.
ADSP-BF539/ADSP-BF539F
uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices web site (www.analog.com)--use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
EXAMPLE CONNECTIONS AND LAYOUT CONSIDERATIONS
Figure 9 shows an example circuit connection of the ADSPBF539/ADSP-BF539F connecting to a MOST network. This diagram is intended as an example and exact connections and recommended circuit values should be obtained from Analog Devices.
VOLTAGE REGULATOR LAYOUT GUIDELINES
Regulator external component placement, board routing, and bypass capacitors all have a significant effect on noise injected into the other analog circuits on-chip. The VROUT1-0 traces and voltage regulator external components should be considered as noise sources when doing board layout and should not be routed or placed near sensitive circuits or components on the board. All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the ADSPBF539/ADSP-BF539F as possible. For further details on the on-chip voltage regulator and related board design guidelines, see the EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors applications note on the Analog Devices web site (www.analog.com)--use site search on "EE-228.".
MXVR BOARD LAYOUT GUIDELINES
MLF pin * Capacitors: C1: 0.1F (PPS type, 2% tolerance recommended) C2: 0.01F (PPS type, 2% tolerance recommended) * Resistor: R1: 220 ohm (1% tolerance) * The RC network connected to the MLF pin should be located physically close to the MLF pin on the board. * The RC network should be wired up and connected to the MLF pin using wide traces. * The capacitors in the RC network should be grounded to MXEGND.
DESIGNING AN EMULATOR COMPATIBLE PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator
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ADSP-BF539/ADSP-BF539F
VDDINT (1.2 V) ADSP-BF539F FB PIVDD 0.01 F 0.1 F MTXON Power Gating Circuit 27 MTX MRX MXEGND MRXON 5V 5V
Preliminary Technical Data
MOST FOT Rx_Vdd Tx_Vdd MOST Network
TX_Data RX_Data Status
49.152 MHz Oscillator CLKO MXI MXO MLF MFS 33 R1 220 C2 0.01 F C1 0.1 F MMCLK 33 MBCLK TSCLK0 MXEGND RSCLK0 DT0PRI SDATA BCLK MCLK
RFS0 33 L/RCLK Audio DAC Audio Channels
Figure 9. Example connections of ADSP-BF539/ADSP-BF539F to MOST Network
* The RC network should be shielded using MXEGND traces. * Avoid routing other switching signals near the RC network to avoid crosstalk. MXI driven with external Clock Oscillator IC (recommended) * MXI should be driven with the clock output of a 49.152MHz or 45.1584MHz clock oscillator IC. * MXO should be left unconnected. * Avoid routing other switching signals near the oscillator and clock output trace to avoid crosstalk. When not possible, shield traces with ground. MXI/MXO with external Crystal * The crystal must be a 49.152MHz or 45.1584MHz fundamental mode crystal. * The crystal and load capacitors should be placed physically close to the MXI and MXO pins on the board. * The load capacitors should be grounded to MXEGND. * The crystal and load capacitors should be wired up using wide traces. * Board trace capacitance on each lead should not be more than 3pF. * Trace capacitance plus load capacitance should equal the load capacitance specification for the crystal. * Avoid routing other switching signals near the crystal and components to avoid crosstalk. When not possible, shield traces and components with ground.
MXEGND - MXVR Crystal Oscillator and MXVR PLL Ground * Should be routed with wide traces or as ground plane. * Should be tied together to other board grounds at only one point on the board. * Avoid routing other switching signals near to MXEGND to avoid crosstalk. MXEVDD - MXVR Crystal Oscillator 3.3V Power * Should be routed with wide traces or as power plane. * Locally bypass MXEVDD with 0.1F and 0.01F decoupling capacitors to MXEGND. * Avoid routing other switching signals near to MXEVDD to avoid crosstalk. MPIVDD - MXVR PLL 1.2V Power * Should be routed with wide traces or as power plane. * A ferrite bead should be placed between the 1.2V VDDINT power plane and the MPIVDD pin for noise isolation. * Locally bypass MPIVDD with 0.1F and 0.01F decoupling capacitors to MXEGND. * Avoid routing other switching signals near to MPIVDD to avoid crosstalk. Fiber Optic Transceiver (FOT) Connections * The traces between ADSP-BF539/ADSP-BF539F and the FOT should be kept as short as possible. * The receive data trace connecting the FOT Receive Data output pin to the ADSP-BF539/ADSP-BF539F MRX input pin should not have a series termination resistor. The edge
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Preliminary Technical Data
rate of the FOT Receive Data signal driven by the FOT is typically very slow and further degradation of the edge rate is not desirable. * The transmit data trace connecting the ADSPBF539/ADSP-BF539F MTX output pin to the FOT Transmit Data input pin should have a 27 Ohm series termination resistor placed close to the ADSPBF539/ADSP-BF539F MTX pin. * The receive data trace and the transmit data trace between the ADSP-BF539/ADSP-BF539F and the FOT should not be routed close to each other in parallel over long distances to avoid crosstalk.
ADSP-BF539/ADSP-BF539F
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ADSP-BF539/ADSP-BF539F
PIN DESCRIPTIONS
ADSP-BF539/ADSP-BF539F processor pin definitions are listed in Table 10. In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiTable 10. Pin Descriptions
Pin Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 BR BG BGH Asynchronous Memory Control AMS3-0 ARDY AOE ARE AWE Flash Control FCE FRESET Synchronous Memory Control SRAS SCAS SWE SCKE CLKOUT SA10 SMS Timers TMR0 TMR1/PPI_FS1 TMR2/PPI_FS2 Parallel Peripheral Interface Port/GPIO PF0/SPI0SS PF1/SPI0SEL1/TMRCLK PF2/SPI0SEL2 PF3/SPI0SEL3/PPI_FS3 I/O I/O I/O I/O Programmable Flag 0/SPI Slave Select Input Programmable Flag 1/SPI Slave Select Enable 1/ External Timer Reference Programmable Flag 2/SPI Slave Select Enable 2 Programmable Flag 3/SPI Slave Select Enable 3/ PPI Frame Sync 3 I/O I/O I/O Timer 0 Timer 1/PPI Frame Sync1 Timer 2/PPI Frame Sync2 O O O O O O O Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output A10 Pin Bank Select I I Flash Enable (ADSP-BF539F only) Flash Reset (ADSP-BF539F only) O I O O O Bank Select Hardware Ready Control Output Enable Read Enable Write Enable O I/O O I O O Address Bus for Async/Sync Access Data Bus for Async/Sync Access Bus Request Bus Grant Bus Grant Hang Type Function
Preliminary Technical Data
plexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics.
Driver Type1 Pull-Up/Down Requirement A A Pull High When Not Used A A A Pull LOW when not used. A A A Leave unconnected for ADSP-BF539 Leave unconnected for ADSP-BF539 A A A A A B A A C C C C C C C
Byte Enables/Data Masks for Async/Sync Access A
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Preliminary Technical Data
Table 10. Pin Descriptions (Continued)
Pin Name PF4/SPI0SEL4/PPI15 PF5/SPI0SEL5/PPI14 PF6/SPI0SEL6/PPI13 PF7/SPI0SEL7/PPI12 PF8/PPI11 PF9/PPI10 PF10/PPI9 PF11/PPI8 PF12/PPI7 PF13/PPI6 PF14/PPI5 PF15/PPI4 PPI3-0 PPI_CLK Controller Area Network CANTX/GPIOC0 CANRX/GPIOC1 Media Transceiver ( MXVR)/ General Purpose I/O MTX/GPIOC5 MTXON/GPIOC9 MRX/GPIOC4 MRXON MXI MXO MLF MMCLK/GPIOC6 MBCLK/GPIOC7 MFS/GPIOC8 GP Two Wire Interface Port SDA0 SCL0 SDA1 SCL1 I/O 5V TWI0 Serial Data I/O 5V TWI0 Serial Clock I/O 5V TWI1 Serial Data I/O 5V TWI1 Serial Clock I/O I/O I 5V I O I I/O I/O I/O I MXVR Transmit Data/GPIO_C_5 MXVR Transmit FOT On/GPIO_C_9 MXVR FOT Receive On MXVR Crystal Input MXVR Crystal Output MXVR Loop Filter MXVR Master Clock/GPIO_C_6 MXVR Bit Clock/GPIO_C_7 MXVR Frame Sync/GPIO_C_8 GPIO_C_4-9 Enable I/O 5V CAN Transmit/GPIO_C_0 I/O 5V CAN Receive/GPIO_C_1 Type Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Programmable Flag 4/ SPI Slave Select Enable 4/PPI 15 Programmable Flag 5/ SPI Slave Select Enable 5/PPI 14 Programmable Flag 6/ SPI Slave Select Enable 6/PPI 13 Programmable Flag 7/ SPI Slave Select Enable 7/PPI 12 Programmable Flag 8/PPI 11 Programmable Flag 9/PPI 10 Programmable Flag 10/PPI 9 Programmable Flag 11/PPI 8 Programmable Flag 12/PPI 7 Programmable Flag 13/PPI 6 Programmable Flag 14/PPI 5 Programmable Flag 15/PPI 4 PPI3-0 PPI Clock
ADSP-BF539/ADSP-BF539F
Driver Type1 Pull-Up/Down Requirement C C C C C C C C C C C C C
C C
C C C Pull LOW when not used. Pull High When Not Used Pull LOW when not used. Leave unconnected when not used. Pull LOW when not used. C C C Pull LOW when not used. E2 E2 E2 E2
I/O 5V MXVR Receive Data/GPIO_C_4
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ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Pin Name Serial Port0 RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC Serial Port1 RSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC Serial Port2 RSCLK2 / GPIOE0 RFS2 / GPIOE1 DR2PRI /GPIOE2 DR2SEC / GPIOE3 TSCLK2 / GPIOE4 TFS2 / GPIOE5 DT2PRI / GPIOE6 DT2SEC / GPIOE7 Serial Port3 RSCLK3 / GPIOE8 RFS3 / GPIOE9 DR3PRI / GPIOE10 DR3SEC / GPIOE11 TSCLK3 / GPIOE12 TFS3 / GPIOE13 DT3PRI / GPIOE14 DT3SEC / GPIOE15 I/O I/O I/O I/O I/O I/O I/O I/O SPORT3 Receive Serial Clock/GPIO_E_8 SPORT3 Receive Frame Sync/GPIO_E_9 SPORT3 Receive Data Primary/GPIO_E_10 SPORT3 Receive Data Secondary/GPIO_E_11 SPORT3 Transmit Serial Clock/GPIO_E_12 SPORT3 Transmit Frame Sync/GPIO_E_13 SPORT3 Transmit Data Primary/GPIO_E_14 SPORT3 Transmit Data Secondary/GPIO_E_15 I/O I/O I/O I/O I/O I/O I/O I/O SPORT2 Receive Serial Clock/GPIO_E_0 SPORT2 Receive Frame Sync/GPIO_E_1 SPORT2 Receive Data Primary/GPIO_E_2 SPORT2 Receive Data Secondary/GPIO_E_3 SPORT2 Transmit Serial Clock/GPIO_E_4 SPORT2 Transmit Frame Sync/GPIO_E_5 SPORT2 Transmit Data Primary/GPIO_E_6 SPORT2 Transmit Data Secondary/GPIO_E_7 I/O I/O I I I/O I/O O O SPORT1 Receive Serial Clock SPORT1 Receive Frame Sync SPORT1 Receive Data Primary SPORT1 Receive Data Secondary SPORT1 Transmit Serial Clock SPORT1 Transmit Frame Sync SPORT1 Transmit Data Primary SPORT1 Transmit Data Secondary I/O I/O I I I/O I/O O O SPORT0 Receive Serial Clock SPORT0 Receive Frame Sync SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Serial Clock SPORT0 Transmit Frame Sync SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary Type Function
Preliminary Technical Data
Driver Type1 Pull-Up/Down Requirement D C
D C C C D C
D C C C D C
D C C C D C
D C C C
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Preliminary Technical Data
Table 10. Pin Descriptions (Continued)
Pin Name SPI0 Port MOSI0 MISO0 SCK0 SPI1 Port MOSI1 / GPIOD0 MISO1 / GPIOD1 SCK1 / GPIOD2 SPI1SS / GPIOD3 SPI1SEL / GPIOD4 SPI2 Port MOSI2 / GPIOD5 MISO2 / GPIOD6 SCK2 / GPIOD7 SPI2SS / GPIOD8 SPI2SEL / GPIOD9 UART0 Port RX0 TX0 UART1 Port RX1 / GPIOD10 TX1 / GPIOD11 UART2 Port RX2 / GPIOD12 TX2 / GPIOD13 Real Time Clock RTXI RTXO JTAG Port TCK TDO TDI TMS TRST EMU Clock CLKIN XTAL I O Clock/Crystal Input Crystal Output I O I I I O JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset Emulation Output I O RTC Crystal Input RTC Crystal Output I/O I/O UART2 Receive/GPIO_D_12 UART2 Transmit/GPIO_D_13 I/O I/O UART1 Receive/GPIO_D_10 UART1 Transmit/GPIO_D_11 I O UART Receive UART Transmit I/O I/O I/O I/O I/O SPI2 Master Out Slave In/GPIO_D_5 SPI2 Master In Slave Out/GPIO_D_6 SPI2 Clock/GPIO_D_7 SPI2 Slave Select Input/GPIO_D_8 SPI2 Slave Select Enable/GPIO_D_9 I/O I/O I/O I/O I/O SPI1 Master Out Slave In/GPIO_D_0 SPI1 Master In Slave Out/GPIO_D_1 SPI1 Clock/GPIO_D_2 SPI1 Slave Select Input/GPIO_D_3 SPI1 Slave Select Enable/GPIO_D_4 I/O I/O I/O SPI0 Master Out Slave In SPI0 Master In Slave Out SPI0 Clock Type Function
ADSP-BF539/ADSP-BF539F
Driver Type1 Pull-Up/Down Requirement C C3 D C C D C C C C D C C
C C C C C Pull LOW when not used.
C
Pull LOW when JTAG port not used. C
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ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Pin Name Mode Controls RESET NMI BMODE1-0 Voltage Regulator VROUT0 VROUT1 Supplies VDDEXT VDDINT VDDRTC MPIVDD MXEVDD MXEGND GND
1 2
Preliminary Technical Data
Driver Type1 Pull-Up/Down Requirement
Type Function I I I O O P P P P P G G Reset Non-maskable Interrupt Boot Mode Strap External FET Drive 0 External FET Drive 1 I/O Power Supply Internal Power Supply Real Time Clock Power Supply MXVR Internal Power Supply MXVR External Power Supply MXVR Ground Ground
Pull High When Not Used
Leave unconnected when not used. Leave unconnected when not used.
Refer to Figure 38 on Page 59 to Figure 49 on Page 60. Open drain output. See version 2.1 of I2C specification for proper resistor value. 3 Pull HIGH through a 4.7 kW resistor if booting via the SPI port.
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Preliminary Technical Data SPECIFICATIONS
Component specifications are subject to change without notice.
ADSP-BF539/ADSP-BF539F
RECOMMENDED OPERATING CONDITIONS
Parameter VDDINT VDDEXT VDDRTC VIH VIHCLKIN VIL TAMBIENT
1 2
Min Internal Supply Voltage
1
Nominal 1.2 3.3
Max 1.32 3.6 3.6 3.6 3.6 0.6 85
Unit V V V V V V C
0.95 2.7 2.25 2.0 2.2 -0.3 -40
External Supply Voltage2 Real Time Clock Power Supply Voltage High Level Input Voltage3, @ VDDEXT =maximum High Level Input Voltage , @ VDDEXT =maximum Low Level Input Voltage3, 5, @ VDDEXT =minimum Automotive Ambient Operating Temperature
4
Parameter value applies also to MPIVDD. Parameter value applies also to MXEVDD. 3 The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum VIH The following bi-directional pins are 3.3 V tolerant: DATA15-0, MISO0, MOSI0, PF15-0, PPI3-0, MTXON, MMCLK, MBCLK, MFS, MTX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, SCK0, TFS0, TFS1, and TMR2-0. The following input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE1-0, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP. 4 Parameter value applies to the CLKIN and MXI input pins. 5 Parameter value applies to all input and bi-directional pins.
RECOMMENDED OPERATING CONDITIONS --APPLIES TO 5V TOLERANT PINS
Parameter1 VIH5V2 VIL5V2
1 2
Min 2.0 -0.3
Nominal
Max 5.5 0.8
Unit V V
High Level Input Voltage, @ VDDEXT =maximum Low Level Input Voltage, @ VDDEXT =minimum
Specifications subject to change without notice. The 5.V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, MRX, CANRX, CANTX. The following input-only pins are 5 V tolerant: MRXON.
ELECTRICAL CHARACTERISTICS
Parameter1 VOH VOL IIH IIL IOZH IOZL CIN
1 2
Test Conditions @ VDDEXT =3.0V, IOH = -0.5 mA @ VDDEXT =3.0V, IOL = 2.0 mA @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT =maximum, VIN = 0 V @ VDDEXT = maximum, VIN = VDD maximum @ VDDEXT = maximum, VIN = 0 V fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V
5 2
Min 2.4
Max 0.4 TBD TBD TBD TBD TBD
Unit V V A A A A pF
High Level Output Voltage2 Low Level Output Voltage High Level Input Current3 Low Level Input Current
4
Three-State Leakage Current4 Three-State Leakage Current Input Capacitance5, 6
Specifications subject to change without notice. Applies to output and bidirectional pins. 3 Applies to input pins. 4 Applies to three-statable pins. 5 Applies to all signal pins. 6 Guaranteed, but not tested.
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ADSP-BF539/ADSP-BF539F
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage3 Input Voltage4 Output Voltage Swing Load Capacitance5 Junction Temperature Under Bias Storage Temperature Range
1 2
Preliminary Technical Data
PACKAGE INFORMATION
The information presented in Figure 10 and Table 12 provides information about how to read the package brand and relate it to specific product features. For a complete listing of product offerings, see the Ordering Guide on Page 69.
Rating
1
a
ADSP-BF539 tppZccc vvvvvv.x n.n yyww country_of_origin
-0.3 V to +1.4 V -0.3 V to +3.8 V -0.5 V to 3.6 V -0.5 V to 5.5 V -0.5 V to VDDEXT +0.5 V 200 pF +125C -65C to +150C
2
B
Figure 10. Product Information on Package
Table 12. Package Brand Information
Brand Key W t pp Z ccc vvvvvv.x n.n yyww Field Description Automotive Grade (Optional) Temperature Range Package Type Lead Free Option (Optional) See Ordering Guide Assembly Lot Code Silicon Revision Date Code
Parameter value applies also to MPIVDD. Parameter value applies also to MXEVDD and VDDRTC. 3 Applies to 100% transient duty cycle. For other duty cycles see Table 11. 4 Applies to pins designated as 5V tolerant only. 5 For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5V) for ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Table 11. Maximum Duty Cycle for Input Transient Voltage
VIN Min (V) -0.50 -0.70 -0.80 -0.90 -1.00
1
1
VIN Max (V) +3.80 +4.00 +4.10 +4.20 +4.30
Maximum Duty Cycle 100% 40% 25% 15% 10%
Applies to all signal pins with the exception of CLKIN, MXI, MXO, MLF, VROUT1-0, XTAL.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF539/ADSP-BF539F processor feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrE |
Page 28 of 70 | May 2006
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 13 describes the timing requirements for the ADSPBF539/ADSP-BF539F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator
ADSP-BF539/ADSP-BF539F
(VCO) operating frequencies, as described in Absolute Maximum Ratings on Page 28. Table 14 describes Phase Locked Loop operating conditions.
Table 13. Core Clock Requirements--ADSP-BF539/ADSP-BF539F--500 MHz
Parameter tCCLK tCCLK tCCLK tCCLK tCCLK Core Cycle Period (VDDINT =1.20 V minimum) Core Cycle Period (VDDINT =1.045 V minimum) Core Cycle Period (VDDINT =0.95 V minimum) Core Cycle Period (VDDINT =0.85 V minimum) Core Cycle Period (VDDINT =0.80 V minimum) Minimum 2.00 2.25 2.50 3.00 4.00 Maximum Unit ns ns ns ns ns
Table 14. Phase Locked Loop Operating Conditions
Parameter fVCO Voltage Controlled Oscillator (VCO) Frequency Minimum 50 Maximum Max CCLK Unit MHz
Table 15. Maximum SCLK Conditions
Parameter1 fSCLK CLKOUT/SCLK Frequency (VDDINT 1.14 V) fSCLK CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
1
VDDEXT = 3.3 V 133 100
VDDEXT = 2.5 V 133 100
Unit MHz MHz
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
Rev. PrE |
Page 29 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Clock and Reset Timing
Table 16 and Figure 11 describe clock and reset operations. Per Absolute Maximum Ratings on Page 28, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 500/133 MHz. Table 16. Clock and Reset Timing
Parameter Timing Requirements tCKIN tCKINL tCKINH tWRST
1 2
Preliminary Technical Data
Minimum CLKIN Period CLKIN Low Pulse1 CLKIN High Pulse
1
Maximum 100.0
Unit ns ns ns ns
20.0 8.0 8.0 11 tCKIN
RESET Asserted Pulsewidth Low2
Applies to bypass mode and non-bypass mode. Applies after power-up sequence is complete. At power-up, the processor's internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
Figure 11. Clock and Reset Timing
Rev. PrE |
Page 30 of 70 | May 2006
Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 17 and Table 18 on Page 31 and Figure 12 and Figure 13 on Page 33 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY. Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter Timing Requirements tSDAT tHDAT tSARDY tHARDY tDO tHO
1
ADSP-BF539/ADSP-BF539F
Min DATA15-0 Setup Before CLKOUT DATA15-0 Hold After CLKOUT ARDY Setup Before the Falling Edge of CLKOUT ARDY Hold After the Falling Edge of CLKOUT Output Delay After CLKOUT Output Hold After CLKOUT
1 1
Max
Unit ns ns ns ns
2.1 0.8 tbd tbd 6.0 0.8
ns ns
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter Timing Requirements tSDAT tHDAT tDANR tHAA tDO tHO
1 2
Min DATA15-0 Setup Before CLKOUT DATA15-0 Hold After CLKOUT ARDY Negated Delay from AMSx Asserted ARDY Asserted Hold After ARE Negated Output Delay After CLKOUT Output Hold After CLKOUT2
2 1
Max
Unit ns ns
2.1 0.8 0.0 6.0 0.8
(S+RA-2)*tSCLK ns ns ns ns
S = number of programmed setup cycles, RA = number of programmed read access cycles. Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
Rev. PrE |
Page 31 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES
Preliminary Technical Data
ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE
CLKOUT
tDO
AMSx
tHO
ABE1-0 ADDR19-1
BE, ADDRESS
AOE
tDO
ARE
tHO
tHARDY tSARDY
ARDY
tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. PrE |
Page 32 of 70 | May 2006
Preliminary Technical Data
SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES
ADSP-BF539/ADSP-BF539F
ACCESS EXTENDED HOLD 1 CYCLE
CLKOUT
tDO
AMSx
tHO
ABE1-0 ADDR19-1
BE, ADDRESS
AOE
tDO
ARE
tHO
tHAA tDANR
ARDY
tSDAT tHDAT
DATA15-0 READ
Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. PrE |
Page 33 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Asynchronous Memory Write Cycle Timing
Table 19 and Table 20 on Page 34 and Figure 14 and Figure 15 on Page 35 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY. Table 19. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter Timing Requirements tSARDY tHARDY tDDAT tENDAT tDO tHO
1
Preliminary Technical Data
Min ARDY Setup Before the Falling Edge of CLKOUT ARDY Hold After the Falling Edge of CLKOUT DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT Output Hold After CLKOUT1
1
Max
Unit ns ns
tbd tbd 6.0 1.0 6.0 0.8
Switching Characteristics ns ns ns ns
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter Timing Requirements tDANR tHAA tDDAT tENDAT tDO tHO
1 2
Min ARDY Negated Delay from AMSx Asserted1 ARDY Asserted Hold After ARE Negated DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT Output Hold After CLKOUT2
2
Max
Unit
(S+WA-2)*tSCLK ns 0.0 6.0 1.0 6.0 0.8 ns ns ns ns ns
Switching Characteristics
S = number of programmed setup cycles, WA = number of programmed write access cycles. Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
Rev. PrE |
Page 34 of 70 | May 2006
Preliminary Technical Data
SETUP 2 CYCLES PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED 1 CYCLE HOLD 1 CYCLE
ADSP-BF539/ADSP-BF539F
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
tDO tHO
AWE
t SARDY
ARDY
t SARDY t ENDAT
DATA15-0 WRITE DATA
t HARD Y
t HARDY
t DDAT
Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
SETUP 2 CYCLES PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
tDO
AWE
tHO
tDANW
tHAA
ARDY
t ENDAT
DATA15-0 WRITE DATA
Figure 15. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. PrE |
Page 35 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
SDRAM Interface Timing
Table 21. SDRAM Interface Timing
Parameter Timing Requirements tSSDAT tHSDAT tSCLK tSCLKH tSCLKL tDCAD tHCAD tDSDAT tENSDAT
1
Preliminary Technical Data
Minimum DATA Setup Before CLKOUT DATA Hold After CLKOUT CLKOUT Period CLKOUT Width High CLKOUT Width Low Command, ADDR, Data Delay After CLKOUT1 Command, ADDR, Data Hold After CLKOUT1 Data Disable After CLKOUT Data Enable After CLKOUT 1.0 0.8 2.1 0.8 7.5 2.5 2.5
Maximum
Unit ns ns ns ns ns
Switching Characteristics
6.0 6.0
ns ns ns ns
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
t SCLK
CLKOUT
tSCLKH
tSSDAT t HSDAT
DATA (IN)
tSCLKL
tDCAD tENSDAT
DATA(OUT)
tD SDA T tHCAD
t DCAD
CMND ADDR (OUT)
t HCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 16. SDRAM Interface Timing
Rev. PrE |
Page 36 of 70 | May 2006
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 22 and Table 23 on Page 37 and Figure 17 and Figure 18 on Page 39 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 22. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter Timing Requirements tBS tBH tSD tSE tDBG tEBG tDBH tEBH BR Setup to Falling Edge of CLKOUT Falling Edge of CLKOUT to BR Deasserted Hold Time CLKOUT Low to xMS, Address, and RD/WR disable CLKOUT Low to xMS, Address, and RD/WR enable CLKOUT High to BG High Setup CLKOUT High to BG Deasserted Hold Time CLKOUT High to BGH High Setup CLKOUT High to BGH Deasserted Hold Time
ADSP-BF539/ADSP-BF539F
Min tbd tbd
Max
Unit ns ns
Switching Characteristics 4.5 4.5 3.6 3.6 3.6 3.6 ns ns ns ns ns ns
Table 23. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter Timing Requirements tWBR tSD tSE tDBG tEBG tDBH tEBH BR Pulsewidth CLKOUT Low to xMS, Address, and RD/WR disable CLKOUT Low to xMS, Address, and RD/WR enable CLKOUT High to BG High Setup CLKOUT High to BG Deasserted Hold Time CLKOUT High to BGH High Setup CLKOUT High to BGH Deasserted Hold Time 2 x tSCLK 4.5 4.5 3.6 3.6 3.6 3.6 ns ns ns ns ns ns ns Switching Characteristics Min Max Unit
Rev. PrE |
Page 37 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
CLKOUT
Preliminary Technical Data
tBS
BR
tBH
tSD
AMSx
tSE
tSD
tSE
ADDR19-1 ABE1-0
tSD
tSE
AWE ARE
tDBG
BG
tEBG
tDBH
BGH
tEBH
Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrE |
Page 38 of 70 | May 2006
Preliminary Technical Data
CLKOUT
ADSP-BF539/ADSP-BF539F
tWBR
BR
tSD
AMSx
tSE
tSD
tSE
ADDR19-1 ABE1-0
tSD
tSE
AWE ARE
tDBG
BG
tEBG
tDBH
BGH
tEBH
Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrE |
Page 39 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Parallel Peripheral Interface Timing
Table 24 and Figure 19, Figure 20, Figure 21, and Figure 22 describe Parallel Peripheral Interface operations. Table 24. Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW tPCLK tSFSPE tHFSPE tSDRPE tHDRPE tDFSPE tHOFSPE tDDTPE tHDTPE
1
Preliminary Technical Data
Min PPI_CLK Width PPI_CLK Period
1
Max
Unit ns ns ns ns ns ns
6.0 15.0 3.0 3.0 2.0 4.0 10.0 0.0 10.0 0.0
External Frame Sync Setup Before PPI_CLK External Frame Sync Hold After PPI_CLK Receive Data Setup Before PPI_CLK Receive Data Hold After PPI_CLK Internal Frame Sync Delay After PPI_CLK Internal Frame Sync Hold After PPI_CLK Transmit Data Delay After PPI_CLK Transmit Data Hold After PPI_CLK
Switching Characteristics -- GP Output and Frame Capture Modes ns ns ns ns
PPI_CLK frequency cannot exceed fSCLK/2
FRAME SYNC IS DRIVEN OUT POLC = 0 PPI_CLK
DATA0 IS SAMPLED
PPI_CLK POLC = 1 t t POLS = 1 PPI_FS1 POLS = 0
HOFSPE DFSPE
POLS = 1 PPI_FS2 POLS = 0 tSDRPE tHDRPE
PPI_DATA
Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrE |
Page 40 of 70 | May 2006
Preliminary Technical Data
FRAME SYNC IS SAMPLED FOR DATA0
ADSP-BF539/ADSP-BF539F
DATA0 IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1
DATA1 IS SAMPLED
t tSFSPE POLS = 1 PPI_FS1 POLS = 0
HFSPE
POLS = 1 PPI_FS2 POLS = 0 t
SDRPE
t
HDRPE
PPI_DATA
Figure 20. PPI GP Rx Mode with External Frame Sync Timing
FRAME SYNC IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1 t t POLS = 1 PPI_FS1 POLS = 0
SFSPE HFSPE
DATA0 IS DRIVEN OUT
POLS = 1 PPI_FS2 POLS = 0 tHDTPE
PPI_DATA
DATA0
Figure 21. PPI GP Tx Mode with External Frame Sync Timing
Rev. PrE |
Page 41 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
FRAME SYNC IS DRIVEN OUT
Preliminary Technical Data
DATA0 IS DRIVEN OUT
PPI_CLK POLC = 0 PPI_CLK POLC = 1 t tHOFSPE POLS = 1 PPI_FS1 POLS = 0
DFSPE
POLS = 1 PPI_FS2 POLS = 0 tDDTPE t
HDTPE
PPI_DATA
DATA0
Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrE |
Page 42 of 70 | May 2006
Preliminary Technical Data
Serial Ports Timing
Table 25 through Table 28 on Page 44 and Figure 23 on Page 44 through Figure 25 on Page 46 describe Serial Port operations. Table 25. Serial Ports--External Clock
Parameter Timing Requirements tSFSE tHFSE tSDRE tHDRE tSCLKEW tSCLKE tDFSE tHOFSE tDDTE tHDTE
1 2
ADSP-BF539/ADSP-BF539F
Min TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS) Receive Data Setup Before RSCLK1 Receive Data Hold After RSCLK TSCLK/RSCLK Width TSCLK/RSCLK Period TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2 Transmit Data Delay After TSCLK2 Transmit Data Hold After TSCLK2 0.0 0.0
1 1
Max
Unit ns ns ns ns ns ns
3.0 3.0 3.0 3.0 4.5 15.0 10.0 10.0
Switching Characteristics ns ns ns ns
Referenced to sample edge. Referenced to drive edge.
Table 26. Serial Ports--Internal Clock
Parameter Timing Requirements tSFSI tHFSI tSDRI tHDRI tSCLKEW tSCLKE tDFSI tHOFSI tDDTI tHDTI tSCLKIW
1 2
Min TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1 Receive Data Setup Before RSCLK1 Receive Data Hold After RSCLK1 TSCLK/RSCLK Width TSCLK/RSCLK Period TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS) Transmit Data Delay After TSCLK2 Transmit Data Hold After TSCLK TSCLK/RSCLK Width
2 2
Max
Unit ns ns ns ns ns ns
8.0 -2.0 6.0 0.0 4.5 15.0 3.0 -1.0 3.0 -2.0 4.5
Switching Characteristics ns ns ns ns ns
Referenced to sample edge. Referenced to drive edge.
Table 27. Serial Ports--Enable and Three-State
Parameter Switching Characteristics tDTENE tDDTTE tDTENI tDDTTI
1
Min Data Enable Delay from External TSCLK1 Data Disable Delay from External TSCLK Data Enable Delay from Internal TSCLK1 Data Disable Delay from Internal TSCLK1
1
Max
Unit ns
0 10.0 -2.0 3.0
ns ns ns
Referenced to drive edge.
Rev. PrE |
Page 43 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Table 28. External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE tDTENLFS
1
Preliminary Technical Data
Min Max 10.0 0 Unit ns ns
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2 Data Enable from late FS or MCE = 1, MFD = 0
1, 2
MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE. 2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLK RSCLK
tSCLKEW
tDFSE tHOFSE
RFS
tDFSE tSFSI tHFSI
RFS
tHOFSE
tSFSE
tHFSE
tSDRI
DR
tHDRI
DR
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TSCLK TSCLK
tSCLKEW
tDFSI tHOFSI
TFS
tDFSE tSFSI tHFSI
TFS
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
DT DT
tDDTE tHDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE TSCLK (EXT) TFS ("LATE", EXT.) TSCLK / RSCLK DRIVE EDGE
tDTENE
DT DRIVE EDGE TSCLK (INT) TFS ("LATE", INT.) TSCLK / RSCLK DRIVE EDGE
tDDTTE
tDTENI
DT
tDDTTI
Figure 23. Serial Ports
Rev. PrE |
Page 44 of 70 | May 2006
Preliminary Technical Data
EXTERNAL RFS WITHMCE =1, MFD= 0 (INTERNAL OREXTERNAL CLOCK) DRIVE RSCLK SAMPLE DRIVE
ADSP-BF539/ADSP-BF539F
tSFSE/I
RFS
tHOFSE/I
tDDTE/I tDTENLFS
DT
tHDTE/I
2NDBIT
1ST BIT
tDDTLFSE
LATEEXTERNAL TFS (INTERNAL OREXTERNAL CLOCK) DRIVE TSCLK SAMPLE DRIVE
tSFSE/I
TFS
tHOFSE/I
tDDTE/I TDTENLFS
DT 1ST BIT
tHDTE/I
2NDBIT
tDDTLFSE
Figure 24. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrE |
Page 45 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE
Preliminary Technical Data
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I tDTENLSCK
DT 1ST BIT
tHDTE/I
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS DRIVE SAMPLE DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I tDTENLSCK
DT 1ST BIT
tHDTE/I
2ND BIT
tDDTLSCK
Figure 25. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrE |
Page 46 of 70 | May 2006
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port --Master Timing
Table 29 and Figure 26 describe SPI port master operations. Table 29. Serial Peripheral Interface (SPI) Port--Master Timing
Parameter Timing Requirements tSSPIDM tHSPIDM tSDSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tDDSPIDM tHDSPIDM Data Input Valid to SCK Edge (Data Input Setup) SCK Sampling Edge to Data Input Invalid SPI0SELx Low to First SCK edge (x=0 or 1) Serial Clock High period Serial Clock Low period Serial Clock Period Last SCK Edge to SPI0SELx High (x=0 or 1) Sequential Transfer Delay SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold)
ADSP-BF539/ADSP-BF539F
Min 7.5 -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 0 -1.0
Max
Unit ns ns ns ns ns ns ns ns
Switching Characteristics
6 4.0
ns ns
SPISELx (OUTPUT)
tSDSCIM
SCK (CPOL = 0) (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCK (CPOL = 1) (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT) CPHA=1 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
tSSPIDM
LSB VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHA=0 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port--Master Timing
Rev. PrE |
Page 47 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Serial Peripheral Interface (SPI) Port --Slave Timing
Table 30 and Figure 27 describe SPI port slave operations. Table 30. Serial Peripheral Interface (SPI) Port--Slave Timing
Parameter Timing Requirements tSPICHS tSPICLS tSPICLK tHDS tSPITDS tSDSCI tSSPID tHSPID tDSOE tDSDHI tDDSPID tHDSPID Serial Clock High Period Serial Clock low Period Serial Clock Period Last SCK Edge to SPI0SS Not Asserted Sequential Transfer Delay SPI0SS Assertion to First SCK Edge Data Input Valid to SCK Edge (Data Input Setup) SCK Sampling Edge to Data Input Invalid SPI0SS Assertion to Data Out Active SPI0SS Deassertion to Data High impedance SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold)
Preliminary Technical Data
Min 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 1.6 1.6 0 0 0 0
Max
Unit ns ns ns ns ns ns ns ns
Switching Characteristics 8 8 10 10 ns ns ns ns
SPISS (INPUT)
tSPICHS
SCK (CPOL = 0) (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCK (CPOL = 1) (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
LSB
MISO (OUTPUT) CPHA=1 MOSI (INPUT)
MSB
tSSPID
MSB VALID
tHSPID
tSSPID
tHSPID
LSB VALID
tDSOE
MISO (OUTPUT) CPHA=0 MOSI (INPUT)
tDDSPID
MSB LSB
tDSDHI
tHSPID tSSPID
MSB VALID LSB VALID
Figure 27. Serial Peripheral Interface (SPI) Port--Slave Timing
Rev. PrE |
Page 48 of 70 | May 2006
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter (UART) Port Timing
Figure 28 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 28 there is some latency between the generation internal UART
CLKOUT (SAMPLE CLOCK)
ADSP-BF539/ADSP-BF539F
interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
RXD
DATA(5-8) STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ
START TXD DATA(5-8) STOP (1-2)
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT
Figure 28. UART Port--Receive and Transmit Timing
Rev. PrE |
Page 49 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Programmable Flags Cycle Timing
Table 31 and Figure 29 describe programmable flag operations. Table 31. Programmable Flags Cycle Timing
Parameter Timing Requirement tWFI tDFO Flag input pulsewidth Flag output delay from CLKOUT low
Preliminary Technical Data
Minimum tSCLK + 1
Maximum
Unit ns
Switching Characteristic 6 ns
CLKOUT
tDFO
PF (OUTPUT) FLAG OUTPUT
tWFI
PF (INPUT) FLAG INPUT
Figure 29. Programmable Flags Cycle Timing
Rev. PrE |
Page 50 of 70 | May 2006
Preliminary Technical Data
Timer Cycle Timing
Table 32 and Figure 30 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of fSCLK/2 MHz. Table 32. Timer Cycle Timing
Parameter Timing Characteristics tWL tWH tHTO
1 2
ADSP-BF539/ADSP-BF539F
Minimum Timer Pulsewidth Input Low1 (measured in SCLK cycles) Timer Pulsewidth Input High1 (measured in SCLK cycles) Timer Pulsewidth Output2 (measured in SCLK cycles) 1 1 1
Maximum
Unit SCLK SCLK
Switching Characteristic (232-1) SCLK
The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES)
tWL
tWH
Figure 30. Timer PWM_OUT Cycle Timing
Rev. PrE |
Page 51 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
JTAG Test And Emulation Port Timing
Table 33 and Figure 31 describe JTAG port operations. Table 33. JTAG Port Timing
Parameter Timing Requirements tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW tDTDO tDSYS
1
Preliminary Technical Data
Minimum TCK Period TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High System Inputs Setup Before TCK High1 System Inputs Hold After TCK High
1
Maximum
Unit ns ns ns ns ns TCK
20 4 4 4 5 4 10 0 12
TRST Pulsewidth2 (measured in TCK cycles) TDO Delay from TCK Low System Outputs Delay After TCK Low3
Switching Characteristics ns ns
System Inputs=ARDY, BMODE1-0, BR, DATA15-0.DR0PRI, DR0SEC, DR1PRI, DR1SEC, MISO0, MOSI0, NMI, PF15-0, PPI_CLK, PPI3-0.SCL0, SCL1, SDA0, SDA1, SCK, MTXON, MRXON, MMCLK, MBCLK, MFS, MTX, MRX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RESET, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, RX0,.SCK0, TFS0, TFS1, and TMR2-0, 2 50 MHz Maximum 3 System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15-0, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MISO0, MOSI0, PF15-0, PPI3-0, MTXON, MRXON, MMCLK, MBCLK, MFS, MTX, MRX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DR2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, TSCLK3, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, CLKOUT, TX0, SA10, SCAS, SCK0, SCKE, SMS, SRAS, SWE, and TMR2-0.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 31. JTAG Port Timing
Rev. PrE |
Page 52 of 70 | May 2006
Preliminary Technical Data
TWI Controller Timing
Table 34 through Table 41 and Figure 32 through Figure 35 describe the TWI Controller operations. Table 34. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 100 kHz
Parameter tSU:STA tHD:STA tSU:STO tBUF Start condition setup time Start condition hold time Stop condition setup time Bus free time between STOP and START condition
ADSP-BF539/ADSP-BF539F
Min 4.7 4.0 4.0 4.7
Max
Unit s s s s
Table 35. TWI Controller Timing: Bus Data Requirements, Slave Mode, 100 kHz
Parameter tHIGH tLOW tR tF tHD:DAT tSU:DAT CB
1
Min Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Data input hold time Data input setup time
1
Max
Unit s s
4.0 4.7 1000 300 0 250 400
ns ns ns ns pF
Bus capacitive loading
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Table 36. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 400 kHz
Parameter tSU:STA tHD:STA tSU:STO tBUF Start condition setup time Start condition hold time Stop condition setup time Bus free time between STOP and START condition Min 0.6 0.6 0.6 1.3 Max Unit s s s s
Table 37. TWI Controller Timing: Bus Data Requirements, Slave Mode, 400 kHz
Parameter tHIGH tLOW tR tF tHD:DAT tSU:DAT CB
1
Min Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Data input hold time Data input setup time
1
Max
Unit s s
0.6 1.3 TBD TBD 0 100 400 300 300 0.9
ns ns s ns pF
Bus capacitive loading
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Rev. PrE |
Page 53 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Table 38. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 100 kHz
Parameter tSU:STA tHD:STA tSU:STO tBUF Start condition setup time Start condition hold time Stop condition setup time Bus free time between STOP and START condition
Preliminary Technical Data
Min 4.7 4.0 4.0 4.7 Max Unit s s s s
Table 39. TWI Controller Timing: Bus Data Requirements, Master Mode, 100 kHz
Parameter tHIGH tLOW tR tF tHD:DAT tSU:DAT CB
1 2
Min Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Data input hold time Data input setup time
1
Max
Unit s s
4.0 4.7 1000 300 0 250 400
2
ns ns ns ns pF
Bus capacitive loading
A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification).
Table 40. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 400 kHz
Parameter tSU:STA tHD:STA tSU:STO tBUF Start condition setup time Start condition hold time Stop condition setup time Bus free time between STOP and START condition Min 0.6 0.6 0.6 1.3 Max Unit s s s s
Table 41. TWI Controller Timing: Bus Data Requirements, Master Mode, 400 kHz
Parameter tHIGH tLOW tR tF tHD:DAT tSU:DAT CB
1 2
Min Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Data input hold time Data input setup time
1
Max
Unit s s
0.6 1.3 TBD TBD 0 100 400
2
300 300 0.9
ns ns s ns pF
Bus capacitive loading
A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification).
Rev. PrE |
Page 54 of 70 | May 2006
Preliminary Technical Data
ADSP-BF539/ADSP-BF539F
SCL
tHD:STA tSU:STA
SDA
tHD:STO tSU:STO
START
STOP
Figure 32. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode
tF tR
tH IGH
tLO W
SCL
tSU :S TA
SDA (IN)
tH D :STA
tH D :D A T
tS U :D AT
tS U :STO
tA A
tA A
tB UF
SDA (OUT)
Figure 33. TWI Controller Timing: Bus Data, Slave Mode
SCL
tHD:STA tSU:STA tSU:STO
tHD:STO
SDA
START
STOP
Figure 34. TWI Controller Timing: Bus Start/Stop Bits, Master Mode
Rev. PrE |
Page 55 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
tF tH IGH tLO W tR
Preliminary Technical Data
SCL
tSU :S TA
SDA (IN)
tH D :STA
tH D :D A T
tS U :D AT
tS U :STO
tA A
tA A
tB UF
SDA (OUT)
Figure 35. TWI Controller Timing: Bus Data, Master Mode
Rev. PrE |
Page 56 of 70 | May 2006
Preliminary Technical Data
MXVR Timing
Table 42 through Table 43 and Figure 36 describe the MXVR operations. Table 42. MXVR Timing--Input Clock Requirements
Parameter Timing Requirements tCKIN MXI Period1 tCKINL MXI Low Pulse tCKINH MXI High Pulse
1
ADSP-BF539/ADSP-BF539F
Min 20 8 8
Max
Unit ns ns ns
For FS=48 KHz, fMXI should be 49.152 MHz. For Fs=44.1 KHz, fMXI should be 45.1584 MHz. For FS=38 KHz, fMXI should be 38.912 MHz.
Table 43. MXVR Timing--Rise and Fall Time
Parameter tR tF Min Max TBD TBD Unit ns ns
MTX/MMCLK/MBCLK/MFS/MTXON Rise Time MTX/MMCLK/MBCLK/MFS/MTXON Fall Time
TBD
Figure 36. MXVR Timing
Rev. PrE |
Page 57 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
CAN Timing
Table 44 and Figure 37 describe the CAN operations. Table 44. CAN Timing--Rise and Fall Time
Parameter tR tF
Preliminary Technical Data
CANTX rise time CANTX fall time
Minimum -
Maximum TBD TBD
Unit ns ns
TBD
Figure 37. CAN Timing
Rev. PrE |
Page 58 of 70 | May 2006
Preliminary Technical Data
OUTPUT DRIVE CURRENTS
Figure 38 shows typical current-voltage characteristics for the output drivers of the ADSP-BF539/ADSP-BF539F processor. The curves represent the current drive capability of the output drivers as a function of output voltage.
120 100 80
SOURCE CURRENT (mA)
200 150 100
SOURCE CURRENT (mA)
ADSP-BF539/ADSP-BF539F
V DD E XT = 3.0V @ 95C V DD E XT = 3.3V @ 25C VD D EX T = 3.6V @ - 40C VO H 50 0
-50 -100
V D DE XT = 2.25V @ 95C V D DE XT = 2.50V @ 25C V D DE XT = 2.75V @ -40C V OH
60 40 20 0
-20 -40 -60 -80 -100
VOL
-150 -200
0
0. 5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOLTAGE (V)
V OL
Figure 41. Drive Current B (High VDDEXT)
80 VD D EXT = 2.25V @ 95C 60 40 V OH 20 0
-20
0
0.5
1.0
1.5
2.0
2.5
3.0
VD D EXT = 2.50V @ 25C VD D EX T = 2.75V @ -40C
Figure 38. Drive Current A (Low VDDEXT)
150 VD D EX T = 3.0V @ 95C 100
SOURCE CURRENT (mA)
VD D EX T = 3.3V @ 25C VD D EX T = 3.6V @ -40C
SOURCE CURRENT (mA)
SOURCE VOL TAGE (V)
VOL
-40
50 VO H
-60
0
0
0.5
1.0
1.5
2.0
2. 5
3.0
SOURCE VOLTAGE (V)
-50
Figure 42. Drive Current C (Low VDDEXT)
VOL
100 80 VD D EX T = 3.0V @ 95 C VD D EX T = 3.3V @ 25 C V DD E XT = 3.6V @ -40C
-100
-150
0
0. 5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE CURRENT (mA)
60 40
SOURCE VOLTAGE (V)
Figure 39. Drive Current A (High VDDEXT)
150 VD D EX T = 2.25V @ 95C V DD E XT = 2.50V @ 25C VD DE XT = 2.75V @ -40C
VOH 20 0
-20 -40
100
SOURCE CURRENT (mA)
50 V OH
VO L
-60 -80
0
0
0. 5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOLTAGE (V)
-50
Figure 43. Drive Current C (High VDDEXT)
V OL
-100
-150
0
0.5
1.0
1.5
2.0
2. 5
3.0
SOURCE VOLTAGE (V)
Figure 40. Drive Current B (Low VDDEXT)
Rev. PrE |
Page 59 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
100 80 60
SOURCE CURRENT (mA)
80
Preliminary Technical Data
60 40
SOURCE CURRENT (mA)
V D DE XT = 2.25V @ 95C V D DE XT = 2.50V @ 25C VD D E XT = 2.75V @ -40C
VD D EX T = 3.0V @ 95C VD D EX T = 3.3V @ 25C V DD E XT = 3.6V @ -40C
40 VOH 20 0
-20 -40
20 VO H 0
-20 -40
V OL
-60 -80
VOL
-60 -80
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0. 5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 44. Drive Current D (Low VDDEXT)
150 V D DE XT = 3.0V @ 95 C V D DE XT = 3.3V @ 25 C V DD E XT = 3.6V @ -40C
Figure 47. Drive Current E (High VDDEXT)
0 V DD E XT = 2.25V @ 95C V DD E XT = 2.50V @ 25C VD D EX T = 2.75V @ -40 C
100
-10
SOURCE CURRENT (mA)
50 VOH 0
SOURCE CURRENT (mA)
-20
-30 V OL -40
-50
V OL
-100
-50
-150
-60
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 45. Drive Current D (High VDDEXT)
50 40 30 VD D EX T = 2.25V @ 95 C VD D EX T = 2.50V @ 25 C VD D EX T = 2.75V @ - 40C VOH
SOURCE CURRENT (mA)
Figure 48. Drive Current F (Low VDDEXT)
0 -10 -20 -30 -40 VOL -50 -60 -70 -80 VD D EX T = 3.0V @ 95C VD D EX T = 3.3V @ 25C V D D EXT = 3.6V @ -40C
SOURCE CURRENT (mA)
20 10 0
-10 -20 -30
V OL
-40 -50
0
0.5
1.0
1.5
2.0
2.5
3. 0
0
0. 5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOL TAGE (V)
SOURCE VOLTAGE (V)
Figure 46. Drive Current E (Low VDDEXT)
Figure 49. Drive Current F (High VDDEXT)
Rev. PrE |
Page 60 of 70 | May 2006
Preliminary Technical Data
POWER DISSIPATION
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external output drivers (PEXT). Table 45 through Table 47 show the power dissipation for internal circuitry (VDDINT). See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for definitions of the various operating -modes and for instructions on how to minimize system power. Many operating conditions can affect power dissipation. System designers should refer to EE-229: Estimating Power for ADSP-BF531/ADSP-BF532 Blackfin Processors on the Analog Devices website (www.analog.com)--use site search on "EE-229." This document provides detailed information for optimizing your design for lowest power. Table 45. Internal Power Dissipation (Hibernate mode)
IDD (nominal ) IDDHIBERNATE IDDRTC3
1 2
ADSP-BF539/ADSP-BF539F
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 50 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is 1.5 V for VDDEXT (nominal) = 2.5/3.3 V.
INPUT OR OUTPUT
VMEAS
VMEAS
Figure 50. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
1
Unit A A
2
50 20
Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 51, "Output Enable/Disable," on page 62. The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for VDDEXT (nominal) = 2.5/3.3 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED - t TRIP If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Nominal assumes an operating temperature of 25C. Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V). 3 Measured at VDDRTC = 3.3 V at 25C.
Table 46. Internal Power Dissipation (Deep Sleep mode)
VDDINT1 0.95 1.00 1.10 1.26
1
IDD (nominal2) 28.00 32.00 40.00 54.00
Unit mA mA mA mA
Assumes VDDINT is regulated externally. 2 Nominal assumes an operating temperature of 25C.
Output Disable Time Measurement
1
3
Table 47. Internal Power Dissipation (Full On mode)
VDDINT @ fCCLK (MHz) 0.95 @ 50 MHz 0.95 @ 250 MHz 0.95 @ 300 MHz 1.00 @ 350 MHz 1.10 @ 444 MHz 1.26 @ 500 MHz
1
2
IDD (nominal ) 46.00 98.00 110.00 132.00 180.00 235.00
Unit mA mA mA mA mA mA
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 51. t DIS = t DIS_MEASURED - t DECAY The time for the voltage on the bus to decay by V is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: t DECAY = ( C L V ) I L The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V for VDDEXT (nominal) = 2.5/3.3 V. The time tDIS+_MEASURED is the interval from when the reference signal switches, to when the output voltage decays V from the measured output high or output low voltage.
Processor executing 75% dual MAC, 25% ADD with moderate data bus activity. 2 Assumes VDDINT is regulated externally. 3 Nominal assumes an operating temperature of 25C.
Rev. PrE |
Page 61 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF539/ADSP-BF539F processor's output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on Page 29 (for example tDSDAT for an SDRAM write cycle as shown in Table 21 on Page 36).
Preliminary Technical Data
The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.
14 RISE AND FALL TIME ns (10% t0 90%)
ABE_B[0] (133 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85C
12
RISE TIME
10 8 FALL TIME
6 4
REFERENCE SIGNAL
tDIS_MEASURED tDIS
VOH (MEASURED) VOL (MEASURED)
tENA_MEASURED tENA
2 0
0
50
VOH (MEASURED)
V
VOH(MEASURED) VTRIP(HIGH) VTRIP(LOW) VOL(MEASURED)
100 150 LOAD CAPACITANCE (pF)
200
250
VOL (MEASURED) + V
Figure 53. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver A at VDDEXT (min)
ABE0 (133 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C
12
tDECAY
tTRIP
RISE AND FALL TIME ns (10% to 90%)
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE
10
Figure 51. Output Enable/Disable
RISE TIME
8 FALL TIME 6
TO OUTPUT PIN 30pF
50 VLOAD
4
2
Figure 52. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
0
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
Capacitive Loading
Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 52). VLOAD is 1.5 V for VDDEXT (nominal) = 2.5/3.3 V. Figure 53 on Page 62 through Figure 60 on Page 63 show how output rise time varies with capacitance.
Figure 54. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver A at VDDEXT (max)
Rev. PrE |
Page 62 of 70 | May 2006
Preliminary Technical Data
12 RISE AND FALL TIME ns (10% to 90%)
ADSP-BF539/ADSP-BF539F
20 RISE AND FALL TIME ns (10% to 90%) 18 16
CLKOUT (CLKOUT DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85C
PF9 (33 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C
10
RISE TIME
8 FALL TIME
RISE TIME
14 12 FALL TIME 10 8 6 4 2
6
4
2
0
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
0
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
Figure 55. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver B at VDDEXT (min)
CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C
Figure 58. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver C at VDDEXT (max)
SCK (66 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85C
10 RISE AND FALL TIME ns (10% to 90%) 9 8
18 RISE AND FALL TIME ns (10% to 90%) 16 14 12 10
RISE TIME
7 6 FALL TIME 5 4 3 2 1 0
RISE TIME
FALL TIME 8 6 4 2 0
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
Figure 56. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver B at VDDEXT (max)
PF9 (33 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85C
Figure 59. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver D at VDDEXT (min)
SCK (66 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C
30 RISE AND FALL TIME ns (10% to 90%)
14 RISE AND FALL TIME ns (10% to 90%)
25
12 10
RISE TIME
20
RISE TIME
8 FALL TIME 6 4 2
15 FALL TIME 10
5
0 0
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
0
50
100 150 LOAD CAPACITANCE (pF)
200
250
Figure 57. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver C at VDDEXT (min)
Figure 60. Typical Rise and Fall Times (10%-90%) versus Load Capacitance for Driver D at VDDEXT (max)
Rev. PrE |
Page 63 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( JT x P D ) where: TJ = Junction temperature ( C) TCASE = Case temperature ( C) measured by customer at top center of package. JT = From Table 48 or Table 49 PD = Power dissipation (see Power Dissipation on Page 61 for the method to calculate PD) Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + ( JA x P D ) where: TA = Ambient temperature ( C) Values of JC are provided for package comparison and printed circuit board design considerations when an external heatsink is required. Values of JB are provided for package comparison and printed circuit board design considerations. In Table 48 and Table 49, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 48. Thermal Characteristics BC-316 Without Flash
Parameter JA JMA JMA JC JT JT JT 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 21.6 18.8 18.1 5.36 0.13 0.25 0.25 Unit C/W C/W C/W C/W C/W C/W C/W
Preliminary Technical Data
Table 49. Thermal Characteristics BC-316 With Flash
Parameter JA JMA JMA JC JT JT JT 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 20.9 18.1 17.4 5.01 0.12 0.24 0.24 Unit C/W C/W C/W C/W C/W C/W C/W
Rev. PrE |
Page 64 of 70 | May 2006
Preliminary Technical Data 316-BALL MINI-BGA PINOUT
Figure 61 lists the top view of the mini-BGA pin configuration. Figure 62 lists the bottom view of the mini-BGA pin configuration.
A1 BALL A A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDDINT GND VDDRTC NC B C D E F G H J K L M N P R T U V W Y
ADSP-BF539/ADSP-BF539F
Table 50 on Page 66 lists the mini-BGA pinout by pin number. Table 51 on Page 67 lists the mini-BGA pinout by signal.
A1 BALL
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 GND VDDRTC VDDINT VDDEXT I/O VROUTx
5
4
3
2
1
NC
I/O VROUTx VDDEXT Note: H18 and Y14 are NC for ADSP-BF539 and I/O (FCE and FRESET) for ADSP-BF539F
Note: H18 and Y14 are NC for ADSP-BF539 and I/O (FCE and FRESET) for ADSP-BF539F
Figure 61. 316-Ball Mini-BGA Pin Configuration (Top View)
Figure 62. 316-Ball Mini-BGA Pin Configuration (Bottom View)
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Page 65 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Table 50. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number)
Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 Signal GND PF10 PF11 PPI_CLK PPI0 PPI2 PF15 PF13 VDDRTC RTXO RTXI GND CLKIN XTAL MLF MXO MXI MRXON VROUT1 GND PF8 GND PF9 PF3 PPI1 PPI3 PF14 PF12 SCL0 SDA0 CANRX CANTX NMI RESET MXEVDD MXEGND MTXON GND GND VROUT0 PF6 PF7 GND GND RX1 TX1 Ball No. C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D7 D8 D9 D10 D11 D12 D13 D14 D18 D19 D20 E1 E2 E3 E7 E8 E9 E10 E11 E12 E13 E14 E18 E19 E20 F1 F2 F3 F7 Signal SPI2SEL SPI2SS MOSI2 MISO2 SCK2 MPIVDD SPI1SEL MISO1 SPI1SS MOSI1 SCK1 GND MMCLK SCKE PF4 PF5 DT1SEC GND GND GND GND GND GND GND GND GND MBCLK SMS PF1 PF2 GND GND GND GND GND GND GND GND GND GND MTX ARDY PF0 MISO0 GND GND Ball No. F8 F9 F10 F11 F12 F13 F14 F18 F19 F20 G1 G2 G3 G7 G8 G9 G10 G11 G12 G13 G14 G18 G19 G20 H1 H2 H3 H7 H8 H9 H10 H11 H12 H13 H14 H18 H19 H20 J1 J2 J3 J7 J8 J9 J10 J11 Signal GND GND GND GND GND GND GND DT3PRI MRX MFS SCK0 MOSI0 DT0SEC GND GND GND GND GND GND GND GND BR CLKOUT SRAS DT1PRI TSCK1 DR1SEC GND GND GND GND GND GND GND GND FCE SCAS SWE TFS1 DR1PRI DR0SEC GND GND GND GND GND Ball No. J12 J13 J14 J18 J19 J20 K1 K2 K3 K7 K8 K9 K10 K11 K12 K13 K14 K18 K19 K20 L1 L2 L3 L7 L8 L9 L10 L11 L12 L13 L14 L18 L19 L20 M1 M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 M18 Signal GND GND GND AMS0 AMS2 SA10 RFS1 TMR2 GP GND GND GND GND GND GND GND GND AMS3 AMS1 AOE RSCK1 TMR1 GND GND GND GND GND GND GND GND GND TSCK3 ARE AWE DT0PRI TMR0 GND VDDEXT GND GND GND GND GND GND VDDINT TFS3 Ball No. M19 M20 N1 N2 N3 N7 N8 N9 N10 N11 N12 N13 N14 N18 N19 N20 P1 P2 P3 P7 P8 P9 P10 P11 P12 P13 P14 P18 P19 P20 R1 R2 R3 R7 R8 R9 R10 R11 R12 R13 R14 R18 R19 R20 T1 T2
Preliminary Technical Data
Signal ABE0 ABE1 TFS0 DR0PRI GND VDDEXT GND GND GND GND GND GND VDDINT DT3SEC ADDR1 ADDR2 TSCK0 RFS0 GND VDDEXT GND GND GND GND GND GND VDDINT DR3SEC ADDR3 ADDR4 TX0 RSCK0 GND VDDEXT GND GND GND GND GND GND VDDINT DR3PRI ADDR5 ADDR6 RX0 EMU Ball No. T3 T7 T8 T9 T10 T11 T12 T13 T14 T18 T19 T20 U1 U2 U3 U7 U8 U9 U10 U11 U12 U13 U14 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Signal GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT RFS3 ADDR7 ADDR8 TRST TMS GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT RSCK3 ADDR9 ADDR10 TDI GND GND BMODE1 BMODE0 GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT DR2SEC BG BGH DT2SEC GND GND ADDR11 ADDR12 Ball No. W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal TCK GND DATA15 DATA13 DATA11 DATA9 DATA7 DATA5 DATA3 DATA1 RSCK2 DR2PRI DT2PRI RX2 TX2 ADDR18 ADDR15 ADDR13 GND ADDR14 GND TDO DATA14 DATA12 DATA10 DATA8 DATA6 DATA4 DATA2 DATA0 RFS2 TSCK2 TFS2 FRESET SCL1 SDA1 ADDR19 ADDR17 ADDR16 GND
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Page 66 of 70 | May 2006
Preliminary Technical Data
Table 51. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)
Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BR CANRX CANTX CLKIN CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Ball No. M19 M20 N19 N20 P19 P20 R19 R20 T19 T20 U19 U20 V19 V20 W18 W20 W17 Y19 Y18 W16 Y17 J18 K19 J19 K18 K20 E20 L19 L20 V14 V15 V5 V4 G18 B11 B12 A13 G19 Y10 W10 Y9 W9 Y8 W8 Y7 W7 Signal DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DR0PRI DR0SEC DR1PRI DR1SEC DR2PRI DR2SEC DR3PRI DR3SEC DT0PRI DT0SEC DT1PRI DT1SEC DT2PRI DT2SEC DT3PRI DT3SEC EMU FCE FRESET GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. Y6 W6 Y5 W5 Y4 W4 Y3 W3 N2 J3 J2 H3 W12 V13 R18 P18 M1 G3 H1 D3 W13 V16 F18 N18 T2 H18 Y14 A1 A12 A20 B2 B18 B19 C3 C4 C18 D7 D8 D9 D10 D11 D12 D13 D14 D18 E3 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. E7 E8 E9 E10 E11 E12 E13 E14 E18 F3 F7 F8 F9 F10 F11 F12 F13 F14 G7 G8 G9 G10 G11 G12 G13 G14 H7 H8 H9 H10 H11 H12 H13 H14 J7 J8 J9 J10 J11 J12 J13 J14 K7 K8 K9 K10 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. K11 K12 K13 K14 L3 L7 L8 L9 L10 L11 L12 L13 L14 M3 M8 M9 M10 M11 M12 M13 N3 N8 N9 N10 N11 N12 N13 P3 P8 P9 P10 P11 P12 P13 R3 R8 R9 R10 R11 R12 R13 T3 U3 V2 V3 V6 Signal GND GND GND GND GND GND GP MBCLK MFS MMCLK MLF MISO0 MISO1 MISO2 MOSI0 MOSI1 MOSI2 MPIVDD MRXON MRX MTX MTXON MXEGND MXEVDD MXI MXO NMI PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PPI_CLK PPI0 PPI1
ADSP-BF539/ADSP-BF539F
Ball No. V17 V18 W2 W19 Y1 Y20 K3 D19 F20 C19 A15 F2 C14 C10 G2 C16 C9 C12 A18 F19 E19 B17 B16 B15 A17 A16 B13 F1 E1 E2 B4 D1 D2 C1 C2 B1 B3 A2 A3 B8 A8 B7 A7 A4 A5 B5 Signal PPI2 PPI3 RESET RFS0 RFS1 RFS2 RFS3 RSCK0 RSCK1 RSCK2 RSCK3 RTXI RTXO RX0 RX1 RX2 SA10 SCAS SCK0 SCK1 SCK2 SCKE SCL0 SCL1 SDA0 SDA1 SMS SPI1SEL SPI1SS SPI2SEL SPI2SS SRAS SWE TCK TDI TDO TFS0 TFS1 TFS2 TFS3 TMR0 TMR1 TMR2 TMS TRST TSCK0 Ball No. A6 B6 B14 P2 K1 Y11 T18 R2 L1 W11 U18 A11 A10 T1 C5 W14 J20 H19 G1 C17 C11 C20 B9 Y15 B10 Y16 D20 C13 C15 C7 C8 G20 H20 W1 V1 Y2 N1 J1 Y13 M18 M2 L2 K2 U2 U1 P1 Signal TSCK1 TSCK2 TSCK3 TX0 TX1 TX2 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball No. H2 Y12 L18 R1 C6 W15 M7 N7 P7 R7 T7 T8 T9 T10 T11 U7 U8 U9 U10 U11 V7 V8 V9 V10 V11 M14 N14 P14 R14 T12 T13 T14 U12 U13 U14 V12 A9 B20 A19 A14
Rev. PrE |
Page 67 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
OUTLINE DIMENSIONS
Dimensions in Figure 63--316-Ball Mini Ball Grid Array (BC-316) are shown in millimeters.
Preliminary Technical Data
17.00 BSC SQ A1 BALL INDICATOR A B C D E F G H J K L M N P R T U V W Y
15.20 BSC SQ 0.80 BSC BALL PITCH A1 BALL
TOP VIEW
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW
0.30 MIN
0.12 MAX COPLANARITY 1.70 1.61 1.46 SIDE VIEW DETAIL A 0.50 BALL DIAMETER 0.45 0.40 SEATING PLANE DETAIL A
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM, WITH THE EXCEPTION OF BALL DIAMETER. 3. CENTER DIMENSIONS ARE NOMINAL.
Figure 63. 316-Ball Mini Ball Grid Array (BC-316)
Rev. PrE |
Page 68 of 70 | May 2006
Preliminary Technical Data
SURFACE MOUNT DESIGN
Table 52 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 52. BGA Data for Use with Surface Mount Design
Package 316-Ball Mini Ball Grid Array (BC-316) Ball Attach Type Solder Mask Defined
ADSP-BF539/ADSP-BF539F
Solder Mask Opening 0.40 mm diameter
Ball Pad Size 0.50 mm diameter
ORDERING GUIDE
Model1, 2 ADSP-BF539BBCZ-5A ADSP-BF539WBBCZ-5A ADSP-BF539YBCZ-4A ADSP-BF539WYBCZ-4A ADSP-BF539BBCZ-5F4
4
Temperature Range3 -40C to +85C -40C to +85C -40C to +105C -40C to +105C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array 316-Ball Mini Ball Grid Array
Package Instruction Option Rate (Max) BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 BC-316 500 MHz 500 MHz 400 MHz 400 MHz 500 MHz 500 MHz 500 MHz 500 MHz 400 MHz 400 MHz 400 MHz 400 MHz
Operating Voltage (Nominal) 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O 1.0 V internal, 2.5 V or 3.3 V I/O
ADSP-BF539WBBCZ5F44 ADSP-BF539BBCZ-5F85 ADSP-BF539WBBCZ5F85 ADSP-BF539YBCZ-4F44 ADSP-BF539WYBCZ4F44 ADSP-BF539YBCZ-4F8
1 2
5
ADSP-BF539WYBCZ4F85
W indicates this product is available for use in specific automotive applications. Contact your local ADI sales office for specific ordering information. Z indicates Pb-free part. 3 Referenced temperature is ambient temperature. 4 F4 indicates 256K x 16-bit flash memory. 5 F8 indicates 512K x 16-bit flash memory.
Rev. PrE |
Page 69 of 70 | May 2006
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06167-0-5/06(PrE)
Rev. PrE |
Page 70 of 70 | May 2006

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